DATASHEET SEARCH SITE | WWW.ALLDATASHEET.COM
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 13
Technical content
Features
Frequency range 5 GHz in 10/11 prescaler modulus 4 GHz in 5/6 prescaler modulus Phase noise floor figure of merit: -230 dBc/Hz Selectable prescaler modulus of 5/6 or Low power: 80 mA at 2.8V Serial or direct mode access Internal phase detector Packaged in a 48-lead 7x7 mm QFN Figure 1. Functional Diagram
Applications
Industrial applications Military applications Point-to-point radios Cellular base stations CATV equipment Reference Divider Phase Detector Prescaler 5/6 or Loop Filter VCO RFOUT FIN FREF Main Counter Control Logic Serial Control Fc Fp Direct Control PE33241
Table 1. Pin Descriptions Figure 2. Pin Configurations (Top View) Figure 3. Package Type
2 R4 Direct Input R counter bit 4
3 R5 Direct Input R counter bit 5
4 A3 Direct Input A counter bit 3
5 N/C Both Note 3 No connect
6 GND Both Ground
7 M3 Direct Input M counter bit 3
8 M2 Direct Input M counter bit 2
9 M1 Direct Input M counter bit 1
10 M0 Direct Input M counter bit 0
12 GND Both Ground
13 M8 Direct Input M counter bit 8
14 M7 Direct Input M counter bit 7
Table 1. Pin Descriptions (continued)
18 GND Both Ground
20 A0 Direct Input A counter bit 0
22 A2 Direct Input A counter bit 2
24 N/C Both Note 3 No connect
29 F in Both Input
30 GND Both Ground
32 Cext Both Output
35 PD_D̅ Both Output PD_D is pulse down when fp leads fc
36 PD_U̅ Both Output PD_U is pulse down when fc leads fp
42 GND Both Ground
43 N/C Both Note 3 No connect
44 R0 Direct Input R counter bit 0
45 R1 Direct Input R counter bit 1
46 R2 Direct Input R counter bit 2
47 R3 Direct Input R counter bit 3
48 GND Both Ground
- All digital input pins have 70 k Ω pull-down resistors to ground
- No connect pins can be left open or floating
Table 2. Absolute Maximum Ratings Table 4. ESD Ratings exceeding the rating specified. devices are immune to latch-up. Table 3. Operating Ratings Table 5. DC Characteristics: VDD = 2.65 to 2.95V, -40°C < TA < 85°C, unless otherwise specified
Table 6. AC Characteristics: VDD = 2.65 to 2.95V, -40°C < TA < 85°C, unless otherwise specified Sclk rising edge to S_WR rising edge. S_WR falling edge to Sclk rising edge.
800 MHz ≤ Freq < 1200 MHz
1200 MHz ≤ Freq ≤ 5 GHz
1200 MHz ≤ Freq ≤ 4 GHz
Table 6. AC Characteristics: VDD = 2.65 to 2.95V, -40°C < TA < 85°C, unless otherwise specified (continued)
- CMOS logic levels can be used to drive the reference input. If the V DD of the CMOS driver matches the VDD of the PLL IC, then the reference input can be DC
- Parameter is guaranteed through characterization only and is not tested
- Parameters below are not tested for die sales. These parameters are verified during the element evaluation
- 0 dBm minimum is recommended for improved phase noise performance when sine-wave is applied
- +2 dBm or higher is recommended for improved phase noise performance
generates up and down frequency control signals. Figure 4. Functional Block Diagram
©2010-2013 Peregrine Semiconductor Corp. All rights reserved. Document No. DOC-15014-3 │ UltraCMOS® RFIC Solutions Main Counter Chain Normal Operating Mode The main counter chain divides the RF input frequency, Fin, by an integer derived from the user- defined values in the “M” and “A” counters. It is composed of the 5/6 or 10/11 selectable modulus prescaler, modulus select logic, and 9-bit M counter. The prescaler can be set to either 5/6 or 10/11 based on the Pre_5/6_SEL pin. Setting Pre_en “low” enables the 5/6 or 10/11 prescaler. Setting Pre_en “high” allows F in to bypass the prescaler and powers down the prescaler. The output from the main counter chain, fp, is related to the VCO frequency, Fin, by the following equation: where A M + 1, 1 ≤ M ≤ 511 Or fp = Fin / [5 x (M + 1) + A] where A M + 1, 1 ≤ M ≤ 511 When the loop is locked, Fin is related to the reference frequency, fr, by the following equation: where A M + 1, 1 ≤ M ≤ 511 Or Fin = [5 x (M + 1) + A] x [fr / (R + 1)] where A M + 1, 1 ≤ M ≤ 511 A consequence of the upper limit on A is that: in Integer-N mode, to obtain contiguous channels, Fin must be = 90 x [FR / (R + 1)] with 10/11 modulus Fin must be = 20 x [FR / (R + 1)] with 5/6 modulus The A counter can accept values as high as 15, but in typical operation it will cycle from 0 to 9 between increments in M. Programming the M counter with the minimum allowed value of “1” will result in a minimum M counter divide ration of “2”. Prescaler Bypass Mode Setting Pre_en “high” allows F in to bypass and power down the prescaler. In this mode, the 5/6 or 10/11 prescaler and A register are not active, and the input VCO frequency is divided by the M counter directly. The following equation relates F in to the reference frequency, fr: where 1 ≤ M ≤ 511 Reference Counter The reference counter chain divides the reference frequency, fr, down to the phase detector comparison frequency, fc. The output frequency of the 6-bit R counter is related to the reference frequency by the following equation: where 0 ≤ R ≤ 63 Note that programming R with “0” will pass the reference frequency, fr, directly to the phase detector.
Figure 5. Data is transferred to the counters as register on the rising edge of Sclk, MSB (B0) first. according to the timing diagram shown in Figure 5. enabled by asserting the ENH input “low”. shown in Table 7 and Table 8. Table 7. Primary Register Programming Table 8. Enhancement Register Programming
- Serial data clocked serially on Sclk rising edge while E_WR “high” and captured in the double buffer on E_WR falling edge.
Figure 5. Serial Interface Mode Timing Diagram The functions of the enhancement register bits are shown below with all bits active “high”. Table 9. Enhancement Register Bit Functionality
The phase detector is triggered by rising edges from the main Counter (fp) and the reference counter (fc). It has two outputs, namely PD_U, and PD_D . If the divided VCO leads the divided reference in phase or frequency (fp leads fc), PD_D pulses “low”. If the divided reference leads the divided VCO in phase or frequency (fr leads fp), PD_U pulses “low”. The width of either pulse is directly proportional to phase offset between the two input signals, fp and fc. The phase detector gain is 400 mV/radian. PD_U and PD_D are designed to drive an active loop filter which controls the VCO tune voltage. PD_U pulses result in an increase in VCO frequency and PD_D results in a decrease in VCO frequency. A lock detect output, LD is also provided, via the pin Cext. Cext is the logical “NAND” of PD_U and PD_D waveforms, which is driven through a series 2k ohm resistor. Connecting Cext to an external shunt capacitor provides integration. Cext also drives the input of an internal inverting comparator with an open drain output. Thus LD is an “AND” function of PD_U and PD_D. See Figure 4 for a functional block diagram of this circuit.
0.10 C A B
0.90 MAX
Figure 6. Package Drawing Figure 7. Top Marking Specifications
Table 10. Ordering Information Figure 8. Tape and Reel Drawing
- Camber in compliance with EIA 481
- Pocket position relative to sprocket hole measured as
specifications for product development. Specifications and features may change in any manner without notice. of this information. Use shall be entirely at the user’s own risk. No patent rights or licenses to any circuits described in this datasheet are implied or granted to any third party. are trademarks of Peregrine Semiconductor Corp. For sales and contact information please visit www.psemi.com.