PE29102 PSEMI | Alldatasheet

Document overview

  • Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
  • PDF pages: 16

Technical content

Features

  • High- and low-side FET drivers
  • Dead-time control
  • Fast propagation delay, 9 ns
  • Tri-state enable mode
  • Sub-nanosecond rise and fall time
  • 2A/4A peak source/sink current
  • Package – flip chip

Applications

  • Class D audio
  • DC–DCconversions
  • AC–DC conversions
  • Wireless charging
  • Envelope tracking
  • L i D A R Product Description The PE29102 is an integrated high-speed driver designed to control the gates of external power devices, such as enhancement mode gallium nitride (GaN) FETs. T he outputs of the PE29102 are capable of providing switching transition speeds in the sub-nanosecond range for switching applications up to 40 MHz. The PE29102 is optimized for matched dead time and offers best-in-class propagation delay to improve system bandwidth. High switching speeds result in smaller peripheral components and enable innovative designs for applications such as class D audio and wireless charging. T he PE29102 is available in a flip chip package. The PE29102 is manufactured on Peregrine’s UltraCMOS process, a patented advanced form of silicon-on- insulator (SOI) technology, offering the performance of GaAs with the economy and integration of conventional CMOS. Figure 1 • PE29102 Functional Diagram NOT RECOMMENDED FOR NEW DESIGNS

Page 2 of 16 DOC-81227-7 – (11/2018) www.psemi.com Absolute Maximum Ratings Exceeding absolute maximum ratings listed in Table 1 may cause permanent damage. Operation should be restricted to the limits in Table 2. Operation between operating range maximum and absolute maximum for extended periods may reduce reliability. ESD Precautions When handling this UltraCMOS device, observe the same precautions as with any other ESD-sensitive devices. Although this device contains circuitry to protect it from damage due to ESD, precautions should be taken to avoid exceeding the rating specified in Table 1. Latch-up Immunity Unlike conventional CMOS devices, UltraCMOS devices are immune to latch-up. Table 1 • Absolute Maximum Ratings for PE29102 Parameter/Condition Min Max Unit Low-side bias (LSB) to low-side source (LSS) –0.3 7 V High-side bias (HSB) to high-side source (HSS) –0.3 7 V Input signal –0.3 7 V HSS to LSS –100 100 V HSS to GND -1 100 V LSS to GND -1 100 V ESD voltage HBM(*), all pins 500 V Note: * Human body model (JEDEC JS–001, Table 2A). NOT RECOMMENDED FOR NEW DESIGNS

DOC-81227-7 – (11/2018) Page 3 of 16 www.psemi.com PE29102 High-speed FET Driver Recommended Operating Conditions Table 2 lists the recommended operating conditions for the PE29102. Devices should not be operated outside the recommended operating conditions listed below. Table 2 • Recommended Operating Conditions for PE29102 Parameter Min Typ Max Unit Supply for driver front-end, VDD 4.0 5.0 6.0 V Supply for high-side driver, HSB 4.0 5.0 6.0 V Supply for low-side driver, LSB 4.0 5.0 6.0 V HIGH level input voltage, VIH 1.6 6.0 V LOW level input voltage, VIL 0 0.6 V HSS range 0 60 V LSS range 0 60 V Operating temperature –40 +105 °C Junction temperature –40 +125 °C NOT RECOMMENDED FOR NEW DESIGNS

Page 4 of 16 DOC-81227-7 – (11/2018) www.psemi.com Electrical Specifications Table 3 provides the key electrical specifications @ +25 °C, V DD = 5V, 100 pF load, HSB and LSB bootstrap diode included unless otherwise specified. Table 3 • DC Characteristics Parameter Condition Min Typ Max Unit DC Characteristics VDD quiescent current VDD = 5V 1.3 mA HSB quiescent current VDD = 5V 2.7 mA LSB quiescent current VDD = 5V 2.7 mA Total quiescent current VDD = 5V 6.7 9.0 mA VDD quiescent current VDD = 6V 1.6 mA HSB quiescent current VDD = 6V 3.6 mA LSB quiescent current VDD = 6V 3.6 mA Total quiescent current VDD = 6V 9.0 11.6 mA Under Voltage Lockout Under voltage release (rising) 3.6 3.8 V Under voltage hysteresis 400 mV Gate Drivers HSGPU/LSGPU pull-up resistance 1.9 Ω HSGPD/LSGPD pull-down resistance 1.3 Ω HSGPU/LSGPU leakage current HSB–HSG PU = 5V, LSB–LSGPU = 5V 10 µA HSGPD/LSGPD leakage current HSG PD–HSS = 5V, LSGPD–LSS = 5V 10 µA Dead-time Control Dead-time control voltages 80 kΩ resistor to GND 1.3 V Dead-time from HSG going low to LSG going high RDHL = 30 kΩ 1.9 ns RDHL = 80.6 kΩ 7.0 ns RDHL = 150 kΩ 13.6 ns RDHL = 255 kΩ 23.5 ns Dead-time from LSG going low to HSG going high RDLH = 30 kΩ 1.8 ns RDLH = 80.6 kΩ 6.7 ns RDLH = 150 kΩ 13.2 ns RDLH = 255 kΩ 22.7 ns Switching Characteristics LSG turn-off propagation delay At min dead time 9.1 ns HSG rise time 10 - 90% with 100pF load 0.9 ns LSG rise time 10 - 90% with 100pF load 0.9 ns HSG fall time 90 - 10% with 100pF load 0.8 ns LSG fall time 90 - 10% with 100pF load 0.9 ns NOT RECOMMENDED FOR NEW DESIGNS

DOC-81227-7 – (11/2018) Page 5 of 16 www.psemi.com PE29102 High-speed FET Driver Control Logic Table 4 provides the control logic truth table for the PE29102. Minimum output pulse width 2.8 5.0 ns Max switching frequency @ 50% duty cycle RDHL = RDLH = 80 kΩ 40 MHz Table 3 • DC Characteristics (Cont.) Parameter Condition Min Typ Max Unit Table 4 • Truth Table for PE29102 EN IN HSGPU–HSS HSGPD–HSS LSGPU–LSS LSGPD–LSS L L Hi–Z L H Hi–Z L H H Hi–Z Hi–Z L H L Hi–Z L Hi–Z L H H Hi–Z L Hi–Z L NOT RECOMMENDED FOR NEW DESIGNS

DOC-81227-7 – (11/2018) Page 9 of 16 www.psemi.com PE29102 High-speed FET Driver Theory of Operation General The PE29102 is intended to drive both the high-side (HS) and the low-side (LS) gates of external power FETs, such as enhancement mode GaN FETs, for power man agement applications. The PE29102 is suited for applica- tions requiring higher switching speeds due to the reduced parasitic properties of the high resistivity insulating substrate inherent with Peregrine’s UltraCMOS process. The driver uses a single-ended pulse width modulation (PWM) input that feeds a dead-time controller, capable of generating a small and accurate dead-time. The dead-time circuit prevents shoot-through current in the output stage. The propagation delay of the dead-time controller must be small to meet the fast switching require- ments when driving GaN FETs. The differential outputs of the dead-time controller are then level-shifted from a low-voltage domain to a high-voltage domain required by the output drivers. Each of the output drivers includes two separate pull-up and pull-down outputs allowing independent control of the turn-on and turn-off gate loop resistance. The low imped ance output of the drivers improves external power FETs switching speed and efficiency, and minimizes the effects of the voltage rise time (dv/dt) transients. Under-voltage Lockout An internal under-voltage lockout (UVLO) feature prevents the PE29102 from powering up before input voltage rises above the UVLO threshold of 3.6V (typ), and 400 mV (typ) of hysteresis is built in to prevent false triggering of the UVLO circuit. T he UVLO must be cleared and the EN pin must be released before the part will be enabled. Dead-time Adjustment The PE29102 features a dead-time adjustment that allows t he user to control the timing of the LS and HS gates to eliminate any large shoot-through currents, which could dramatically reduce the efficiency of the circuit and potentially damage the GaN FETs. Two external resist ors control the timing of outputs in the dead-time controller block. The timing waveforms are illustrated in Figure 6 . The dead-time resistors only affect the rising edge of th e low-side gate (LSG) and high-side gate (HSG) outputs. Dead-time resistor RDLH will delay the rising edge of HS G, thus providing the desired dead-time between LSG falling and HSG rising. Likewise, dead-time resistor RDHL will delay the rising edge of LSG, thus providing the desired dead-time between HSG falling and LSG rising. Figure 7 shows the resulting dead-time versus the external resistor values with both HS and LS bias diode/capacitors installed as indicated in Figure 5 . The LS bias diode and capacitor are included for symmetry only and are not required for the part to function. Removing the LS bias diode will increase the LSG voltage by approximately 0.3V, resulting in a wider separation of the t DHL and tDLH curves in Figure 7 . Phase Control Pin 10 (PHCTL) controls the polarity of the gate driver outputs. When PHCTL is low, the HSG will be in phase with the input signal. When PHCTL is high, the LSG w ill be in phase with the input signal. The PHCTL pin includes an internal pull-down resistor and can be left floating. NOT RECOMMENDED FOR NEW DESIGNS

Page 12 of 16 DOC-81227-7 – (11/2018) www.psemi.com Evaluation Board The PE29102 evaluation board (EVB) allows the user to evaluate the PE29102 gate driver in either a full-bridge configuration or two independent half-bridge configurat ions. The EVB is assembled with two PE29102 FET drivers and four GS61004B E-mode GaN FETs. Refer to Peregrine Semiconductor DOC-82956 for more infor- mation. Because the PE29102 is capable of generating fast switchin g speeds, the printed circuit board (PCB) layout is a critical component of the design. The layout should o ccupy a small area with the power FETs and external bypass capacitors placed as close as possible to the driver to reduce any resonances associated with the gate loops, common source and power loop inductances. Sinc e the maximum allowable gate-to-source voltage for the GS61004B FETs is 7V, resonance in the gate loops can generate ringing that can degrade the performance and potentially damage the power devices due to high voltage spikes. Additionally, it is important to keep ground paths short. The PCB is fabricated on FR4 material, with a total thi ckness of 0.062 inches. A minimum copper thickness of 1.5 ounces or more is recommended on the PCB outer layers to limit resistive losses and improve thermal spreading. Figure 9 • PE29102 Evaluation Board Assembly NOT RECOMMENDED FOR NEW DESIGNS

DOC-81227-7 – (11/2018) Page 13 of 16 www.psemi.com PE29102 High-speed FET Driver Pin Configuration This section provides pin information for the PE29102. Figure 10 shows the pin map of this device for the available package. Table 5 provides a description for each pin. Figure 10 • Pin Configuration (Top View–Bumps Down) 1640 µm (−20 / +30 µm) 2040 µm (−20 / +30 µm) HSSHSBNCRDLH IN GND RDHL V DD LSB LSS LSGPD HSGPUEN PHCTL HSGPD 1213141516 5432 LSGPU Table 5 • Pin Descriptions for PE29102 Pin No. Pin Name Description

1 HSGPD High-side gate drive pull-down

2 HSS High-side source

3 HSB High-side bias

4 NC No connection (ground or float)

5 RDLH

Dead-time control resistor sets LSG falling to HSG rising delay (external resistor to GND)

6 HSG

PU High-side gate drive pull-up 7(*) EN Enable active low, tri-state outputs when high 8(*) IN Control input

9 LSGPU Low-side gate drive pull-up

10(*) PHCTL Controls the polarity of the gate driver outputs

11 GND Ground

12 LSGPD Low-side gate drive pull-down

13 LSS Low-side source

14 LSB Low-side bias

15 VDD +5V supply voltage

16 RDHL

Dead-time control resistor sets HSG falling to LSG rising delay (external resistor to ground) Note: * Internal 100k pull down resistor NOT RECOMMENDED FOR NEW DESIGNS

Page 14 of 16 DOC-81227-7 – (11/2018) www.psemi.com Die Mechanical Specifications This section provides the die mechanical specifications for the PE29102. Table 6 • Die Mechanical Specifications for PE29102 Parameter Min Typ Max Unit Test Condition Die size, singulated (x,y) 2040 × 1640 µm Including sapphire, max tolerance = –20/+30 Wafer thickness 180 200 220 µm Wafer size µm Bump pitch 400 µm Bump height 85 µm Bump diameter 110 µm max tolerance = ±17 Figure 11 • Recommended Land Pattern for PE29102 BUMPS DOWN SIDE VIEW BUMPS UP 2.040+0.03 -0.02 1.640+0.03 -0.02 0.22 (x14) 0.40 0.085±0.013 RECOMMENDED LAND PATTERN 0.40 0.20±0.02 Ø0.090±0.008 (x16)Ø0.110±0.017 (x16) NOT RECOMMENDED FOR NEW DESIGNS

DOC-81227-7 – (11/2018) Page 15 of 16 www.psemi.com PE29102 High-speed FET Driver Tape and Reel Specification This section provides tape-and-reel information for the PE29102. Figure 12 • Tape and Reel Specifications for PE29102. Device Orientation in Tape Pin 1 Notes: 1. 10 sprocket hole pitch cumulative tolerance ±0.2. 2. Camber in compliance with EIA 481. 3. Pocket position relative to sprocket hole measured as true position of pocket, not pocket hole. Direction of Feed Bo Ao T D0D1 WoFE A A Ko SEE NOTE 3 SEE NOTE 3 SEE NOTE 1 Pocket Nominal Tolerance Ao 1.9 +/- 0.05 Bo 2.3 +/- 0.05 Ko 0.4 +/- 0.05 P1 4.0 +/- 0.1 Wo 8.0 +0.3 / -0.1 F 3.5 +/- 0.05 D1 0.5 +/- 0.05 D0 1.5 + 0.1 / - 0 E1 . 8 + / - 0 . 1 P0 4.0 +/- 0.1 P2 2.0 +/- 0.05 T 0.2 +/- 0.05 NOT RECOMMENDED FOR NEW DESIGNS

Product Specification www.psemi.com DOC-81227-7 – (11/2018) Document Categories Advance Information The product is in a formative or design st age. The datasheet contains design target specifications for pr oduct development. Spe cifications and features may change in any manner without notice. Preliminary Specification The datasheet contains preliminar y data. Additional data may be added at a later date. pSemi reserves the right to change speci fications at any time without notice in order to supply the best possible product. Product Specification The datasheet contains final data. In the event pSemi decides to change the specifications, pSemi will notify customers of the intended changes by issuing a CNF (Customer Notification Form). Sales Contact For additional information, contact Sales at sales@psemi.com. Disclaimers The information in this document is believed to be reliable. Ho wever, pSemi assumes no liability for the use of this informatio n. Use shall be entirely at the user’s own risk. No patent rights or licenses to any circui ts described in this document ar e implied or granted to any t hird party. pSemi’s products are not designed or intended for use in devices or syst ems intended for surgical implant, or in other applications intended to support or sustain life, or in any application in which the failure of t he pSemi product could create a si tuation in which personal injury or death might occur. pSemi assumes no liability for damages, including consequential or incidental damages, arising out of the use of its products in such applications. Patent Statement pSemi products are protected under one or more of the following U.S. patents: patents.psemi.com Copyright and Trademark ©2018, pSemi Corporation. All rights reserved. The Peregrine Se miconductor name, Peregrine Semi conductor logo and UltraCMOS are registered trademarks and the pSemi name, pSemi logo, HaRP and DuNE are tr ademarks of pSemi Corporation in the U.S. and other countries. High-speed FET Driver

Ordering Information

Table 7 lists the available ordering code for the PE29102. Table 7 • Order Code for PE29102 Order Codes Description Packaging Shipping Method PE29102A-X PE29102 flip chip Die on tape and reel 500 units/T&R PE29102A-Z PE29102 flip chip Die on tape and reel 3000 units/T&R NOT RECOMMENDED FOR NEW DESIGNS