PDI1284P11 NEXPERIA | Alldatasheet
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Technical content
Datasheet sections
- 3.3 V parallel interface transceiver/buffer
3.3 V parallel interface transceiver/buffer
designed for hosts or peripherals operating at 3.3 V to interface 3.3 V or 5.0 V devices. from the B-bus to the A-bus, depending on the state of the direction pin DIR. are TTL compatible with at least 400 mV of input hysteresis at VCC = 3.3 V.
- Asynchronous operation
- 8-bit transceivers
- Six additional buffer/driver lines peripheral to cable
- Five additional control lines from cable
- 5 V tolerant
- ESD protection:
- HBM JESD22-A114E exceeds 2000 V
- MM JESD22-A115-A exceeds 200 V
- Latch-up current protection exceeds 500 mA per JEDEC Std 19
- Input hysteresis
- Low-noise operation
- IEEE 1284 compliant level 1 and 2
- Overvoltage protection on B/Y side for off-state
- A side 3-state option
- B side active or resistive pull-up option
- Cable side supply voltage for 5 V or 3 V operation 3. Ordering information
Table 1. Ordering information
- Functional diagram 001aai290 CNTLHD DIR OEAHD HD PLHI PLHO A14 C14 HD A10 Y10HD A11 Y11HD A12 Y12HD A13 Y13 HD HD CNTL A2 B2 HD CNTL A3 B3 HD CNTL A4 B4 HD CNTL A5 B5 HD CNTL A6 B6 HD CNTL A7 B7 HD CNTL A15 C15 A16 C16 A17 C17 HLHO HLHI A8 B8 HD CNTL Fig. 1. Logic symbol PDI1284P11 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 4 — 6 July 2021 2 / 14
Table 2. Pin description
[1] Pin with pull-up resistor to load cable. Table 3. Function table [1] signal on the A side, that particular B/Y side resistor is switched off to stop current drain from VCC through it.
Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
- Recommended operating conditions
Table 5. Operating conditions
Table 6. Static characteristics Tamb = 0 °C to 70 °C; ground = 0 V; unless specified otherwise. [1] Typical values at Tamb = 25 °C. [2] Includes extra ICC(B) current from pull-up resistors, i.e. ICC(B) = (total number of LOW inputs on B and C sides) × (VCC(B) / RPU).
Table 7. Dynamic characteristics VCC = 3.0 V to 3.6 V; ground = 0 V; CL = 50 pF; RL = 500 Ω; Tamb = 0 °C to 70 °C; unless specified otherwise. [1] Value at Tamb = 25 °C and VCC = 3.3 V. [2] tpd is the same as tPLH and tPHL. [3] tdis is the same as tPHZ and tPLZ. [4] ten is the same as tPZH and tPZL.
VOL and VOH are the typical voltage output levels that occur with the output load. Measurement data is given in Table 8. SR is measured for both a LOW-to-HIGH and a HIGH-to-LOW transition. Table 8. Slew rate measurements
Test circuit is shown in Fig. 7. Measurement points are given in Table 9. VOL and VOH are the typical voltage output levels that occur with the output load. Test conditions are given in Table 9. Table 9. Test data for test circuit measuring enable disable times Bn to An
CL = load capacitance includes jig and probe capacitance. RT = termination resistance should be equal to the output impedance of the pulse generator. Table 10. Test conditions for An, Bn and Yn outputs IO is measured by forcing 0.5VCC on the output. The output impedance can then be calculated as Ro = 0.5VCC / |IO|.
- Package outline ReferencesOutline version European projection Issue date IEC JEDEC JEITA SOT362-1 MO-153 sot362-1_po 03-02-19 13-08-05 Unit mm max nom min 0.15 0.28 0.2 12.6 0.5 0.8 A Dimensions (mm are the original dimensions) Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm SOT362-1 A1 A2 1.05 A3 bp c D(1) θE(2) e HE L Lp Q v w y Z 8.3 0.86.2 0.50 pin 1 index v A θ A D Lp Q E Z c L 1 24 48 25 e w y X A HE bp detail X (A3) 0 5 mm scale 2.5 Fig. 10. Package outline SOT362-1 (TSSOP48) PDI1284P11 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 4 — 6 July 2021 11 / 14
Table 11. Abbreviations Table 12. Revision history
- Legal texts have been adapted to the new company name where appropriate.
- Type number PDI1284P11DL (SOT370-1 / SSOP48) removed.
- Section 7: Derating values for Ptot total power dissipation removed.
- Fig. 10: Package outline drawing SOT362-1 (TSSOP48) updated. PDI1284P11_3 20080825 Product data sheet - PDI1284P11_2 Modifications: • The format of this data sheet has been redesigned to comply with the new identityguidelines of NXP Semiconductors.
- Legal texts have been adapted to the new company name where appropriate.
- Quick reference table removed.
- Table 7, tPHL: Maximum value of 20 ns replaced by 23 ns.
- Table 11: Abbreviations list added. PDI1284P11_2 19990917 Product specification - PDI1284P11_1 PDI1284P11_1 19970915 Product specification - - PDI1284P11 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 4 — 6 July 2021 12 / 14
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Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. PDI1284P11 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 4 — 6 July 2021 13 / 14