PD1165 SIEMENS | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 8
Technical content
SIEMENS AKTIENGESELLSCHAF 47E D MM 8235605 0027031 b MBSIEG THIS7 SIEMENS HIGH EFFICIENCY RED PD1165 VERY BRIGHT GREEN PD 1167 1.16” Square 8 x 8 Dot Matrix Programmable Display™ Module With On Board Drivers, Built-in RAM and Software Controllable Features Package Dimensions in Inches (mm) y =o ‘elelezeretezeze) se { bese bt eleteteeletere) A gg a | SHEFF Set 0090500 oe Um UCU oe SEE Pn ae | POQDOSSG| 4B ee A eve = MSF | POOQGOOD Ff oo eee " il Pia Vest: ae Re ante ‘ ™ wv ‘ Tong nor id, See alles eS Ye Re . . . id | wt = METRE Tolerance + 010 (25) 2 HEAT Sam, : “ ay S01 9 FEATURES DESCRIPTION * Active Display Size 1.16” Square The high efficiency red PD 1165 and very bright green © 0.11” Diam. Dots on 0.15" Centers PD 1167 are modular 8x8 dot matrix Programmable Displays. They are constructed with highly efficient III/V * Very Bright Green or High Efficiency Red maternal LEDs, packaged in a reflector package for max- © Intensity Matched and Binned imum dot illumination. Further optimizing light output are © Readable from 35 Feet . builtin CMOS drive circuits. These circuits strobe the LEDs . at peak currents that give the best time averaged luminous Viewing Angle +75° intensity for the power required. The user has complete con * Interlocking X-Y Stackable Packages for Larger trol of the display through further built-in CMOS circuttry. Displays The display appearance can be set by programming an « On board CMOS Circuits with Complete Drive 8 bit RAM. Circults and Logic Interfaces Features such as blinking, synchronizing, blanking, one of * Each Dot Addressable Over TTL Compatible, 8 Bit nine intensity levels or lamp tests are easily programmed BUS through a control word. Additional external connections are * Alternate Language & Graphics Programmi available for clock inputs, clock outputs and total intensity ii nguege rap roa ied contro! through an externai resistor. Capability * Cascadable-Synchronizable Logic for Expanded All products are 100% bured-in and tested, then sub- Display Systems jected to out-going AQL's of 25% for brightness matching, * Software Controlled Attributes: visual alignment and dimensions, .065% for electrical and
9 Levels of Intensity Settings functional,
Memory Clear . The display is constructed of epoxy filled polycarbonate with Blanking o oun two interconnected pebs A heat sink is attached to coo! the ullt-in Lamp Test device with its 20 pin dip lead construction. The package is * 100% Burned in Prior to Final Test wave solderable and has been fully qualified for operation © 20 Pin DIP Package: 0.6” Wide Rows, 0.1” Pin and storage over a temperature range from ~20°C to +70°C. Spacing * Wave Solderable * -20°C to +70°C Operating Range 2-146
STEMENS AKTIENGESELLSCHAF 4?7E D MM 8235605 0027032 8 MBESIEG T-41-37 Maximum Ratings Optical Characteristics @25°C Vin, Input Voltage Levels Relative (Green) 565 nm typ. Storage Temperature —20°C to +70°C Active Display Size oe woe 1.16" square « Relative Humidity (non condensing) @65°C 90% DotSze . .. fee eee ee O11" diam, B Ta= -20°C. . oe 1.6W Time Averaged Luminous intensity bad Zz @70°C (8j,=25°CM) . Lo. . 95°C 17 modidot typ below the Seating Plane, t<5 sec . 260°C _Display Average Intensity Matching Recommended Operating Conditions - 20°C to +70°C Bin to Bin Matching Ratio [ Parameter Tin. [Wom. TWax. [Unite] (@ccent bn) 19:1 Omax Vee. Supply vag Vw inputVotage High [27 | [|v | Vi lput Vorage tow |_| 0a | v_| Cosk Fan Out [Te Tis [os] Note 1 The number of displays that can be synchronized by one “master” display clock depends on how ‘clean’ the line 1s The maximum can only be achieved in very ‘clean’ electncal environments A buffer 1s required for larger systems or noisy environments DC CHARACTERISTICS log Blank 3.0 20 | 3.0 10 | 20 | mA | WR=Voc=5.0V Vin=08V olan ——| is [wo] pao pve |_| os |e [ma [voonsov loc 64 dots on at full 205 A . intensity. 2) 235 | 265 230 185 mA | Voo=50V fue Pee To Peo Pe a6 Toa [vco=s ov [wos TO os os Pv fas vveosasv Notes 1, Average LED dive current is 3 mA Peak current at 1% duty cycle '8 typically 25 mA 2. RDIM can be used to reduce Igc and subsequently lower the nominal display intensity level See figure (2) for typroal brightness reductions with the use of Ret PO 1165 2-147
SIEMENS AKTIENGESELLSCHAF 4?E D MM 8235605 0027033 T MMSIEG T-4l -37 WRITE CYCLE RESET TIMING RST i Ta TREW: . v0-07 {| Y Tas: Tou: oR POWER ON TO FIRST WRITE TIMING Tees -—Tww: Vee wy, Teen Twew WR Ano CE DATA BUS TRANSITIONS AT CL = 150 pF TIMING MEASUREMENT LEVELS. 90% 10-07 soy 50V 25V I t oov AC CHARACTERISTICS Over Operating Temperature Range at Voc =45 V [Parameter Symbol | —-20°C (tun) [+ 5°C tun) [470°C (oan) [Unita] nacre Set Up Tre | tg 10 | 0 0 [ee use wah [Tw 20 0 0 Data Set Up Time a [ono enete aa tine [Tose [ef 0] oo nacress Had Time | tay [ 8 | [aso tre | toe 0 [eset use wat | taaw [0 0 | > ro] Minimum Time Between - Twew 2 ms Power Up and the First Write Operation Total Wnte Time Twa 35 45 (Tas +Tww +ToH) Notes 1 50 ys or 2 clock cycies minimum The intemal clock frequency 1s between 60 and 80 KHz. If an external clock 1s supped, # should be held between 60 and 60 kHz
2 Tww must be less than Tos
STEMENS AKTIENGESELLSCHAF 4?E D MM 8235605 0027034 1 M@MSIEG T-41-37 TOP VIEW : PIN DEFINITIONS Pin rw ~~ fwz0 1. BST Resets the System Active low. SSSCOSSO 2. CLKoyr Clock output for daisy chaining 8 200 0g 3. WR Writes data into the display. Active low. Be como, [ooo 9 4, CE Chip Enable. Active low. Ze 80 900) 5. AO Address Input (LSB) = So000005 6 AL Address Input s < NN 7 he Address Input (MSB) aw. pw it 8. A3 Address Input for control words. 9. CLKiy Clock Input for daisy chaining
10 Rom Controls Brightness through Rexr
- Voc Plus 5 volts power pin 12. DO Data Bus Bit 0 (LSB) 13. Dt Data Bus Bit 1 PD 1165, PD 1167 PINOUT 14, D2 Data Bus Bit 2 1 FST 20 GND 15. 03 Data Bus Bit 3 2 CLKOUT 49 07 16. D4 Data Bus Bit 4 3 WR 18 D6 17. 08 Data Bus Bit 5 4 CE 17° D5 18. D6 Data Bus Bit 6
5 AO 16 D4 19 O07 Data Bus Bit 7 (MSB)
6 AT 15 D3 20. GND Ground
7 A2 14 D2
8 AB 13° DI
9 CLKIN 12 DO FUNCTIONAL DESCRIPTION
to ROM i Veo The PD 1165 (PD 1167) block diagram includes the mayor blocks and internal registers. Display Memory consists of a 8x8 bit RAM block for the display columns and rows. Each one of the eight bit corres- pond to a LED and each eight bit cluster corresponds to a column It also contains a 1x8 bit block to serve as Control PD 1165 (PD 1167) BLOCK DIAGRAM Word Register The Input Logic consists of Data Buffers, Control Logic and tata 4, Address Decode Logic. A00RESS Damped NUT | et The Oscillator (OSC) Logic generates clock for internal courao, Sy and external use Reset function is a part of this block. The Multiplex Logic generates multiplex scheme for A column and row drivers, intensity control and blinking. The Row Drivers drive 8 rows of eight LEDs each. The row oan drive currents could be trimmed using an external resistor x ware of, ] (Row) to set the nominal display brightness, The Column Drivers drive 8 columns of eight LEDs each ‘ The Display consists of 64 LEDs connected in clusters of 8 to form columns and rows. PD 165 2-149
- Float (tr-state) all display puts. 1 3 ¢ tee
- Apply Vcc and GND to the display. 0 1 1 0 Seventh Column
- Activate inputs as required enabling the display (Observe r 1 1 1 | Eighth Column
- Float (tr-state) all active input signals to the display. When the appropriate column is addressed, a specific LED
- Turn off power to the display. can be “written” on or off by identifying the appropriate row.
SIGNAL CONDITIONING/INPUT BUFFERING remain untl rewritten or cleared. microprocessor and displays, the inputs should be buffered CONTROL WORD OPERATION . 8035) will require the pulse from the microprocessor to be ireemented in the Paloma mannet. FIGURE 1. WRITE DELAY CIRCUIT FOR ,.P's THAT possible. Note 2 O=Low 1=High, X=Dont Care, $=appropnate intensity code.
STEMENS AKTIENGESELLSCHAF 4?E D MM 8235605 0027036 S MBSIEG These intensity levels are proportional to the total display Lamp Test D6, D2, D1, DO T-41-37 brightness. Each device 1s intensity categorized, however, The lamp test is only functional with the intensity level set to this maximum brightness category can be lowered through 50%. This does not affect display RAM. an external resistor See figure (2) for the characteristic - relationship of intensity to Rext. A 4K resistor would be D7 08 D5 D4 03 D2 Di Do equivalent to one intensity category shit. 0 1 X X 0 © 1 14 | Tunall LEDs on at 50% brightness g Fi Memory Clear D7, D6 EE sure 2, Luminous Intensity VS. Bom [Or Os G5 54 G5 G2 DF DOT Operon] | | BB 0 1 0 xX X X $ $_ § | Clear Display RAM, Ss | | \\- turn off LEDs TT | Reset Timing D7, D6 ea gael Timing reset is necessary for synchronizing display blinking for multiple display systems. It has no effect on display 5 4 RAM E j 07 D6 BS D4 3 D2 bi DO] Operation] Z z 24 A / DESIGN CONSIDERATIONS / MULTIPLE DISPLAY SYSTEMS
2 The PD 1165 (PD 1167) parts may be cascaded for flat panel
/ displays of any size. If blinking 1s to be used, up to 15 displays can be synchronized to one “master” display clock j as descnibed earlier. Additional displays will require a buffer rr to drive the clock load. Rom -K The connection scheme is straight forward as illustrated in figure (3) below.
1 Buss together: Data lines, Address lines, Write Enable
lines, Reset lines, Voc (with proper capacitors for power Display Blank (D3): The D3 bit will visually clear the supply conditioning) and GND lines. display, biank it, without affecting the display RAM LED 2. Terminate the Data, Address and Write lines of the pattern.) “master” display to the microprocessor interface 3. Terminate the CE lines of the “slave” displays to the [o x x x 4 $$ S[k |], appropiate mercprocessoy acres decoders Nao) winosgha ena Sea ha iopay Gan ba Gnneay 4 Connect the clock out (pin 2) of the “master” display to (ole 1 Although it 1s not recommended, the display can be dim “slave” strobing the blank instruction on and off If this is done, frequen- the buffer forior clock in (pin 9), of the “slave” displays. es of 1 KHz or more should be utized to avoid fickenng This flat panel sub assembly can then be interfaced easily Clock Select (D4): The appropriate clock selection should with microprocessors, such as the 8035, as illustrated in be included in the control word. For multiple display igure (4) : systems, external synchronized clocks should be used when For systems with synchronized blinking, an initializing control . blinking 1s required for uniform display appearance. One softword reset should precede the instructions for clearing, display can act as a master clock for up to 15 other displays brightness, clock selection, etc. Provided the D4 bit 1s properly set. INTENSITY MATCHING x X X 0 X $ $$ | Internal Clock For best matching, displays from one bin should be used. It xX X X 1 =X $ $$ | External Clock is often acceptable, under normal viewing conditions, to use displays from two neighboring bins. The RDIM connection allows users to set intensity levels to match displays of all Blink Control DS intensity levels. PO 1165 2-151
sonnel, tools, tables, and transport carriers that come in and |sopropyl Alcohol. solder using a grounded iron set to 260°C Blakeslee, Chicago, IL; Dow Chemical, Midland, MI; El. Wave soldering 1s also possible following these conditions. DuPont de Nemours & Co., Wilmington, DE. the PC board or a package surface temperature of 70°C. current Siemens Optoelectronic Data Book. POST SOLDER CLEANING PROCEDURES Hardware, New Albany, IN. acceptable. Do not use commercial dishwasher detergents. FIGURE 3. GENERAL INTERFACE CIRCUIT
SIEMENS AKTIENGESELLSCHAF 47E D @@ 86235605 0027038 9 MBSIEG . FIGURE 4. MICROPROCESSOR INTERFACE CIRCUIT T-41-37 ths omy ooniat ovie EE so RI ane 4 _ a ao &* OQ . wo 0 9 . z 4 eS 2 rs Me Fy ie Fi {io | § Fy | H vst} Lu ‘ jd 8 wl! = ee TT 2 er bs 7 008 as 7 oy cael 7 el So So st Wiadace + eh ——fe tee hs OS = 8 403 lo $ cope t Poo 3 1) coos soe OS os on ed eee ee ES ee
2 EER eee =
EIU] oe arn 8 coo = ET co; eo . : HHH? Ef: Het ES oo me mos eos Hy + EF} OPTICAL CONSIDERATIONS Optimal filter enhancements for any condition can be . gained through the use of circular polanzed, anti-reflective, The 1.19” high character of the PD 1165 (PD 1167) allows band-pass fiers. The circular polanzing further enhances readability up to 36 feet. Froper fier gelection will alow the contrast by reducing the light that travels through the filter user to bud a display that can be utiized over this distance. : and reflects back off the display to less than 19. . Filters enhance the contrast ratio between a lit LED and the P
4 Several fiter manufacturers supply quality filter materials,
Character background. The only limitation 's cost, The Some of them are: Panelgraphic Corporation, W. Caldwell, cost/benefit ratio for filters can be maximized by first con- Nu: SGL Homelite, Wilmington, DE; 3M Company, Visual sidenng the ambient lighting environment Products Division, St. Paul, MN; Polaroid Corporation Incandescent (with almost no green) or fluorescent (with Polarizer Division, Cambndge, MA; Marks Polarized Corp- almost no red) lights do not have the flat spectral response _—_oration, Deer Park, NY; Hoya Optics, Inc., Fremont, CA. of sunlight. Plastic band-pass filters are inexpensive and One final note on mounting filters. Recessing display and etfectve n optimizing contrast ratios. The PD 1165 is ahigh (he inal note on mounting Tfers Reoessing cisplay efficiency red display and should be matched with a long shading effect in’ overhead lighting situations. Several Bezel wavelength pass filer in the 570 nm to 590 nm range. The manufacturers are: R.M.F. Products, Batavia, IL; Nobex PD 1167 should be matched with a yellow-green band:ase Components, Griffith Plastic Corp., Burlingame, CA; Photo filter that peaks at 565 nm. For display systems of multiple Chemical Products of California, Santa Monica, CA: |.E.E- colors (using other Siemens displays), neutral density grey re ee ee . CA: | filters offer the best compromise. * ¥ . Additional contrast enhancement can be gained through Refer to Siemens Appnote 23 for further mformation. shading the displays. Plastic band-pass filers with builtin REPLACEMENT louvers offer the “next step up” in contrast improvement Also, plastic fiers can be further improved with ant Should a display nested within a panel be damaged, reflective coatings to reduce glare, The trade-off 1s “fuzzy” replacement can be made by trimming the tabs off the characters. Mounting the fiters close to the display reduces neighboring displays adjacent to the damaged displays this effect. Care should be taken not to overheat the plastic «Row # 0 and Column # 0 (typically above and to the lett) filters by allowing for proper air flow. Once the interlocking tabs are trimmed (using a razor blade- type cut), the damaged device may be removed and replaced - ord 2-153