Microcontroller

PC8260

ATMEL Corporation

The PC8260 PowerQUICC II™ is a versatile communications processor that integrates on one chip, a high-performance PowerPC (PC603e) RISC microprocessor, a highly flexible system integration…

Manufacturer: ATMEL Corporation

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PC8260 ATMEL | Alldatasheet

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Features

PC603e™ Microprocessor(EmbeddedPowerPC™ Core)at100-200MHz – 140MIPSat100MHz(Dhrystone2.1) – 280MIPSat200MHz(Dhrystone2.1) – High-performance,SuperscalarMicroprocessor – DisableCPUMode – ImprovedLow-powerCore – 16-KbyteDataand16-KbyteInstructionCache,Four-waySetAssociative – MemoryManagementUnit – NoFloatingPointUnit – CommonOn-chipProcessor(COP)
SystemIntegrationUnit(SIU) – MemoryController,IncludingTwoDedicatedSDRAMMachines – PCIupto66MHz(AvailableinSubsequentVersions) – HardwareBusMonitorandSoftwareWatchdogTimer – IEEE1149.1JTAGTestAccessPort
High-performanceCommunicationsProcessorModule(CPM)withOperating Frequencyupto166MHz – PowerPCandCPMMayRunatDifferentFrequencies – SupportsSerialBitRatesupto710Mbpsat133MHz – ParallelI/ORegisters – On-board24KBytesofDual-portRAM – TwoMulti-channelControllers(MCCs)EachSupporting128Full-duplex,64-Kbps, HDLCLines – VirtualDMAFunctionality
TwoBusArchitectures:One64-bitPowerPCandOne32-bitLocalBus(orPCIon PC8265)
TwoUTOPIALevel-2Master/SlavePorts,BothwithMulti-PHYSupport.OneCan Support8/16bitData
ThreeMILInterfaces
EightTDMInterfaces(T1/E1),TwoTDMPortsCanBeGluelesstoT3/E3
PowerConsumption:2.5Wat133MHz

Description

ThePC8260PowerQUICCII ™ isaversatilecommunicationsprocessorthatinte- gratesononechip,ahigh-performancePowerPC(PC603e)RISCmicroprocessor,a highlyflexiblesystemintegrationunit,a ndmanycommunicationsperipheralcontrol- lersthatcanbeusedinavarietyofapplications,particularlyincommunicationsand networkingsystems. ThecoreisanembeddedvariantofthePC603emicroprocessor,specificallyreferred tolaterinthisdocumentastheEC603e,with16Kbytesofinstructioncacheand16 Kbytesofdatacacheandnofloating-pointunit(FPU).Thesysteminterfaceunit(SIU) consistsofaflexiblememorycontrollerthatinterfacestoalmostanyuser-defined memorysystem,a60x-to-PCIbusbridge(availableinfuturerevisions)andmany otherperipherals,makingthisdeviceacompletesystemonachip. Thecommunicationsprocessormodule(CPM)includesalltheperipheralsfoundin thePC860,withtheadditionofthreehigh-performancecommunicationchannelsthat supportnewemergingprotocols(forexample,155-MbpsATMandFastEthernet). Equippedwithdedicatedhardware,t hePC8260canhandleupto256full-duplex, time-division,multiplexedlogicalchannels. PowerPC-based Communications Processors PC8260 PowerQUICCII™ Rev.2131B–HIREL–02/03

2 PC8260PowerQUICCII

2131B–HIREL–02/03 ScreeningQuality Packaging Thisproductismanufacturedinfullcompliancewith:

UpscreeningbaseduponAtmelstandards.
Fullmilitarytemperaturerange(T J=-55°C,TJ=+125°C)
Industrialtemperaturerange(T J=-40°C,TJ=+110°C)
Corepowersupply: 2.5V±5%(L-Specfor200MHz) 2.50Vto2.75V(R-Specfor250MHz)(tbc)
I/Opowersupply:3.0Vto3.6V
480-ballTapeBallGridArraypackage(TBGA37.5mmx37.5mm)

2131B–HIREL–02/03 PC8260Architecture GeneralOverview ThePC8260hastwoexternalbusestoaccommodatebandwidthrequirementsfromthe highspeedsystemcoreandtheveryfastcommunicationschannels.Thedeviceiscom- posedofthefollowingthreemajorfunctionalblocks:

A64-bitPowerPCcorederivedfromtheEC603ewithMMUsandcaches.
Asysteminterfaceunit(SIU).
Acommunicationsprocessormodule(CPM).BoththesystemcoreandtheCPM haveaninternalPLL,whichallowsindependentoptimizationofthefrequenciesat whichtheyrun.ThesystemcoreandCPMarebothconnectedtothe60xbus. Figure1.PC8260BlockDiagram MCC MCC FCC FCC FCC SCC SCC SCC SCC SMC SMC SPI Clock Counter Memory Controller Bus Interface Unit System Functions 60x-to-Local Bus Bridge 60x-to-PCI Bus Bridge (PC8265 only) I C2 PCI/ Local Bus Time Slot Assigner Serial Interface

8 TDMs

2 UTOPIA 3 Mlls Non-Multiplexed I/O

32-Bit RISC Communications Processor (CP) and Program ROM Serial DMAs

4 Virtual

4 PC8260PowerQUICCII

2131B–HIREL–02/03 EC603eCore TheEC603ecoreisderivedfromthePowerPC603emicroprocessorwithoutthefloat- ing-pointunitandwithpowermanagement modifications.Thecoreisahigh- performancelow-powerimplementationofthePowerPCfamilyofreducedinstruction setcomputer(RISC)microprocessors.TheEC603ecoreimplementsthe32-bitportion ofthePowerPCarchitecture,whichprovides32-biteffectiveaddresses,integerdata typesof8,16and32bits.TheEC603ecacheprovidessnoopingtoensuredatacoher- encywithothermasters.ThishelpsensurecoherencybetweentheCPMandsystem core. Thecoreincludes16Kbytesofinstructioncacheand16Kbytesofdatacache.Ithasa 64-bitsplit-transactionexternaldatabuswhichisconnecteddirectlytotheexternal PC8260pins. TheEC603ecorehasaninternalcommonon-chip(COP)debugprocessor.Thispro- cessorallowsaccesstointernalscanchainsfordebuggingpurposes.Itisalsousedas aserialconnectiontothecoreforemulatorsupport. TheEC603ecoreperformancefortheSPEC 95benchmarkforintegeroperations rangesbetween4.4and5.1at200MHz.InDhrystone2.1MIPS,theEC603eis280 MIPSat200MHz(comparedto86MIPSofthePC860at66MHz). TheEC603ecorecanbedisabled.Inthis mode,thePC8260functionsasaslave peripheraltoanexternalcoreortoanotherPC8260devicewithitscoreenabled.

2131B–HIREL–02/03 SystemInterfaceUnit (SIU) TheSIUconsistsofthefollowing:

A60x-compatibleparallelsystembusconfigurableto64-bitdatawidth.ThePC8260 supports64-,32-,16-,and8-bitportsizes.ThePC8260internalarbiterarbitrates betweeninternalcomponentsthatcanaccessthebus(systemcore,PCIbridge, CPM,andoneexternalmaster).Thisarbitercanbedisabled,andanexternal arbitercanbeusedifnecessary.
Alocal(32-bitdata,32-bitinternaland18-bitexternaladdress)bus.Thisbusis usedtoenhancetheoperationoftheveryhigh-speedcommunicationcontrollers. Withoutrequiringextensivemanipulationbythecore,thebuscanbeusedtostore connectiontablesforATMorbufferdescriptors(BDs)forthecommunication channelsorrawdatathatistransmittedbetweenchannels.Thelocalbusis synchronoustothe60xbusandrunsatthesamefrequency.
Thelocalbuscanbeconfiguredasa32-bitdataandupto66MHzPCI(version2.1) bus.InPCImodethebuscanbeprogrammedasahostorasanagent.ThePCI buscanbeconfiguredtorunsynchronouslyorasynchronouslytothe60xbus.The PC8260hasaninternalPCIbridgewithanefficient60x-to-PCIDMAformemory blocktransfers.
ApplicationsthatrequireboththelocalbusandPCIbusneedtoconnectanexternal PCIbridge.
Amemorycontrollersupporting12memorybanksthatcanbeallocatedforeither thesystemorthelocalbus.Thememorycontrollerisanenhancedversionofthe PC8260memorycontroller.Itsupportsthreeuser-programmablemachines. BesidessupportingallPC8260features,thememorycontrolleralsosupports SDRAMwithpagemodeandaddressdatapipeline
SupportsJTAGcontrollerIEEE1149.1testaccessport(TAP).
Abusmonitorthatprevents60xbuslock-ups,areal-timeclock,aperiodicinterrupt timer,andothersystemfunctionsusefulinembeddedapplications.
GluelessinterfacetoL2cacheand4-/16-K-entryCAM.

6 PC8260PowerQUICCII

2131B–HIREL–02/03 Communication ProcessorModule(CPM) TheCPMcontainsfeaturesthatallowthePC 8260toexcelinavarietyofapplications targetedmainlyfornetworkingandtelecommunicationmarkets. TheCPMisasupersetofthePC8260PowerQUICCCPM,withenhancementsonthe CPperformanceandadditionalhardwareandmicrocoderoutinesthatsupporthighbit rateprotocolslikeATM(upto155Mbpsfull-duplex)andFastEthernet(100Mbpsfull- duplex). ThefollowinglistsummarizesthemajorfeaturesoftheCPM:

Thecommunicationsprocessor(CP)isanembedded32-bitRISCcontroller residingonaseparatebus(CPMlocalbus)fromthe60xbus(usedbythesystem core).Withthisseparatebus,theCPdoesnotaffecttheperformanceofthe PowerPCcore.TheCP handlesthelowerlayertasksandDMAcontrolactivities, leavingthePowerPCcorefreetohandlehigherlayeractivities.TheCPhasan instructionsetoptimizedforcommunications,butcanalsobeusedforgeneral- purposeapplications,relievingthesys-temcoreofsmalloftenrepeatedtasks.
TwoserialDMAs(SDMAs)thatcandosimultaneoustransfers,optimizedforburst transferstothe60xbusandtothelocalbus.
Threefull-duplex,serialfastcommunicationscontrollers(FCCs)supportingATM (155Mbps)protocolthroughUTOPIA2interface(therearetwoUTOPIAinterfaces onthePC8260),IEEE802.3andFastEthernetprotocols,HDLCuptoE3rates(45 Mbps)andtotallytransparentoperation.EachFCCcanbeconfiguredtotransmit fullytransparentandreceiveHDLC,orvice-versa.
Twomultichannelcontrollers(MCCs)thatcanhandleanaggregateof256x64 KbpsHDLCortransparentchannels,multiplexedonuptoeightTDMinterfaces. TheMCCalsosupportssuper-channelsofrateshigherthan64Kbpsand subchannelingofthe64-Kbpschannels.
Fourfull-duplexserialcommunicationscontrollers(SCCs)supporting IEEE802.3/Ethernet,high-levelsynchronousdatalinkcontrol,HDLC,localtalk, UART,synchronousUART,BISYNCandtransparent.
Twofull-duplexserialmanagementcontrollers(SMC)supportingGCI,UART,and transparentoperations.
Serialperipheralinterface(SPI)andI 2Cbuscontrollers.
Time-slotassigner(TSA)thatsupportsmultiplexingofdatafromanyofthefour SCCs,threeFCCs,andtwoSMCs. SoftwareCompatibility Issues Asmuchaspossible,thePC8260CPMfeaturesweremadesimilartothoseofthepre- viousdevices(PC860).Thecodeportseas ilyfrompreviousdevicestothePC8260, exceptfornewprotocolssupportedbythePC8260. Althoughmanyregistersarenew,mostregistersretaintheoldstatusandeventbits,so anunderstandingoftheprogrammingmodelsofthe68360,PC860,orPC850ishelpful. NotethatthePC8260initializationcoderequireschangesfromthePC8260initialization code.

2131B–HIREL–02/03 DifferencesBetween PC860andPC8260 ThefollowingPC860featuresarenotincludedinthePC8260:

On-chipcrystaloscillators(mustuseexternaloscillator)
4MHzoscillator(inputclockmustbeatthebusspeed)
Lowpower(standby)modes
Battery-backupreal-timeclock(mustuseexternalbattery-backupclock)
BDM(COPoffersmostofthesamefunctionality)
Truelittleendianmode(exceptthePCIbus)
PCMCIAinterface
Infrared(IR)port
QMCprotocolinSCC(256HDLCchannelsaresupportedbytheMCCs)
Multiplyandaccumulate(MAC)blockintheCPM
Centronicsport(PIP)
AsynchronousHDLCprotocol(optionalRAMmicrocode)
Pulse-widthmodulatedoutputs
SCCEthernetcontrolleroptiontosample1bytefromtheparallelportwhena receiveframeiscomplete.
ParallelCAMinterfaceforSCC(Ethernet) SerialProtocolTable Table1summarizesavailableprotocolsforeachserialport. Table1.PC8260SerialProtocols Port Protocol FCC SCC MCC SMC ATM(Utopia) x 100BaseT x 10BaseT x x HDLC x x x HDLC_BUS x Transparent x x x x UART x x DPLL x Multichannel x

8 PC8260PowerQUICCII

2131B–HIREL–02/03 PinAssignment Table2showsthepinoutofthePC8260. Table2.Pinout PinName Ball BR W5 BG F4 ABB/IRQ2 E2 TS E3 A0 G1 A1 H5 A2 H2 A3 H1 A4 J5 A5 J4 A6 J3 A7 J2 A8 J1 A9 K4 A10 K3 A11 K2 A12 K1 A13 L5 A14 L4 A15 L3 A16 L2 A17 L1 A18 M5 A19 N5 A20 N4 A21 N3 A22 N2 A23 N1 A24 P4 A25 P3 A26 P2 A27 P1 A28 R1 A29 R3 A30 R5

2131B–HIREL–02/03 A31 R4 TTO F1 TT1 G4 TT2 G3 TT3 G2 TT4 F2 TBST D3 TSIZ0 C1 TSIZ1 E4 TSIZ2 D2 TSIZ3 F5 AACK F3 ARTRY E1 DBG V1 DBB/IRQ3 V2 D0 B20 D1 A18 D2 A16 D3 A13 D4 E12 D5 D9 D6 A6 D7 B5 D8 A20 D9 E17 D10 B15 D11 B13 D12 A11 D13 E9 D14 B7 D15 B4 D16 D19 D17 D17 D18 D15 D19 C13 D20 B11 Table2.Pinout(Continued) PinName Ball

10 PC8260PowerQUICCII

2131B–HIREL–02/03 D21 A8 D22 A5 D23 C5 D24 C19 D25 C17 D26 C15 D27 D13 D28 C11 D29 B8 D30 A4 D31 E6 D32 E18 D33 B17 D34 A15 D35 A12 D36 D11 D37 C8 D38 E7 D39 A3 D40 D18 D41 A17 D42 A14 D43 B12 D44 A10 D45 D8 D46 B6 D47 C4 D48 C18 D49 E16 D50 B14 D51 C12 D52 B10 D53 A7 D54 C6 D55 D5 D56 B18 Table2.Pinout(Continued) PinName Ball

2131B–HIREL–02/03 D57 B16 D58 E14 D59 D12 D60 C10 D61 E8 D62 D6 D63 C2 DPO/RSRV/EXT_BR2 B22 IRQ1/DP1/EXT_BG2 A22 IRQ2/DP2/TLBISYNC/EXTDBG2 E21 IRQ3/DP3/CKSTP_OUT/EXTBR3 D21 IRQ4/DP4/CORE_SRESET/EXTBG3 C21 IRQ5/DP5/TBEN/EXT_DBG3 B21 IRQ6/DP6/CSEO A21 IRQ7/DP7/CSE1 E20 PSDVAL V3 TA C22 TEA V5 GBL/IRQ1 W1 CI/BADDR29/IRQ2 U2 WT/BADDR30/IRQ3 U3 L2_HIT/IRQ4 Y4 CPU_BG/BADDR31/IRQ5 U4 CPU_DBG R2 CPU_BR Y3 CS0 F25 CS1 C29 CS2 E27 CS3 E28 CS4 F26 CS5 F27 CS6 F28 CS7 G25 CS8 D29 CS9 E29 CS10/BCTL1 F29 Table2.Pinout(Continued) PinName Ball

12 PC8260PowerQUICCII

2131B–HIREL–02/03 CS11/APO G28 BADDR27 T5 BADDR28 U1 ALE T2 BCTL0 A27 PWE0/PSDQM0/PBS0 C25 PWE1/PSDDQM1/PBS1 E24 PWE2/PSDDQM2/PBS2 D24 PWE3/PSDDQM3/PBS3 C24 PWE4/PSDDQM4/PBS4 B26 PWE5PSDDQM5/PBS5 A26 PWE6/PSDDQM6/PBS6 B25 PWE7/PSDDQM7/PBS7 A25 PSDA10/PGL0 E23 PSDWE/PGPL1 B24 POE/OSDRAS/PGPL2 A24 PSDCAS/PGPL3 B23 PGTA/PUPMWAIT/PGPL4/PPBS A23 PSDAMUX/PGPL5 D22 LWE0/LSDDQM0/LBS0 H28 LWE1/LSDDQM1/LBS1 H27 LWE2/LSDDQM2/LBS2 H26 LWE3/LSDDQM3/LBS3 G29 LSDA10/LGPL0 D27 LSDWE/LGPL1 C28 LOE/LSDRAS/LGPL2 E26 LSDCAS/LGPL3 D25 LGTA/LUPMWAIT/LGPL4/LPBS C26 LGPL5 B27 LWR D28 LA14 N27 LA15/SMI T29 LA16 R27 LA17/CKSTP_OUT R26 LA18 R29 LA19 R28 Table2.Pinout(Continued) PinName Ball

2131B–HIREL–02/03 LA20 W29 LA21 P28 LA22 N26 LA23 AA27 LA24 P29 LA25 AA26 LA26 N25 LA27 AA25 LA28/CORE_SRESET AB29 LA29 AB28 LA30 P25 LA31 AB27 LCLD0 H29 LCLD1 J29 LCLD2 J28 LCLD3 J27 LCLD4 J26 LCLD5 J25 LCLD6 K25 LCLD7 L29 LCLD8 L27 LCLD9 L26 LCLD10 L25 LCLD11 M29 LCLD12 M28 LCLD13 M27 LCLD14 M26 LCLD15 N29 LCLD16 T25 LCLD17 U27 LCLD18 U26 LCLD19 U25 LCLD20 V29 LCLD21 V28 LCLD22 V27 LCLD23 V26 Table2.Pinout(Continued) PinName Ball

14 PC8260PowerQUICCII

2131B–HIREL–02/03 LCL_D24 W27 LCL_D25 W26 LCL_D26 W25 LCL_D27 Y29 LCL_D28 Y28 LCL_D29 Y25 LCL_D30 AA29 LCL_D31 AA28 LCL_DP0 L28 LCL_DP1 N28 LCL_DP2 T28 LCL_DP3 W28 IRQ0/NMI_OUT T1 IRQ7INT_OUT/APE D1 TRST AH3 TCK AG5 TMS AJ3 TDI AE6 TDO AF5 TRIS AB4 PORESET AG6 HRESET AH5 SRESET AF6 QREQ AA3 RSTCONF AJ4 MODCK1/AP1/TC0/BNKSEL0 W2 MODCK2/AP2/TC1/BNKSEL1 W3 MODCK3/AP3/TC2/BNKSEL2 W4 XFC AB2 CLKIN AH4 PA0/RESTART1/DREQ/FCC2_UTM_TXADDRS AC29 PA1/REJECT1/FCC2_UTM_TXADDR1/DONE3 AC25 PA2/CLK20/FCC2_UTM_TXADDR0/DACK3 AE28 PA3/CLK19/FCC2_UTM_RXADDR0/DACK4/L1RXD1A2 AG29 PA4/REJECT2/FCC2/RXADDR1/DONE4 AG28 PA5/RESTART2/DREQ4/FCC2_UTMRXADDR2 AG26 Table2.Pinout(Continued) PinName Ball

2131B–HIREL–02/03 PA6/L1RSYNCA1 AE24 PA7/SMSYN2/L1TSYNCA1/L1GNTA1 AH25 PA8/SMRSXD2/L1RXD0A1/L1RXDA1 AF23 PA9/SMTXD2/L1TXD0A1 AH23 PA10/FCC1_UT8_RXD0/FCC1_UT16_RXD8/MSNUM5 AE22 PA11/FCC1_UT8_RXD1/FCC1_UT16_RXD9/MSNUM4 AH22 PA12/FCC1_UT8_RXD2/FCC1_UT16_RXD10/MSNUM3 AJ21 PA13/FCC1_UT8_RXD3/FCC1_UT16_RXD11/MSNUM2 AH20 PA14/FCC1_UT8_RXD4/FCC1_UT16_RXD12/FCC1_RXD3 AG19 PA15/FCC1_UT8_RXD5/FCC1_UT16_RXD13/FCC1_RXD2 AF18 PA16/FCC1_UT8_RXD6/FCC1_UT16_RXD14/FCC1_RXD1 AF17 PA17/FCC1_UT8_RXD7/FCC1_UT16_RXD15/FCC1_RXD0/FCC1_RXD AE16 PA18/FCC1_UT8_TXD7/FCC1_UT16_TXD15/FCC1_TXD0/FCC1_TXD AJ16 PA19/FCC1_UT8_TXD6/FCC1_UT16_TXD14/FCC1_TXD1 AG15 PA20/FCC1_UT8_TXD5/FCC1_UT16_TXD13/FCC1_TXD2 AJ13 PA21/FCC1_UT8_TXD4/FCC1_UT16_TXD12/FCC1_TXD3 AE13 PA22/FCC1_UT8_TXD3/FCC1_UT16_TXD11 AF12 PA23/FCC1_UT8_TXD2/FCC1_UT16_TXD10 AG11 PA24/FCC1_UT8_TXD1/FCC1_UT16_TXD9/MSNUM1 AH9 PA25/FCC1_UT8_TXD0/FCC1_UT16_TXD8/MSNUM0 AJ8 PA26/FCC1_UTM_RXCLAV/FCC1_UTS_RXCLAV/FCC1_MII_RX_ER AH7 PA27/FCC1_UT_RXSOC/FCC1_MII_RX DV AF7 PA28/FCC1_UTM_RXENB/FCC1_UTS_RXENB/FCC1_MII_TX_EN AD5 PA29/FCC1_UT_TXSOC/FCC1_MII_TX_ER AF1 PA30/FCC1_UTM_TXCLAV/FCC1_UTS_TXCLAV/FCC1_MII_CRS/FCC1_RTS AD3 PA31/FCC1_UTM_TXENB/FCC1_UTS_TXENB/FCC1_MII_COL AB5 PB4/FCC3_TXD3/FCC2_UT8_RXD0/L1RSYNCA2/FCC3_RTS AD28 PB5/FCC3_TXD2/FCC2_UT8_RXD1/L1TSYNCA2/L1GNTA2 AD26 PB6/FCC3_TXD1/FCC2_UT8_RXD2/L1RXDA2/L1RXD0A2 AD25 PB7/FCC3_TXD0/FCC3_TXD/FCC2_UT8_RXD3/L1TXDA2/L1TXD0A2 AE26 PB8/FCC2_UT8_TXD3/FCC3_RXD0/FCC3 RXD/TXD3/L1RSYNCD1 AH27 PB9/FCC2_UT8_TXD2/FCC3_RXD1/L1TXD2A2/L1TSYNCD1/L1GNTD1 AG24 PB10/FCC2_UT8_TXD1/FCC3_RXD2/L1RXDD1 AH24 PB11/FCC3_RXD3/FCC2_UT8_TXD0/L1TXDD1 AJ24 PB12/FCC3_MII_CRS/L1CLKOB1/L1RSYNCC1/TXD2 AG22 PB13/FCC3_MII_COL/L1RQB1 /L1TSYNCC1/L1GNTC1/L1TXD1A2 AH21 Table2.Pinout(Continued) PinName Ball

16 PC8260PowerQUICCII

2131B–HIREL–02/03 PB14/FCC3_MIL_TX_EN/RXD3/L1RXDC1 AG20 PB15/FCC3_MIL_TX_ER/RXD2/L1TXDC1 AF19 PB14/FCC3_MIL_RX_ER/L1CLKOA1/CLK18 AJ18 PB17FCC3_MIL_RX_DV/L1RQA1/CLK17 AJ17 PB18/FCC2_UT8_RXD4/FCC2_RXD3/L1CLKOD2/L1RXD2A2 AE14 PB19/FCC2_UT8_RXD5/FCC2_RXD2/L1RQD2/L1RXD3A2 AF13 PB20/FCC2_UT8_RXD6/FCC2 RXD1/L1RSYNCD2/L1TXD1A1 AG12 PB21/FCC2_UT8_RXD7/FCC2_RXD0/FCC2_RXD/ L1TSYNCD2/L1GNTD2/L1TXD2A1 AH11 PB22/FCC2_UT8_TXD7/FCC2_TXD0/FCC2_L1RXD1A1/L1RXDD2 AH16 PB23/FCC2_UT8_TXD6/FCC2_TXD1/L1RXD2A1/L1RXDD2 AE15 PB24/FCC2_UT8_TXD5/FCC2_TXD2/L1RXD3A1/L1RSYNCC2 AJ9 PB25/FCC2_UT8_TXD4/FCC2_TXD3/L1TSYNCC2/L1GNTC2/L1TXD3A1 AE9 PB26/FCC2_MII_CRS/FCC2_UT8_TXD1/L1RXDC2 AJ7 PB27/FCC2_MII_COL/FCC2_UT8_TXD0/L1TXDC2 AH6 PB28/FCC2_MII RX_ER/FCC2_RTS/L1TSYNCB2/L1GNTB2/TXD1 AE3 PB29/FCC2_UTM_RXCLAV/FCC2_UTS_RXCLAV/ L1RSYNCB2/FCC2_MII_TX_EN AE2 PB30/FCC2_MII_RX_DV/FCC2_UT_TXSOC/1RXDB2 AC5 PB31/FCC2_MII_TX_ER/FCC2_UT_RXSOC/L1TXDB2 AC4 PC0/DREQ1/BRGO7/SMSYN2/L1CLKOA2 AB26 PC1/DREQ2/BRGO6/L1RQA2 AD29 PC2/FCC3_CD/FCC2_UT8_TXD3/DONE2 AE29 PC3/FCC3_CTS/FCC2_UT8_TXD2/DACk2/CTS4 AE27 PC4/FCC2_UTM_RXENB/FCC2_UTS_RXENB/SI2_L1ST4/FCC2_CD AF27 PC5/FCC2_UTM_TXCLAV/FCC2_UTS_TXCLAV/SI2_L1ST3/FCC2_CTS AF24 PC6/FCC1_CD/L1CLKOC1/FCC1_UTM_RXADDR2/FCC1_UTSRXADDR2/ FCC1_UTM_RXCLAV1 AJ26 PC7/FCC1_CTS/L1RQC1/ FCC1_UTM_TXADDR2/FCC1_UTS_TXADDR2/FCC1_UTM_TSCLAV1 AJ25 PC8/CD4/RENA4/FCC1_UT16_TXD0/SI2_L1ST2/CTS3 AF22 PC9/CTS4/CLSN4/FCC1_UT16_TXD1/SI2_L1ST1/L1TSYNCA2/L1GNTA2 AE21 PC10/CD3/RENA3/FCC1_UT16_TXD2/SI1_L1ST4/FCC2_UT8_RXD3 AF20 PC11/CTS3/CLSN3/L1CLKOD1/L1TXD3A2/FCC2_UT8_RXD2 AE19 PC12/CD2/RENA2/SI1_L1ST3/FCC1_UTM_RXADDR1/FCC1_UTS_RXADDR1 AE18 PC13/CTS2/SLSN2/L1RQD1/FCC1_UTM_TXADDR1/FCC1_UTS_TXADDR1 AH18 PC14/CD1/RENA1/FCC1_UTM_RXADDR0/FCC1_UTS_RXADDR0 AH17 Table2.Pinout(Continued) PinName Ball

2131B–HIREL–02/03 PC15/CTS1/CLSN1/SMTXD2/FCC1_UTM_TXADDR0/FCC1_UTS_TXADDR0 AG16 PC16/CLK16/TIN3 AF15 PC17/CLK15/TIN4/BRGO8 AJ15 PC18/CLK14/TGATE2 AH14 PC19/CLK13/BRGO7 AG13 PC20/CLK12/TGATE1 AH12 PC21/CLK11/BTGO6 AJ11 PC22/CLK10/DONE1 AG10 PC23/CLK9/BRGO5/DACK1 AE10 PC24/FCC2_UT8_TXD3/CLK8/TOUT4 AF9 PC25/FCC2_UT8_TXD2/CLK7/BRGO4 AE8 PC26/CLK6/TOUT3/TMCLK AJ6 PC27/FCC3_TXD/FCC3_TXD0/CLK5/BRGO3 AG2 PC28/CLK4/TIN1/TOUT2/CTS2/CLSN2 AF3 PC29/CLK3/TIN2/BRGO2/CTS1/CLSN1 AF2 PC30/FCC2_UT8_TXD3/CLK2/TOUT1 AE1 PC31/CLK1/BRGO1 AD1 PD4/BRGO8/L1TSYNCD1/L1GNTD1/FCC3_RTS/SMRXD2 AC28 PD5/FCC1_UT16_TXD3/DONE1 AD27 PD6/FCC1_UT16_TXD4/DACK1 AF29 PD7/SMSYN1/FCC1_UTM_TXADDR3/FCC1_UTS_TXADDR3/FCC1_TXCLAV2 AF28 PD8/SMRXD1/FCC2_UT_TXPRTY/BRGO5 AG25 PD9/SMTXD1/FCC2_UT_RXPRTY/BRGO3 AH26 PD10/L1CLKOB2/FCC2_UT8_RXD1/L1RSYNCB1/BRGO4 AJ27 PD11/L1RQB2 /FCC2_UT8_RXD0/L1TSYNCB1/L1GNTB1 AJ23 PD12/SI1_L1ST2/L1RXDB1 AG23 PD13/SI1_L1ST1/L1RTDB1 AJ22 PD14/FCC1_UT16_RXD0/L1CLKOC2/L2CSCL AE20 PD15/FCC1_UT16_RXD1/L1RQC2/I2CSDA AJ20 PD16/FCC1_UT_TXPRTY/L1TSYNCC1/L1GNTC1/SPIMISO AG18 PD17/FCC1_UT_RXPRTY/BRGO2/SPIMOSI AG17 PD18/FCC1_UTM_RXADDR4/FCC1_UTS_RXADDR4/FCC1_UTM_RXCLAV3/ SPICLK AF16 PD19/FCC1_UTM_RXADDR4/FCC1_UTS_RXADDR4/FCC1_UTM TXCLAV3/SPISEL/BRGO1 AH15 PD20/RTS4/TENA4/FCC1_UT16_RXD2/L1RSYNCA2 AJ14 PD21/TXD4/FCC1_UT16_RXD3/L1RXD0A2/L1RXDA2 AH13 Table2.Pinout(Continued) PinName Ball

18 PC8260PowerQUICCII

2131B–HIREL–02/03 Notes: 1. Mustbepulleddownorleftfloating. 2. Mustbepulleddownorleftfloating.However,ifcompatibilitywithHiP4siliconisrequired,thispinmustbepulleduporleft floating. 3. For information on how to use this pin, refer to MPC8260 PowerQUICC II Thermal Resistor Guide available at www.motorola.com/semiconductors. PD22/RXD4/FCC1_UT16_TXD5/L1TXD0A2/L1TXDA2 AJ12 PD23/RTS3/TENA3/FCC1_UT16_RXD4/L1RSYNCD1 AE12 PD24/TXD3/FCC1_UT16_RXD5/L1RXDD1 AF10 PD25/RXD3/FCC1_UT16_TXD6/L1TXDD1 AG9 PD26/RTS2 /TENA2/FCC1_UT16_RXD6/L1RSYNCC1 AH8 PD27/TXD2/FCC1_UT16_RXD7/L1RXDC1 AG7 PD28/RXD2/FCC1_UT16_TXD7/L1TXDC1 AE4 PD29/RTS1/TENA1/FCC1_UTM_RXADDR3/FCC1_UTS_RXADDR3/ FCC1 UTMRXCLAV2 AG1 PD30/FCC2_UTM_TXENB/FCC2_UTS_TXENB/TXD1 AD4 PD31/RXD1 AD2 VCCSYN AB3 VCCSYN1 B9 GNDSYN AB1 THERMAL0(thermalball)(3) AA1 THERMAL1(thermalball)(3) AG4 SPARE1(1) AE11 SPARE4(1) U5 SPARE5(2) AF25 SPARE6(1) V4 I/OPower AG21,AG14,AG8,AJ1,AJ2,AH1,AH2,AG3, AF4,AE5,AC27,Y27,T27,P27,K26,G27, AE25,AF26,AG27,AH28,AH29,AJ28,AJ29, C7,C14,C16,C20,C23,E10,A28,A29,B28, B29,C27,D26,E25,H3,M4,T3,AA4,A1,A2, B1,B2,C3,D4,E5 CorePower U28,U29,K28,K29,A9,A19,B19,M1,M2,Y1, Y2,AC1,AC2,AH19,AJ19,AH10,AJ10,AJ5 Ground AA5,AF21,AF14,AF8,AE7,AF11, AE17,AE23,AC26,AB25,Y26,V25, T26,R25,P26,M25,K27,H25, G26,D7,D10,D14,D16,D20,D23, C9,E11,E13,E15,E19,E22,B3, G5,H4,K5,M3,P5,T4,Y5,AA2, AC3 Table2.Pinout(Continued) PinName Ball

2131B–HIREL–02/03 SymbolsusedinTable2aredescribedinTable4. Table3.SymbolLegend OVERBAR Signalswithoverlines,suchasTA,areactivelow UTM IndicatesthatasignalispartoftheUTOPIAmasterinterface UTS IndicatesthatasignalispartoftheUTOPIAslaveinterface 2UT8 Indicatesthatasignalispartofthe8-bitUTOPIAinterface UT16 Indicatesthatasignalispartofthe16-bitUTOPIAinterface MII Indicatesthatasignalispartofthemediaindependentinterface

20 PC8260PowerQUICCII

2131B–HIREL–02/03 Figure2.PowerQUICCIIExternalSignals A[0:31] TT[0:4] TSIZ[0:3] TBST GBL/IRQ1 CI/BADDR29/IRQ2 WT/BADDR30/IRQ3 L2_HIT/IRQ4 CPU_BG/BADDR31/IRQ5 CPU_DBG CPU_BR BR BG ABB/IRQ2 TS AACK ARTRY DBG DBB/IRQ3 D[0:63] NC/DP0/RSRV /EXT_BR2 IRQ1/DP1/EXT_BG2 IRQ2/DP2/TLBISYNC/EXT_DBG2 IRQ3/DP3/CKSTP_OUT/EXT_BR3 IRQ4/DP4/CORE_SRESET /EXT_BG IRQ5/DP5/TBEN/EXT_DBG3 IRQ6/DP6/CSE0 IRQ7/DP7/CSE1 PS_DVAL TA TEA IRQ0/NMI_OUT IRQ7/INT_OUT/APE CS[0:9] CS[10]/BCTL1/DBG_DIS CS[11]/AP[0] BADDR[27:28] ALE BCTL0 PWE[0:7]/PSDDQM[0:7]/PBS[0:7] PSDA10/PGPL0 PSDWE/PGPL1 POE/PSDRAS/PGPL2 PSDCAS/PGPL3 PGTA/PUPMWAIT/PGPL4/PPBS PSDAMUX/PGPL5 TMS TDI TCK TRST TDO VCCSYN/GNDSYN/VCCSYN1/VDDH/VDD/VSS P AR / L_A14 SMI/FRAME / L_A15 TRDY / L_A16 CKSTOP_OUT/IRDY / L_A17 STOP/ L_A18 DEVSEL / L_A19 IDSEL / L_A20 PERR / L_A21 SERR / L_A22 REQ0 / L_A23 REQ1 / L_A24 GNT0 / L_A25 GNT1 / L_A26 CLK / L_A27 CORE_SRESET/RST / L_A28 INTA/ L_A29 LOCK/ L_A30 L_A31 AD[0:31]/LCL_D[0:31] C/BE[0:3] /LCL_DP[0:3] LBS[0:3]/LSDDQM [0:3]/L WE [0:3] LGPL0/LSDA10 LGPL1/LSDWE LGPL2/LSDRAS/LOE LGPL3/LSDCAS LPBS/LGPL4/LUPW AIT/LGT A LGPL5 LWR PA[0:31] PB[4:31] PC[0:31] PD[4:31] PORESET RSTCONF HRESET SRESET QREQ XFC CLKIN TRIS BNKSEL[0]/TC[0]/AP[1]/MODCK1 BNKSEL[1]/TC[1]/AP[2]/MODCK2 BNKSEL[2]/TC[2]/AP[3]/MODCK3 TERM[0:1] NC 100 L O C A L B U S x B U S M E M C J T A G R S T C L K M E M C P I O

2131B–HIREL–02/03 SignalDescriptions ThePowerQUICCIIsystembussignalsconsistofallthelinesthatinterfacewiththeexternalbus.Manyoftheselinesper- formdifferentfunctions,dependingonhowtheuserassignsthem.Eachsignal’spinnumbercanbefoundinTable4. Table4.ExternalSignals Pin SignalName Type Description BR 60xBusRequest I/O Thisisanoutputwhenanexternalarbiterisusedandaninputwhenan internalarbiterisused.Asanoutput,thePowerQUICCIIassertsthispin torequestownershipofthe60xbus.Asaninput,anexternalmaster shouldassertthispintorequest60xbusownershipfromtheinternal arbiter. BG 60xBusGrant I/O Thisisanoutputwhenaninternalarbiterisusedandaninputwhenan internalarbiterisused.Asanoutput,thePowerQUICCIIassertsthispin togrant60xbusownershiptoanexternalbusmaster.Asaninput,an externalarbitershouldassertthispintogrant60xbusownershiptothe PowerQUICCII. ABB IRQ2 60xAddressBusBusy I/O AsanoutputthePowerQUICCIIassertsthispinforthedurationofthe addressbustenure.FollowinganAACK,whichterminatestheaddress bustenure,thePowerQUICCIInegatesABBforafractionofabuscycle andthanstopsdrivingthispin.Asaninput,thePowerQUICCIIwillnot assume60xbusownership,aslongasitsensesthispinisassertedby anexternal60xbusmaster. InterruptRequest2 I Thisinputisoneoftheeightexternallinesthatcanrequest(bymeansof theinternalinterruptcontroller)aserviceroutinefromthecore. TS T-S60xBusTransferStart I/O Assertionofthispinsignalsthebeginningofanewaddressbustenure. ThePowerQUICCIIassertsthissignalwhenoneofitsinternal60xbus masters(core,dma,PCIbridge)beginsanaddresstenure.Whenthe PowerQUICCIIsensesthispinbeingassertedbyanexternal60xbus master,itwillrespondtotheaddressbustenureasrequired(snoopif enabled,accessinternalPowerQUICCIIresourcesandmemory controllersupport). A[0:31] 60xAddressBus I/O WhenthePowerQUICCIIisintheexternalmasterbusmode,thesepins functionasthe60xaddressbus.ThePowerQUICCIIdrivestheaddress ofitsinternal60xbusmastersandwillrespondtoaddressesgenerated byexternal60xbusmasters.WhenthePowerQUICCIIisintheinternal masterbusmode,thesepinsareusedasaddresslinesconnectedto memorydevicesandcontrolledbythePowerQUICCII’smemory controller. TT[0:4] 60xBusTransferType I/O The60xbusmasterdrivesthesepinsduringtheaddresstenureto specifythetypeofthetransaction. TBST 60xBusTransferBurst I/O The60xbusmasterassertsthispintoindicatethatthecurrent transactionisabursttransaction(transfers4doublewords). TSIZ[0:3] 60xTransferSize I/O The60xbusmasterdrivesthesepinswithavalueindicatingtheamount ofbytestransferredinthecurrenttransaction. AACK 60xAddressAcknowledge I/O A60xbusslaveassertsthissignaltoindicatethatithasidentifiedthe addresstenure.Assertionofthissignalterminatestheaddresstenure. ARTRY 60xAddressRetry I/O Assertionofthissignalindicatesthatthebustransactionshouldbe retriedbythe60xbusmaster.ThePowerQUICCIIassertsthissignalto enforcedatacoherencywithitsinternalcacheandtopreventdeadlock situations.

22 PC8260PowerQUICCII

2131B–HIREL–02/03 DBG 60xDataBusGrant I/O Thisisanoutputwhenaninternalarbiterisusedandaninputwhenan externalarbiterisused.Asanoutput,thePowerQUICCIIassertsthis pintogrant60xdatabusownershiptoanexternalbusmaster.Asan input,theexternalarbitershouldassertthispintogrant60xdatabus ownershiptothePowerQUICCII. DBB IRQ3 60xDataBusBusy I/O AsanoutputthePowerQUICCIIassertsthispinforthedurationofthe databustenure.FollowingaTA,whichterminatesthedatabustenure, thePowerQUICCIInegatesDBBforafractionofabuscycleandthen stopsdrivingthispin.Asaninput,thePowerQUICCIIwillnotassume 60xdatabusownership,aslongasitsensesthispinisassertedbyan external60xbusmaster. InterruptRequest3 I Thisinputisoneoftheeightexternallinesthatcanrequest(bymeansof theinternalinterruptcontroller)aserviceroutinefromthecore. D[0:63] 60xDataBus I/O Inwritetransactions,the60xbusmasterdrivesthevaliddataonthis bus.Inreadtransactions,the60xslavedrivesthevaliddataonthisbus. DP[0] RSRV EXTBR2 60xDataParity0 I/O The60xagentthatdrivesthedatabus,alsodrivesthedataparity signals.Thevaluedrivenonthedataparity0pinshouldprovideodd parity(oddnumberof1’s)onthegroupofsignalsthatincludedataparity 0andD[0:7]. Reservation O Thevaluedrivenonthisoutputpinrepresentsthestateofthecoherency bitinthereservationaddressregisterthatisusedbytheIwarxand stwcx.instructions. ExternalBusRequest2 I Anexternalmastershouldassertthispintorequest60xbusownership fromtheinternalarbiter. IRQ1 DP[1] EXTBG2 InterruptRequest1 I Thisinputisoneoftheeightexternallinesthatcanrequest(bymeansof theinternalinterruptcontroller)aserviceroutinefromthecore. 60xDataParity1 I/O The60xagentthatdrivesthedatabus,alsodrivesthedataparity signals.Thevaluedrivenonthedataparity1pinshouldprovideodd parity(oddnumberof1’s)onthegroupofsignalsthatincludesdata parity1andD[8:15]. ExternalBusGrant2 O ThePowerQUICCIIassertsthispintogrant60xbusownershiptoan externalbusmaster. IRQ2 DP[2] TLBISYNC EXTDBG2 InterruptRequest2 I Thisinputisoneoftheeightexternallinesthatcanrequest(bymeansof theinternalinterruptcontroller)aserviceroutinefromthecore. 60xDataParity2 I/O The60xagentthatdrivesthedatabus,alsodrivesthedataparity signals.Thevaluedrivenonthedataparity2pinshouldprovideodd parity(oddnumberof1’s)onthegroupofsignalsthatincludesdata parity2andS[16:23]. TLBSync: I Thisinputpincanbeusedtosynchronize60xcoreinstructionexecution tohardwareindications.Assertingthispinwillforcethecoretostop instructionexecutionfollowingatlbsincinstructionexecution.Thecore resumesinstructionexecutiononcethispinisnegated. ExternalDataBusGrant2 O ThePowerQUICCIIassertsthispintogrant60xdatabusownershipto anexternalbusmaster. Table4.ExternalSignals(Continued) Pin SignalName Type Description

2131B–HIREL–02/03 IRQ3 DP[3] CKSTPOUT EXTBR3 InterruptRequest3 I Thisinputisoneoftheeightexternallinesthatcanrequest(bymeansof theinternalinterruptcontroller)aserviceroutinefromthecore. 60xDataParity3 I/O The60xagentthatdrivesthedatabus,alsodrivesthedataparity signals.Thevaluedrivenonthedataparity3pinshouldprovideodd parity(oddnumberof1’s)onthegroupofsignalsthatincludesdata parity3andD[24:31]. CheckstopOutput O Assertionofthispinindicatesthatthecoreisinitscheckstopmode. ExternalBusRequest3 I Anexternalmastershouldassertthispintorequest60xbusownership fromtheinternalarbiter. IRQ4 DP[4] CORESRESET EXTBG3 InterruptRequest4 I Thisinputisoneoftheeightexternallinesthatcanrequest(bymeansof theinternalinterruptcontroller)aserviceroutinefromthecore. 60xDataParity4 I/O The60xagentthatdrivesthedatabus,alsodrivesthedataparity signals.Thevaluedrivenonthedataparity4pinshouldprovideodd parity(oddnumberof1’s)onthegroupofsignalsthatincludesdata parity4andD[32:39]. Coresystemreset I Assertingthispinwillforcethecoretobranchtoitsresetvector. ExternalBusGrant3 O ThePowerQUICCIIassertsthispintogrant60xdatabusownershipto anexternalbusmaster. IRQ5 DP[5] TBEN EXTDBG3 InterruptRequest5 I Thisinputisoneoftheeightexternallinesthatcanrequest(bymeansof theinternalinterruptcontroller)aserviceroutinefromthecore. 60xDataParity5 I/O The60xagentthatdrivesthedatabus,alsodrivesthedataparity signals.Thevaluedrivenonthedataparity5pinshouldprovideodd parity(oddnumberof1’s)onthegroupofsignalsthatincludesdata parity5andD[40:47]. TimeBaseEnable I ThisisacountenableinputtotheTimeBasecounterinthecore. ExternalBusGrant3 O ThePowerQUICCIIassertsthispintogrant60xdatabusownershipto anexternalbusmaster. IRQ6 DP[6] CSE[0] InterruptRequest6 I Thisinputisoneoftheeightexternallinesthatcanrequest(bymeansof theinternalinterruptcontroller)aserviceroutinefromthecore. 60xDataParity6 I/O The60xagentthatdrivesthedatabus,alsodrivesthedataparity signals.Thevaluedrivenonthedataparity6pinshouldprovideodd parity(oddnumberof1’s)onthegroupofsignalsthatincludedataparity 6andD[48:55]. CacheSetEntry0 O Thecachesetentryoutputsfromthecore,representthecache replacementsetelementforthecurrentcoretransactionreloadinginto, orwritingoutof,thecache. IRQ7 DP[7] CSE[1] InterruptRequest7 I Thisinputisoneoftheeightexternallinesthatcanrequest(bymeansof theinternalinterruptcontroller)aserviceroutinefromthecore. 60xDataParity7 I/O The60xmasterorslavethatdrivesthedatabus,alsodrivesthedata paritysignals.Thevaluedrivenonthedataparity7pinshouldprovide oddparity(oddnumberof1’s)onthegroupofsignalsthatincludedata parity7andD[56:63]. CacheSetEntry1 O Thecachesetentryoutputsfromthecore,representthecache replacementsetelementforthecurrentcoretransactionreloadinginto, orwritingoutof,thecache. Table4.ExternalSignals(Continued) Pin SignalName Type Description

24 PC8260PowerQUICCII

2131B–HIREL–02/03 PSDVAL 60xDataValid I/O Assertionofthe PSDVAL pinindicatesthatadatabeatisvalidonthe databus.ThedifferencebetweentheTApinandthe PSDVALpinisthat theTApinisassertedtoindicate60xdatatransferterminations,while the PSDVALsignalisassertedwitheachdatabeatmovement.Thus, alwayswhenTAisasserted, PSDVALwillbeasserted,but,when PSDVALisasserted,TAisnotnecessarilyasserted.Forexample,when adouble-doubleword(2x64bits)transferisinitiatedbytheSDMAtoa memorydevicethathas32bitsportsize, PSDVALwillbeasserted3 timeswithoutTAand,finally,bothpinswillbeassertedtoterminatethe transfer. TA TransferAcknowledge I/O AssertionoftheTA pinindicatesthata60xdatabeatisvalidonthedata bus.For60xsinglebeattransfers,assertionofthispinindicatesthe terminationofthetransfer.For60xbursttransfers,thispinwillbe assertedfourtimestoindicatethetransferoffourdatabeats,withthe lastassertionindicatingtheterminationofthebursttransfer. T EA TransferError Acknowledge I/O Assertionofthispinindicatesabuserror.60xmasterswithinthe PowerQUICCIImonitorthestateofthispin.PowerQUICCII’sinternal busmonitormayassertthispinifithasidentifieda60xtransferthatis hung. GBL IRQ1 Global I/O Whena60xmasterwithinthechipinitiatesabustransactionitdrives thispin.Whenanexternal60xmasterinitiatesabustransaction,it shoulddrivethispin.Assertionofthispinindicatesthatthetransferis globalanditshouldbesnoopedbycachesinthesystem.The PowerQUICCIIdatacachemonitorsthestateofthispin. InterruptRequest1 I Thisinputisoneoftheeightexternallinesthatcanrequest(bymeansof theinternalinterruptcontroller)aserviceroutinefromthecore. CI BADDR29 IRQ2 CacheInhibit O Thispinisanoutputpin.ItisusedforL2cachecontrol.Foreach BADDR29PowerQUICCII60xtransactioninitiatedinthecore,thestate ofthispinindicatesifthistransactionshouldbecachedornot.Assertion oftheCIpinindicatesthatthetransactionshouldnotbecached. BurstAddress29 O Therearefiveburstaddressoutputpins.Thesepinsareoutputsofthe 60xmemorycontroller.Thesepinsareusedinexternalmaster configurationandareconnecteddirectlytomemorydevicescontrolled byPowerQUICCIImemorycontroller. InterruptRequest2 I Thisinputisoneoftheeightexternallinesthatcanrequest(bymeansof theinternalinterruptcontroller)aserviceroutinefromthecore. WT BADDR30 IRQ3 WriteThrough O OutputusedforL2cachecontrol.ForeachcoreinitiatedPowerQUICCII 60xtransaction,thestateofthispinindicatesifthetransactionshouldbe cachedusingwrite-throughorcopy-backmode.AssertionofWT indicatesthatthetransactionshouldbecachedusingthewrite-through mode. BurstAddress30 O Therearefiveburstaddressoutputpins.Thesepinsareoutputsofthe 60xmemorycontroller.Thesepinsareusedinexternalmaster configurationandareconnecteddirectlytomemorydevicescontrolled byPowerQUICCII’smemorycontroller. InterruptRequest3 I Thisinputisoneoftheeightexternallinesthatcanrequest(bymeansof theinternalinterruptcontroller)aserviceroutinefromthecore. Table4.ExternalSignals(Continued) Pin SignalName Type Description

2131B–HIREL–02/03 L2HIT IRQ4 L2CacheHit I ThispinisusedforL2cachecontrol.Assertionofthispinindicatesthat the60xtransactionwillbehandledbytheL2cache.Inthiscase,the memorycontrollerwillnotstartanaccesstothememoryitcontrols. InterruptRequest4 I Thisinputisoneoftheeightexternallinesthatcanrequest(bymeansof theinternalinterruptcontroller)aserviceroutinefromthecore. CPUBG BADDR31 IRQ5 CPUBusGrant O Thevalueofthe60xcorebusgrantisdrivenonthispinforthe BADDR31useofanexternalL2cache.Thedrivenbusgrantisnon qualified.thatis,intheIRQ5caseofexternalarbiter,theusershould qualifythissignalwiththebusgrantinputtothePowerQUICCIIbefore connectingittotheL2Cache. Burstaddress31 O Therearefiveburstaddressoutputsofthe60xmemorycontrollerused intheexternalmasterconfigurationandareconnecteddirectlytothe memorydevicescontrolledbyPowerQUICCII’smemorycontroller. InterruptRequest5 I Thisinputisoneoftheeightexternallinesthatcanrequest(bymeansof theinternalinterruptcontroller)aserviceroutinefromthecore. CPU DBG CPUBusDataBusGrant O Thevalueofthe60xcoredatabusgrantisdrivenonthispinfortheuse ofanexternalL2cache. CPUBR CPUBusRequest O Thevalueofthe60xcorebusrequestisdrivenonthispinfortheuseof anexternalL2cache. CS[0:9] ChipSelect O Theseareoutputpinsthatenablespecificmemorydevicesor peripheralsconnectedtoPowerQUICCIIbuses. CS[10] BCTL1 DBGDIS ChipSelect O Thisisanoutputpinthatenablesspecificmemorydevicesor peripheralsconnectedtoPowerQUICCIIbuses. BufferControl1 O Outputsignalwhosefunctionistocontrolbuffersonthe60xdatabus. ThispinwillusuallybeusedwithBCTL0.Theexactfunctionofthispinis definedbythevalueofSIUMCR[BCTLC].See6.5.1.8SIUModule ConfigurationRegisterfordetails. DataBusGrantDisable O ThisisanoutputwhenthePowerQUICCIIisinexternalarbitermode andaninputwhenthePowerQUICCIIisininternalarbitermode.When thispinisasserted,the60xbusarbitershouldnegateallofitsDBG outputstopreventdatabuscontention. CS[11] AP[0] ChipSelect O Outputthatenablesspecificmemorydevicesorperipheralsconnected toPowerQUICCIIbuses. AddressParity0 I/O The60xmasterthatdrivestheaddressbus,alsodrivestheaddress paritysignals.Thevaluedrivenonaddressparity0pinshouldprovide oddparity(oddnumberof1’s)onthegroupofsignalsthatincludes addressparity0andA[0:7]. BADDR[27:28] BurstAddress27:28 O Therearefiveburstaddressoutputpins.Thesepinsareoutputsofthe 60xmemorycontroller.Usedinexternalmasterconfigurationand connecteddirectlytothememorydevicescontrolledbyPowerQUICC II’smemorycontroller. ALE AddressLatchEnable O Thisoutputpincontrolstheexternaladdresslatchthatshouldbeusedin externalmaster60xbusconfiguration. BCTLO BufferControl0 AnOutputwhosefunctionistocontrolbuffersonthe60xdatabus.This pinwillusuallybeusedwithBCTL1thatisMUXedonCS10.Theexact functionofthispinisdefinedbythevalueofSIUMCR[BCTLC].See 6.5.1.8SIUModuleConfigurationRegisterfordetails. Table4.ExternalSignals(Continued) Pin SignalName Type Description

26 PC8260PowerQUICCII

2131B–HIREL–02/03 PWE[0:7] PSDDQM[0:7] PBS[0:7] 60xBusWriteEnable O Outputsofthe60xbusGPCM,thesepinsselectbytelanesfor PSDDQM[0-7]writeoperations. 60xBusSDRAMDQM O TheDQMpinsareoutputsoftheSDRAMcontrolmachine.Thesepins selectspecificbytelanesofSRAMdevices. 60xBusUPMByteSelect O ThebyteselectpinsareoutputsoftheUPMinthememorycontroller. Theyareusedtoselectspecificbytelanesduringmemoryoperations. ThetimingofthesepinsisprogrammedintheUPM.Theactualdriven valuedependsontheaddressandsizeofthetransactionandtheport sizeoftheaccesseddevice. PSDA10 PGPLO 60xBusSDRAMA10 O Anoutputfromthe60xbusSDRAMcontroller,thispinispartofthe addresswhenarowaddressisdrivenandispartofthecommandwhen acolumnaddressisdriven. 60xBusUPMGeneral PurposeLine0 O ThisisoneofsixgeneralpurposeoutputlinesfromUPM.Thevalues andtimingofthispinareprogrammedintheUPM; PSDWE PGPL1 60xBusSDRAMWrite Enable O Anoutputfromthe60xbusSDRAMcontroller.Thispinshouldbe connectedtoSRAM’sWEinput. 60xBusUPMGeneral PurposeLine1 O ThisisoneofsixgeneralpurposeoutputlinesfromUPM.Thevalues andtimingofthispinareprogrammedintheUPM. POE PSDRAS PGPL2 60xBusOutputEnable O Theoutputenablepinisanoutputofthe60xbusGPCM.Thispin controlstheoutputbufferofmemorydevicesduringreadoperations. 60xBusSDRAMRAS O Outputfromthe60xbusSDRAMcontroller.Thispinshouldbe connectedtoSDRAM’sRASinput. 60xBusUPMGeneral PurposeLine2. O ThisisoneofsixgeneralpurposeoutputlinesfromtheUPM.Thevalues andtimingofthispinareprogrammedintheUPM. PSDCAS PGPL3 60xbusSDRAMCAS O Outputfromthe60xbusSDRAMcontroller.Thispinshouldbe connectedtoSDRAM’sCASinput. 60xBusUPMGeneral Purposeline3 O ThisisoneofsixgeneralpurposeoutputlinesfromtheUPM.Thevalues andtimingofthispinareprogrammedintheUPM. PGTA PUPMWAIT PGPL4 PPBS 60xGPCMTA I ThisinputpinisusedfortransactionterminationduringGPCM operation.Thispinrequiresexternalpullupresistorforproperoperation. 60xBusUPMWait I ThisisaninputtotheUPM.Anexternaldevicemayholdthispinlowto forcetheUPMtowaituntilthedeviceisreadyforthecontinuationofthe operation. 60xBusUPMGeneral PurposeLine4 O ThisisoneofsixgeneralpurposeoutputlinesfromUPM.Thevalues andtimingofthispinareprogrammedintheUPM. 60xBusParityByteSelect O Insystemsinwhichdataparityisstoredinaseparatechip,thisoutputis usedasthebyteselectforthatchip. PSDAMUX PGPL5 60xSDRAMAddress Multiplexer O Thisoutputpincontrolsthe60xSDRAMaddressmultiplexerwhenthe PowerQUICCIIisinexternalmastermode. 60xBusGeneralPurpose Line5 O ThisisoneofsixgeneralpurposeoutputlinesfromUPM.Thevalues andtimingofthispinareprogrammedintheUPM. Table4.ExternalSignals(Continued) Pin SignalName Type Description

2131B–HIREL–02/03 LWE[0:3] LSDDQM[0:3] LBS[0:3] LocalBusWriteEnable O ThewriteenablepinsareoutputsoftheLocalbusGPCM.Thesepins selectspecificbytelanesforwriteoperations. LocalBusSDRAMDQM O TheDQMpinsareoutputsoftheSDRAMcontrolmachine.Thesepins selectspecificbytelanesofSDRAMdevices. LocalBusUPMbyteselect O ThebyteselectpinsareoutputsoftheUPMinthememorycontroller. Theyareusedtoselectspecificbytelanesduringmemoryoperations. ThetimingofthesepinsisprogrammedintheUPM.Theactualdriven valuedependsontheaddressandsizeofthetransactionandtheport sizeoftheaccesseddevice. LSDA10 LGPL0 LocalBusSDRAMA10 O Outputfromthe60xbusSDRAMcontroller.Thispinispartofthe addresswhenarowaddressisdrivenandispartofthecommandwhen acolumnaddressisdriven. LocalBusUPMGeneral PurposeLine0 O ThisisoneofsixgeneralpurposeoutputlinesfromtheUPM.Thevalues andtimingofthispinareprogrammedintheUPM. LSDWE LGPL1 LocalBusSDRAMWrite Enable O OutputfromthelocalbusSDRAMcontroller.Thispinshouldbe connectedtoSDRAM’sWEinput. LocalBusUPMGeneral PurposeLine1 O ThisisoneofsixgeneralpurposeoutputlinesfromtheUPM.Thevalues andtimingofthispinareprogrammedintheUPM. LOE LSDRAS LGPL2 LocalBusOutputEnable O TheoutputenablepinisanoutputoftheLocalbusGPCM.Thispin controlstheoutputbufferofmemorydevicesduringreadoperations. LocalBusSDRAMRAS O OutputfromtheLocalbusSDRAMcontroller.Thispinshouldbe connectedtotheSDRAMRASinput. LocalbusUPMGeneral PurposeLine2 O ThisisoneofsixgeneralpurposeoutputlinesfromUPM.Thevalues andtimingofthispinareprogrammedintheUPM. LSDCAS LGPL3 LocalBusSDRAMCAS O OutputfromtheLocalbusSDRAMcontroller.Thispinshouldbe connectedtoSDRAM’sCASinput. LocalBusUPMGeneral PurposeLine3 O ThisisoneofsixgeneralpurposeoutputlinesfromtheUPM.Thevalues andtimingofthispinareprogrammedintheUPM. LGTA LUPWAIT LGPL4 LPBS LocalBusGPCMTA I ThisinputpinisusedfortransactionterminationduringGPCM operation.Thispinrequiresanexternalpullupresistorforproper operation. LocalBusUPMWait I ThisisaninputtotheUPM.Anexternaldevicemayholdthispinlowto forcetheUPMtowaituntilthedeviceisreadyforthecontinuationofthe operation. LocalBusUPMGeneral PurposeLine4 O ThisisoneofsixgeneralpurposeoutputlinesfromUPM.Thevalues andtimingofthispinisprogrammedintheUPM. LocalBusParityByte Select O Insystemsinwhichthedataparityisstoredinaseparatechip,this outputisusedasthebyteselectforthatchip. LGPL5 LocalBusUPMGeneral PurposeLine5 O ThisisoneofsixgeneralpurposeoutputlinesfromtheUPM.Thevalues andtimingofthispinareprogrammedintheUPM. LWR LocalWrite O Thelocalwritepinisanoutputfromthelocalbusmemorycontroller.Itis usedtodistinguishbetweenreadandwritetransactions. Table4.ExternalSignals(Continued) Pin SignalName Type Description

28 PC8260PowerQUICCII

2131B–HIREL–02/03 L_A14 PCI_PAR LocalBusAddress14 O Inthelocaladdressbus,bit14ismostsignificantandbit31isleast significant. PCIParity I/O Assertionofthispinindicatesthatoddparityisdrivenacross PCI_AD[0:31]andPCI_C/BE[0-3]duringaddressanddataphases. Negationofthispinindicatesthatevenparityisdrivenacrossthe PCI_AD[0-31]andPCI_C/BE[0-3]signalsduringaddressanddata phases. L_A15 PCI_FRAME SMI LocalBusAddress15 O Inthelocaladdressbus,bit14ismostsignificantandbit31isleast significant. PCIFramei I/O ThispinisdrivenbythePowerQUICCIIwhenitsinterfaceistheinitiator ofaPCItransfer.ThispinisassertedtoindicatethataPCItransferison going. SystemManagement Interrupt I Systemmanagementinterruptinputtothecore. L-A16 PCI_TRDY LocalBusAddress16 O Inthelocaladdressbus,bit14ismostsignificantandbit31isleast significant. PCITargetReady I/O ThispinisdrivenbythePowerQUICCIIwhenitsPCIinterfaceisthe targetofaPCItransfer.AssertionofthispinindicatesthatthePCItarget isreadytosendoracceptadatabeat. L_A17 PCI_IRDY CKSTP_OUT LocalBusAddress17 O Inthelocaladdressbus,bit14ismostsignificantandbit31isleast significant. PCIInitiatorReady I/O ThispinisdrivenbythePowerQUICCIIwhenitsPCIinterfaceisthe initiatorofaPC]transfer.AssertionofthispinindicatesthatthePCI initiatorisreadytosendoracceptadatabeat. CheckstopOutput O AssertionofCKSTP_OUT indicatesthecoreisincheckstopmode. L_A18 PCI_STOP LocalBusAddress18 O Inthelocaladdressbus,bit14ismostsignificantandbit31isleast significant. PCIStop I/O ThispinisdrivenbythePowerQUICCIIwhenitsPCIinterfaceisthe targetofaPCItransfer.AssertionofthispinindicatesthatthePCItarget isrequestingtostopthePCItransfer. L_A19 PCI_DEVESEL LocalBusAddress19 O Inthelocaladdressbus,bit14ismostsignificantandbit31isleast significant. PCIDeviceSelect I/O ThispinisdrivenbythePowerQUICCIIwhenitsPCIinterfaceisthe targetofaPCItransfer.AssertionofthispinindicatesthataPCItarget hasrecognizedanewPCItransferwithanaddressthatbelongstothe PCItarget. L_A20 PCI_IDSEL LocalBusAddress20 O Inthelocaladdressbus,bit14ismostsignificantandbit31isleast significant. PCIIDselect I UsedtoselectPowerQUICCII’sPCIinterfaceduringaPCIconfiguration cycle. L_A21 PCI_PERR LocalBusAddress21 O Inthelocaladdressbus,bit14ismostsignificantandbit31isleast significant. PCIParityError I/O Assertionofthispinindicatesthataparityerrorwasdetectedduringa PCItransfer. Table4.ExternalSignals(Continued) Pin SignalName Type Description

2131B–HIREL–02/03 L_A22 PCI_SERR LocalBusAddress22 O Inthelocaladdressbus,bit14ismostsignificantandbit31isleast significant. PCISystemError I/O AssertionofthispinindicatesthataPCIsystemerrorwasdetected duringaPCItransfer. L_A23 PCI_REQ0 LocalBusAddress23 O Inthelocaladdressbus,bit14ismostsignificantandbit31isleast significant. PCIArbiterRequest0 I/O WhenPowerQUICCII’sinternalPCIarbiterisused,thisisaninputpin. InthismodeassertionofthispinindicatesthatanexternalPCIagentis requestingthePCIbus.WhenanexternalPCIarbiterisused,thisisan outputpin.InthismodeassertionofthispinindicatesthatPowerQUICC II’sPCIinterfaceisrequestingthePCIbus. L_A24 PCI_REQ1 LocalBusAddress24 O Inthelocaladdressbus,bit14ismostsignificantandbit31isleast significant. PCIArbiterRequest1 I WhenPowerQUICCII’sinternalPCIarbiterisused,assertionofthispin indicatesthatanexternalPCIagentisrequestingthePCIbus. L_A25 PCI_GNT0 LocalBusAddress25 O Inthelocaladdressbus,bit14ismostsignificantandbit31isleast significant. PCIArbiterGrant0 I/O WhenPowerQUICCII’sinternalPCIarbiterisused,thisisanoutputpin. Inthismode,assertionofthispinindicatesthatanexternalPCIagent thatrequestedthePCIbuswiththeREQ0pinisgrantedthebus.When anexternalPCIarbiterisused,thisisaninputpin.Inthismode, assertionofthispinindicatesthatPowerQUICCII’sPCIinterfaceis grantedthePCIbus. L_A26 PCI_GNT1 LocalBusAddress26 O Inthelocaladdressbus,bit14ismostsignificantandbit31isleast significant. PCIArbiterGrant1 O WhenPowerQUICCII’sinternalPCIarbiterisused,assertionofthispin indicatesthattheexternalPCIagentthatrequestedthePCIbuswiththe REQ1pinisgrantedthebus. L_A27 CLKOUT LocalBusAddress27 O Inthelocaladdressbus,bit14ismostsignificantandbit31isleast significant. ClockOutputpin O InaPCIsystemwherePC8260’sPCIinterfaceisconfiguredtooperate fromanexternalPCIclock,the60xbusclockisdrivenonCLKOUT.Ina PCIsystemwherethePC8260’sPCIinterfaceisconfiguredtogenerate thePCIclock,thePCIclockisdrivenonCLKOUT.ThePCIclock frequencyrangeis25-66MHz. L_A28 PCI_RST CORE_SRESET LocalBusAddress28 O Inthelocaladdressbusbit14ismostsignificantandbit31isleast significant. PCIReset I/O WhenthePC8260isthehostinthePCIsystem,PCI_RST isanoutput. WhenthePC8260isnotthehostofthePCIsystem,PCI_RSTisan input. CoreSystemReset I Thisaninputtothecore.Whenthisinputpinisassertedthecore branchestoitsresetvector. Table4.ExternalSignals(Continued) Pin SignalName Type Description

30 PC8260PowerQUICCII

2131B–HIREL–02/03 L_A29 PCI_INTA LocalBusAddress29 O Inthelocaladdressbus,bit14ismostsignificantandbit31isleast significant. PCIINTA I/O WhenthePowerQUICCIIisthehostinthePCIsystem,thispinisan inputfordeliveringPCIinterruptstothehost.WhenthePowerQUICCII isnotthehostofthePCIsystem,thispinisanoutputusedbythe PowerQUICCIItosignalaninterrupttothePCIhost. L_A30 LocalBusAddress30 O Inthelocaladdressbus,bit14ismostsignificantandbit31isleast significant. L_A31 DLLSYNC LocalBusAddress31 O Inthelocaladdressbus,bit14ismostsignificantandbit31isleast significant. DLLSynchronization I DLLSYNCisusedtoeliminateskewfortheclockdrivenonCLKOUT. LCL_D[0:31] PCI_AD[0:31] LocalBusData I/O Inthelocaldatabus,bit0ismostsignificantandbit31isleast significant. PCIAddressData I/O PCIbusaddressdatainput/outputpins.InthePCIaddressdatabus,bit 31ismostsignificantandbit0isleastsignificant. LCL_DP[0:3] PCI_C/BE[0:3] LocalBusDataParity I/O InlocalbuswriteoperationsthePowerQUICCIIdrivesthesepins.In localbusreadoperationstheaccesseddevicedrivesthesepins. LCL_DP(0)isdrivenwithavaluethatgivesoddparitywithLCL_D(0:7). LCL-DP(1)isdrivenwithavaluethatgivesoddparitywithLCL_D(8:15). LCL_DP(2)isdrivenwithavaluethatgivesoddparitywith LCL_D(16:23). LCL_DP(3)isdrivenwithavaluethatgivesoddparitywith LCL_D(24:31) PCPCommand/Byte Enable I/O ThePowerQUICCIIdrivesthesepinswhenitistheinitiatorofaPCI transfer. IRQ0 NMI_OUT Interruptrequest0 I Thisinputisoneoftheeightexternallinesthatcanrequest(bymeansof theNMI-OUTinternalinterruptcontroller)aserviceroutinefromthe core. NonMaskableInterrupt Output O ThisisanoutputdrivenfromPowerQUICCII’sinternalinterrupt controller.Assertionofthisoutputindicatesthatanunmaskedinterrupt ispendinginPowerQUICCII’sinternalinterruptcontroller. IRQ7 INT_OUT APE InterruptRequest7 I Thisinputisoneoftheeightexternallinesthatcanrequest(bymeansof theinternalinterruptcontroller)aserviceroutinefromthecore. InterruptOutput O ThisisanoutputdrivenfromPowerQUICCII’sinternalinterrupt controller.Assertionofthisoutputindicatesthatanunmaskedinterrupt ispendinginPowerQUICCII’sinternalinterruptcontroller. AddressParityError O ThisoutputpinwillbeassertedwhenthePowerQUICCII’sdetects wrongparitydrivenonitsaddressparitypinsbyanexternalmaster TRST TestReset(JTAG) I ThisistheresetinputtoPowerQUICCII’sJTAG/COPcontroller. TCK TestClock(JTAG) I ThispinprovidestheclockinputforPowerQUICCII’sJTAG/COP controller. TMS TestModeSelect(JTAG) I ThispincontrolsthestateofPowerQUICCII’sJTAG/COPcontroller. TDI TestDataIn(JTAG) I ThispinisthedatainputtoPowerQUICCII’sJTAG/COPcontroller. TDO TestDataOut(JTAG) O ThispinisthedataoutputfromPowerQUICCII’sJTAG/COPcontroller. Table4.ExternalSignals(Continued) Pin SignalName Type Description

2131B–HIREL–02/03 TRIS ThreeState I AssertingTRIS forcesallotherPowerQUICCII’spinstohighimpedance state. PORESET Power-onReset I Whenasserted,thisinputlinecausesthePowerQUICCIItoenter power-onresetstate. HRESET HardReset I/O Thisopendrainline,whenasserted,causesthePowerQUICCIItoenter hardresetstate. SRESET SoftReset I/O Thisopendrainline,whenasserted,causesthePowerQUICCIItoenter softresetstate. QREQ QuiescentRequest O ThispinindicatesthatPowerQUICCII’sinternalcoreisabouttoenterits lowpowermode.InthePowerQUICCII,thispinwillbetypicallyusedfor debugpurposes. RSTCONF ResetConfiguration I ThisinputlienissampledbythePowerQUICCIIduringtheassertionof theHRESETsignal.Ifthelineisasserted,theconfigurationmodeis sampledintheformofthehardresetconfigurationworddrivenonthe databus.Whenthislineisnegated,thedefaultconfigurationmodeis adoptedbythePowerQUICCII.Noticethattheinitialbaseaddressof internalregistersisdeterminedinthissequence. MODCK1 AP[1] TC[0] BNKSEL[0] ClockModeInput I Definestheoperatingmodeofinternalclockcircuits. AddressParity1 I/O The60xmasterthatdrivestheaddressbus,alsodrivestheaddress paritysignals.Thevaluedrivenontheaddressparity1pinshould provideoddparity(oddnumberof1’s)onthegroupofsignalsthat includesaddressparity1and[A8:15]. TransferCode0 O Thetransfercodeoutputpinssupplyinformationthatcanbeusefulfor debugpurposesforeachofthePowerQUICCIIinitiatedbus transactions. BankSelect0 O ThebankselectoutputsareusedforselectingSDRAMbankwhenthe PowerQUICCIIisin60xcompatiblebusmode. MODCK2 AP[2] TC[1] BNKSEL[1] ClockModeInput I Definestheoperatingmodeofinternalclockcircuits. AddressParity2 I/O The60xmasterthatdrivestheaddressbus,alsodrivestheaddress paritysignals.Thevaluedrivenontheaddressparity2pinshould provideoddparity(oddnumberof1’s)onthegroupofsignalsthat includesaddressparity2and[A16:23]. TransferCode1 O Thetransfercodeoutputpinssupplyinformationthatcanbeusefulfor debugpurposesforeachofthePowerQUICCIIinitiatedbus transactions. BankSelect1 O ThebankselectoutputsareusedforselectingSDRAMbankwhenthe PowerQUICCIIisin60xcompatiblebusmode. Table4.ExternalSignals(Continued) Pin SignalName Type Description

32 PC8260PowerQUICCII

2131B–HIREL–02/03 MODCK3 AP[3] TC[2] BNKSEL[2] ClockModeInput I Definestheoperatingmodeofinternalclockcircuits. AddressParity3 I/O The60xmasterthatdrivestheaddressbus,alsodrivestheaddress paritysignals.Thevaluedrivenontheaddressparity3pinshould provideoddparity(oddnumberof1’s)onthegroupofsignalsthat includesaddressparity3and[A24:314]. TransferCode2 O Thetransfercodeoutputpinssupplyinformationthatcanbeusefulfor debugpurposesforeachofthePowerQUICCIIinitiatedbus transactions. BankSelect2 O ThebankselectoutputsareusedforselectingSDRAMbankwhenthe PowerQUICCIIisin60xcompatiblebusmode. XFC ExternalFilterCapacitance I InputconnectionforanexternalcapacitorfilterforPLLcircuity. CLKIN ClockIn I PrimaryclockinputtoPowerQUICCII’sPLL. PA[0:31] PortABits0:31 I/O GeneralPurposeI/OPort PB[4:31] PortBBits4:31 I/O GeneralPurposeI/OPort PC[0:31] PortCBits0:31 I/O GeneralPurposeI/OPort PD[4:31] PortDBits4:31 I/O GeneralPurposeI/OPort VDD VDDH VCCSYN GNDSYN VCCSYN1 PowerSupply PowerSupply PowerSupply SpecialGround PowerSupply Powersupplyoftheinternallogic PowersupplyoftheI/Obuffers PowersupplyofthePLLcircuity SpecialgroundofthePLLcircuity Powersupplyofthecore’sPLLcircuity Table4.ExternalSignals(Continued) Pin SignalName Type Description

2131B–HIREL–02/03 ApplicableDocuments 1. MIL-STD-883:Testmethodsandproceduresforelectronics. 2. SQ32S0100.0:Qualitylevelsforsuppliedcomponents. Requirements General Themicrocircuitsareinaccordancewitht heapplicabledocumentsandasspecified herein. TerminalConnections TheterminalconnectionsareshowninTable2onpage8. AbsoluteMaximumRatings Note: Absolutemaximumratingsarestressratingsonly.Functionaloperation(seeTableon page34)atthemaximumsisnotguaranteed.Stressbeyondthoselistedmayaffect devicereliabilityorcausepermanentdamage. Warning VINmustnotexceedV DDHbymorethan2.5Vatanytime,includingduringpower-on reset.VDDHmustnotexceedVDD/VCCSYNbymorethan1.6Vatanytime,includingduring power-onreset.V DD/VCCSYN mustnotexceedV DDHbymorethan0.4Vatanytime, includingduringpower-onreset.Itisrecommendedtouseabootstrapdiodebetween thepowerrails,asshowninFigure3. Figure3.BootstrapDiodesforPower-upSequencing SelectthebootstrapdiodessothatanominalV DD/VCCSYN issourcedfromtheV DDH powersupplyuntiltheV DD/VCCSYN powersupplybecomesactive.InFigure3,two MUR420Schottkybarrierdiodesareconnectedinaseries;eachhasaforwardvoltage F)of0.6Vathighcurrents,andsoprovidesa1.2Vdrop,maintaining2.1Vonthe2.5V powerline.Oncethecore/PLLpowersupplystabilizesat2.5V,thebootstrapdiode(s) willbereversebiasedwithnegligibleleakagecurrent. Table5.MaximumRatings Symbol Rating Value Unit VDD CoreSupplyVoltage -0.3/2.75 V VCCSYN PLLSupplyVoltage -0.3/2.75 V VDDH I/OSupplyVoltage -0.3/3.6 V VIN InputVoltage (GND-0.3)/3.6 V TSTG StorageTemperatureRange -65/+150 °C MUR420 MUR420 2.5V(VDD/VCCSYN) 3.3V (VDDH)I/O Power Core/Pll Power

34 PC8260PowerQUICCII

2131B–HIREL–02/03 Theforwardvoltageshouldbeeffectiveatthecurrentlevelsneededbytheprocessor, approximately2-3amps.Thatis,donotusediodeswithonlyanominalVFwhichdrops toolowathighcurrent. RecommendedOperating Conditions Note: Therecommendedandtestedoperatingconditions.Properdeviceoperationoutsideof theseconditionsisnotguaranteed. Thisdevicecontainscircuitrytoprotectagainstdamageduetohighstaticvoltageor electricalfields.However,itisadvisedthatnormalprecautionsbetakentoavoidappli- cationofanyvoltageshigherthanmaximum-ratedvoltagestothishigh-impedance circuit.Operationalreliabilityisenhanced ifunusedinputsaretiedtoanappropriate logicvoltagelevel(eitherGNDorV CC). Notes: 1. Assumesasinglelayerboardwithnothermalbias 2. Naturalconvection 3. Assumesafourlayerboard Table6.RecommendedOperationalVoltageConditions Symbol Rating 2.5VDevice Unit VDD CoreSupplyVoltage 2.4/2.7 V VCCSYN PLLSupplyVoltage 2.4/2.7 V VDDH I/OSupplyVoltage 3.15/3.465 V VIN InputVoltage GND-0.3/3.6 V TJ JunctionTemperature -55/+125 °C Table7.ThermalCharacteristics Symbol Characteristics Value Unit AirFlow Θ JA ThermalResistanceforTBGA 13.5 (1) °C/W NC (2) Θ JA 11.0(1) °C/W 1m/s Θ JA 10.8(3) °C/W NC Θ JA 8.5(3) °C/W 1m/s

2131B–HIREL–02/03 PowerConsiderations Theaveragechip-junctiontemperature,TJ,in°Ccanbeobtainedfromthefollowing: ( 1 ) where T A=ambienttemperature°C QJA=packagethermalresistance,junctiontoambient,°C/W PD=PINT+PI/O PINT=IDDxVDDWatts–chipinternalpower PI/O=powerdissipationoninputandoutputpins–userdetermined Canbeneglectedformostapplications.IfPI/Oisneglected,anapproximaterelationship betweenPDandTJisthefollowing: PD=K/(TJ+273°C) (2) Solvingequations(1)and(2)forKgives: (3) WhereKisaconstantpertainingtotheparticularpart.Kcanbedeterminedfromequa- tion(3)bymeasuringP D(atequilibrium)foraknownT A.UsingthisvalueofK,the valuesofPDandTJcanbeobtainedbysolvingequations(1)and(2)iterativelyforany valueofTA. LayoutPractices EachV CCpinonthePC8260shouldbeprovidedwithalow-impedancepathtothe board’spowersupply.Eachgroundpinshouldlikewisebeprovidedwithalow-imped- ancepathtoground.Thepowersupplypinsdrivedistinctgroupsoflogiconchip.The V CCpowersupplyshouldbebypassedtogroundusingatleastfour0.1µFby-pass capacitorslocatedascloseaspossibletothefoursidesofthepackage.Thecapacitor leadsandassociatedprintedcircuittracesconnectingtochipV CCandgroundshouldbe kepttolessthanhalfaninchpercapacitorlead.Afour-layerboardisrecommended, employingtwoinnerlayersasV CCandGNDplanes. AlloutputpinsonthePC8260havefastriseandfalltimes.Printedcircuit(PC)trace interconnectionlengthshouldbeminimizedinordertominimizeundershootandreflec- tionscausedbythesefastoutputswitchi ngtimes.Thisrecommendationparticularly appliestotheaddressanddatabusses.MaximumPCtracelengthsofsixinchesare recommended.Capacitancecalculationsshouldconsideralldeviceloadsaswellas parasiticcapacitancesduetothePCtraces.AttentiontoproperPCBlayoutandbypass- ingbecomesespeciallycriticalinsystems withhighercapacitiveloadsbecausethese loadscreatehighertransientcurrentsintheV CCandGNDcircuits.Pullupallunused inputsorsignalsthatwillbeinputsduringre set.Specialcareshouldbetakentomini- mizethenoiselevelsonthePLLsupplypins. TJ TA PD Θ JA•()+= PIO⁄ 0,3 PINT•< KP D TA 273°C+()•Θ PD• 2+=

36 PC8260PowerQUICCII

2131B–HIREL–02/03 ElectricalCharacteristics DCElectricalSpecification ThissectiondescribestheDCelectricalch aracteristicsforthePC8260.Themeasure- mentsinTable8assumethefollowingsystemconditions: TC=-55°Cto+125°C VDD=2.0±5%VDC VDDH=3.3±5%VDC GND=0VDC TheleakagecurrentismeasuredfornominalVDDHandVDD,orboth.VDDHandVDDmust varyinthesamedirection(forexample,bothVDDHandVDDvarybyeither+5%or-5%). Table8.DCElectricalCharacteristics Symbol Characteristic Min Max Unit VIH InputHighVoltage,AllInputsExceptCLKIN 2.0 3.465 V VIL InputLowVoltage GND 0.8 V VIHC CLKINInputHighVoltage 2.4 3.465 V VILC CLKINInputLowVoltage GND 0.4 V IIN InputLeakageCurrent,VIN=VDDH 10 µA IOZ Hi-Z(offstate)LeakageCurrent,VIN=VDDH 10 µA IL SignalLowInputCurrent,VIL=0.8V TBD TBD µA IH SignalHighInputCurrent,VIH=2.0V TBD TBD µA VOH OutputHighVoltage,IOH=-2mA ExceptXFC,andOpenDrainPins 2.4 V

2131B–HIREL–02/03 VOL IOL=7.0mA BR BG ABB/IRQ2 TS A[0:31] TT[0:4] TBST TSIZE[0:3] AACK ARTRY DBG DBB/IRQ3 D[0:63] DP(0)/RSRV DP(1)/IRQ1 DP(2)/TLBISYNC/IRQ2 DP(3)/IRQ3 DP(4)/IRQ4 DP(5)/TBEN/IRQ5 DP(6)/CSE(0)/IRQ6 DP(7)/CSE(1)/IRQ7 PSDVAL TA TEA GBL/IRQ1 CI/BADDR29/IRQ2 WT/BADDR30/IRQ3 L2_HIT/IRQ4 CPU_BG/BADDR31/IRQ5 CPU_DBG CPU_BR IRQ0 /NMI_OUT IRQ7/INT_OUT/APE PORESET SRESET RSTCONF QREQ 0.4 V Table8.DCElectricalCharacteristics(Continued) Symbol Characteristic Min Max Unit

38 PC8260PowerQUICCII

2131B–HIREL–02/03 VOL IOL=5.3mA CS[0:9] CS(10)/BCTL1 CS(11)/AP(0) BADDR[27–28] ALE BCTL0 PWE(0:7)/PSDDQM(0:7)/PBS(0:7) PSDA10/PGPL0 PSDWE/PGPL1 POE/PSDRAS/PGPL2 PSDCAS/PGPL3 PGTA/PUPMWAIT/PGPL4/PPBS PSDAMUX/PGPL5 LWE[0–3]LSDDQM(0:3)/LBS([0–3] LSDA10/LGPL0 LSDWE/LGPL1 LOE/LSDRAS/LGPL2 LSDCAS/LGPL3 LGTA/LUPMWAIT/LGPL4/LPBS LGPL5 LWR MODCK1/AP(1)/TC(0)/BNKSEL(0) MODCK2/AP(2)/TC(1)/BNKSEL(1) MODCK3/AP(3)/TC(2)/BNKSEL(2) IOL=3.2mA L_A14 L_A15/SMI L_A16 L_A17/CKSTP_OUT L_A18 L_A19 L_A20 L_A21 L_A22 L_A23 L_A24 L_A25 L_A26 L_A27 L_A28/CORE_SRESET 0.4 V Table8.DCElectricalCharacteristics(Continued) Symbol Characteristic Min Max Unit

2131B–HIREL–02/03 VOL L_A29 L_A30 L_A31 LCL_D(0:31) LCL_DP(0:3) PA[0:31] PB[4:31] PC[0:31] PD[4:31] TDO 0.4 V Table8.DCElectricalCharacteristics(Continued) Symbol Characteristic Min Max Unit

40 PC8260PowerQUICCII

2131B–HIREL–02/03 ACElectricalSpecifications Includedinthissectionareillustrationsandtablesofclockdiagrams,signals,andCPM outputsandinputs.NotethatACtimingsarebasedona50pFload.Typicaloutput bufferimpedancesareshowninTable9. Note: Thesearetypicalvaluesat65°C.Theimpedancemayvaryby±25%withprocessand temperature. Althoughthespecificationsgenerallyrefertotherisingedgeoftheclock,thefollowing ACtimingdiagramsalsoapplywhenthefallingedgeistheactiveedge. Figure4.FCCExternalClockDiagram Figure5.FCCInternalClockDiagram Table9.OutputBufferImpedances OutputBuffers TypicalImpedance (Ω) 60xbus 40 Localbus 40 MemoryController 40 ParallelI/O 46 PCI 25 FCC Output Signals FCC Input Signals sp36b/sp37b sp17b sp16b Serial CLKin FCC Output Signals FCC Input Signals sp36a/sp37a sp17a sp16a BRG_OUT

2131B–HIREL–02/03 Figure6.SCC/SMCSPI/I2CExternalClock Figure7.SCC/SMC/SPI/I2CInternalClockDiagram Figure8.PIO,TimerandDMASignalDiagram sp18 sp19b sp38b/sp39b SCC/SMCSPI/I2C Output Signals SCC/SMCSPI/I2C Input Signals Serial CLKin sp38a/sp39a sp19asp18a BRG_OUT SCC/SMC/SPI/I2C Input Signals SCC/SMC/SPI/I2C Output Signals sp23 sp42/sp43 sp42 sp22 CLKin PIO/TIMER/DMA Input Signals PIO/TIMER/DMA Output Signals PIO Output Signals

42 PC8260PowerQUICCII

2131B–HIREL–02/03 Figure9.TDMSignalDiagram Note: Outputspecificationsaremeasuredfromthe1.4VleveloftherisingedgeofCLKINtothe TTLlevel(0.8or2.0V)ofthesignal.Timingismeasuredatthepin. Note: InputspecificationsaremeasuredfromtheTTLlevel(0.8or2.0V)ofthesignaltothe1.4 leveloftherisingedgeofCLKIN.Timingismeasuredatthepin. Table10.ACCharacteristicsforCPMOutputs Spec_num Characteristics MaxDelay(ns) MinDelay(ns) sp36a/sp37a FCCOutputs–Internalclock (NMSI) sp36b/sp37b FCCOutputs–Externalclock (NMSI) 18 2 sp40/sp41 TDMOutputs 35 5 sp38a/sp39a SCC/SMC/SPI/I2COutputs– InternalClock(NMSI) 20 0 sp38b/sp39b EX_SCC/SMC/SPI/I2COutputs– ExternalClock(NMSI) 30 0 sp42/sp43 PIO/TIMER/DMAOutputs 14 1 Table11.ACCharacteristicsforCPMInputs Spec_num Characteristics Setup(ns) Hold(ns) sp16a/sp17a FCCInputs–Internalclock(NMSI) 10 0 sp16b/sp17b FCCInputs–Externalclock(NMSI) 5 3 sp20/sp21 TDMInputs 20 20 sp18a/sp19a ISCC/SMC/SPI/I2CInputs– InternalClock(NMSI) 20 0 sp18b/sp19b SCC/SMC/SPI/I2CInputs– ExternalClock(NMSI) sp22/sp23 PIO/TIMER/DMAOutputs 10 3 sp40/sp41 sp21sp20 Serial CLKin TDM Input Signals TDM Output Signals

2131B–HIREL–02/03 Figure10.InteractionofBusSignals Figure11.ECCModeDiagram sp10 sp10 sp10 sp31/sp30 sp32/sp30 sp33a/sp30 sp35/sp30 All Other Output Signals DATA Bus Output Signals ADD/ADD_atr/BADDR/CI/GBL/WT Output Signals PSDVAL/TEA/TA Output Signals All Other Input Signals Data Bus Name Input Signal AACK/ARTRY/TA/TEA/DBG/BG/BR Input Signals CLKin sp11 sp12 sp15 sp33b/sp30 sp10 sp10 sp10 sp13 sp14 DP Mode Output Signal DP Mode Input Signal DATA Bus, ECC, and PARITY Mode Input Signals

44 PC8260PowerQUICCII

2131B–HIREL–02/03 Figure12.MEMCModeDiagram Note: Generally,allPC8260busandsystemoutputsignalsaredrivenfromtherisingedgeof theinputclock(CLKin).Memorycontrollersignals,however,triggeronfourpointswithin aCLKincycle.Eachcycleisdividedbyfourinternalticks:T1,T2,T3,andT4.T1always occursattherisingedgeofCLKin(andT3atthefallingedge),butthespacingofT2and T4dependsonthePLLclockratioselected,asshowninTable12. Figure13.InternalTickSpacingforMemoryControllerSignals Note: TheUPMmachineandGPCMmachineoutputschangeontheinternaltickdetermined bythememorycontrollerprogramming.TheACspecificationsarerelativetotheinternal tick.NotethatSDRAMmachineoutputschangeonlyontheCLKin’srisingedge. Table12.TickSpacingforMemoryControllerSignals PLLClockRadio TickSpacing(T1OccursattheRisingEdgeofCLKin) T2 T3 T4 1:2,1:3,1:4,1:5,1:6 1/4CLKin 1/2CLKin 3/4CLKin 1:2.5 3/10CLKin 1/2CLKin 8/10CLKin 1:3.5 4/14CLKin 1/2CLKin 11/14CLKin sp34/sp30 CLKin V_CLK Memory Controller Signals T1 T2 T3 T4 T4T3 T2T1 for 1:2.5 for 1:3.5 T4T3 T1 T2 CLKin CLKin CLKin

2131B–HIREL–02/03 Notes: 1. InputspecificationsaremeasuredfromTTLlevel(0.8or2.0V)ofthesignaltothe1.4 leveloftherisingedgeofCLKIN. 2. Timingsaremeasuredatthepins. Notes: 1. Outputspecificationsaremeasuredfromthe1.4VleveloftherisingedgeofCLKINto theTTLlevel(0.8or2.0V)ofthesignal. 2. Timingsaremeasuredatthepin. Activatingdatapipelining(settingBRx[DR]i nthememorycontroller)improvestheAC timing.Whendatapipeliningisactivated,sp12canbeusedfordatabussetupeven whenECCorPARITYareused.Also,sp33acanbeusedastheACspecificationforDP signals. Table13.ACCharacteristicsforSIUInputs Spec_num Characteristics Setup(ns) Hold(ns) sp11/sp10 AACK /ARTRY/TA/TEA/DBG/BG/BR 61 sp12/sp10 DataBusinNormalmode 5 1 sp13sp10 DataBusinECCandPARITYModes 8 1 sp14/sp10 DPpins 8 1 sp15/sp10 AllOtherPins 5 1 Table14.ACCharacteristicsforSIUOutputs Spec_num Characteristics MaxDelay(ns) MinDelay(ns) sp31/sp30 PSDVAL /TEA/TA 10 1 sp32/sp30 ADD/ADD_atr./BADDR/CIGBL/WT 8 1 sp33a/sp30 DataBus 8 1 sp33b/sp30 DP 12 1 sp34/sp10 MemcSignals/ALE 6 1 sp35/sp10 AllOtherSignals 7 1

46 PC8260PowerQUICCII

2131B–HIREL–02/03 ClockConfigurationModes ToconfigurethemainPLLmultiplicationfactorandthecore,CPM,and60xbusfrequencies,theMODCK[1:3]pinsare sampledwhileHRESETisasserted.Table15showstheeightbasicconfigurationmodes.Another49modesareavailable byusingtheconfigurationpin(RSTCONF)anddrivingfourpinsonthedatabus. Table15.ClockDefaultModes MODCK[1–3] InputClock Frequency (MH)z CPMMultiplication Factor CPM Frequency (MHz) CoreMultiplication Factor Core Frequency (MHz) 000 33 3 100 4 133 001 33 3 100 5 166 010 33 4 133 4 133 011 33 4 133 5 166 100 66 2 133 2.5 166 101 66 2 133 3 200 110 66 2.5 166 2.5 166 111 66 2.5 166 3 200 Table16.ClockConfigurationModes MODCK_H– MODCK[1–3] InputClock Frequency (MHz) CPMMultiplication Factor CPM Frequency (MHz) CoreMultiplicationFactor Core Frequency (MHz) 0001_000 33 2 66 4 133 0001_001 33 2 66 5 166 0001_010 33 2 66 6 200 0001_011 33 2 66 7 233 0001_100 33 2 66 8 266 0001_101 33 3 100 4 133 0001_110 33 3 100 5 166 0001_111 33 3 100 6 200 0010_000 33 3 100 7 233 0010_001 33 3 100 8 266 0010_010 33 4 133 4 133 0010_011 33 4 133 5 166 0010_100 33 4 133 6 200 0010_101 33 4 133 7 233 0010_110 33 4 133 8 266

2131B–HIREL–02/03 0010_111 33 5 166 4 133 0011_000 33 5 166 5 166 0011_001 33 5 166 6 200 0011_010 33 5 166 7 233 0011_011 33 5 166 8 266 0011_100 33 6 200 4 133 0011_101 33 6 200 5 166 0011_110 33 6 200 6 200 0011_111 33 6 200 7 233 0100_000 33 6 200 8 266MHz 0100_001 Reserved 0100_010 0100_011 0100_100 0100_101 0100_110 0100_111 Reserved 0101_000 0101_001 0101_010 0101_011 0101_100 0101_101 66 2 133 2 133 0101_110 66 2 133 2.5 166 0101_111 66 2 133 3 200 0110_000 66 2 133 3.5 233 0110_001 66 2 133 4 266 0110_010 66 2 133 4.5 300 0110_011 66 2.5 166 2 133 0110_100 66 2.5 166 2.5 166 Table16.ClockConfigurationModes(Continued) MODCK_H– MODCK[1–3] InputClock Frequency (MHz) CPMMultiplication Factor CPM Frequency (MHz) CoreMultiplicationFactor Core Frequency (MHz)

48 PC8260PowerQUICCII

2131B–HIREL–02/03 Notes: 1. Thistabledescribesallpossibleclockconfigurationswhenusingthehardresetconfigurationsequence.Notethatcloc k configurationchangesonlyafterPORisasserted. 2. Becauseofspeeddependencies,notallofthepossibleconfigurationsinthistablemaybeapplicable. 3. The66MHzconfigurationsarerequiredforinputclockfrequencieshigherthan50MHz.33MHzconfigurationsarerequired forinputclockfrequenciesbelow50MHz. 4. Theusershouldchoosetheinputclockfrequency,andthemultiplicationfactoroftheCPMsothatthefrequencyoftheCPM willbebetween50MHzand166MHzfora2Vpart,andbetween66MHzand233MHzfora2.5Vpart. 0110_101 66 2.5 166 3 200 0110_110 66 2.5 166 3.5 233 0110_111 66 2.5 166 4 266 0111_000 66 2.5 166 4.5 300 0111_001 66 3 200 2 133 0111_010 66 3 200 2.5 166 0110_101 66 2.5 166 3 200 0110_110 66 2.5 166 3.5 233 0110_111 66 2.5 166 4 266 0111_000 66 2.5 166 4.5 300 0111_001 66 3 200 2 133 0111_010 66 3 200 2.5 166 0111_011 66 3 200 3 200 0111_100 66 3 200 3.5 233 0111_101 66 3 200 4 266 0111_110 66 3 200 4.5 300 0111_111 66 3.5 233 2 133 1000_000 66 3.5 233 2.5 166 1000_001 66 3.5 233 3 200 1000_010 66 3.5 233 3.5 233 1000_011 66 3.5 233 4 266 1000_100 66 3.5 233 4.5 300 Table16.ClockConfigurationModes(Continued) MODCK_H– MODCK[1–3] InputClock Frequency (MHz) CPMMultiplication Factor CPM Frequency (MHz) CoreMultiplicationFactor Core Frequency (MHz)

2131B–HIREL–02/03 Status LimitingValues LimitingvaluesgivenareinaccordancewiththeAbsoluteMaximumRatingSystem (IEC134).Stressaboveoneormoreofthelimitingvaluesmaycausepermanentdam- agetothedevice.Thesearestressratingsonlyandoperationofthedeviceattheseor atanyotherconditionsabovethosegivenintheCharacteristicssectionsofthespecifi- cationisnotimplied.Exposuretolimitingvaluesforextendedperiodsmayaffectdevice reliability. ApplicationInformation Whereapplicationinformationisgiven,itisadvisoryanddoesnotformpartofthe specification. LifeSupportApplications Theseproductsarenotdesignedforuseinlifesupportappliances,devices,orsystems wheremalfunctionoftheseproductscanreas onablybeexpectedtoresultinpersonal injury.ATMEL-Grenoblecustomersusingorsellingtheseproductsforuseinsuchappli- cationsdosoattheirownriskandagreetofullyindemnifyAtmel-Grenobleforany damagesresultingfromsuchimproperuseorsale. Table17.DatasheetStatus DatasheetStatus Validity ObjectiveSpecification Thisdatasheetcontainstargetandgoalspecificationfor discussionwithcustomerandapplicationvalidation. Validbeforedesignphase TargetSpecification Thisdatasheetcontainstargetorgoalspecificationsfor productdevelopment. Validduringthedesignphase PreliminarySpecification∝ Site Thisdatasheetcontainspreliminarydata.Additionaldata maybepublishedlater.Thiscouldincludesimulation results. Validbeforethecharacterization phase PreliminarySpecification β Site Thisdatasheetalsocontainscharacterizationresults. Validbeforetheindustrialization phase. ProductSpecification Thisdatasheetcontainsfinalproductspecifications. Validforproductionpurposes

50 PC8260PowerQUICCII

2131B–HIREL–02/03 PackageDimensionsTBGA480 B A C ± E ± ± F ± 0.150 ± T ± T HG A C E G J L N R U W AA AC AE All measurements are in mm. Top V iew B D F H K M P T V Y AB AD AF CORNER K L Bottom V iew K INDEX 480X ϕ D AGAH 2 8 2 6 2 4 2 2 2 0 1 8 1 6 1 4 1 2 1 0 8642 2 9 2 7 2 5 2 3 2 1 1 9 1 7 1 5 1 3 1 1 97531 AJ 4X 0.2 A B C D G H K L MIN MAX

37.5 BSC

1.45 1.65 0.65 0.85

1.27 BSC

0.85 0.95

35.56 BSC

0.50 0.70 Notes: 1. Dimensions and tolerancing per asme Y14.5M-1994. 2. Dimensions in millimeters. 3. Dimension b is measured at the maximum solder ball diameter. Parallel to primary datum A. 4. Primary datum A and the seating plane are defined by the spherical crowns of the solder balls.

2131B–HIREL–02/03 OrderingInformation RevisionA1 Prefix(1) Temperature Range: Tj Screening Level(2) Package PC 8260 M TP 200 M: -55, +125 ˚C V: -40, +110 ˚C U TP: TBGA Max. Internal Processor Speed(2) 200/200 MHz 150/150 MHz (1) Atmel-Grenoble (2) U: Upscreening (X) Type Prototype (A1 ) Revision Level For availability of the different versions, contact your sales office.

52 PC8260PowerQUICCII

2131B–HIREL–02/03 RevisionB1andAbove Prefix(1) Temperature Range: Tj Package: PC 8260 M TP IFB M: -55, +125 °C V: -40, +110 °C U TP: TBGA A = 50, B = 66, C= 75 D = 83, E = 100, F = 133 G = 150, H = 166, I = 200 J = 233, K = 266, L = 300 M = 333 U: Upscreening (X) Type Prototype Revision Level V = 1.8 V ± 0.1 Volt (1) Atmel-Grenoble (2) For availability of the different versions, contact your sales office. Screening Level(2) CPU/CPM/Bus Speed (MHz) Core Voltage

Printedonrecycledpaper. ©AtmelCorporation2003. AtmelCorporationmakesnowarrantyfortheuseofitsproducts ,otherthanthoseexpresslycont ainedintheCompany’sstandard warranty whichisdetailedinAtmel’sTermsandC onditionslocatedontheCompany’swebsite. TheCompanyassumesnoresponsibilityfor anyerrors whichmayappearinthisdocument,reserves therighttochangedevicesorspecificati onsdetailedhereinatanytimewithoutn otice,anddoes notmakeanycommitmenttoupdatetheinformationcontainedherei n.NolicensestopatentsorotherintellectualpropertyofAt melaregranted bytheCompanyinconnectionwiththesaleofAtmelproducts,expr esslyorbyimplication.Atme l’sproductsarenotauthorized foruseascritical componentsinlifesupportdevicesorsystems. AtmelHeadquarters AtmelOperations CorporateHeadquarters 2325OrchardParkway SanJose,CA95131 TEL1(408)441-0311 FAX1(408)487-2600 Europe AtmelSarl RoutedesArsenaux41 CasePostale80 CH-1705Fribourg Switzerland TEL(41)26-426-5555 FAX(41)26-426-5500 Asia Room1219 ChinachemGoldenPlaza 77ModyRoadTsimshatsui EastKowloon HongKong TEL(852)2721-9778 FAX(852)2722-1369 Japan 9F,TonetsuShinkawaBldg. 1-24-8Shinkawa Chuo-ku,Tokyo104-0033 Japan TEL(81)3-3523-3551 FAX(81)3-3523-7581 Memory 2325OrchardParkway SanJose,CA95131 TEL1(408)441-0311 FAX1(408)436-4314 Microcontrollers 2325OrchardParkway SanJose,CA95131 TEL1(408)441-0311 FAX1(408)436-4314 LaChantrerie BP70602 44306NantesCedex3,France ASIC/ASSP/SmartCards ZoneIndustrielle 13106RoussetCedex,France 1150EastCheyenneMtn.Blvd. ColoradoSprings,CO80906 TEL1(719)576-3300 FAX1(719)540-1759 ScottishEnterpriseTechnologyPark MaxwellBuilding EastKilbrideG750QR,Scotland TEL(44)1355-803-000 FAX(44)1355-242-743 RF/Automotive Theresienstrasse2 Postfach3535 74025Heilbronn,Germany TEL(49)71-31-67-0 FAX(49)71-31-67-2340 1150EastCheyenneMtn.Blvd. ColoradoSprings,CO80906 TEL1(719)576-3300 FAX1(719)540-1759 Biometrics/Imaging/Hi-RelMPU/ HighSpeedConverters/RFDatacom AvenuedeRochepleine BP123 38521Saint-EgreveCedex,France e-mail literature@atmel.com WebSite http://www.atmel.com 2131B–HIREL–02/03 0M ATMEL ®istheregisteredtrademarkofAtmel. Othertermsandproductnamesmaybethetrademarksofothers.

Product Information

PC8260 specifications and overview.

Summary

PowerPC-based Communications Processors

Description

The PC8260 PowerQUICC II™ is a versatile communications processor that integrates on one chip, a high-performance PowerPC (PC603e) RISC microprocessor, a highly flexible system integration unit, and many communications peripheral controllers that can be used in a variety of applications, particularly in communications and networking systems.

Source title PC8260 Datasheet(PDF) - ATMEL Corporation

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