PC755

PC755 ATMEL | Alldatasheet

Document overview

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Technical content

Features

• 18.1SPECint95, Estimates 12.3 SPECfp95 at 400 MHz (PC755)
• 15.7SPECint95, 9SPECfp95 at 350 MHz (PC745)
• 733 MIPS at 400 MHz (PC755) at 641 MIPS at 350 MHz (PC745)
• Selectable Bus Clock (12 CPU Bus Dividers up to 10x)
• PD Typical 6.4W at 400 MHz, Full Operating Conditions
• Nap, Doze and Sleep Modes for Power Savings
• Superscalar (3 Instructions per Clock Cycle) Two Instruction + Branch
• 4 Beta Byte Virtual Memory, 4-GByte of Physical Memory
• 64-bit Data and 32-bit Address Bus Interface
• 32-KB Instruction and Data Cache
• Six Independent Execution Units
• Write-back and Write-through Operations
• fINT max = 400 MHz (TBC)
• fBUS max = 100 MHz
• Voltage I/O 2.5V/3.3V; Voltage Int 2.0V

Description

The PC755 and PC745 PowerPC ® microprocessors are high-performance, low- power, 32-bit implementations of the PowerPC Reduced Inst ruction Set Computer (RISC) architecture, especially enhanced for embedded applications. The PC755 and PC745 microprocessors differ only in that the PC755 features an enhanced, dedicated L2 cache interface with on-chip L2 tags. The PC755 is a drop-in replacement for the award winning PowerPC 750 ™ microprocessor and is footprint and user software code compatible with the MPC7400 microprocessor with AltiVec ™ technology. The PC745 is a drop-in replacement for the PowerPC 740 ™ microproces- sor and is also footprint and user software code compatible with the PowerPC 603e ™ microprocessor. PC755/745 microprocesso rs provide on-chip debug support and are fully JTAG-compliant. The PC745 microprocessor is pin compatible with the TSPC603e family. ZF suffix PBGA255 Flip-Chip Plastic Ball Grid Array ZF suffix PBGA360 Flip-Chip Plastic Ball Grid Array G suffix CBGA360 Ceramic Ball Grid Array GH suffix HITCE 360 Ceramic Ball Grid Array GS suffix CI-CGA360 Ceramic Ball Grid Array with Solder Column Interposer (SCI) PowerPC 755/745 RISC Microprocessor PC755/745 Preliminary β-site Rev. 2138D–HIREL–06/03

2 PC755/745

• CBGA + CI-CGA + FC-PBGA up scr eenings based upon Atmel standards
• HiTCE
• Full military temperature range (Tj = -55 °C,+125°C) industrial temperature range (Tj = -40°C,+110°C) General Description Simplified Block Diagram The PC755 is targeted for low power sy stems and supports power management fea- tures such as doze, nap, sleep, and dynamic power management. The PC755 consists of a processor core and an internal L2 Tag combined with a dedicated L2 cache inter- face and a 60x bus.

Figure 1. PC755 Block Diagram

2 Instructions

2138D–HIREL–06/03 General Parameters The following list provides a summary of the general parameters of the PC755: Features This section summarizes features of the PC755’s implementation of the PowerPC archi- tecture. Major features of the PC755 are as follows:

• Branch Processing Unit – Four instructions fetched per clock – One branch processed per cycle (plus resolving 2 speculations) – Up to 1 speculative stream in execut ion, 1 additional speculative stream in fetch – 512-entry branch history table (BHT) for dynamic prediction – 64-entry, 4-way set associative Branch Target Instructi on Cache (BTIC) for eliminating branch delay slots
• Dispatch Unit – Full hardware detection of dependenc ies (resolved in the execution units) – Dispatch two instructions to six independent units (system, branch, load/store, fixed-point unit 1, fixed-point unit 2, floating-point) – Serialization control (pre dispatch, postdispatch, execution serialization)
• Decode – Register file access – Forwarding control – Partial instruction decode
• Completion – 6 entry completion buffer – Instruction tracking and peak completion of two instructions per cycle – Completion of instructions in program order while supporting out-of-order instruction execution, completion se rialization and all instruction flow changes
• Fixed Point Units (FXUs) that share 32 GPRs for Integer Operands – Fixed Point Unit 1 (FXU1)-multiply, di vide, shift, rotate, arithmetic, logical – Fixed Point Unit 2 (FXU2)-shif t, rotate, arithmetic, logical Technology 0.22 µm CMOS, six-layer metal Die size 6.61 mm x 7.73 mm (51 mm2) Transistor count 6.75 million Logic design Fully-static Packages PC745 Surface mount 255 Plastic Ball Grid Array (PBGA) PC755 Surface mount 360 Plastic Ball Grid Array (PBGA) Surface mount 360 Ceramic Ball Grid Array (CI-CGA, CBGA, HiTCE) Core power supply 2V ± 100 mV DC (nominal; some parts support core voltages down to 1.8V; see Table 5 for recommended operating conditions) I/O power supply 2.5V ± 100 mV DC or 3.3V ± 165 mV DC (input thresholds are configuration pin selectable)

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2138D–HIREL–06/03 – Single-cycle arithmetic, shifts, rotates, logical – Multiply and divide support (multi-cycle) – Early out multiply

• Floating-point Unit and a 32-entry FPR File – Support for IEEE-754 standard single and double precision floating point arithmetic – Hardware support for divide – Hardware support for denormalized numbers – Single-entry reservation station – Supports non-IEEE mode fo r time-critical operations
• System Unit – Executes CR logical instructions a nd miscellaneous system instructions – Special register transfer instructions
• Load/Store Unit – One cycle load or store cache access (byte, half-word, word, double-word) – Effective address generation – Hits under misses (one outstanding miss) – Single-cycle unaligned access within double word boundary – Alignment, zero padding, sign extend for integer register file – Floating point internal format conversion (alignment, normalization) – Sequencing for load/store multiples and string operations – Store gathering – Cache and TLB instructions – Big and Little-endian byte addressing supported – Misaligned Little-endian supported – Level 1 Cache structure – 32K, 32 bytes line, 8-way set a ssociative instruction cache (iL1) – 32K, 32 bytes line, 8-way se t associative data cache (dL1) – Cache locking for both instruction and data caches, selectable by group of ways – Single-cycle cache access – Pseudo least-recently used (PLRU) replacement – Copy-back or Write Through data cache (on a page per page basis) – Supports all PowerPC memory coherency modes – Non-Blocking instruction and data cache (one outstanding miss under hits) – No snooping of instruction cache
• Level 2 (L2) Cache Interface (not implemented on PC745) – Internal L2 cache controller and tags; external data SRAMs – 256K, 512K, and 1-Mbyte 2-way set associative L2 cache support – Copyback or write-through data cache (on a page basis, or for all L2) – Instruction-only mode and data-only mode. – 64 bytes (256K/512K) or 128 bytes (1M) sectored line size

2138D–HIREL–06/03 – Supports flow through (register-buffer) synchronous burst SRAMs, pipelined (register-register) synchronous burst SRAMs (3-1-1-1 or strobeless 4-1-1-1) and pipelined (register-register) late-write synchronous burst SRAMs – L2 configurable to direct mapped SR AM interface or split cache/direct mapped or private memory – Core-to-L2 frequency divisors of 1, 1.5, 2, 2.5, and 3 supported – 64-bit data bus – Selectable interface voltages of 2.5V and 3.3V – Parity checking on both L2 address and data

• Memory Management Unit – 128 entry, 2-way set associative instruction TLB – 128 entry, 2-way set associative data TLB – Hardware reload for TLBs – Hardware or optional software tablewalk support – 8 instruction BATs and 8 data BATs – 8 SPRGs, for assistance with software tablewalks – Virtual memory support for up to 4 hexabytes (2 52) of virtual memory – Real memory support for up to 4 gigabytes (2 32) of physical memory
• Bus Interface – Compatible with 60X processor interface – 32-bit address bus – 64-bit data bus, 32-bit mode selectable – Bus-to-core frequency multipliers of 2x , 3x, 3.5x, 4x, 4.5x, 5x, 5.5x, 6x, 6.5x, 7x, 7.5x, 8x, 10x supported – Selectable interface voltages of 2.5V and 3.3V. – Parity checking on both address and data busses
• Power Management – Low-power design with thermal requirements very similar to PC740/750. – Selectable interface voltage of 1.8V/2.0 V can reduce power in output buffers (compared to 3.3V) – Three static power saving modes: doze, nap, and sleep – Dynamic power management
• Testability – LSSD scan design – IEEE 1149.1 JTAG interface
• Integrated Thermal Management Assist Unit – One-ship thermal sensor and control logic – Thermal Management Interrupt for software regulation of junction temperature

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tion of the top surface view. Figure 2. Pinout of the PC745, 255 PBGA Package as Viewed from the Top Surface

8 PC755/745

Pinout Listings Table 1 provides the pinout listing for the PC745, 255 PBGA package. Table 1. Pinout Listing for the PC745, 255 PBGA Package

or supply voltages see Table 3.

1. These are test signals for factory use only and must be pulled up to OV DD for normal machine operation.
2. To allow for future I/O voltage changes, provide t he option to connect BVSEL independently to either OVDD (selects 3.3V) or

to OGND (selects 1.8V/2.0V).

1. Uses one of 15 existing no -connects in PC745’s 255-BGA package.
2. Internally tied to GND in the PC745 255 -BGA package to indicate to the power supply that a low -voltage processor is

present. This signal is not a power supply input. Table 1. Pinout Listing for the PC745, 255 PBGA Package (Continued)

10 PC755/745

Table 2. Pinout Listing for the PC755, 360 PBGA, CBGA and CI-CGA Packages + HiTCE(8)

Table 2. Pinout Listing for the PC755, 360 PBGA, CBGA and CI-CGA Packages + HiTCE(8) (Continued)

12 PC755/745

VIN or supply voltages see Table 5.

1. These are test signals for factory use only and must be pulled up to OV DD for normal machine operation.
2. To allow for future I/O voltage changes, provide the option to connect BVSEL and L2VSEL independently to either OV DD

(selects 3.3V) or to OGND (selects 1.8V/2.0V).

1. These pins are reserved for potential future use as additional L2 address pins.
2. Uses one of 9 existing no -connects in PC750’s 360-BGA package.
3. Internally tied to L2OV DD in the PC755 360-BGA package to indicate the power present at the L2 cache interface. This sig-

nal is not a power supply input.

1. This is different from the PC745 255-BGA package.

Figure 4. PC755 Microprocessor Signal Groups

14 PC755/745

pliance with Atmel Grenoble standard screening. Applicable Documents 1) MIL-STD-883: Test methods and procedures for electronics. 2) MIL-PRF-38535 appendix A: General specifications for microcircuits. permanent damage to the device.

1. Caution: V IN must not exceed OVDD or L2OVDD by more than 0.3V at any time including during power-on reset.
2. Caution: L2OV DD/OVDD must not exceed V DD/AVDD/L2AVDD by more than 1.6V during normal operation. During power-on

for up to 40 ms. Excursions beyond 3.3V or 40 ms are not supported.

1. Caution: V DD/AVDD/L2AVDD must not exceed L2OV DD/OVDD by more than 0.4V during normal operation. During power-on

for up to 40 ms. Excursions beyond 1.0V or 40 ms are not supported.

1. This is a DC specifications only. V IN may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure

Table 3. Absolute Maximum Ratings(1)

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ture, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance.

1. Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal.
2. Per JEDEC JESD51-6 with the board horizontal.

Table 5. Recommended Operating Conditions(1) Table 6. Package Thermal Characteristics

1. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on

the top surface of the board near the package.

1. Thermal resistance between the die and the case top surf ace as measured by the co ld plate method (MIL SPEC-883

Method 1012.1) with the calculated case temperature. The actual value of RÉýJC for the part is less than 0.1°C/W. Note: Refer to Section “Thermal Management Information“ page 19 for more details about thermal management. Table 7 provides the package thermal characteristics for the PC755, HiTCE. Notes: 1. Simulation, no convection air flow.

1. Per JEDEC JESD51-6 with the board horizontal.

• The die junction-to-case (or top-of-die for exposed silicon) thermal resistance
• The die junction-to-ball thermal resistance Figure 6 depicts the primary heat transfer path for a package with an attached heat sink mounted to a printed-circuit board. Heat generated on the active side of the ch ip is conducted through the silicon, then through the heat sink attach material (or thermal interface material), and finally to the heat sink where it is removed by forced-air convection. Since the silicon thermal resistance is quite small, for a first-order analysis, the tempera- ture drop in the silicon may be neglected. Thus, the heat sink attach material and the heat sink conduction/convective thermal resistances are the dominant terms.

Table 7. Package Thermal Characteristics for HiTCE Package Table 8. Package Thermal Characteristics for CI-CGA

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Figure 6. C4 Package with Head Sink Mounted to a Printed-circuit Board Note the internal versus external package resistance. Motorola PC755 RISC Microprocessor User’s manual. Thermal Assist Unit in the PC750 Microprocessor”.

1. The comparator settling time value must be converted into the number of CPU clocks

that need to be written into the THRM3 SPR.

1. Guaranteed by design and characterization.

Table 9. Thermal Sensor Specifications at Recommended Operating Conditions

not exceed 5.5 pounds of force. Figure 7. Package Exploded Cross-Sectional View with Several Heat Sink Options

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Figure 8. Thermal Performance of Select Thermal Interface Material mance of these thermal interface materials improves with increasing contact pressure. circuit board (see Figure 7). This spring force should not exceed 5.5 pounds of force. mechanical strength to meet equipment shock/vibration requirements.

40°C. The air temperature rise within a cabinet (T r) may be in the range of 5 to 10 °C. The thermal resistance of the thermal interface material ( θint) is typically about 1 °C/W. versus airflow velocity is shown in Figure 9. Figure 9. Thermalloy #2328B Heat Sink-to-Ambient Thermal Resistance Versus Air- maximum operating temperature of the component.

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2138D–HIREL–06/03 Though the die junction-to-ambient and the heat sink-to-ambient thermal resistances are a common figure-of-merit used for comparing the thermal performance of various microelectronic packaging te chnologies, one should exercise caution when only using this metric in determining thermal management because no single parameter can ade- quately describe three-dimensional heat flow. The final die-junction operating temperature, is not only a function of the component-level thermal resistance, but the system-level design and its operating conditions. In addition to the component’s power consumption, a number of factors affect the final operating die-junction temperature — airflow, board population (local heat flux of adjacent components), heat sink efficiency, heat sink attach, heat sink placement, nex t-level interconnect technology, system air temperature rise, altitude, etc. Due to the complexity and the many variations of system-level boundary conditions for today’s microelectronic equipment, the combined effects of the heat transfer mecha- nisms (radiation, convection and conduction) may vary widely. For these reasons, we recommend using conjugate heat transfer models for the board, as well as, system-level designs. To expedite system-level thermal analysis, several “compact” thermal-package models are available within FLOTHERM ®. These are available upon request. Power consideration Power management The PC755 provides four power modes, sele ctable by setting the appropriate control bits in the MSR and HIDO registers. The four power modes are as follows:

• Full-power: This is the default power state of the PC755. The PC755 is fully powered and the internal functional units operate at the full processor clock speed. If the dynamic power management mode is enabled, functional units that are idle will automatically enter a low-power state without affecting performance, software execution, or external hardware.
• Doze: All the functional units of the PC755 are disabled except for the time base/decrementer registers and the bus snooping logic. When the processor is in doze mode, an external asynchronous interrupt, a system management interrupt, a decrementer exception, a hard or soft reset, or machine check brings the PC755 into the full-power state. The PC755 in doze mode maintains the PLL in a fully powered state and locked to the system external clock input (SYSCLK) so a transition to the full-power state takes only a few processor clock cycles.
• Nap: The nap mode further reduces power consumption by disabling bus snooping, leaving only the time base register and the PLL in a powered state. The PC755 returns to the full-power state upon receipt of an external asynchronous interrupt, a system management interrupt, a decrementer exception, a hard or soft reset, or a machine check input (MCP). A return to full-power state from a nap state takes only a few processor clock cycles. When the processor is in nap mode, if QACK is negated, the processor is put in doze mode to support snooping.
• Sleep: Sleep mode minimizes power consumpt ion by disabling all internal functional units, after which external system logic may disable the PPL and SUSCLK. Returning the PC755 to the full-power state requires the enabling of the PPL and SYSCLK, followed by the assertion of an external asynchronous interrupt, a system management interrupt, a hard or soft reset, or a machine check input (MCP) signal after the time required to relock the PPL.

VDD power. Worst case power consumption for AVDD = 15 mW and L2AVDD = 15 mW.

1. Maximum power is measured at nominal V DD (see Table 5) while running an entirely
2. Typical power is an average value measured at the nominal recommended V DD

(see Table 5) and 65×C in a system while running a typical code sequence.

1. Not 100% tested. Characterized and periodically sampled.

Table 10. Power Consumption for PC755

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Notes: 1. Nominal voltages; See Table 5 for recommended operating conditions.

1. For processor bus signals, the reference is OV DD while L2OVDD is the reference for the L2 bus signals.
2. Excludes test signals (LSSD_MODE, L1_TSTCLK, L2_TSTCLK) and IEEE 1149.1 boundary scan (JTAG) signals.
3. Capacitance is periodically sampled rather than 100% tested.
4. The leakage is measured for nominal OV DD and VDD, or both OVDD and VDD must vary in the same direction (for example,

both OVDD and VDD vary by either +5% or -5%). maximum processor core frequency. Table 11. DC Electrical Specifications at Recommended Operating Conditions (see Table 5)

26 PC755/745

“L2 Clock AC Specifications» page 28. measured at the pin; time-of-flight delays must be added for trace lengths, vias, and connectors in the system.

1. THe symbology used for timing specifications herein follows the pattern of t (signal)(state)(reference)(state) for inputs and
2. The setup and hold time is with re spect to the rising edge of HRESET (see Figure 11).
3. This specification is for configuration mode select only. Also note that the HRESET must be held asserted for a minimum of

255 bus clocks after the PLL re-lock time during the power-on reset sequence.

1. t SYSCLK is the period of the external clock (SYSCLK) in nanoseconds (ns). The numbers given in the table must be multiplied

by the period of SYSCLK to compute the actual time duration (in nanoseconds) of the parameter in question.

1. Mode select signals are BVSEL, L2VSEL, PLL_CFG[0 -3]
2. Guaranteed by design and characterization.
3. Bus mode select pins must remain stable during operation. Changing the logic states of BVSEL or L2VSEL during operation

not supported. Once HRESET is negated the states of the bus mode selection pins must remain stable. Figure 11 provides the mode select input timing diagram for the PC755. Figure 11. Mode Input Timing Diagram Table 13. Processor Bus Mode Selection AC Timing Specifications(1)

28 PC755/745

Figure 13 provides the input/output timing diagram for the PC755. Figure 13. Input/Output Timing Diagram aligned with the PC755 core clock at the SRAMs. bus loading, and printed circuit board trace length.

1. Therefore functional operation and AC timing information are tested at core-to-L2

than maximum rated frequencies. L2CLKOUTA and L2CLKOUTB which are used to latch or enable data at the SRAMs. are actually measured relative to SYSCLK. The L2CLKOUTA and L2CLKOUTB signals should not have more than two loads. and L2CLK_OUTB must have equal loading.

1. The nominal duty cycle of the L2CLK is 50% measured at midpoint voltage.
2. The DLL re -lock time is specified in terms of L2CLKs. The number in the table must be multiplied by the period of L2CLK to

compute the actual time duration in nanoseconds. Re-lock timing is guaranteed by design and characterization.

1. The L2CR[L2SL] bit should be set for L2CLK frequencies less t han 110 MHz. This adds more delay to each tap of the DLL.
2. Allowable skew between L2SYNC_OUT and L2SYNC_IN.
3. This output jitter number represents the maximum delay of one tap forward or one tap back from the current DLL tap as the

Table 15. L2CLK Output AC Timing Specification. At VDD = AVDD = 2.0V 100 mV; -55 ≤ Tj ≤ +125°C, OVDD = 3.3V

30 PC755/745

The L2CLK_OUT timing diagram is shown in Figure 14. Figure 14. L2CLK_OUT Output Timing Diagram defined in Figure 15 and Figure 16 for the loading conditions described in Figure 17. Table 16. L2 Bus Interface AC Timing Specifications at Recommended Operating Conditions

32 PC755/745

18, Figure 19, Figure 20, and Figure 21. tion. The output timings are measured at the pins . All output timings assume a purely resistive 50 Ω load (See Figure 18). Time-of-flight delays must be added for trace lengths, vias, and connectors in the system.

1. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.
2. Non -JTAG signal input timing with respect to TCK.
3. Non -JTAG signal output timing with respect to TCK.
4. Guaranteed by design and characterization.

Figure 18 provides the AC test load for TDO and the boundary-scan outputs of the PC755. Figure 18. ALTERNATE AC Test Load for the JTAG Interface Table 17. JTAG AC Timing Specifications (Independent of SYSCLK)(1)

34 PC755/745

Figure 22 provides the test access port timing diagram. Figure 22. Test Access Port Timing Diagram reset signals must bemerged into these signals with logic. casewhere a JTAG interfacemay need to be wired onto the system in debug situations. footprint for a header to be added when needed. the 0.025" square-post 0.100" centered header assembly (often called a Berg header). The connector typically has pin 14 removed as a connector key.

Figure 23. JTAG Interface Connection header to OVDD with a 10 kΩ pull-up resistor.

1. Key location; pin 14 is not physically present on the COP header.
2. Component not populated. Populate only if debug tool does not drive QACK.
3. Populate only if debug tool uses an open-drain ty pe output and does not actively deassert QACK.
4. If the JTAG interface is implemented, connect HRESET from the target source to TRST from the COP header though an

the part through a 0Ω isolation resistor.

36 PC755/745

print for a header to be added when needed. the 0.025” square-post 0.100” centered header assembly (often called a “Berg” header). The connector typically has pin 14 removed as a connector key. Figure 24 shows the COP connector diagram. Figure 24. COP Connector Diagram bottom, while still others number the pins counter clockwise from pin one (as with an IC). system and is an input to the PC755 informing it that it can go into the quiescent state. Pins 10, 12 and 14 are no-connects.

2138D–HIREL–06/03 Preparation for Delivery Packaging Microcircuits are prepared for delivery in accordance with MIL-PRF-38535. Certificate of Compliance Atmel offers a certificate of compliances with each shipment of parts, affirming the prod- ucts are in compliance either with MIL-PRF-883 and guarantying the parameters not tested at temperature extremes for the entire temperature range. Handling MOS devices must be handled with certain precautions to avoid damage due to accu- mulation of static charge. Input protection devices have been designed in the chip to minimize the effect of static buildup. However, the following handling practices are recommended: 1. Devices should be handled on benches with conductive and grounded surfaces. 2. Ground test equipment, tools and operator. 3. Do not handle devices by the leads. 4. Store devices in conductive foam or carriers. 5. Avoid use of plastic, rubber, or silk in MOS areas. 6. Maintain relative humidity above 50 percent if practical. 7. For CI-CGA packages, use specific tray to take care of the highest height of the package compared with the normal CBGA. Package Mechanical Data The following sections provide the package parameters and mechanical dimensions for the PC745, 255 PBGA package as well as the PC755, 360 CBGA and PBGA packages. While both the PC755 plastic and the ceramic packages are described here, both pack- ages are not guaranteed to be available at the same time. All new designs should allow for either ceramic or plastic BGA packages for this device. For more information on designing a common footprint for both plastic and ceramic package types, please con- tact your local Motorola sales office. Parameters for the PC745 Package Parameters for the PC745 PBGA The package parameters are as provided in the following list. The package type is 21 x 21 mm, 255-lead plastic ball grid array (PBGA). Mechanical Dimensions of the Figure 25 provides the mechanical dimensions and bottom surface nomenclature of the PC745, 255 PBGA package. Package outline 21 x 21 mm Interconnects 255 (16 x 16 ball array – 1) Pitch 1.27 mm (50 mil) Minimum module height 2.25 mm Maximum module height 2.80 mm Ball diameter (typical) 0.75 mm (29.5 mil)

38 PC755/745

Figure 25. Mechanical Dimensions and Bottom Surface Nomenclature of the PC745 PBGA 25 mm, 360-lead plastic ball grid array (PBGA).

1. DIMENSIONING AND TOLERANCING
2. DIMENSIONS IN MILLIMETERS.
3. TOP SIDE A1 CORNER INDEX IS A
4. CAPACITOR PADS MAY BE UNPOPULATED.

40 PC755/745

Figure 27. Mechanical Dimensions and Bottom Surface Nomenclature of PC755 (CBGA)

1. DIMENSIONING AND TOLERANCING
2. DIMENSIONS IN MILLIMETERS.
3. TOP SIDE A1 CORNER INDEX IS A

42 PC755/745

Figure 29. Mechanical Dimensions and Bottom Surface Nomenclature of PC755 (CI-CGA)

1.27 BSC

1. DIMENSIONING AND TOLERANCING
2. DIMENSIONS IN MILLIMETERS.
3. TOP SIDE A1 CORNER INDEX IS A

Notes: 1. PLL_CFG[0:3] settings not listed are reserved.

1. The sample bus-to-core frequencies shown are for reference onl y. Some PLL configurations may select bus, core, or VCO

page 25 for valid SYSCLK, core, and VCO frequencies.

1. In PLL-bypass mode, the SYSCLK input signal clocks the internal processor directly, the PLL is disabled, and the bus mode

is set for 1:1 mode operation. This mode is intended for factory use and emulator tool use only. Note: The AC timing specifications given in this document do not apply in PLL-bypass mode.

1. In PLL off mode, no clocking occurs inside the PC755 regardless of the SYSCLK input.

Table 18. PC755 Microprocessor PLL Configuration

0011 PLL off/bypass PLL off, SYSCLK clocks core circuitry directly, 1x bus-to-core implied

1111 PLL off PLL off, no core clocking occurs

44 PC755/745

clocking of the internal latches in the L2 bus interface. be filtered of any noise in the 500 kHz to 10 MHz resonant frequency range of the PLL. mended over a single large value capacitor. Table 19. Sample Core-to-L2 Frequencies

46 PC755/745

be connected to the power and ground planes through two vias to minimize inductance. Suggested bulk capacitors – 100-330 µF (AVX TPS tantalum or Sanyo OSCON). nals must remain unconnected. tance of the pull-up devices. NO TAG describes the driver impedance measurement circuit described above. Figure 32. Driver Impedance Measurement Circuit

48 PC755/745

2138D–HIREL–06/03 In addition, CKSTP_OUT is an open-drain style output that requires a pull-up resistor (1 kΩ – 5 kΩ ) if it is used by the system. During inactive periods on the bus, the address and transfer attributes may not be driven by any master and may, therefore, float in the high-impedance state for relatively long periods of time. Since the processor must continually moni tor these signals for snooping, this float condition may cause additional power draw by the input receivers on the processor or by other receivers in the system. These signals can be pulled up through weak (10 kΩ ) pull-up resistors by the system or may be otherwise driven by the system during inactive periods of the bus to avoid this additional power draw, but address bus pull-up resistors are not neccessary for proper device operation. The snooped address and transfer attribute inputs are: A[0:31], AP[0:3], TT[0:4], TBST , and GBL. The data bus input receivers are normall y turned off when no read operation is in progress and, therefore, do not require pull-up resistors on the bus. Other data bus receivers in the system, howeve r, may require pull-ups, or that those signals be other- wise driven by the system during inactive pe riods by the system. The data bus signals are: DH[0:31], DL[0:31], and DP[0:7]. If 32-bit data bus mode is selected, the input receivers of the unused data and parity bits will be disabled, and their outputs will drive logic zeros when they would otherwise nor- mally be driven. For this mode, these pins do not require pull-up resistors, and should be left unconnected by the system to minimize possible output switching. If address or data parity is not used by the system, and the respective parity checking is disabled through HID0, the input receivers fo r those pins are disa bled, and those pins do not require pull-up resistors and should be left unconnected by the system. If all par- ity generation is disabled through HID0, then all parity checking should also be disabled through HID0, and all parity pins may be left unconnected by the system. Definitions Datasheet Status Validity Objective specification This datasheet contains target and goal specification for discussion with customer and application validation. Before design phase. Target specification This datasheet contains target or goal specification for product development. Valid during the design phase. Preliminary specification ∝ site This datasheet contains preliminary data. Additional data may be published later; could include simulation result. Valid before characterization phase. Preliminary specification β site This datasheet contains also characterization results. Valid before the industrialization phase. Product specification This datasheet contains final product specification. Valid for production purpose. Limiting Values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application Information

Where application information is given, it is advisory and does not form part of the specification.

2138D–HIREL–06/03 Life Support

Applications

These products are not designed for use in lif e support appliances, devices, or systems where malfunction of these pr oducts can reasonably be expect ed to result in personal injury. Atmel customers using or selling these products for use in such applications do so at their own risk and agree to fully indem nity Atmel for any damages resulting from such improper use or sale. Differences with Commercial Part

Ordering Information

Note: For availability of different vers ions, contact your Atmel sales office. Commercial part Military part Temperature range Tj = 0 to 105°C Tj = -55°C to 125°C PC755C M ZF U 300 L x Type Package: ZF: FC-PBGA G: CBGA GS: CI-CGA GH: HiTCE Screening Level(1) U: Upscreening Test Revision Level(1) E: Rev. 2.8 Temperature Range: Tj M: -55 C, +125 C V: -40 C, +110 C Bus divider (to be confirmed) L: Any valid PLL configuration Max internal processor speed 300: 300 MHz 350: 350 MHz 366: 366 MHz 400: 400 MHz

Printed on recycled paper. Disclaimer: Atmel Corporation makes no warranty for the use of its products , other than those expressly contained in the Company’s standar d warranty which is detailed in Atmel’s Terms and Conditions loca ted on the Company’s web site. The Company assumes no responsibi lity for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time wi thout notice, and does not make any commitment to update the information contained herei n. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel produc ts, expressly or by implicati on. Atmel’s products are not aut horized for use as critical components in life support devices or systems. Atmel Corporation Atmel Operations

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