PC7457

PC7457 ATMEL | Alldatasheet

Document overview

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Technical content

Features

 3000 Dhrystone 2.1 MIPS at 1.3 GHz  Selectable Bus Clock (30 CPU Bus Dividers up to 28x)  13 Selectable Core-to-L3 Frequency Divisors  Selectable MPx/60x Interface Voltage (1.8V, 2.5V)  Selectable L3 Interface of 1.8V or 2.5V  PD Typical 12.6W at 1 GHz at VDD = 1.3V; 8.3W at 1 GHz at VDD = 1.1V, Full Operating Conditions  Nap, Doze and Sleep Modes for Power Saving  Superscalar (Four Instructions Fetched Per Clock Cycle)  4 GB Direct Addressing Range  Virtual Memory: 4 Hexabytes (252)  64-bit Data and 32-bit Address Bus Interface  Integrated L1: 32 KB Instruction and 32 KB Data Cache  Integrated L2: 512 KB  11 Independent Execution Units and Three Register Files  Write-back and Write-through Operations  fINT Max = 1 GHz (1.2 GHz to be Confirmed)  fBUS Max = 133 MHz/166 MHz

Description

This document is primarily concerned with the PowerPC™ PC7457; however, unless otherwise noted, all information here also applies to the PC7447. The PC7457 and PC7447 are implementations of the PowerPC microprocessor family of reduced instruction set computer (RISC) microprocessors. This document describes pertinent electrical and physical characteristics of the PC7457. The PC7457 is the fourth implementation of the fourth generation (G4) microproces- sors from Motorola. The PC7457 implements the full PowerPC 32-bit architecture and is targeted at networking and computing systems applications. The PC7457 consists of a processor core, a 512 Kbyte L2, and an internal L3 tag and controller which sup- port a glueless backside L3 cache through a dedicated high-bandwidth interface. The PC7447 is identical to the PC7457 except it does not support the L3 cache interface. The core is a high-performance superscalar design supporting a double-precision floating-point unit and a SIMD multimedia unit. The memory storage subsystem sup- ports the MPX bus interface to main memory and other system resources. The L3 interface supports 1, 2, or 4M bytes of external SRAM for L3 cache and/or private memory data. For systems implementing 4M bytes of SRAM, a maximum of 2M bytes may be used as cache; the remaining 2M bytes must be private memory. Note that the PC7457 is a footprint-compatible, drop-in replacement in a PC7455 application if the core power supply is 1.3V. PowerPC 7457 RISC Microprocessor PC7457/47 Preliminary Specification α-site Rev. 5345B–HIREL–02/04

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5345B–HIREL–02/04 Screening  CBGA Upscreenings Based on Atmel Standards  Full Military Temperature Range (Tj = -55°C, +125°C), Industrial Temperature Range (Tj = -40°C, +110°C)  CBGA Package, HiTCE Package for the 7447 TBC G suffix CBGA 360 Ceramic Ball Grid Array GH suffix HITCE 360 Ceramic Ball Grid Array (TBC) CBGA 483

Figure 1. PC7457 Microprocessor Block Diagram

16 Rename

Notes:1. The L3 cache interface is not implemented on the PC7447.

1. The Castout Queue and Push Queue share resources such for a combined total of 10 entries.

The Castout Queue itself is limited to 9 entries, ensuring 1 entry will be available for a push.

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General Parameters Table 1 provides a summary of the general parameters of the PC7457. Table 1. Device Parameters

PC7457/47 [Preliminary] 5345B–HIREL–02/04 – Four integer units (IUs) that share 32 GPRs for integer operands Three identical IUs (IU1a, IU1b, and IU1c) can execute all integer instructions except multiply, divide, and move to/from special-purpose register instructions IU2 executes miscellaneous instructions including the CR logical operations, integer multiplication and division instructions, and move to/from special- purpose register instructions – Five-stage FPU and a 32-entry FPR file Fully IEEE 754-1985-compliant FPU for both single- and double-precision operations Supports non-IEEE mode for time-critical operations Hardware support for denormalized numbers Thirty-two 64-bit FPRs for single- or double-precision operands – Four vector units and 32-entry vector register file (VRs) Vector permute unit (VPU) Vector integer unit 1 (VIU1) handles short-latency AltiVec ™ integer instructions, such as vector add instructions (vaddsbs, vaddshs, and vaddsws, for example) Vector integer unit 2 (VIU2) handles longer-latency AltiVec integer instructions, such as vector multiply add instructions (vmhaddshs, vmhraddshs, and vmladduhm, for example) Vector floating-point unit (VFPU) – Three-stage load/store unit (LSU) Supports integer, floating-point, and vector instruction load/store traffic Four-entry vector touch queue (VTQ) supports all four architected AltiVec data stream operations Three-cycle GPR and AltiVec load latency (byte, half-word, word, vector) with one-cycle throughput Four-cycle FPR load latency (single, double) with one-cycle throughput No additional delay for misaligned access within double-word boundary Dedicated adder calculates effective addresses (EAs) Supports store gathering

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5345B–HIREL–02/04 Performs alignment, normalization, and precision conversion for floating- point data Executes cache control and TLB instructions Performs alignment, zero padding, and sign extension for integer data Supports hits under misses (multiple outstanding misses) Supports both big- and little-endian modes, including misaligned little-endian accesses  Three issue queues FIQ, VIQ, and GIQ can accept as many as one, two, and three instructions, respectively, in a cycle. Instruction dispatch requires the following: – Instructions can be dispatched only from the three lowest IQ entries – IQ0, IQ1, and IQ2 – A maximum of three instructions can be dispatched to the issue queues per clock cycle – Space must be available in the CQ for an instruction to dispatch (this includes instructions that are assigned a space in the CQ but not in an issue queue)  Rename buffers – 16 GPR rename buffers – 16 FPR rename buffers – 16 VR rename buffers  Dispatch unit – Decode/dispatch stage fully decodes each instruction  Completion unit – The completion unit retires an instruction from the 16-entry completion queue (CQ) when all instructions ahead of it have been completed, the instruction has finished execution, and no exceptions are pending – Guarantees sequential programming model (precise exception model) – Monitors all dispatched instructions and retires them in order – Tracks unresolved branches and flushes instructions after a mispredicted branch – Retires as many as three instructions per clock cycle  Separate on-chip L1 Instruction and data caches (Harvard Architecture) – 32 Kbyte, eight-way set-associative instruction and data caches – Pseudo least-recently-used (PLRU) replacement algorithm – 32-byte (eight-word) L1 cache block – Physically indexed/physical tags – Cache write-back or write-through operation programmable on a per-page or per-block basis – Instruction cache can provide four instructions per clock cycle; data cache can provide four words per clock cycle – Caches can be disabled in software – Caches can be locked in software

PC7457/47 [Preliminary] 5345B–HIREL–02/04 – MESI data cache coherency maintained in hardware – Separate copy of data cache tags for efficient snooping – Parity support on cache and tags – No snooping of instruction cache except for icbi instruction – Data cache supports AltiVec LRU and transient instructions – Critical double- and/or quad-word forwarding is performed as needed. Critical quad-word forwarding is used for AltiVec loads and instruction fetches. Other accesses use critical double-word forwarding  Level 2 (L2) cache interface – On-chip, 512 Kbyte, eight-way set-associative unified instruction and data cache – Fully pipelined to provide 32 bytes per clock cycle to the L1 caches – A total nine-cycle load latency for an L1 data cache miss that hits in L2 – PLRU replacement algorithm – Cache write-back or write-through operation programmable on a per-page or per-block basis – 64-byte, two-sectored line size – Parity support on cache  Level 3 (L3) cache interface (not implemented on PC7447) – Provides critical double-word forwarding to the requesting unit – Internal L3 cache controller and tags – External data SRAMs – Support for 1, 2, and 4M bytes (MB) total SRAM space – Support for 1 or 2 MB of cache space – Cache write-back or write-through operation programmable on a per-page or per-block basis – 64-byte (1 MB) or 128-byte (2 MB) sectored line size – Private memory capability for half (1 MB minimum) or all of the L3 SRAM space for a total of 1-, 2-, or 4-MB of private memory – Supports MSUG2 dual data rate (DDR) synchronous Burst SRAMs, PB2 pipelined synchronous Burst SRAMs, and pipelined (register-register) Late Write synchronous Burst SRAMs – Supports parity on cache and tags – Configurable core-to-L3 frequency divisors – 64-bit external L3 data bus sustains 64-bit per L3 clock cycle  Separate memory management units (MMUs) for Instructions and data – 52-bit virtual address; 32- or 36-bit physical address – Address translation for 4 Kbyte pages, variable-sized blocks, and 256M bytes segments – Memory programmable as write-back/write-through, caching- inhibited/caching-allowed, and memory coherency enforced/memory coherency not enforced on a page or block basis – Separate IBATs and DBATs (eight each) also defined as SPRs

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5345B–HIREL–02/04 – Separate instruction and data translation lookaside buffers (TLBs) Both TLBs are 128-entry, two-way set-associative, and use LRU replacement algorithm TLBs are hardware- or software-reloadable (that is, on a TLB miss a page table search is performed in hardware or by system software)  Efficient data flow – Although the VR/LSU interface is 128 bits, the L1/L2/L3 bus interface allows up to 256 bits – The L1 data cache is fully pipelined to provide 128 bits/cycle to or from the VRs – L2 cache is fully pipelined to provide 256 bits per processor clock cycle to the L1 cache – As many as eight outstanding, out-of-order, cache misses are allowed between the L1 data cache and L2/L3 bus – As many as 16 out-of-order transactions can be present on the MPX bus – Store merging for multiple store misses to the same line. Only coherency action taken (address-only) for store misses merged to all 32 bytes of a cache block (no data tenure needed) – Three-entry finished store queue and five-entry completed store queue between the LSU and the L1 data cache – Separate additional queues for efficient buffering of outbound data (such as castouts and write-through stores) from the L1 data cache and L2 cache  Multiprocessing support features include the following: – Hardware-enforced, MESI cache coherency protocols for data cache – Load/store with reservation instruction pair for atomic memory references, semaphores, and other multiprocessor operations  Power and thermal management – 1.6V processor core – The following three power-saving modes are available to the system: Nap—Instruction fetching is halted. Only those clocks for the time base, decrementer, and JTAG logic remain running. The part goes into the doze state to snoop memory operations on the bus and then back to nap using a QREQ/QACK processor-system handshake protocol Sleep—Power consumption is further reduced by disabling bus snooping, leaving only the PLL in a locked and running state. All internal functional units are disabled Deep sleep— When the part is in the sleep state, the system can disable the PLL. The system can then disable the SYSCLK source for greater system power savings. Power-on reset procedures for restarting and relocking the PLL must be followed on exiting the deep sleep state

PC7457/47 [Preliminary] 5345B–HIREL–02/04 – Thermal management facility prov ides software-controllable thermal management. Thermal management is performed through the use of three supervisor-level registers and a PC7457-specific thermal management exception – Instruction cache throttling provides control of instruction fetching to limit power consumption  Performance monitor can be used to help debug system designs and improve software efficiency  In-system testability and debugging features through JTAG boundary-scan capability  Testability – LSSD scan design – IEEE 1149.1 JTAG interface – Array built-in self test (ABIST) – factory test only  Reliability and serviceability – Parity checking on system bus and L3 cache bus – Parity checking on the L2 and L3 cache tag arrays

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Figure 2. PC7457 Microprocessor Signal Groups Notes: 1. For the PC7457, there are 19 L3_ADDR signals, (L3_ADDR[0:18].

1. For the PC7447 and PM7457, there are 5 PLL_CFG signals, (PLL_CFG[0:4].

compliance with Atmel standard screening.

1. MIL-STD-883: Test methods and procedures for electronics
2. MIL-PRF-38535: Appendix A: General specifications for microcircuits

or cause permanent damage to the device.

1. Caution: VDD /AVDD must not exceed OVDD /GVDD by more than 1V during normal operation; this limit may be exceeded for a

maximum of 20 ms during power-on reset and power-down sequences.

1. Caution: OVDD /GVDD must not exceed VDD /AVDD by more than 2V during normal operation; this limit may be exceeded for a

maximum of 20 ms during power-on reset and power-down sequences.

1. BVSEL must be set to 0, such that the bus is in 1.8V mode.
2. BVSEL must be set to HRESET or 1, such that the bus is in 2.5V mode.
3. L3VSEL must be set to ¬HRESET (inverse of HRESET), such that the bus is in 1.5V mode.

Table 2. Absolute Maximum Ratings(1)

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1. L3VSEL must be set to 0, such that the bus is in 1.8V mode.
2. L3VSEL must be set to HRESET or 1, such that the bus is in 2.5V mode.
3. Caution: VIN must not exceed OVDD or GVDD by more than 0.3V at any time including during power-on reset.
4. VIN may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 3.
5. This voltage is the input to the filter discussed in Section “PLL Power Supply Filtering” on page 54 and not necessarily the

voltage at the AVDD pin which may be reduced from VDD by the filter.

1. ¬HRESET is the inverse of HRESET.

Figure 3. Overshoot/Undershoot Voltage Table 3. Recommended Operating Conditions(1)

applied to the OVDD or GVDD power pins. Notes: 1. Not implemented on PC7447.

1. Caution: The input threshold selection must agree with the OVDD /GVDD voltages sup-

plied. See notes in Table 2.

1. If used, pull-down resistors should be less than 250Ω
2. Applicable to L3 bus interface only. ¬HRESET is the inverse of HRESET.

Notes: 1. See “Thermal Management Information” on page 15 for more details about thermal management.

1. Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) tempera-

ture, ambient temperature, airflow, power dissipation of other components on the board, and board thermal resistance.

1. Per SEMI G38-87 and JEDEC JESD51-2 with the single-layer board horizontal.
2. Per JEDEC JESD51-6 with the board horizontal.
3. Thermal resistance between the die and the printed-circuit board per JEDEC JESD51-8. Board temperature is measured on

the top surface of the board near the package.

1. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883

Method 1012.1) with the calculated case temperature. The actual value of RθJC for the part is less than 0.1°C/W. Table 4. Input Threshold Voltage Setting Table 5. Package Thermal Characteristics(1)

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attached heat sink mounted to a printed-circuit board. Figure 4. C4 Package with Heat Sink Mounted to a Printed-Circuit Board Note the internal versus external package resistance. heat sink where it is removed by forced-air convection. the heat sink conduction/convective thermal resistances are the dominant terms.

is suggested. If a spring clip is used, the spring force should not exceed 10 pounds. Figure 5. Package Exploded Cross-sectional View with Several Heat Sink Options

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and a joint with thermal grease as a function of contact pressure. ments, manufacturability, service temperature, dielectric properties, cost, etc. Figure 6. Thermal Performance of Select Thermal Interface Material

PC7457/47 [Preliminary] 5345B–HIREL–02/04 R θJC is the junction-to-case thermal resistance R θint is the adhesive or interface material thermal resistance R θsa is the heat sink base-to-ambient thermal resistance Pd is the power dissipated by the device During operation, the die-junction temperatures (Tj) should be maintained less than the value specified in Table 3 on page 12. The temperature of air cooling the component greatly depends on the ambient inlet air temperature and the air temperature rise within the electronic cabinet. An electronic cabinet inlet-air temperature (T a) may range from 30° to 40°C. The air temperature rise within a cabinet (Tr) may be in the range of 5° to 10°C. The thermal resistance of the thermal interface material (Rθint) is typically about 1.5°C/W. For example, assuming a Ta of 30°C, a Tr of 5°C, a CBGA package RθJC = 0.1, and a typical power consumption (Pd) of 18.7W, the following expression for Tj is obtained: Die-junction temperature: Tj = 30°C + 5°C + (0.1°C/W + 1.5°C/W + θsa) × 18.7W For this example, a Rθsa value of 2.1°C/W or less is required to maintain the die junction temperature below the maximum value of Table 3 on page 12. Though the die junction-to-ambient and the heat sink-to-ambient thermal resistances are a common figure-of-merit used for comparing the thermal performance of various microelectronic packaging technologies, one should exercise caution when only using this metric in determining thermal management because no single parameter can ade- quately describe three-dimensional heat flow. The final die-junction operating temperature is not only a function of the component-level thermal resistance, but the system-level design and its operating conditions. In addition to the component's power consumption, a number of factors affect the final operating die-junction temperature – airflow, board population (local heat flux of adjacent components), heat sink efficiency, heat sink attach, heat sink placement, next-level interconnect technology, system air temperature rise, altitude, etc. Due to the complexity and the many variations of system-level boundary conditions for today's microelectronic equipment, the combined effects of the heat transfer mecha- nisms (radiation, convection, and conduction) may vary widely. For these reasons, we recommend using conjugate heat transfer models for the board, as well as system-level designs. For system thermal modeling, the PC7447 and PC7457 thermal model is shown in Fig- ure 4 on page 14. Four volumes will be used to represent this device. Two of the volumes, solder ball, and air and substrate, are modeled using the package outline size of the package. The other two, die, and bump and underfill, have the same size as the die. The silicon die should be modeled 9.64 × 11 × 0.74 mm with the heat source applied as a uniform source at the bottom of the volume. The bump and underfill layer is mod- eled as 9.64 × 11 × 0.69 mm (or as a collapsed volume) with orthotropic material properties: 0.6W/(m × K) in the xy-plane and 2W/(m × K) in the direction of the z-axis. The substrate volume is 25 × 25 × 1.2 mm (PC7447) or 29 × 29 × 1.2 mm (PC7457), and this volume has 18W/(m × K) isotropic conductivity. The solder ball and air layer is mod- eled with the same horizontal dimensions as the substrate and is 0.9 mm thick. It can also be modeled as a collapsed volume using orthotropic material properties: 0.034W/(m × K) in the xy-plane direction and 3.8W/(m × K) in the direction of the z-axis.

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Figure 7. Recommended Thermal Model of PC7447 and PC7457

1. Typical power is an average value measured at the nominal recommended VDD (see

achieving 2.3 Dhrystone MIPs/MHz. Table 6. Power Consumption for PC7457

1. Maximum power is the average measured at nominal VDD and maximum operating
2. Doze mode is not a user-definable state; it is an intermediate state between full-

Table 7 provides the DC electrical characteristics for the PC7457. Notes: 1. Nominal voltages; see Table 3 on page 12 for recommended operating conditions.

1. For processor bus signals, the reference is OVDD while GVDD is the reference for the L3 bus signals.
2. Excludes test signals and IEEE 1149.1 boundary scan (JTAG) signals.
3. The leakage is measured for nominal OV

example, both OVDD and VDD vary by either +5% or -5%).

1. Capacitance is periodically sampled rather than 100% tested.
2. Applicable to L3 bus interface only

Table 7. DC Electrical Specifications (see Table 3 on page 12 for Recommended Operating Conditions)

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core frequency; See “Ordering Information” on page 59. forth, and may be less than the value given in Table 8. Table 8. Clock AC Timing Specifications (See Table 3 on page 12 for Recommended Operating Conditions)

600 MHz 867 MHz 1000 MHz

867 MHz 1000 MHz 1200 MHz 1267 MHz

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are provided in section “L3 Clock AC Specifications” on page 24. are measured at the pin; time-of-flight delays must be added for trace lengths, vias, and connectors in the system. Table 9. Processor Bus AC Timing Specifications(1) (at Recommended Operating Conditions, see Table 3 on page 12.)

1. The symbology used for timing specifications herein follows the pattern of t(signal)(state)(reference)(state) for inputs and

output hold time can be read as the time from the rising edge (KH) until the output went invalid (OX).

1. tSYSCLK is the period of the external clock (SYSCLK) in ns. The numbers given in the table must be multiplied by the period of

SYSCLK to compute the actual time duration (in ns) of the parameter in question.

1. According to the bus protocol, TS is driven only by the currently active bus master. It is asserted low then precharged high

precharge.The high-impedance behavior is guaranteed by design.

1. Guaranteed by design and not tested.
2. According to the bus protocol, ARTRY can be driven by multiple bus masters through the clock period immediately following

output hold timing is tested for the signal asserted.The high-impedance behavior is guaranteed by design.

1. According to the MPX bus protocol, SHD0 and SHD1 can be driven by multiple bus masters beginning the cycle of TS. Tim-

1.0 tSYSCLK . The edges of the precharge vary depending on the programmed ratio of core to bus (PLL configurations).

1. BMODE [0:1] and BVSEL are mode select inputs and are sampled before and after HRESET negation. These parameters

inputs must remain stable after the second sample. See Figure 9 on page 23 for sample timing. Figure 9. Mode Input Timing Diagram

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Figure 10 provides the input/output timing diagram for the PC7457. Figure 10. Input/Output Timing Diagram specifications as defined in Figure 11 on page 25. skews, where applicable, do need to be accounted for in an AC timing analysis.

1. Therefore, functional operation and AC timing information are tested at core-to-L3

divisors which result in L3 frequencies at 250 MHz or lower. minimum L3 clock frequency and period are fSYSCLK and tSYSCLK , respectively.

1. The nominal duty cycle of the L3 output clocks is 50% measured at midpoint voltage.
2. Maximum possible skew between L3_CLK0 and L3_CLK1. This parameter is critical to the address and control signals

which are common to both SRAM chips in the L3.

1. Maximum possible skew between L3_CLK0 and L3_ECHO_CLK1 or between L3_CLK1 and L3_ECHO_CLK3 for PB2 or

data driven from the SRAM, each of which drives data based on L3_CLK0 or L3_CLK1.

1. Guaranteed by design and not tested. The input jitter on SYSCLK affects L3 output clocks and the L3 address, data and

Figure 11. L3_CLK_OUT Output Timing Diagram Table 10. L3_CLK Output AC Timing Specifications at Recommended Operating Conditions (see Table 3 on page 12)

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to their single load. Figure 12 shows the AC test load for the L3 interface. Figure 12. AC Test Load for the L3 Interface interface will meet the maximum frequency operation of appropriately chosen SRAMs. PC7450 RISC Microprocessor Family User’s Manual. more information, see the PC7450 RISC Microprocessor Family User’s Manual.

1. This specification is the delay from a rising or falling edge on the internal_L3_CLK

signal to the corresponding rising or falling edge at the L3CLK[n] pins.

1. This specification is the delay from a rising or falling edge of L3_ECHO_CLK[n] to

data valid and ready to be sampled from the FIFO. rized in Table 12 on page 28. ing parameters of the L3 bus in any way. Table 11. Sample Points Calculation Parameters

28 PC7457/47 [Preliminary]

Notes: 1. Refer to the PC7450 RISC Microprocessor Family User’s Manual for specific information regarding L3OHCR.

1. See Table 13 on page 29 and Table 14 on page 32 for more information.
2. Guaranteed by design; not tested or characterized.
3. Increasing values of L3CLKn_OH delay the L3_CLKn signal, effectively decreasing the output valid and output hold times of

all signals latched relative to that clock signal by the SRAM; see Figure 13 on page 30 and Figure 15 on page 33. control, data, and L3_CLKn signals have propagated across the printed-wiring board. Table 12. Effect of L3OHCR Settings on L3 Bus AC Timing

data is set by using the sample point settings defined in the L3CR register. ing shown in Figure 12 on page 26. Notes: 1. Rise and fall times for the L3_CLK output are measured from 20% to 80% of GVDD .

1. For DDR, all input specifications are measured from the midpoint of the signal in question to the midpoint voltage of the ris-

ing or falling edge of the input L3_ECHO_CLKn (see Figure 14 on page 31). Input timings are measured at the pins.

1. For DDR, the input data will typically follow the edge of L3_ECHO_CLKn as shown in Figure 14. For consistency with other

input setup time specifications, this will be treated as negative input setup time.

1. tL3_CLK /4 is one-fourth the period of L3_CLKn. This parameter indicates that the PC7457 can latch an input signal that is

edges of L3_ECHO_CLKn at any frequency.

1. All output specifications are measured from the midpoint voltage of the rising (or for DDR write data, also the falling) edge of

purely resistive 50Ω load (see Figure 12 on page 26).

1. For DDR, the output data will typically lead the edge of L3_CLKn as shown in Figure 14 on page 31. For consistency with

other output valid time specifications, this will be treated as negative output valid time.

1. tL3_CLK /4 is one-fourth the period of L3_CLKn. This parameter indicates that the specified output signal is actually launched

prior to the edge on which the SRAM will sample it and ending one-fourth of a clock period after the edge it will be sampled.

1. Assumes default value of L3OHCR. See “Effects of L3OHCR Settings on L3 Bus AC Specifications” on page 27 for more

Table 13. L3 Bus Interface AC Timing Specifications for MSUG2 at Recommended Operating Conditions

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Figure 13 shows the typical connection diagram for the PC7457 interfaced to MSUG2 DDR SRAMs. Figure 13. Typical Source Synchronous 4M bytes L3 Cache DDR Interface Note: 1. Or as recommended by SRAM manufacturer for single-ended clocking.

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returned to the PC7457 inputs L3_ECHO_CLK0 and L3_ECHO_CLK2, respectively. L3_ECHO_CLK0 and L3_ECHO_CLK2. Notes: 1. Rise and fall times for the L3_CLK output are measured from 20% to 80% of GVDD .

1. Timing behavior and characterization are currently being evaluated.
2. All input specifications are measured from the midpoint of the signal in question to the midpoint voltage of the rising edge of

the input L3_ECHO_CLKn (see Figure 14 on page 31). Input timings are measured at the pins.

1. All output specifications are measured from the midpoint voltage of the rising edge of L3_CLKn to the midpoint of the signal
2. tL3_CLK /4 is one-fourth the period of L3_CLKn. This parameter indicates that the specified output signal is actually launched

before the edge on which the SRAM will sample it and ending one-fourth of a clock period after the edge it will be sampled.

1. Assumes default value of L3OHCR. See “Effects of L3OHCR Settings on L3 Bus AC Specifications” on page 27 for more

Table 14. L3 Bus Interface AC Timing Specifications for PB2 and Late Write SRAMs at Recommended Operating Condi-

34 PC7457/47 [Preliminary]

Figure 16 shows the L3 bus timing diagrams for the PC7457 interfaced to PB2 or Late Write SRAMs. Figure 16. L3 Bus Timing Diagrams for Late Write or PB2 SRAMs Figure 17. AC Test Load

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Figure 19. JTAG Clock Input Timing Diagram Figure 20. TRST Timing Diagram Figure 21. Boundary-scan Timing Diagram

Figure 22. Test Access Port Timing Diagram  Devices should be handled on benches with conductive and grounded surfaces.  Ground test equipment, tools and operator.  Do not handle devices by the leads.  Store devices in conductive foam or carriers.  Avoid use of plastic, rubber or silk in MOS areas.  Maintain relative humidity above 50% if practical.

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5345B–HIREL–02/04 Package Mechanical Data The following sections provide the package parameters and mechanical dimensions for the CBGA package. Package Parameters for the PC7447, 360 CBGA The package parameters are as provided in the following list. The package type is 25 × 25 mm, 360-lead ceramic ball grid array (CBGA). Package outline 25 mm × 25 mm Interconnects 360 (19 × 19 ball array - 1) Pitch 1.27 mm (50 mil) Minimum module height 2.72 mm Maximum module height 3.24 mm Ball diameter 0.89 mm (35 mil)

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vides the pinout listing for the PC7457, 483 CBGA package. Note: This pinout is not compatible with the PC750, PC7400, or PC7410 360 BGA package. Table 16. Pinout Listing for the PC7447, 360 CBGA Package

Table 16. Pinout Listing for the PC7447, 360 CBGA Package (Continued)

42 PC7457/47 [Preliminary]

5345B–HIREL–02/04 Notes: 1. OV DD supplies power to the processor bus, JTAG, and all control signals; and VDD supplies power to the processor core and the PLL (after filtering to become AVDD ). To program the I/O voltage, connect BVSEL to either GND (selects 1.8V) or to HRESET (selects 2.5V). If used, the pull-down resistor should be less than 250Ω. For actual recommended value of VIN or supply voltages see Figure 3 on page 12. 2. Unused address pins must be pulled down to GND. 3. These pins require weak pull-up resistors (for example, 4.7 kΩ) to maintain the control signals in the negated state after they have been actively negated and released by the PC7447 and other bus masters. 4. This signal selects between MPX bus mode (asserted) and 60x bus mode (negated) and will be sampled at HRESET going high. 5. This signal must be negated during reset, by pull up to OVDD or negation by ¬HRESET (inverse of HRESET), to ensure proper operation. 6. Internal pull up on die. 7. Ignored in 60x bus mode. 8. These signals must be pulled down to GND if unused, or if the PC7447 is in 60x bus mode. 9. These input signals are for factory use only and must be pulled down to GND for normal machine operation. 10. It is recommended this test signal be tied to HRESET ; however, other configurations will not adversely affect performance. 11. These signals are for factory use only and must be left unconnected for normal machine operation. 12. These input signals are for factory use only and must be pulled up to OVDD for normal machine operation. 13. This pin can externally cause a performance monitor event. Counting of the event is enabled via software. 14. This signal must be asserted during reset, by pull down to GND or assertion by HRESET , to ensure proper operation

44 PC7457/47 [Preliminary]

Figure 26 shows the connectivity of the substrate capacitor pads for the PC7447, 360 CBGA. All capacitors are 100 nF . Figure 26. Substrate Bypass Capacitors for the PC7447, 360 CBGA 29 × 29 mm, 483-lead ceramic ball grid array (CBGA).

46 PC7457/47 [Preliminary]

Table 17. Pinout Listing for the PC7457, 483 CBGA Package

Table 17. Pinout Listing for the PC7457, 483 CBGA Package (Continued)

48 PC7457/47 [Preliminary]

become AVDD ). For actual recommended value of VIN or supply voltages, see Table 3 on page 12.

1. Unused address pins must be pulled down to GND.
2. These pins require weak pull-up resistors (for example, 4.7 kΩ) to maintain the control signals in the negated state after they

have been actively negated and released by the PC7457 and other bus masters.

1. This signal selects between MPX bus mode (asserted) and 60x bus mode (negated) and will be sampled at HRESET
2. This signal must be negated during reset, by pull up to OVDD or negation by ¬HRESET (inverse of HRESET), to ensure
3. To program the processor interface I/O voltage, connect BVSEL to either GND (selects 1.8V) or to HRESET (selects 2.5V).

resistors should be less than 250Ω.

1. These signals must be pulled down to GND if unused or if the PC7457 is in 60x bus mode.
2. These input signals for factory use only and must be pulled down to GND for normal machine operation.
3. Power must be supplied to GVDD , even when the L3 interface is disabled or unused.
4. It is recommended that this test signal be tied to HRESET; however, other configurations will not adversely affect
5. These input signals are for factory use only and must be pulled up to OVDD for normal machine operation.
6. These signals are for factory use only and must be left unconnected for normal machine operation.
7. This pin can externally cause a performance monitor event. Counting of the event is enabled via software.
8. This signal must be asserted during reset, by pull down to GND or assertion by HRESET, to ensure proper operation.
9. These pins are internally connected to VDD . They are intended to allow an external device to detect the core voltage level

present at the processor core. If unused, they must be connected directly to VDD or left unconnected.

50 PC7457/47 [Preliminary]

Figure 26 shows the connectivity of the substrate capacitor pads for the PC7457, 483 CBGA. All capacitors are 100 nF . Figure 30. Substrate Bypass Capacitors for the PC7457, 483 CBGA

1 GHz column in Table 8 on page 20. Table 18. PC7457 Microprocessor PLL Configuration Example for 1267 MHz Parts

52 PC7457/47 [Preliminary]

Notes: 1. PLL_CFG[0:4] settings not listed are reserved.

1. The sample bus-to-core frequencies shown are for reference only. Some PLL configurations may select bus, core, or VCO

frequencies which are not useful, not supported, or not tested for by the PC7455; See “Clock AC Specifications” on page 20. for valid SYSCLK, core, and VCO frequencies.

1. In PLL-bypass mode, the SYSCLK input signal clocks the internal processor directly and the PLL is disabled. However, the

frequency. This mode is intended for factory use and emulator tool use only. Note: The AC timing specifications given in this document do not apply in PLL-bypass mode.

00110 PLL bypass PLL off, SYSCLK clocks core circuitry directly

11110 PLL off PLL off, no core clocking occurs

Table 18. PC7457 Microprocessor PLL Configuration Example for 1267 MHz Parts (Continued)

1. In PLL-off mode, no clocking occurs inside the PC7455 regardless of the SYSCLK input.

quency of the PC7457 core, and timing analysis of the circuit board routing. Specifications” on page 24 for valid L3_CLK frequencies and for more information regarding the maximum L3 frequency.

1. These core frequencies are not supported by all speed grades; see Table 8 on page 20.

Table 19. Sample Core-to-L3 Frequencies(1)

54 PC7457/47 [Preliminary]

capacitors with minimum effective series inductance (ESL) is recommended. periphery of the 483 CBGA footprint, without the inductance of vias. voltages described in this specification. tering requirements of the PC7457 and will make updated recommendations as needed. Note that this recommendation applies to Rev. 1.1 devices only. Figure 31. PLL Power Supply Filter Circuit high frequency noise in its power supply, especially while driving large capacitive loads. in the PCB, utilizing short traces to minimize inductance. 0508 or 0603 orientations where connections are made along the length of the part. equal value are recommended over using multiple values of capacitance.

the remainder of the L3 interface may be left unterminated. To measure Z0, an external resistor is connected from the chip pad to OVDD or GND. Figure 32. Driver Impedance Measurement tion temperature and is relatively unaffected by bus voltage. Table 20. Impedance Characteristics with VDD = 1.5V, OVDD = 1.8V ±5%, Tj = 5° - 85°C

56 PC7457/47 [Preliminary]

5345B–HIREL–02/04 Pull-up/Pull-down Resistor Requirements The PC7457 requires high-resistive (weak: 4.7 kΩ) pull-up resistors on several control pins of the bus interface to maintain the control signals in the negated state after they have been actively negated and released by the PC7457 or other bus masters. These pins are TS , ARTRY, SHDO, and SHD1. Some pins designated as being for factory test must be pulled up to OVDD or down to GND to ensure proper device operation. For the PC7447, 360 BGA, the pins that must be pulled up to OVDD are LSSD_MODE and TEST[0:3]; the pins that must be pulled down to GND are L1_TSTCLK and TEST[4]. For the PC7457, 483 BGA, the pins that must be pulled up to OVDD are LSSD_MODE and TEST[0:5]; the pins that must be pulled down are L1_TSTCLK and TEST[6]. The CKSTP_IN signal should likewise be pulled up through a pull-up resistor (weak or stronger: 4.7 – 1 kΩ) to prevent erroneous assertions of this signal. In addition, the PC7457 has one open-drain style output that requires a pull-up resistor (weak or stronger: 4.7 – 1 kΩ) if it is used by the system. This pin is CKSTP_OUT If pull-down resistors are used to configure BVSEL or L3VSEL, the resistors should be less than 250Ω (see Table 16 on page 40). Because PLL_CFG[0:4] must remain stable during normal operation, strong pull-up and pull-down resistors (1 kΩ or less) are rec- ommended to configure these signals in order to protect against erroneous switching due to ground bounce, power supply noise or noise coupling. During inactive periods on the bus, the address and transfer attributes may not be driven by any master and may, therefore, float in the high-impedance state for relatively long periods of time. Because the PC7457 must continually monitor these signals for snooping, this float condition may cause excessive power draw by the input receivers on the PC7457 or by other receivers in the system. It is recommended that these signals be pulled up through weak (4.7 kΩ) pull-up resistors by the system, or that they may be oth- erwise driven by the system during inactive periods of the bus. The snooped address and transfer attribute inputs are A[0:35], AP[0:4], TT[0:4], CI , WT, and GBL. If extended addressing is not used, A[0:3] are unused and must be pulled low to GND through weak pull-down resistors. If the PC7457 is in 60x bus mode, DTI[0:3] must be pulled low to GND through weak pull-down resistors. The data bus input receivers are normally turned off when no read operation is in progress and, therefore, don’t require pull-up resistors on the bus. Other data bus receiv- ers in the system, however, may require pull-ups, or that those signals be otherwise driven by the system during inactive periods by the system. The data bus signals are D[0:63] and DP[0:7]. If address or data parity is not used by the system, and the respective parity checking is disabled through HID0, the input receivers for those pins are disabled, and those pins don’t require pull-up resistors and should be left unconnected by the system. If all parity generation is disabled through HID0, then all parity checking should also be disabled through HID0, and all parity pins may be left unconnected by the system. The L3 interface does not normally require pull-up resistors.

PC7457/47 [Preliminary] 5345B–HIREL–02/04 JTAG Configuration Signals Boundary-scan testing is enabled through the JTAG interface signals. The TRST signal is optional in the IEEE 1149.1 specification, but is provided on all processors that imple- ment the PowerPC architecture. While it is possible to force the TAP controller to the reset state using only the TCK and TMS signals, more reliable power-on reset perfor- mance will be obtained if the TRST signal is asserted during power-on reset. Because the JTAG interface is also used for accessing the common on-chip processor (COP) function, simply tying TRST to HRESET is not practical. The COP function of these processors allows a remote computer system (typically, a PC with dedicated hardware and debugging software) to access and control the internal operations of the processor. The COP interface connects primarily through the JTAG port of the processor, with some additional status monitoring signals. The COP port requires the ability to independently assert HRESET or TRST in order to fully control the processor. If the target system has independent reset sources, such as voltage moni- tors, watchdog timers, power supply failures, or push-button switches, then the COP reset signals must be merged into these signals with logic. The arrangement shown in Figure 31 allows the COP port to independently assert HRESET or TRST, while ensuring that the target can drive HRESET as well. If the JTAG interface and COP header will not be used, TRST should be tied to HRESET through a 0Ω isolation resistor so that it is asserted when the system reset signal (HRESET) is asserted, ensuring that the JTAG scan chain is initialized during power-on. While Motor- ola recommends that the COP header be designed into the system as shown in Figure 31 on page 54, if this is not possible, the isolation resistor will allow future access to TRST in the case where a JTAG interface may need to be wired onto the system in debug situations. The COP header shown in Figure 31 adds many benefits – breakpoints, watchpoints, register and memory examination/modification, and other standard debugger features are possible through this interface – and can be as inexpensive as an unpopulated foot- print for a header to be added when needed. The COP interface has a standard header for connection to the target system, based on the 0.025" square-post, 0.100" centered header assembly (often called a Berg header). The connector typically has pin 14 removed as a connector key. There is no standardized way to number the COP header shown in Figure 31; conse- quently, many different pin numbers have been observed from emulator vendors. Some are numbered top-to-bottom then left-to-right, while others use left-to-right then top-to- bottom, while still others number the pins counter clockwise from pin 1 (as with an IC). Regardless of the numbering, the signal placement recommended in Figure 31 is com- mon to all known emulators. The QACK signal shown in Figure 31 is usually connected to the PCI bridge chip in a system and is an input to the PC7457 informing it that it can go into the quiescent state. Under normal operation this occurs during a low-power mode selection. In order for COP to work, the PC7457 must see this signal asserted (pulled down). While shown on the COP header, not all emulator products drive this signal. If the product does not, a pull-down resistor can be populated to assert this signal. Additionally, some emulator products implement open-drain type outputs and can only drive QACK asserted; for these tools, a pull-up resistor can be implemented to ensure this signal is deasserted when it is not being driven by the tool. Note that the pull-up and pull-down resistors on the QACK signal are mutually exclusive and it is never necessary to populate both in a system. To preserve correct power-down operation, QACK should be merged via logic so that it also can be driven by the PCI bridge.

58 PC7457/47 [Preliminary]

Figure 33. JTAG Interface Connection header to OVDD with a 10 kΩ pull-up resistor.

1. Key location; pin 14 is not physically present on the COP header.
2. Component not populated. Populate only if debug tool does not drive QACK.
3. Populate only if debug tool uses an open-drain type output and does not actively deassert QACK.
4. If the JTAG interface is implemented, connect HRESET from the target source to TRST from the COP header though an

the part through a 0Ω isolation resistor.

1. Though defined as a No-Connect, it is a common and recommended practice to use pin 12 as an additional GND pin for

PC7457/47 [Preliminary] 5345B–HIREL–02/04 Definitions Datasheet Status

Applications

These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Atmel customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Atmel for any damages resulting from such improper use or sale. Table 21. Datasheet Status This datasheet contains preliminary data. extended periods may affect device reliability.

Application Information

Where application information is given, it is advisory and does not form part of the specification.

60 PC7457/47 [Preliminary]

5345B–HIREL–02/04

Ordering Information

Note: 1. For availability of the different versions, contact your local Atmel sales office. PC 7457 V G U 1000 Lx Prefix Type Screening Level(1) U: Upscreening Revision Level(1) Rev. B, C Application modifier(1) L: 1.3V ± 50 mV N: 1.1V ± 50 mV Max internal processor speed(1)

933 MHz

1000 MHz

1200 MHz (TBC)

Temperature Range: Tj (1) Prototype (X) V: -40˚C, 110˚C M: -55˚C +125˚C Package G: CBGA PC 7447 V G U 1000 Lx Prefix Type Screening Level(1) U: Upscreening Revision Level(1) Rev. B, C Application modifier(1) L: 1.3V ± 50 mV N: 1.1V ± 50 mV Max internal processor speed(1) Temperature Range: Tj (1) Prototype (X) V: -40˚C, 110˚C M: -55˚C +125˚C Package G: CBGA GH: HITCE (TBC)

Table 22 provides a revision history for this hardware specification. Table 22. Document Revision History Added specifications for 1267 MHz devices; removed specs for 1300 MHz devices.

62 PC7457/47 [Preliminary]

5345B–HIREL–02/04

i PC7457/47 [Preliminary] 5345B–HIREL–02/04

ii PC7457/47 [Preliminary] 5345B–HIREL–02/04

PC7457/47 [Preliminary] 5345B–HIREL–02/04

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