PC7410

PC7410 ATMEL | Alldatasheet

Document overview

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Technical content

Features

 22.8 SPECint95 (estimated), 17SPECfp95 at 500 MHz (estimated)  917MIPS at 500 MHz  Selectable Bus Clock (14 CPU Bus Dividers Up To 9x)  Seven Selectable Core-to-L2 Frequency Divisors  Selectable 603 Interface Voltage Below 3.3V (1.8V, 2.5V)  Selectable L2 interface of 1.8V or 2.5V  PD Typical 5.3W at 500 MHz, Full Operating Conditions  Nap, Doze and Sleep Modes for Power Saving  Superscalar (Four Instructions fetched per Clock Cycle)  4 GB Direct Addressing Range  Virtual Memory: 4 hexabytes (252)  64-bit Data and 32-bit Address Bus Interface  32 KB Instruction and Data Cache  Eight Independent Execution Units and Three Register Files  Write-back and Write-through Operations  fINT Max = 450 MHz 500 MHz  fBUS Max = 133 MHz

Description

The PC7410 is the second microprocessor that uses the fourth (G4) full implementa- tion of the PowerPC™ Reduced Instruction Set Computer (RISC) architecture. It is fully JTAG-compliant. The PC7410 maintains some of the characteristics of G3 microprocessors:  The design is superscalar, capable of issuing three instructions per clock cycle into eight independent execution units  The microprocessor provides four software controllable power-saving modes and a thermal assist unit management  The microprocessor has separate 32-Kbyte, physically-addressed instruction and data caches with dedicated L2 cache interface with on-chip L2 tags In addition, the PC7410 integrates full hardware-based multiprocessing capability, including a 5-state cache coherency protocol (4 MESI states plus a fifth state for shared intervention) and an implementation of the new AltiVec™ technology instruc- tion set. New features have been developed to make latency equal for double-precision and single-precision floating-point operations involving multiplication. Additionally, in mem- ory subsystem (MSS) bandwidth, the PC7410 offers an optional, high-bandwidth MPX bus interface. Unlike the PC7400, the PC7410 does not support the 3.3V I/O on the L2 cache interface. PowerPC 7410 RISC Microprocessor Product Specification PC7410 Rev. 2141D–HIREL–02/04

2 PC7410

2141D–HIREL–02/04 Screening  CBGA Upscreenings Based on Atmel Standards  Full Military Temperature Range (Tj = -55°C, +125°C), Industrial Temperature Range (Tj = -40°C, +110°C)  CI-CGA Package Version, HiTCE Package Version G suffix CBGA 360 Ceramic Ball Grid Array GH suffix HITCE 360 Ceramic Ball Grid Array CI±CGA 360 Ceramic Ball Grid Array with Solder Column Interposer (SCI) GS suffix

Figure 1. PC7410 Microprocessor Block Diagram

6 Rename

2 Instructions

4 PC7410

General Parameters Table 1 provides a summary of the general parameters of the PC7410. Note: 1. 3.3V I/O bus not supported for 1.5V core power supply processor version. Table 1. Device Parameters

2141D–HIREL–02/04 – Completion of instructions in program order while supporting out-of-order instruction execution, completion serialization and all instruction flow changes  Fixed-point Units (FXUs) that Share 32 GPRs for Integer Operands – Fixed-point unit 1 (FXU1)—multiply, divide, shift, rotate, arithmetic, logical – Fixed-point unit 2 (FXU2)—shift, rotate, arithmetic, logical – Single-cycle arithmetic, shifts, rotates, logical – Multiply and divide support (multi-cycle) – Early out multiply  Three-stage Floating-point Unit and a 32-entry FPR File – Support for IEEE-754 standard single- and double-precision floating-point arithmetic – Three-cycle latency, one-cycle throughput (single or double precision) – Hardware support for divide – Hardware support for denormalized numbers – Time deterministic non-IEEE mode  System Unit – Executes CR logical instructions and miscellaneous system instructions – Special register transfer instructions  AltiVec Unit – Full 128-bit data paths – Two dispatchable units: vector permute unit and vector ALU unit – Contains its own 32-entry 128-bit vector register file (VRF) with six renames – The vector ALU unit is further sub-divided into the vector simple integer unit (VSIU), the vector complex integer unit (VCIU) and the vector floating-point unit (VFPU). – Fully pipelined  Load/Store Unit – One-cycle load or store cache access (byte, half-word, word, double-word) – Two-cycle load latency with one-cycle throughput – Effective address generation – Hits under misses (multiple outstanding misses) – Single-cycle unaligned access within double-word boundary – Alignment, zero padding, sign extend for integer register file – Floating-point internal format conversion (alignment, normalization) – Sequencing for load/store multiples and string operations – Store gathering – Executes the cache and TLB instructions – Big- and little-endian byte addressing supported – Misaligned little-endian supported – Supports FXU, FPU, and AltiVec load/store traffic – Complete support for all four architecture AltiVec DST streams  Level 1 (L1) Cache Structure – 32K 32-byte line, 8-way set associative instruction cache (iL1)

6 PC7410

2141D–HIREL–02/04 – 32K 32-byte line, 8-way set associative data cache (dL1) – Single-cycle cache access – Pseudo least-recently-used (LRU) replacement – Data cache supports AltiVec LRU and transient instructions algorithm – Copy-back or write-through data cache (on a page-per-page basis) – Supports all PowerPC memory coherency modes – Non-blocking instruction and data cache – Separate copy of data cache tags for efficient snooping – No snooping of instruction cache except for ICBI instruction  Level 2 (L2) Cache Interface – Internal L2 cache controller and tags; external data SRAMs – 512K, 1M and 2-Mbyte 2-way set associative L2 cache support – Copyback or write-through data cache (on a page basis or for all L2) – 32-byte (512K), 64-byte (1M), or 128-byte (2M) sectored line size – Supports pipelined (register-register) synchronous burst SRAMs and pipelined (register-register) late-write synchronous burst SRAMs – Supports direct mapped mode for 256K, 512K, 1M or 2 Mbytes of SRAM (either all, half or none of L2 SRAM must be configured as direct mapped. – Core-to-L2 frequency divisors of ÷1, ÷1.5, ÷2, ÷2.5, ÷3, ÷3.5, and ÷4 supported – 64-bit data bus which also support 32-bits bus mode – Selectable interface voltages of 1.8V and 2.5V  Memory Management Unit – 128 entry, 2-way set associative instruction TLB – 128 entry, 2-way set associative data TLB – Hardware reload for TLBs – Four instruction BATs and four data BATs – Virtual memory support for up to four petabytes (2 52) of virtual memory – Real memory support for up to four gigabytes (232) of physical memory – Snooped and invalidated for TLBI instructions  Efficient Data Flow – All data buses between VRF , load/store unit, dL1, iL1, L2 and the bus are 128 bits wide – dL1 is fully pipelined to provide 128 bits per cycle to/from the VRF – L2 is fully pipelined to provide 128 bits per L2 clock cycle to the L1s – Up to eight outstanding out-of-order cache misses between dL1 and L2/bus – Up to seven outstanding out-of-order transactions on the bus – Load folding to fold new dL1 misses into older outstanding load and store misses to the same line – Store miss merging for multiple store misses to the same line. Only coherency action taken (i.e., address only) for store misses merged to all 32 bytes of a cache line (no data tenure needed). – Two-entry finished store queue and four-entry completed store queue between load/store unit and dL1

2141D–HIREL–02/04 – Separate additional queues for efficient buffering of outbound data (castouts, write throughs, etc.) from dL1 and L2  Bus Interface – MPX bus extension to 60X processor interface – Mode-compatible with 60x processor interface – 32-bit address bus – 64-bit data bus – Bus-to-core frequency multipliers of 2x, 2.5x, 3x, 3.5x, 4x, 4.5x, 5x, 5.5x, 6x, 6.5x, 7x, 7.5x, 8x, 9x supported – Selectable interface voltages of 1.8V, 2.5V and 3.3V  Power Management – Low-power design with thermal requirements very similar to PC740 and PC750 – Low voltage 1.8V or 1.5V processor core – Selectable interface voltages of 1.8V can reduce power in output buffers – Three static power saving modes: doze, nap, and sleep – Dynamic power management  Testability – LSSD scan design – IEEE 1149.1 JTAG interface – Array built-in self test (ABIST) – factory test only – Redundancy on L1 data arrays and L2 tag arrays  Reliability and Serviceability – Parity checking on 60x and L2 cache buses

8 PC7410

2141D–HIREL–02/04 Signal Description Figure 2. PC7410 Microprocessor Signal Groups PCX7410 VDD OV DD AV DD L2OV DD L2AV DD 13 49 1 GND TS CHK GBL ARTRY WT CI DBG D[0:63] DP[0:7] TA DTI1 TEA BR BG ABB/AMON[0] A[0:31] AP[0:3] TT[0:4] TBST TSIZ[0:2] AACK DBWO, DTI(0) DBB, DMON(0) DTI(2) L2CE L2WE SRESET HRESET HIT L2ADDR[0:18] L2DATA[0:63] L2DP[0:7] L2CLKOUTA, L2CLKOUTB L2SYNC_OUT L2SYNC_IN L2ZZ INT SMI MCP CKSTP_IN CKSTP_OUT SHDO, SHD1 RSRV TBEN EMODE QREQ QACK DRDY SYSCLK PLL_CFG[0:3] CLK_OUT JTAG:COP Factory Test L1_TSTCLK, L2_TSTCLK BVSEL L2VSEL 112 20 1 L2 Cache Address/Data Address Arbitration Address Bus Address Start Transfer Attribute Address Termination Data Arbitration Data Transfer Data Termination L2 Cache Clock/Control Interrupts ResetProcessor Status Control Clock Control Test Interface LSSD_MODE I/O Voltage Selection

compliance with Atmel-Grenoble standard screening.

1. MIL-STD-883: Test methods and procedures for electronics
2. MIL-PRF-38535: Appendix A: General specifications for microcircuits

beyond those listed may affect device reliability or cause permanent damage to the device.

1. Caution: VIN must not exceed OVDD or L2OVDD by more than 0.2V at any time including during power-on reset.
2. Caution: L2OVDD /OVDD must not exceed VDD /AVDD /L2AVDD by more than 2.0V at any time including during power-on reset;

this limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences.

1. Caution: VDD /AVDD /L2AVDD must not exceed L2OVDD /OVDD by more than 0.4V at any time including during power-on reset;

this limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences.

1. VIN may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 3.
2. PC7410RXnnnLE (Rev 1.4) and later only. Previous revisions do not support 3.3V OVDD and have a maximum value OVDD of

Table 2. Absolute Maximum Ratings(1)

10 PC7410

Figure 3. Overshoot/Undershoot Voltage mum voltage applied to the OVDD or L2OVDD power pins.

1. To select the 2.5V threshold option, L2VSEL/BVSEL should be tied to HRESET so
2. To overcome the internal pull-up resistance, a pull-down resistance less than 250Ω
3. Default voltage setting if left unconnected (internal pulled-up). Parts Rev 1.4 and later
4. Parts Rev 1.4 and later only. Previous revisions do not support 3.3V OVDD , having

BVSEL = 1 selects the 2.5V threshold.

1. Parts Rev 1.4 and later only. Previous revisions do not support BVSEL = HRESET.
2. NSpec does not support the default OVDD setting of 3.3V. The BVSEL input must be

Table 3. Input Threshold Voltage Setting

1. PC7410RXnnnLE (Rev 1.4) and later only. Previous revisions do not support 3.3V OV DD and have a recommended OV DD

value of 2.5V ±100 mV for BVSEL = 1.

1. PC7410RXnnnLE (Rev 1.4) and later only. Previous revisions do not support BVSEL = HRESET.
2. Not supported for N spec with VDD = 1.5V

Table 4. Recommended Operating Conditions(1)

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ture, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance.

1. Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal.
2. Per JEDEC JESD51-6 with the board horizontal.
3. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on

the top surface of the board near the package.

1. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883

Method 1012.1) with the calculated case temperature. The actual value of RθJC for the part is less than 0.1°C/W. See “Thermal Management Information” on page 13 for more details about thermal management. exposed-die packaging technology as in Table 5, the intrinsic conduction thermal resistance paths are shown in Figure 4. Table 6 provides the package thermal characteristics for the PC7410, HiTCE. Notes: 1. Simulation, no convection air flow.

1. Per JEDEC JESD51-6 with the board horizontal.

Table 5. Package Thermal Characteristics CBGA Table 6. Package Thermal Characteristics for HiTCE Package Table 7. Package Thermal Characteristics for CI-CGA

14 PC7410

mance of these thermal interface materials improves with increasing contact pressure. circuit board (see Figure 5). This spring force should not exceed 5.5 pounds of force. adequate mechanical strength to meet equipment shock/vibration requirements. Figure 6. Thermal Performance of Different Thermal Interface Materials

2141D–HIREL–02/04 Heat Sink Selection Example For preliminary heat sink sizing, the die-junction temperature can be expressed as follows: where: Tj = die-junction temperature Ta = inlet cabinet ambient temperature Tr = air temperature rise within the computer cabinet θjc = junction-to-case thermal resistance θint = adhesive or interface material thermal resistance θsa = heat sink base-to-ambient thermal resistance Pd = power dissipated by the device During operation, the die-junction temperatures (Tj) should be maintained less than the value specified in Table 4. The temperature of the air cooling the component greatly depends upon the ambient inlet air temperature and the air temperature rise within the electronic cabinet. An electronic cabinet inlet-air temperature (T a) may range from 30°C to 40°C. The air temperature rise within a cabinet (Tr) may be in the range of 5°C to 10°C. The thermal resistance of the thermal interface material (θint) is typically about 1°C/W. Assuming a Ta of 30°C, a Tr of 5°C, a CBGA package θjc= 0.03, and a power consumption (Pd) of 5.0 watts, the following expression for Tj is obtained: For a Thermally heat sink #2328B, the heat sink-to-ambient thermal resistance (θsa) ver- sus airflow velocity is shown in Figure 7. Tj Ta Tr θjc θint θsa++() Pd×++= Tj 30°C 5°C 0,03°CW⁄ 1,0°CW⁄θ sa++() 5W×++=

16 PC7410

Figure 7. Thermalloy #2328B Heat Sink-to-ambient Thermal Resistance vs. Airflow maximum operating temperature of the component. temperature rise, altitude, etc.

2141D–HIREL–02/04 Due to the complexity and the many variations of system-level boundary conditions for today's microelectronic equipment, the combined effects of the heat transfer mecha- nisms (radiation, convection and conduction) may vary widely. For these reasons, it is recommended to use conjugate heat transfer models for the board, as well as system- level designs. To expedite system-level thermal analysis, several “compact” thermal-package models are available within FLOTHERM ® . These are available upon request. Power Consideration Power Management The PC7410 provides four power modes, selectable by setting the appropriate control bits in the MSR and HIDO registers. The four power modes are:  Full-power: This is the default power state of the PC7410. The PC7410 is fully powered and the internal functional units are operating at the full processor clock speed. If the dynamic power management mode is enabled, functional units that are idle will automatically enter a low-power state without affecting performance, software execution or external hardware.  Doze: All the functional units of the PC7410 are disabled except for the time base/decrementer registers and the bus snooping logic. When the processor is in doze mode, an external asynchronous interrupt, a system management interrupt, a decrementer exception, a hard or soft reset or machine check brings the PC7410 into the full-power state. The PC7410 in doze mode maintains the PLL in a fully powered state and locked to the system external clock input (SYSCLK) so a transition to the full-power state takes only a few processor clock cycles.  Nap: The nap mode further reduces power consumption by disabling bus snooping, leaving only the time base register and the PLL in a powered state. The PC7410 returns to the full-power state upon receipt of an external asynchronous interrupt, a system management interrupt, a decrementer exception, a hard or soft reset or a machine check input (MCP ). A return to full-power state from a nap state takes only a few processor clock cycles. When the processor is in nap mode, if QACK is negated, the processor is put in doze mode to support snooping.  Sleep: Sleep mode minimizes power consumption by disabling all internal functional units, after which external system logic may disable the PLL and SYSCLK. Returning the PC7410 to the full-power state requires the enabling of the PLL and SYSCLK, followed by the assertion of an external asynchronous interrupt, a system management interrupt, a hard or soft reset or a machine check input (MCP ) signal after the time required to relock the PLL.

18 PC7410

power. Worst case power consumption for AVDD = 15 mW and L2AVDD = 15 mW.

1. Maximum power is measured at 105°C, at VDD = 1.8V or 1.5Vwhile running an

units, including AltiVec, maximally busy.

1. Typical power is an average value measured at 65°C, VDD = 1.8V or 1.5V,
2. These values include the use of AltiVec. Without AltiVec operation, estimate a 25%
3. Power consumption derating at low temperatures to be defined after device

Table 8. Power Consumption for PC7410 (1.8V)

Notes: 1. Nominal voltages; see Table 4 for recommended operating conditions.

1. For processor bus signals, the reference is OVDD while L2OVDD is the reference for the L2 bus signals.
2. Excludes factory test signals.
3. Capacitance is periodically sampled rather than 100% tested.
4. The leakage is measured for nominal OVDD and L2OVDD , or both OVDD and L2OVDD must vary in the same direction (for

example, both OVDD and L2OVDD vary by either +5% or –5%).

1. Measured at max OVDD /L2OVDD
2. Excludes IEEE 1149.1 boundary scan (JTAG) signals.

Table 9. DC Electrical Specifications (see Table 4 for Recommended Operating Conditions)

20 PC7410

1. For JTAG support: all signals controlled by BVSEL and L2VSEL will see VIL/VIH/VOL /VOH /CVIH/CVIL DC limits of 1.8V mode

until a different instruction is loaded into the instruction register by either another UpdateIR or a Test-Logic-Reset TAP state. PLL_CFG[0:3] signals. Parts are sold by maximum processor core frequency. Clock AC Specifications Table 10 provides the clock AC timing specifications as defined in Figure 8.

1. Timing is guaranteed by design and characterization.
2. This represents total input jitter, short-term and long-term combined, and is guaranteed by design.
3. Relock timing is guaranteed by design and characterization. PLL-relock time is the maximum amount of time required for

asserted for a minimum of 255 bus clocks after the PLL-relock time during the power-on reset sequence. Table 10. Clock AC Timing Specifications (See Table 4 for Recommended Operating Conditions)

400 MHz 450 MHz 500 MHz

22 PC7410

1. All other output signals are composed of the following - A[0:31], AP[0:3], TT[0:4], TBST, TSIZ[0:2], GBL, WT, CI, DH[0:31],

DL[0:31], DP[0:7], BR, CKSTP_OUT , DRDY, HIT, QREQ , RSRV.

1. According to the 60x bus protocol, ABB and DBB are driven only by the currently active bus master. They are asserted low

time is tested for precharge.The high-Z behavior is guaranteed by design.

1. According to the 60x bus protocol, ARTRY can be driven by multiple bus masters through the clock period immediately fol-

signal asserted. Output valid time is tested for precharge. The high-Z behavior is guaranteed by design.

1. Guaranteed by design and not tested.
2. Output hold time characteristics can be altered by the use of the L2_TSTCK pin during system reset, similar to L2 output

included in future revisions of this specification. Figure 9. Input/Output Timing Diagram

24 PC7410

L2CLK_OUTB must have equal loading.

1. The nominal duty cycle of the L2CLK is 50% measured at midpoint voltage.
2. The DLL re-lock time is specified in terms of L2CLKs. The number in the table must be multiplied by the period of L2CLK to

compute the actual time duration in nanoseconds. Re-lock timing is guaranteed by design and characterization.

1. The L2CR[L2SL] bit should be set for L2CLK frequencies less than 110 MHz. This adds more delay to each tap of the DLL.
2. Allowable skew between L2SYNC_OUT and L2SYNC_IN.
3. Guaranteed by design and not tested. This output jitter number represents the maximum delay of one tap forward or one tap

does not have to be considered in the L2 timing analysis. Table 12. L2CLK Output AC Timing Specifications at Recommended Operating Conditions (See Table 4)

Figure 12. L2CLK_OUT Output Timing Diagram

26 PC7410

defined in Figure 13 and Figure 14 for the loading conditions described in Figure 15. Notes: 1. Rise and fall times for the L2SYNC_IN input are measured from 20% to 80% of L2OVDD .

1. All input specifications are measured from the midpoint of the signal in question to the midpoint voltage of the rising edge of

the input L2SYNC_IN (see Figure 13). Input timings are measured at the pins.

1. All output specifications are measured from the midpoint voltage of the rising edge of L2SYNC_IN to the midpoint of the sig-
2. The outputs are valid for both single-ended and differential L2CLK modes. For pipelined registered synchronous burst

Figure 13. L2 Bus Input Timing Diagram Table 13. L2 Bus Interface AC Timing Specifications at VDD = AVDD = L2AVDD = 1.8V ± 100mV or 1.5V ± 50mV ;

28 PC7410

16, Figure 17, Figure 18 and Figure 19. to the midpoint of the signal in question. The output timings are measured at the pins. delays must be added for trace lengths, vias and connectors in the system.

1. TRST is an asynchronous level sensitive signal. The setup time is for test purposes
2. Non-JTAG signal input timing with respect to TCK.
3. Non-JTAG signal output timing with respect to TCK.
4. Guaranteed by design and characterization

Figure 16. Alternate AC Test Load for the JTAG Interface Figure 17. JTAG Clock Input Timing Diagram Table 14. JTAG AC Timing Specifications (Independent of SYSCLK) (1)at Recom-

30 PC7410

 Devices should be handled on benches with conductive and grounded surfaces.  Ground test equipment, tools and operator.  Do not handle devices by the leads.  Store devices in conductive foam or carriers.  Avoid use of plastic, rubber or silk in MOS areas.  Maintain relative humidity above 50% if practical. package compared with the normal CBGA. 25x25 mm, 360-lead CBGA, HiTCE and CI-CGA.  Dimensions and tolerancing are as per ASME Y14.5M-1994.  All dimensions are in millimeters. A1 corner is designated with a ball missing from the array.  Dimension B is the maximum solder ball diameter measured parallel to datum A. package edge to the chip capacitors. Table 15. Package Parameters

32 PC7410

Figure 23. Cross-section of 360-ball CBGA and HiTCE Package Figure 24. Cross-section of 360-column CI-CGA Package Table 16. Pinout Listing for the PC7410, 360-ball CBGA and CI-CGA packages

Table 16. Pinout Listing for the PC7410, 360-ball CBGA and CI-CGA packages (Continued)

34 PC7410

mended value of VIN or supply voltages, see Table 4.

1. These are test signals for factory use only and must be pulled up to OVDD for normal machine operation.
2. To allow for future I/O voltage changes, provide the option to connect BVSEL and L2VSEL independently to either OVDD
3. Connect to HRESET to trigger post power-on-reset (por) internal memory test.

2141D–HIREL–02/04 5. Ignored in 60x bus mode. 6. Unused output in 60x bus mode. 7. Deasserted (pulled high) at HRESET for 60x bus mode. 8. Uses one of 9 existing no-connects in PC750’s 360-ball BGA package. 9. Internal pull-up on die. 10. Reuses PC750’s DRTRY , DBDIS and TLBISYNC pins (DTI1, DTI2 and EMODE respectively). 11. The VOLTDET pin position on the PC750 360-ball CBGA package is now an L2OVDD pin on the PC7410 packages. 12. Output only for PC7410, was I/O for PC750. 13. Enhanced mode only. 14. To overcome the internal pull-up resistance and ensure this input will recognize a low signal, a pull-down resistance less than 250Ω should be used.

36 PC7410

Figure 25. Mechanical Dimensions and Bottom Surface Nomenclature of the 360-ball CBGA Package

1. Dimensions in millimeters
2. Top side A1 corner index is a metallized feature with various shapes. Bottom side A1 corner is designated with a ball missing

Figure 26. Mechanical Dimensions and Bottom Surface Nomenclature of the 360-ball HiTCE Package

1. Dimensions in millimeters
2. Top side A1 corner index is a metallized feature with various shapes. Bottom side A1 corner is designated with a ball missing

38 PC7410

Figure 27. Mechanical Dimensions and Bottom Surface Nomenclature of the 360-column CI-CGA Package

and maximum core frequencies listed in Table 11. Notes: 1. PLL_CFG[0:3] settings not listed are reserved.

1. The sample bus-to-core frequencies shown are for reference only. Some PLL configurations may select bus, core, or VCO

for valid SYSCLK, core, and VCO frequencies.

1. In PLL-bypass mode, the SYSCLK input signal clocks the internal processor directly, the PLL is disabled, and the bus mode

is set for 1:1 mode operation. This mode is intended for factory use and third- party emulator tool development only. Note: The AC timing specifications given in this document do not apply in PLL-bypass mode.

1. In PLL-off mode, no clocking occurs inside the PC7410 regardless of the SYSCLK input.
2. PLL-off mode should not be used during chip power-up sequencing.

Table 17. PC7410 Microprocessor PLL Configuration(1)(2)(3)(4)(5)

33.3 MHz

50 MHz

66.6 MHz

75 MHz

83.3 MHz

100 MHz

133 MHz

0011 PLL off/bypass PLL off, SYSCLK clocks core circuitry directly, 1x bus-to-core implied

1111 PLL off PLL off, no core clocking occurs

40 PC7410

aligned to the clocking of the internal latches in the L2 bus interface. Table 18. In this example, shaded cells represent settings that, for a given core fre- frequencies listed in Table 14. L2CR[L2SL] bit should be set for L2CLK frequencies less than 150 MHz. the PLL and DLL, respectively. ment the circuit shown in Figure 29. should both implement the circuit shown in Figure 28. vias. The L2AVDD pin may be more difficult to route, but is proportionately less critical. Table 18. Sample Core-to-L2 Frequencies

42 PC7410

2141D–HIREL–02/04 Decoupling Recommendations Due to the PC7410’s dynamic power management feature, large address and data buses and high operating frequencies, the PC7410 can generate transient power surges and high frequency noise in its power supply, especially while driving large capacitive loads. This noise must be prevented from reaching other components in the PC7410 system and the PC7410 itself requires a clean, tightly regulated source of power. There- fore, it is recommended that the system designer place at least one decoupling capacitor at each V DD , OVDD , and L2OVDD pin of the PC7410. It is also recommended that these decoupling capacitors receive their power from separate VDD , (L2)OVDD , and GND power planes in the PCB, utilizing short traces to minimize inductance. These capacitors should have a value of 0.01 µF or 0.1 µF. Only ceramic SMT (surface mount technology) capacitors should be used to minimize lead inductance, preferably 0508 or 0603 orientations where connections are made along the length of the part. Consistent with the recommendations of Dr. Howard Johnson in High Speed Digital Design: A Handbook of Black Magic (Prentice Hall, 1993) and contrary to previous rec- ommendations for decoupling PowerPC microprocessors, multiple small capacitors of equal value are recommended over using multiple values of capacitance. In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB, feeding the VDD , L2OVDD , and OVDD planes to enable quick recharging of the smaller chip capacitors. These bulk capacitors should have a low ESR (equivalent series resistance) rating to ensure the quick response time necessary. They should also be connected to the power and ground planes through two vias to minimize inductance. Suggested bulk capacitors are 100 - 330 µF (AVX TPS tantalum or Sanyo OSCON). Connection Recommendations To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal level. Unused active low inputs should be tied to OVDD . Unused active high inputs should be connected to GND. All NC (no-connect) signals must remain unconnected. Power and ground connections must be made to all external VDD , OVDD , L2OVDD , and GND pins of the PC7410. See “L2 Clock AC Specifications” on page 23 for a discussion of the L2SYNC_OUT and L2SYNC_IN signals. Output Buffer DC Impedance The PC7410 60x and L2 I/O drivers are characterized over process, voltage and tem- perature. To measure Z0, an external resistor is connected from the chip pad to OVDD or GND. Then the value of each resistor is varied until the pad voltage is OVDD /2 (see Fig- ure 31). The output impedance is the average of two components, the resistances of the pull-up and pull-down devices. When data is held low, SW2 is closed (SW1 is open), and RN is trimmed until the voltage at the pad equals OVDD /2. RN then becomes the resistance of the pull-down devices. When data is held high, SW1 is closed (SW2 is open), and RP is trimmed until the voltage at the pad equals OVDD /2. RP then becomes the resistance of the pull-up devices. RP and RN are designed to be close to each other in value. Then Z0 = (RP + RN )/2.

Figure 31. Driver Impedance Measurement tion temperature and is relatively unaffected by bus voltage. and must be pulled up to OVDD for normal machine operation. bounce, power supply noise or noise coupling. up through a pull-up resistor (1 kΩ–5 kΩ) to prevent erroneous assertions of this signal. Table 19. Impedance Characteristics with VDD = 1.8V, OVDD = 1.8V or 2.5V,

44 PC7410

2141D–HIREL–02/04 During inactive periods on the bus, the address and transfer attributes may not be driven by any master and may, therefore, float in the high-impedance state for relatively long periods of time. Since the PC7410 must continually monitor these signals for snooping, this float condition may cause excessive power draw by the input receivers on the PC7410 or by other receivers in the system. These signals can be pulled up through weak (10 kΩ) pull-up resistors by the system, address bus driven mode can be enabled (see the PC7410 RISC Microporcessor Family Users’ Manual for more information on this mode), or these signals may be otherwise driven by the system during inactive peri- ods of the bus to avoid this additional power draw. The snooped address and transfer attribute inputs are: A[0:31], AP[0:3], TT[0:4], CI , WT, and GBL. In systems where GBL is not connected and other devices may be asserting TS for a snoopable transaction while not driving GBL to the processor, we recommend that a strong (1 kΩ) pull-up resistor be used on GBL. Note that the PC7410 will only snoop transactions when GBL is asserted. The data bus input receivers are normally turned off when no read operation is in progress and, therefore, do not require pull-up resistors on the bus. Other data bus receivers in the system, however, may require pull-ups, or that those signals be other- wise driven by the system during inactive periods by the system. The data bus signals are: DH[0:31], DL[0:31], and DP[0:7]. If address or data parity is not used by the system, and the respective parity checking is disabled through HID0, the input receivers for those pins are disabled, and those pins do not require pull-up resistors and should be left unconnected by the system. If parity checking is disabled through HID0, and parity generation is not required by the PC7410 (note that the PC7410 always generates parity), then all parity pins may be left uncon- nected by the system. The L2 interface does not normally require pull-up resistors.

2141D–HIREL–02/04 JTAG Configuration Signals Boundary-scan testing is enabled through the JTAG interface signals. The TRST signal is optional in the IEEE 1149.1 specification, but is provided on all processors that imple- ment the PowerPC architecture. While it is possible to force the TAP controller to the reset state using only the TCK and TMS signals, more reliable power-on reset perfor- mance will be obtained if the TRST signal is asserted during power-on reset. Because the JTAG interface is also used for accessing the common on-chip processor (COP) function, simply tying TRST to HRESET is not practical. The COP function of these processors allows a remote computer system (typically, a PC with dedicated hardware and debugging software) to access and control the internal operations of the processor. The COP interface connects primarily through the JTAG port of the processor, with some additional status monitoring signals. The COP port requires the ability to independently assert HRESET or TRST in order to fully control the processor. If the target system has independent reset sources, such as voltage moni- tors, watchdog timers, power supply failures, or push-button switches, then the COP reset signals must be merged into these signals with logic. The arrangement shown in Figure 32 allows the COP port to independently assert HRESET or TRST, while ensuring that the target can drive HRESET as well. If the JTAG interface and COP header will not be used, TRST should be tied to HRESET through a 0Ω isolation resistor so that it is asserted when the system reset signal (HRESET) is asserted ensuring that the JTAG scan chain is initialized during power-on. While Motor- ola recommends that the COP header be designed into the system as shown in Figure 32, if this is not possible, the isolation resistor will allow future access to TRST in the case where a JTAG interface may need to be wired onto the system in debug situations. The COP header shown in Figure 32 adds many benefits — breakpoints, watchpoints, register and memory examination/modification, and other standard debugger features are possible through this interface — and can be as inexpensive as an unpopulated footprint for a header to be added when needed. The COP interface has a standard header for connection to the target system, based on the 0.025" square-post 0.100" centered header assembly (often called a Berg header). The connector typically has pin 14 removed as a connector key. There is no standardized way to number the COP header shown in Figure 32; conse- quently, many different pin numbers have been observed from emulator vendors. Some are numbered top-to-bottom then left-to-right, while others use left-to-right then top-to- bottom, while still others number the pins counter clockwise from pin 1 (as with an IC). Regardless of the numbering, the signal placement recommended in Figure 32 is com- mon to all known emulators. The QACK signal shown in Figure 32 is usually connected to the PCI bridge chip in a system and is an input to the PC7410 informing it that it can go into the quiescent state. Under normal operation this occurs during a low-power mode selection. In order for COP to work, the PC7410 must see this signal asserted (pulled down). While shown on the COP header, not all emulator products drive this signal. If the product does not, a pull-down resistor can be populated to assert this signal. Additionally, some emulator products implement open-drain type outputs and can only drive QACK asserted; for these tools, a pull-up resistor can be implemented to ensure this signal is deasserted when it is not being driven by the tool. Note that the pull-up and pull-down resistors on the QACK signal are mutually exclusive and it is never necessary to populate both in a system. To preserve correct power-down operation, QACK should be merged via logic so that it also can be driven by the PCI bridge.

46 PC7410

Figure 32. COP Connector Diagram PC7410. Connect pin 5 of the COP header to OVDD with a 10 kΩ pull-up resistor.

1. Key location; pin 14 is not physically present on the COP header.
2. Component not populated. Populate only if debug tool does not drive QACK.
3. Populate only if debug tool uses an open-drain type output and does not actively
4. If the JTAG interface is implemented, connect HRESET from the target source to

part through a 0Ω isolation resistor.

1. The COP port and target board should be able to independently assert HRESET and

TRST to the processor in order to fully control the processor as shown above.

Table 20. COP Pin Definitions 2Q A C K QACK Add 2K pull-down to ground. Must be merged with on-board QACK , if any. 4T R S T TRST Add 2K pull-down to ground. Must be merged with on-board TRST if any. 5 RUN/STOP No Connect Used on 604e; leave no-connect for all other processors. 6 VDD_SENSE VDD Add 2K pull-up to OV DD (for short circuit limiting protection only). checkstopping the processor from a logic analyzer of other external trigger.

10 N/A

11 SRESET SRESET Merge with on-board SRESET , if any.

12 N/A

13 HRESET HRESET Merge with on-board HRESET. 14 N/A Key location; pin should be removed. 15 CKSTP_OUT CKSTP_OUT Add 10K pull-up to OV DD .

16 Ground Digital Ground

48 PC7410

2141D–HIREL–02/04 The COP header shown in Figure 32 adds many benefits – breakpoints, watchpoints, register and memory examination/modification and other standard debugger features are possible through this interface – and can be as inexpensive as an unpopulated foot- print for a header to be added when needed. The COP interface has a standard header for connection to the target system, based on the 0.025” square-post 0.100” centered header assembly (often called a “Berg” header). The connector typically has pin 14 removed as a connector key, as shown in Figure 32.

2141D–HIREL–02/04 Definitions Datasheet Status

Applications

These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Atmel customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Atmel for any damages resulting from such improper use or sale. Table 21. Datasheet Status specifications for product development. This datasheet contains preliminary data. for extended periods may affect device reliability.

Application Information

Where application information is given, it is advisory and does not form part of the specification.

50 PC7410

2141D–HIREL–02/04

Ordering Information

Note: 1. For availability of the different versions, contact your local Atmel sales office. Document Revision History Table 22 provides a revision history for this hardware specification. PC 7410 V GS U L x Prefix Type Package (1) G: CBGA GS: CI-CBGA GH: HITCE Screening Level(1) U: Upscreening Revision Level(1) Rev. E Application modifier (1) L: 1.8V ± 100 mV N: 1.5V ± 50 mV (400 MHz only) Temperature Range: Tj (1) V: -40˚C, +110˚C M: -55˚C, +125˚C Prototype (X) Max Internal Processor Speed(1)

400 MHz

450 MHz

500 MHz (TBC)

Table 22. Document Revision History D Public release, includes Rev 1.1 changes. Section — added package capacitor values. used on the PLL_CFG[0:3] signals. Figure 11 on page 23 — revised mode input diagram to show sample points around HRESET negation. and TRST independently to the CPU. figure for AVDD filter for the CBGA package. pull-ups. Removed TBST from snooped transfer attribute list. TBST is an output and is not snooped.

i PC7410 2141D–HIREL–02/04

ii PC7410 [Preliminary] 2141D–HIREL–02/04

2141D–HIREL–02/04

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