MPC750A MOTOROLA | Alldatasheet
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This document contains information on a new product under development by Motorola. Motorola reserves the right to change or discontinue this product without notice. © Motorola, Inc., 2001. All rights reserved. Table 1. MPC750 Microprocessors from Motorola Freescale Semiconductor, Inc. ARCHIVED BY FREESCALE SEMICONDUCTOR, INC.
MPC750A RISC Microprocessor Hardware Specifications This document contains the following topics: Topic Page Section 1.1, “Overview” 3 Section 1.2, “Features” 4 Section 1.3, “General Parameters” 6 Section 1.4, “Electrical and Thermal Characteristics” 6 Section 1.4.1, “DC Electrical Characteristics” 6 Section 1.4.2, “AC Electrical Characteristics” 10 Section 1.4.2.1, “Clock AC Specifications” 10 Section 1.4.2.2, “60x Bus Input AC Specifications” 12 Section 1.4.2.3, “60x Bus Output AC Specifications” 14 Section 1.4.2.4, “L2 Clock AC Specifications” 15 Section 1.4.2.5, “L2 Bus Input AC Specifications” 18 Section 1.4.2.6, “L2 Bus Output AC Specifications” 19 Section 1.5, “Pin Assignments” 23 Section 1.6, “Pinout Listings” 25 Section 1.7, “Package Description” 29 Section 1.8, “System Design Information” 31 Section 1.9, “Document Revision History 42 To locate any published errata or updates for this document, refer to the website at http://www.mot.com/PowerPC/. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC.
1.1 Overview
and an internal L2 Tag combined with a dedicated L2 cache interface and a 60x bus. Figure 1 shows a block diagram of the MPC750. Figure 1. MPC750 Block Diagram Freescale Semiconductor, Inc. ARCHIVED BY FREESCALE SEMICONDUCTOR, INC.
MPC750A RISC Microprocessor Hardware Specifications
Features
1.2 Features
This section summarizes features of the MPC750’s implementation of the PowerPC architecture. Major features of the MPC750 are as follows:
- Branch processing unit — Four instructions fetched per clock — One branch processed per cycle (plus resolving 2 speculations) — Up to 1 speculative stream in execution, 1 additional speculative stream in fetch — 512-entry branch history table (BHT) for dynamic prediction — 64-entry, 4-way set associative branch target instruction cache (BTIC) for eliminating branch delay slots
- Dispatch unit — Full hardware detection of dependencies (resolved in the execution units) — Dispatch two instructions to six independent units (system, branch, load/store, fixed-point unit 1, fixed-point unit 2, or floating-point) — Serialization control (predispatch, postdispatch, execution serialization)
- Decode — Register file access — Forwarding control — Partial instruction decode
- Load/store unit — One cycle load or store cache access (byte, half-word, word, double-word) — Effective address generation — Hits under misses (one outstanding miss) — Single-cycle misaligned access within double word boundary — Alignment, zero padding, sign extend for integer register file — Floating-point internal format conversion (alignment, normalization) — Sequencing for load/store multiples and string operations — Store gathering — Cache and TLB instructions — Big- and little-endian byte addressing supported — Misaligned little-endian support in hardware
- Fixed-point units — Fixed-point unit 1 (FXU1)—multiply, divide, shift, rotate, arithmetic, logical — Fixed-point unit 2 (FXU2)—shift, rotate, arithmetic, logical — Single-cycle arithmetic, shift, rotate, logical — Multiply and divide support (multi-cycle) — Early out multiply
- Floating-point unit — Support for IEEE-754 standard single- and double-precision floating-point arithmetic — 3 cycle latency, 1 cycle throughput, single-precision multiply-add Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC.
MPC750A RISC Microprocessor Hardware Specifications — 3 cycle latency, 1 cycle throughput, double-precision add — 4 cycle latency, 2 cycle throughput, double-precision multiply-add — Hardware support for divide — Hardware support for denormalized numbers — Time deterministic non-IEEE mode
- System unit — Executes CR logical instructions and miscellaneous system instructions — Special register transfer instructions
- Cache structure — 32K, 32-byte line, 8-way set associative instruction cache — 32K, 32-byte line, 8-way set associative data cache — Single-cycle cache access — Pseudo-LRU replacement — Copy-back or write-through data cache (on a page per page basis) — Supports all PowerPC memory coherency modes — Non-blocking instruction and data cache (one outstanding miss under hits) — No snooping of instruction cache
- Memory management unit — 128 entry, 2-way set associative instruction TLB — 128 entry, 2-way set associative data TLB — Hardware reload for TLBs — 4 instruction BATs and 4 data BATs — Virtual memory support for up to 4 exabytes (2 ) of virtual memory — Real memory support for up to 4 gigabytes (2 ) of physical memory
- Level 2 (L2) cache interface (not implemented on MPC740) — Internal L2 cache controller and 4K-entry tags; external data SRAMs — 256K, 512K, and 1 Mbyte 2-way set associative L2 cache support — Copy-back or write-through data cache (on a page basis, or for all L2) — 64-byte (256K/512K) and 128-byte (1-Mbyte) sectored line size — Supports flow-through (reg-buf) synchronous burst SRAMs, pipelined (reg-reg) synchronous burst SRAMs, and pipelined (reg-reg) late-write synchronous burst SRAMs — Core-to-L2 frequency divisors of ÷1, ÷1.5, ÷2, ÷2.5, and ÷3 supported
- Bus interface — Compatible with 60x processor interface — 32-bit address bus — 64-bit data bus supported
- Integrated power management — Low-power 2.6/3.3-volt design — Three static power saving modes: doze, nap, and sleep Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC.
- Integrated Thermal Management Assist Unit — On-chip thermal sensor and control logic — Thermal Management Interrupt for software regulation of junction temperature.
- Testability — LSSD scan design — JTAG interface
- Reliability and serviceability—Parity checking on 60x and L2 cache buses
1.3 General Parameters
1.4 Electrical and Thermal Characteristics
This section provides the AC and DC electrical specifications and thermal characteristics for the MPC750.
1.4.1 DC Electrical Characteristics
Table 2. Absolute Maximum Ratings Freescale Semiconductor, Inc. ARCHIVED BY FREESCALE SEMICONDUCTOR, INC.
Table 4 provides the package thermal characteristics for the MPC750. for more information on the use of this feature. Specifications for the thermal sensor portion of the TAU are found in Table 5. these conditions is not guaranteed.
- For extended temperature parts marked MPC750ARXnnnTH or MPC740ARXnnnTH only (where nnn is
the operating frequency from Table 8. Table 4. Package Thermal Characteristics Refer to Section 1.8, “System Design Information,” for more details about thermal management. Table 5. Thermal Sensor Specifications
1 Temperature range 0 127 °C 1
2 Comparator settling time 20 — µs 2
3 Resolution 4 — °C 3
- The temperature is the junction temperature of the die. The thermal assist unit’s raw output does not indicate an
the Thermal Assist Unit in the MPC750 Microprocessor”.
- The comparator settling time value must be converted into the number of CPU clocks that need to be written into
- Guaranteed by design and characterization.
Table 3. Recommended Operating Conditions (Continued) Freescale Semiconductor, Inc. ARCHIVED BY FREESCALE SEMICONDUCTOR, INC.
Table 6 provides the DC electrical characteristics for the MPC750. Table 7 provides the power consumption for the MPC750. Table 6. DC Electrical Specifications
- Nominal voltages; See Table 3 for recommended operating conditions.
- For 60x bus signals, the reference is OVdd
while L2OVdd is the reference for the L2 bus signals.
- Excludes test signals (LSSD_MODE, L1_TSTCLK, L2_TSTCLK) and IEEE 1149.1 boundary scan (JTAG) signals.
- Applicable to L2 bus interface only
- Capacitance is periodically sampled rather than 100% tested.
- The leakage is measured for nominal OVdd and Vdd, or both OVdd and Vdd must vary in the same direction (for example, both
OVdd and Vdd vary by either +5% or -5%). Table 7. Power Consumption for MPC750
200 MHz 233 MHz 266 MHz
Freescale Semiconductor, Inc. ARCHIVED BY FREESCALE SEMICONDUCTOR, INC.
1.4.2 AC Electrical Characteristics
maximum processor core frequency; see Section 1.10, “Ordering Information”.
1.4.2.1 Clock AC Specifications
Table 8 provides the clock AC timing specifications as defined in Figure 3.
- These values apply for all valid 60x bus and L2 bus ratios. The values do not include I/O Supply Power (OVdd and
<10% of Vdd power. Worst case power consumption for AVdd = 15 mW and L2AVdd = 15 mW.
- Maximum power is measured at Vdd = 2.7V.
- Typical power is an average value measured at Vdd = AVdd = L2AVdd = 2.6V, OVdd = L2OVdd = 3.3V in a system
executing typical applications and benchmark sequences.
- Full-On mode is measured using worst-case instruction sequence.
Table 8. Clock AC Timing Specifications
1 SYSCLK cycle time 12 40 12 40 12 40 ns
Table 7. Power Consumption for MPC750 (Continued) Freescale Semiconductor, Inc. ARCHIVED BY FREESCALE SEMICONDUCTOR, INC.
Figure 3 provides the SYSCLK input timing diagram. Figure 3. SYSCLK Input Timing Diagram
4 SYSCLK duty cycle
- Caution: The SYSCLK frequency and PLL_CFG[0–3] settings must be chosen such that the resulting
- Rise and fall times for the SYSCLK input are measured from 0.4 to 2.4V.
- Timing is guaranteed by design and characterization.
- The total input jitter (short term and long term combined) must be under ±150 ps.
- Relock timing is guaranteed by design and characterization. PLL-relock time is the maximum amount of time
specification also applies when the PLL has been disabled and subsequently re-enabled during sleep mode. the power-on reset sequence. Table 8. Clock AC Timing Specifications (Continued) Freescale Semiconductor, Inc. ARCHIVED BY FREESCALE SEMICONDUCTOR, INC.
12 MPC750A RISC Microprocessor Hardware Specifications
Figure 5. Input timing specifications for the L2 bus are provided in Section 1.4.2.5, “L2 Bus Input AC Table 9. 60x Bus Input AC Timing Specifications1
- All input specifications are measured from the TTL level (0.8 to 2.0V) of the signal in question to the 1.4V of
the rising edge of the input SYSCLK. Input and output timings are measured at the pin.
- Address/Data/Transfer Attribute inputs are composed of the following—A[0–31], AP[0–3], TT[0–4], TBST ,
- All other signal inputs are composed of the following—TS , ABB, DBB, ARTRY, BG, AACK, DBG, DBWO,
TA, DRTRY, TEA, DBDIS, HRESET, SRESET, INT, SMI, MCP, TBEN, QACK, TLBISYNC.
- The setup and hold time is with respect to the rising edge of HRESET (see Figure 5).
- tsysclk is the period of the external clock (SYSCLK) in nanoseconds (ns). The numbers given in the table
- Guaranteed by design and characterization.
- This specification is for configuration mode select only. Also note that the HRESET must be held asserted
for a minimum of 255 bus clocks after the PLL re-lock time during the power-on reset sequence. Freescale Semiconductor, Inc. ARCHIVED BY FREESCALE SEMICONDUCTOR, INC.
14 MPC750A RISC Microprocessor Hardware Specifications
Table 10 provides the 60x bus output AC timing specifications for the MPC750 as defined in Figure 6. Table 10. 60x Bus Output AC Timing Specifications1
12 SYSCLK to Output Driven (Output Enable
13 SYSCLK to Output Valid (TS, ABB, ARTR Y,
14 SYSCLK to all other Outputs Valid (all
16 SYSCLK to Output High Impedance (all
17 SYSCLK to ABB , DBB High Impedance
18 SYSCLK to AR TR Y High Impedance
20 Maximum Delay to AR TR Y Precharge — 1 t sysclk 4,7
21 SYSCLK to AR TR Y High Impedance After
- All output specifications are measured from the 1.4V of the rising edge of SYSCLK to TTL level (0.8 V or
2.0 V) of the signal in question. Both input and output timing are measured at the pin.
- All maximum timing specifications assume CL = 50 pF.
- This minimum parameter assumes CL = 0 pF.
- tsysclk is the period of the external bus clock (SYSCLK) in nanoseconds (ns). The numbers given in the
- Output signal transitions from GND to 2.0V or OVdd to 0.8V.
- Nominal precharge width for ABB and DBB is 0.5 tsysclk.
- Nominal precharge width for ARTRY is 1.0 tsysclk.
- Guaranteed by design and characterization.
Freescale Semiconductor, Inc. ARCHIVED BY FREESCALE SEMICONDUCTOR, INC.
Figure 6 provides the output timing diagram for the MPC750. Figure 6. Output Timing Diagram
1.4.2.4 L2 Clock AC Specifications
Table 11 provides the L2CLK output AC timing specifications as defined in Figure 7. Table 11. L2CLK Output AC Timing Specifications
23 L2CLK duty cycle 50 % 2
Freescale Semiconductor, Inc. ARCHIVED BY FREESCALE SEMICONDUCTOR, INC.
16 MPC750A RISC Microprocessor Hardware Specifications
- L2CLK outputs are L2CLK_OUTA, L2CLK_OUTB and L2SYNC_OUT pins. The L2 cache interface supports higher frequencies
operating frequencies. L2CLK_OUTA and L2CLK_OUTB must have equal loading.
- The nominal duty cycle of the L2CLK is 50% measured at midpoint voltage.
- The DLL re-lock time is specified in terms of L2CLKs. The number in the table must be multiplied by the period of L2CLK to
compute the actual time duration in nanoseconds. Re-lock timing is guaranteed by design and characterization.
- The L2CR[L2SL] bit should be set for L2CLK frequencies less than 110 MHz
- Guaranteed by design and not tested.
Table 11. L2CLK Output AC Timing Specifications (Continued) Freescale Semiconductor, Inc. ARCHIVED BY FREESCALE SEMICONDUCTOR, INC.
The L2CLK_OUT timing diagram is shown in Figure 7. Figure 7. L2CLK_OUT Output Timing Diagram Freescale Semiconductor, Inc. ARCHIVED BY FREESCALE SEMICONDUCTOR, INC.
18 MPC750A RISC Microprocessor Hardware Specifications
1.4.2.5 L2 Bus Input AC Specifications
The L2 bus input interface AC timing specifications are found in Table 12. Figure 8 shows the L2 bus input timing diagrams for the MPC750. Figure 8. L2 Bus Input Timing Diagrams Table 12. L2 Bus Input Interface AC Timing Specifications1
- All input specifications are measured from the TTL level (0.8V or 2.0V) of the signal in question to the midpoint voltage of the rising
edge of the input L2SYNC_IN. Input timings are measured at the pins (see Figure 8).
- Rise and fall times for the L2SYNC_IN input are measured from 0.4 to 2.4V.
Freescale Semiconductor, Inc. ARCHIVED BY FREESCALE SEMICONDUCTOR, INC.
1.4.2.6 L2 Bus Output AC Specifications
Figure 9 shows the L2 bus output timing diagrams for the MPC750. Table 13. L2 Bus Output Interface AC Timing Specifications1
- All outputs are measured from the midpoint voltage of the rising edge of
output timings are measured at the pins. 2.The outputs are valid for both single-ended and differential L2CLK modes. L2CR[14–15] = 01 is recommended.
- All maximum timing specifications assume CL =20 pF.
- This measurement assumes CL = 5 pF.
Freescale Semiconductor, Inc. ARCHIVED BY FREESCALE SEMICONDUCTOR, INC.
20 MPC750A RISC Microprocessor Hardware Specifications
Figure 9. L2 Bus Output Timing Diagrams Table 14. JTAG AC Timing Specifications (Independent of SYSCLK)
1 TCK cycle time 30 — ns
3 TCK rise and fall times 0 2 ns
4 Specification obsolete, intentionally omitted
5 TRST assert time 25 — ns 1
6 Boundary-scan input data setup time 4 — ns 2
7 Boundary-scan input data hold time 15 — ns 2
8 TCK to output data valid 4 20 ns 3
9 TCK to output high impedance 3 19 ns 3, 4
10 TMS, TDI data setup time 0 — ns
Freescale Semiconductor, Inc. ARCHIVED BY FREESCALE SEMICONDUCTOR, INC.
Figure 10 provides the JTAG clock input timing diagram. Figure 10. JTAG Clock Input Timing Diagram Figure 11 provides the TRST timing diagram. Figure 11. TRST Timing Diagram
11 TMS, TDI data hold time 12 — ns
12 TCK to TDO data valid 4 12 ns
13 TCK to TDO high impedance 3 9 ns 4
- TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.
- Non-JTAG signal input timing with respect to TCK.
- Non-JTAG signal output timing with respect to TCK.
- Guaranteed by design and characterization.
Table 14. JTAG AC Timing Specifications (Independent of SYSCLK) (Continued) Freescale Semiconductor, Inc. ARCHIVED BY FREESCALE SEMICONDUCTOR, INC.
22 MPC750A RISC Microprocessor Hardware Specifications
Figure 12 provides the boundary-scan timing diagram. Figure 12. Boundary-Scan Timing Diagram Figure 13 provides the test access port timing diagram. Figure 13. Test Access Port Timing Diagram Freescale Semiconductor, Inc. ARCHIVED BY FREESCALE SEMICONDUCTOR, INC.
1.5 Pin Assignments
Figure 14. Pinout of the MPC740, 255 CBGA Package as Viewed from the Top Surface Freescale Semiconductor, Inc. ARCHIVED BY FREESCALE SEMICONDUCTOR, INC.
24 MPC750A RISC Microprocessor Hardware Specifications
Figure 15. Pinout of the MPC750, 360 CBGA Package as Viewed from the Top Surface Freescale Semiconductor, Inc. ARCHIVED BY FREESCALE SEMICONDUCTOR, INC.
1.6 Pinout Listings
Table 15 provides the pinout listing for the MPC740, 255 CBGA package. Table 15. Pinout Listing for the MPC740, 255 CBGA Package Freescale Semiconductor, Inc. ARCHIVED BY FREESCALE SEMICONDUCTOR, INC.
26 MPC750A RISC Microprocessor Hardware Specifications
Table 16 provides the pinout listing for the MPC750, 360 CBGA package.
- These are test signals for factory use only and must be pulled up to OVdd for normal machine operation.
- OVdd inputs supply power to the I/O drivers and Vdd inputs supply power to the processor core.
- Internally tied to GND in the MPC740 CBGA package to indicate to the power supply that a low-voltage processor
is present. This signal is not a power supply input. Table 16. Pinout Listing for the MPC750, 360 CBGA Package Table 15. Pinout Listing for the MPC740, 255 CBGA Package (Continued) Freescale Semiconductor, Inc. ARCHIVED BY FREESCALE SEMICONDUCTOR, INC.
Table 16. Pinout Listing for the MPC750, 360 CBGA Package (Continued) Freescale Semiconductor, Inc. ARCHIVED BY FREESCALE SEMICONDUCTOR, INC.
28 MPC750A RISC Microprocessor Hardware Specifications
- These are test signals for factory use only and must be pulled up to OVdd for normal machine operation.
- OVdd inputs supply power to the I/O drivers and Vdd inputs supply power to the processor core.
- Internally tied to L2OVDD in the MPC750 CBGA package to indicate the power present at the L2 cache interface.
This signal is not a power supply input. Caution: This is different from the MPC740 CBGA package.
- These pins are reserved for potential future use as additional L2 address pins.
Freescale Semiconductor, Inc. ARCHIVED BY FREESCALE SEMICONDUCTOR, INC.
MPC750A RISC Microprocessor Hardware Specifications 29 Package Description
1.7 Package Description
The following sections provide the package parameters and mechanical dimensions for the MPC740, 255 CBGA packages.
1.7.1 Parameters for the MPC740
The package parameters are as provided in the following list. The package type is 21 x 21 mm, 255-lead ceramic ball grid array (CBGA). Package outline 21 x 21 mm Interconnects 255 (16 x 16 ball array - 1) Pitch 1.27 mm (50 mil) Minimum module height 2.45 mm Maximum module height 3.00 mm Ball diameter 0.89 mm (35 mil)
1.7.2 Mechanical Dimensions of the MPC740
Figure 16 provides the mechanical dimensions and bottom surface nomenclature of the MPC740, 255 CBGA package. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC.
30 MPC750A RISC Microprocessor Hardware Specifications
Figure 16. Mechanical Dimensions and Bottom Surface Nomenclature of the MPC740
1.7.3 Parameters for the MPC750
ceramic ball grid array (CBGA). Freescale Semiconductor, Inc. ARCHIVED BY FREESCALE SEMICONDUCTOR, INC.
1.7.4 Mechanical Dimensions of the MPC750
Figure 17. Mechanical Dimensions and Bottom Surface Nomenclature of the MPC750
1.8 System Design Information
- DIMENSIONS AND TOLERANCING PER ASME
- DIMENSIONS IN MILLIMETERS.
- DIMENSION b IS THE MAXIMUM SOLDER BALL
DIAMETER MEASURED PARALLEL TO DATUM A.
- D2 AND E2 DEFINE THE AREA OCCUPIED BY THE
PACKAGE EDGE TO THE CHIP CAPACITORS.
- CAPACITORS MAY NOT BE PRESENT ON ALL
- CAUTION MUST BE TAKEN NOT TO SHORT
Freescale Semiconductor, Inc. ARCHIVED BY FREESCALE SEMICONDUCTOR, INC.
32 MPC750A RISC Microprocessor Hardware Specifications
1.8.1 PLL Configuration
configuration for the MPC750 is shown in Table 17 for nominal frequencies. Table 17. MPC750 Microprocessor PLL Configuration
25 MHz
40 MHz
50 MHz
75 MHz
0011 PLL off/bypass PLL off, SYSCLK clocks core circuitry directly, 1x bus-to-core implied
1111 PLL off PLL off, no core clocking occurs
- PLL_CFG[0–3] settings not listed are reserved.
- The sample bus-to-core frequencies shown are for reference only. Some PLL configurations may select bus, core, or VCO
Specifications,” for valid SYSCLK and VCO frequencies.
- In PLL-bypass mode, the SYSCLK input signal clocks the internal processor directly, the PLL is disabled, and the bus mode is
set for 1:1 mode operation. This mode is intended for factory use only. Note: The AC timing specifications given in this document do not apply in PLL-bypass mode.
- In clock-off mode, no clocking occurs inside the MPC750 regardless of the SYSCLK input.
Freescale Semiconductor, Inc. ARCHIVED BY FREESCALE SEMICONDUCTOR, INC.
Table 18 provides sample core-to-L2 frequencies.
1.8.2 PLL Power Supply Filtering
Figure 18. PLL Power Supply Filter Circuit
1.8.3 Decoupling Recommendations
PCB, utilizing short traces to minimize inductance. Table 18. Sample Core-to-L2 Frequencies bit should be set for L2CLK frequencies less than 110 MHz. Freescale Semiconductor, Inc. ARCHIVED BY FREESCALE SEMICONDUCTOR, INC.
34 MPC750A RISC Microprocessor Hardware Specifications
These capacitors should vary in value from 220 pF to 10 µF to provide both high- and low-frequency filtering, and should be placed as close as possible to their associated Vdd or OVdd pins. Suggested values for the Vdd pins—220 pF (ceramic), 0.01 µF (ceramic), and 0.1 µF (ceramic). Suggested values for the OVdd pins—0.01 µF (ceramic), 0.1 µF (ceramic), and 10 µF (tantalum). Only SMT (surface mount technology) capacitors should be used to minimize lead inductance. In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB, feeding the Vdd and OVdd planes, to enable quick recharging of the smaller chip capacitors. These bulk capacitors should have a low ESR (equivalent series resistance) rating to ensure the quick response time necessary. They should also be connected to the power and ground planes through two vias to minimize inductance. Suggested bulk capacitors—100 µF (A VX TPS tantalum) or 330 µF (A VX TPS tantalum).
1.8.4 Connection Recommendations
To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal level. Unused active low inputs should be tied to Vdd. Unused active high inputs should be connected to GND. All NC (no-connect) signals must remain unconnected. Power and ground connections must be made to all external Vdd, OVdd, and GND pins of the MPC750. External clock routing should ensure that the rising-edge of the L2 clock is coincident at the CLK input of all SRAMs and at the L2SYNC_IN input of the MPC750. The L2CLKOUTA network could be used only, or the L2CLKOUTB network could also be used depending on the loading, frequency, and number of SRAMs.
1.8.5 Output Buffer DC Impedance
The MPC750 60x and L2 I/O drivers were characterized over process, voltage, and temperature. To measure Z0, an external resistor is connected to the chip pad, either to OVdd or OGND. Then, the value of such resistor is varied until the pad voltage is OVdd/2; see Figure 19. The output impedance is actually the average of two components, the resistances of the pull-up and pull-down devices. When Data is held low, SW1 is closed (SW2 is open), and RN is trimmed until Pad = OVdd/2. RN then becomes the resistance of the pull-down devices. When Data is held high, SW2 is closed (SW1 is open), and RP is trimmed until Pad = OVdd/2. RP then becomes the resistance of the pull-up devices. With a properly designed driver RP and RN are close to each other in value. Then Z0 = (RP + RN )/2. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC.
Figure 19. Driver Impedance Measurement simulation at 65 °C. As the process varies, the output impedance will be reduced by several ohms. Table 19. Impedance Characteristics Freescale Semiconductor, Inc. ARCHIVED BY FREESCALE SEMICONDUCTOR, INC.
36 MPC750A RISC Microprocessor Hardware Specifications
1.8.6 Pull-up Resistor Requirements
The MPC750 requires high-resistive (weak: 10 KΩ ) pull-up resistors on several control signals of the bus interface to maintain the control signals in the negated state after they have been actively negated and released by the MPC750 or other bus masters. These signals are TS, ABB, DBB, and ARTR Y. In addition, the MPC750 has one open-drain style output that requires a pull-up resistors (weak or stronger: 4.7 KΩ –10 KΩ ) if it is used by the system. This signal is CKSTP_OUT. During inactive periods on the bus, the address and transfer attributes on the bus are not driven by any master and may float in the high-impedance state for relatively long periods of time. Since the MPC750 must continually monitor these signals for snooping, this float condition may cause excessive power draw by the input receivers on the MPC750 or by other receivers in the system. It is recommended that these signals be pulled up through weak (10 KΩ ) pull-up resistors or restored in some manner by the system. The snooped address and transfer attribute inputs are A[0–31], AP[0–3], TT[0–4], TBST, and GBL. The data bus input receivers are normally turned off when no read operation is in progress and do not require pull-up resistors on the data bus. Other data bus receivers in the system, however, may require pullups, or that those signals be otherwise driven by the system during inactive periods. The data bus signals are If address or data parity is not used by the system, and the respective parity checking is disabled through HID0, the input receivers for those pins are disabled, and those pins do not require pull-up resistors and should be left unconnected by the system. If all parity generation is disabled through HID0, then all parity checking should also be disabled through HID0, and all parity pins may be left unconnected by the system. No pull-up resistors are normally required for the L2 interface.
1.8.7 Thermal Management Information
This section provides thermal management information for the ceramic ball grid array (CBGA) package for air-cooled applications. Proper thermal control design is primarily dependent upon the system-level design—the heat sink, airflow and thermal interface material. To reduce the die-junction temperature, heat sinks may be attached to the package by several methods—adhesive, spring clip to holes in the printed-circuit board or package, and mounting clip and screw assembly; see Figure 20. This spring force should not exceed 5.5 pounds of force. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... ARCHIVED BY FREESCALE SEMICONDUCTOR, INC.
Figure 20. Package Exploded Cross-Sectional View with Several Heat Sink Options performance at a given air velocity, spatial volume, mass, attachment method, assembly, and cost. Freescale Semiconductor, Inc. ARCHIVED BY FREESCALE SEMICONDUCTOR, INC.
38 MPC750A RISC Microprocessor Hardware Specifications
1.8.7.1 Internal Package Conduction Resistance
- The die junction-to-case (or top-of-die for exposed silicon) thermal resistance
- The die junction-to-ball thermal resistance Figure 21 depicts the primary heat transfer path for a package with an attached heat sink mounted to a printed-circuit board.
Figure 21. C4 Package with Heat Sink Mounted to a Printed-Circuit Board thermal resistances are the dominant terms.
1.8.7.2 Adhesives and Thermal Interface Materials
joint results in a thermal resistance approximately 7 times greater than the thermal grease joint. manufacturability, service temperature, dielectric properties, cost, etc. Freescale Semiconductor, Inc. ARCHIVED BY FREESCALE SEMICONDUCTOR, INC.
Figure 22. Thermal Performance of Select Thermal Interface Material
77 Dragon Court
3256 West 25th Street
1001 Trout Brook Crossing
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40 MPC750A RISC Microprocessor Hardware Specifications
1.8.7.3 Heat Sink Selection Example
Table 3. The temperature of the air cooling the component greatly depends upon the ambient inlet air velocity is shown in Figure 23. Freescale Semiconductor, Inc. ARCHIVED BY FREESCALE SEMICONDUCTOR, INC.
Figure 23. Thermalloy #2328B Heat Sink-to-Ambient Thermal Resistance Versus Airflow Velocity operating temperature of the component. Engineering offer different heat sink-to-ambient thermal resistances, and may or may not need air flow. interconnect technology, system air temperature rise, altitude, etc. Freescale Semiconductor, Inc. ARCHIVED BY FREESCALE SEMICONDUCTOR, INC.
42 MPC750A RISC Microprocessor Hardware Specifications
1.9 Document Revision History
1.10 Ordering Information
processor frequency, the part numbering scheme also consists of a part modifier and application modifier. Table 20. Document Revision History process with attendant changes in supply voltages and electrical characteristics. Changed Table 2 to include absolute maximum supply voltage for MPC750P . supply voltage down to 2.5V for all parts. Added Table 7 to provide power consumption of MPC750P . 300 MHz to AC specifications. Changed Table 13 and Table 14 to show test conditions appropriate to the process. describing the unique operating conditions of that part. Added extended junction temperature parts to Table 3. Rev 2.1 Removed 333MHz column from Table 13. Rev 2.2 In Table 7, Maximum sleep power is increased to 300 mW. Rev 2.3 Corrected Figure 16 and Figure 17, which omitted some dimensions due to format error. Freescale Semiconductor, Inc. ARCHIVED BY FREESCALE SEMICONDUCTOR, INC.
MPC750A RISC Microprocessor Hardware Specifications 43
Ordering Information
revision code. This refers to the die mask revision number and is specified in the part numbering scheme for identification purposes only. Figure 24. Motorola Part Number Key Freescale Semiconductor, Inc. ARCHIVED BY FREESCALE SEMICONDUCTOR, INC.
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