PC66-222-620

HYS6472V4200GU SIEMENS | Alldatasheet

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Technical content

3.3V 4M x 64/72-Bit 1 BANK SDRAM Module 3.3V 8M x 64/72-Bit 2 BANK SDRAM Module PC66 & PC100 168 pin unbuffered DIMM Modules HYS64(72)V4200GU HYS64(72)V8220GU

• 168 Pin unbuffered 8 Byte Dual-In-Line SDRAM Modules for PC main memory applications
• One bank 4M x 64, 4Mx72 and two bank 8M x 64, 8M x 72 organisation
• Optimized for byte-write non-parity and ECC applications
• JEDEC standard Synchronous DRAMs (SDRAM)
• Fully PC board layout compatible to INTEL’s Rev. 1.0 module specification
• SDRAM Performance:
• Programmed Latencies :
• Single +3.3V(± 0.3V ) power supply
• Programmable CAS Latency, Burst Length and Wrap Sequence (Sequential & Interleave)
• Auto Refresh (CBR) and Self Refresh
• Decoupling capacitors mounted on substrate
• All inputs, outputs are LVTTL compatible
• Serial Presence Detect with E2PROM
• Utilizes 4M x16 SDRAMs in TSOPII-54 packages
• 4096 refresh cycles every 64 ms
• 133,35 mm x 29,31 mm x 4,00 mm card size with gold contact pads -8 -8B -10 Units fCK Clock frequency (max.) 100 100 66 MHz tAC Clock access time 6 6 8 ns Product Speed CL tRCD tRP -8 PC100 2 2 2 -8B PC100 3 2 3 - 1 0 P C 6 6 222 18 . 9 8

HYS64(72)V4200/8220GU SDRAM-Modules Semiconductor Group 2 The HYS64(72)V4200 and HYB64(72)V8220 are an industry standard 168-pin 8-byte Dual in-line Memory Module (DIMM) which are organised as 4M x 64, 4M x 72 in an one bank and 8M x 64, 8M x72 in two banks high speed memory arrays designed with 64Mbit Synchronous DRAMs (SDRAMs Die Rev.B) for non-parity and ECC application. The DIMMs use -8 and -8B speed sort 4M x 16 SDRAM devices in TSOP54 packages to meet the PC100 requirements and -10 parts for 66 MHz bus speed applications. Decoupling capacitors are mounted on the PC board. The PC board design is according to INTEL’s module specification. The DIMMs have a serial presence detect, implemented with a serial E 2PROM using the two pin I2C protocol. The first 128 bytes are utilized by the DIMM manufacturer and the second 128 bytes are available to the end user. All SIEMENS 168-pin DIMMs provide a high performance, flexible 8-byte interface in a 133,35 mm long footprint, with t.d.b. height.

Ordering Information

Address Format: Type Ordering Code Package Descriptions Module Height HYS 64V4200GU-8 PC100-222-620 L-DIM-168-31 100 Mhz 4M x 64 1 bank SDRAM module 1,15” HYS 72V4200GU-8 PC100-222-620 L-DIM-168-31 100 MHz 4M x 72 1 bank SDRAM module 1,15” HYS 64V8220GU-8 PC100-222-620 L-DIM-168-31 100 Mhz 8M x 64 2 bank SDRAM module 1,15” HYS 64V8220GU-8 PC100-222-620 L-DIM-168-31 100 MHz 8M x 72 2 bank SDRAM module 1,15” HYS 64V4200GU-8B PC100-323-620 L-DIM-168-31 100 Mhz 4M x 64 1 bank SDRAM module 1,15” HYS 64V8220GU-8B PC100-323-620 L-DIM-168-31 100 Mhz 8M x 64 2 bank SDRAM module 1,15” HYS 64V4200GU-10 PC66-222-620 L-DIM-168-31 66 Mhz 4M x 64 1 bank SDRAM module 1,15” HYS 72V4200GU-10 PC66-222-620 L-DIM-168-31 66 MHz 4M x 72 1 bank SDRAM module 1,15” HYS 64V8220GU-10 PC66-222-620 L-DIM-168-31 66 Mhz 8M x 64 2 bank SDRAM module 1,15” HYS 64V8220GU-10 PC66-222-620 L-DIM-168-31 66 MHz 8M x 72 2 bank SDRAM module 1,15” A0-A11 Address Inputs (RA0~ RA11 / CA0 ~ CA7, CA10) CLK0 - CLK3 Clock Input BA0 , BA1 Bank Select DQMB0 - DQMB7 Data Mask DQ0 - DQ63 Data Input/Output CS0 - CS3 Chip Select CB0-CB7 Check Bits (x 72 organisation only) Vcc Power (+3.3 Volt) RAS Row Address Strobe Vss Ground CAS Column Address Strobe SCL Clock for Presence Detect WE Read / Write Input SDA Serial Data Out for Pres. Detect CKE0, CKE1 Clock Enable N.C. / DU No Connection Part Number Rows Columns Bank Select Refresh Period Interval 4M x 64 HYS64V4200GU 12 8 2 4k 64 ms 15,6 µs 4M x 72 HYS72V4200GU 12 8 2 4k 64 ms 15,6 µs 8M x 64 HYS64V8220GU 12 8 2 4k 64 ms 15,6 µs 8M x 72 HYS72V8220GU 12 8 2 4k 64 ms 15,6 µs

HYS64(72)V4200/8220GU SDRAM-Modules Semiconductor Group 3 Pin Configuration Note : Pinnames in brackets are for the x72 ECC versions PIN # Symbol PIN # Symbol PIN # Symbol PIN # Symbol

1 VSS 43 VSS 85 VSS 127 VSS

2 DQ0 44 DU 86 DQ32 128 CKE0

3 DQ1 45 CS2 87 DQ33 129 CS3

4 DQ2 46 DQMB2 88 DQ34 130 DQMB6

5 DQ3 47 DQMB3 89 DQ35 131 DQMB7

6 VCC 48 DU 90 VCC 132 NC

7 DQ4 49 VCC 91 DQ36 133 VCC

8 DQ5 50 NC 92 DQ37 134 NC

9 DQ6 51 NC 93 DQ38 135 NC

10 DQ7 52 NC (CB2) 94 DQ39 136 CB6

11 DQ8 53 NC (CB3) 95 DQ40 137 CB7

12 VSS 54 VSS 96 VSS 138 VSS

13 DQ9 55 DQ16 97 DQ41 139 DQ48

14 DQ10 56 DQ17 98 DQ42 140 DQ49

15 DQ11 57 DQ18 99 DQ43 141 DQ50

16 DQ12 58 DQ19 100 DQ44 142 DQ51

17 DQ13 59 VCC 101 DQ45 143 VCC

18 VCC 60 DQ20 102 VCC 144 DQ52

19 DQ14 61 NC 103 DQ46 145 NC

20 DQ15 62 DU 104 DQ47 146 DU

21 NC (CB0) 63 CKE1 105 NC (CB4) 147 NC

22 NC (CB1) 64 VSS 106 NC (CB5) 148 VSS

23 VSS 65 DQ21 107 VSS 149 DQ53

24 NC 66 DQ22 108 NC 150 DQ54

25 NC 67 DQ23 109 NC 151 DQ55

26 VCC 68 VSS 110 VCC 152 VSS

27 WE 69 DQ24 111 CAS 153 DQ56

28 DQMB0 70 DQ25 112 DQMB4 154 DQ57

29 DQMB1 71 DQ26 113 DQMB5 155 DQ58

30 CS0 72 DQ27 114 CS1 156 DQ59

31 DU 73 VCC 115 RAS 157 VCC

32 VSS 74 DQ28 116 VSS 158 DQ60

33 A0 75 DQ29 117 A1 159 DQ61

34 A2 76 DQ30 118 A3 160 DQ62

35 A4 77 DQ31 119 A5 161 DQ63

36 A6 78 VSS 120 A7 162 VSS

37 A8 79 CLK2 121 A9 163 CLK3

38 A10 80 NC 122 BA0 164 NC

39 BA1 81 WP 123 NC 165 SA0

40 VCC 82 SDA 124 VCC 166 SA1

41 VCC 83 SCL 125 CLK1 167 SA2

42 CLK0 84 VCC 126 NC 168 VCC

HYS64(72)V4200/8220GU SDRAM-Modules Semiconductor Group 4 Block Diagram for 4M x 64 and 4M x 72 1 bank SDRAM DIMM modules (HYS64V4200GU) A0-A11, BA0, BA1 VCC VSS D0 - D3, (D4) C E2PROM (256wordx8bit) CS LDQM DQ0-DQ7 UDQM DQ8-DQ15 CS0 DQMB0 DQ(7:0) DQMB1 DQ(15:8) DQMB4 DQ32-DQ39 DQMB5 DQ40-DQ47 D0 - D3, (D4) D0 - D3, (D4) D0 - D3, (D4) D0 - D3, (D4) RAS , CAS, WE CKE0 notes: 1) all resistors are 10 Ohms CLK1,CLK3 10 pF WP SDASA0 SA1 SA2 SA0 SA1 SA2 47kSCL SCL CS LDQM DQ0-DQ7 UDQM DQ8-DQ15 CS LDQM DQ0-DQ7 UDQM DQ8-DQ15 CS2 DQMB2 DQ(23:16) DQMB3 DQ(31:24) DQMB6 DQ(55:48) DQMB7 DQ(63:56) CS LDQM DQ0-DQ7 UDQM DQ8-DQ15 CS LDQM DQ0-DQ7 UDQM DQ8-DQ15 Vcc CB(7:0) 2) D4 is only used in the x72 ECC version Clock Wiring CLK0 2 SDRAM+15pF 3 SDRAM+10pF CLK1 Termination Termination CLK2 2 SDRAM+15pF 2 SDRAM+15pF CLK3 Termination Termination 4M x 64 4M x 72 3) DIMM may combine bytes 0 with 4, 1 with 5, 2 with 6 and 3 with 7 to obtain most advantagous board layout to obtain minimum DQ trance length

HYS64(72)V4200/8220GU SDRAM-Modules Semiconductor Group 5 A0-A11, BA0, BA1 VCC VSS D0 - D7, (D8,D9) C E2PROM (256wordx8bit) CS LDQM DQ0-DQ7 UDQM DQ8-DQ15 CS0 DQMB0 DQ(7:0) DQMB1 DQ(15:8) DQMB4 DQ(39:32) DQMB5 DQ(47:40) D0 - D7, (D8,D9) D0 - D7, (D8,D9) D0 - D7, (D8,D9) D0 - D3, (D8) RAS , CAS, WE CKE0 notes: 1) all resistors are 10 Ohms WP SDASA0 SA1 SA2 SA0 SA1 SA2 47kSCL SCL CS LDQM DQ0-DQ7 UDQM DQ8-DQ15 CS LDQM DQ0-DQ7 UDQM DQ8-DQ15 Vcc CB(7:0) 2) D8 & D9 are only used in the x72 ECC version Clock Wiring CLK0 2 SDRAM+15pF 3 SDRAM+10pF CLK2 2 SDRAM+15pF 2 SDRAM+15pF CLK3 2 SDRAM+15pF 2 SDRAM+15pF 8M x 64 8M x 72 3) DIMM may combine bytes 0 with 4, 1 with 5, 2 with 6 and 3 with 7 to obtain most advantagous board layout to obtain minimum DQ trance length CS LDQM DQ0-DQ7 UDQM DQ8-DQ15 CS LDQM DQ0-DQ7 UDQM DQ8-DQ15 CS LDQM DQ0-DQ7 UDQM DQ8-DQ15 Vcc CS1 CS LDQM DQ0-DQ7 UDQM DQ8-DQ15 CS2 DQMB2 DQ(23:16) DQMB3 DQ(31:24) DQMB6 DQ(55:48) DQMB7 DQ(63:56) CS LDQM DQ0-DQ7 UDQM DQ8-DQ15 CS LDQM DQ0-DQ7 UDQM DQ8-DQ15 CS LDQM DQ0-DQ7 UDQM DQ8-DQ15 CS3 CLK1 2 SDRAM+15pF 3 SDRAM+10pF D4 - D7,(D9)CKE1 VDD 10k

HYS64(72)V4200/8220GU SDRAM-Modules Semiconductor Group 6 DC Characteristics TA = 0 to 70 °C; VSS = 0 V; VDD,V DDQ = 3.3 V ± 0.3 V Capacitance TA = 0 to 70 °C; VDD = 3.3 V ± 0.3 V, f = 1 MHz Parameter Symbol Limit Values Unit min. max. Input high voltage VIH 2.0 Vcc+ 0.3 V Input low voltage VIL – 0.5 0.8 V Output high voltage (IOUT = – 2.0 mA) VOH 2.4 – V Output low voltage (IOUT = 2.0 mA) VOL –0 . 4 V Input leakage current, any input (0 V < VIN < 3.6 V, all other inputs = 0 V) II(L) – 10 10 µA Output leakage current (DQ is disabled, 0 V < VOUT < VCC ) IO(L) – 10 10 µA Parameter Symbol Limit Values Unit max. 4M x 72 max. 8M x 72 Input capacitance (A0 to A11, RAS, CAS, WE) C I1 tbd. tbd. pF Input capacitance (CS0 -CS3, ) C I2 tbd. tbd. pF Input capacitance (CLK0 - CLK3) C ICL tbd. tbd. pF Input capacitance (CKE0, CKE1) C I3 tbd. tbd. pF Input capacitance (DQMB0 - DQMB7) C I4 tbd. tbd. pF Input / Output capacitance (DQ0-DQ63,CB0-CB7) C IO tbd. tbd. pF Input Capacitance (SCL,SA0-2) C sc 88 p F Input/Output Capacitance C sd 10 10 pF

HYS64(72)V4200/8220GU SDRAM-Modules Semiconductor Group 7 Operating Currents (TA = 0 to 70oC, Vdd = 3.3V ± 0.3V 1) (Recommended Operating Conditions unless otherwise noted) Parameter & Test Condition Symb. -8/-8B -10 Note max. OPERATING CURRENT trc=trcmin., tck=tckmin. Ouputs open, Burst Length = 4, CL=3 All banks operated in random access, all banks operated in ping-pong manner to maximize gapless data access ICC1 130 90 mA 1 PRECHARGE STANDBY CURRENT in Power Down Mode CS =VIH (min.), CKE<=Vil(max) tck = min. ICC2P 22 m A 1 tck = Infinity ICC2PS 11 m A 1 PRECHARGE STANDBY CURRENT in Non-Power Down Mode CS = VIH (min.), CKE>=Vih(min) tck = min. ICC2N 35 30 mA 1 tck = Infinity ICC2NS 55 m A 1 NO OPERATING CURRENT tck = min., CS = VIH(min), active state ( max. 4 banks) CKE>=VIH(min.) ICC3N 45 40 mA 1 CKE<=VIL(max.) ICC3P 88 m A 1 BURST OPERATING CURRENT tck = min., Read command cycling ICC4 100 70 mA 1,2 AUTO REFRESH CURRENT tck = min., Auto Refresh command cycling ICC5 130 90 mA 1 SELF REFRESH CURRENT Self Refresh Mode, CKE=0.2V standard version ICC6 11 m A 1

HYS64(72)V4200/8220GU SDRAM-Modules Semiconductor Group 8 AC Characteristics 3)4) TA = 0 to 70 °C; VSS = 0 V; VCC = 3.3 V ± 0.3 V, tT = 1 ns Parameter Symbol Limit Values Unit Note PC100-222 -8B PC100-323 -10 PC66 Clock and Clock Enable Clock Cycle Time CAS Latency = 3 CAS Latency = 2 tCK ns ns System Frequency CAS Latency = 3 CAS Latency = 2 fCK 100 100 100 100 MHz MHz Clock Access Time CAS Latency = 3 CAS Latency = 2 tAC ns ns 4,5) Clock High Pulse Width tCH 3–3– 3 . 5 – n s 6) Clock Low Pulse Width tCL 3–3– 3 . 5 – n s 6) Input Setup time tCS 2–2–3– n s 7) Input Hold Time tCH 1–1–1– n s 7) CKE Setup Time (Power down mode) tCKSP 2 . 5–2 . 5– 3 – n s 8) CKE Setup Time (Self Refresh Exit) tCKSR 8– 1 0 –8– n s 9) Transition time (rise and fall)tT 1–1–1– n s Common Parameters RAS to CAS delay tRCD 2 0–2 0–3 0– n s Precharge Time tRP 2 0–3 0–3 0– n s Active Command Period tRAS 50 100k 60 100k 70 100k ns Cycle Time tRC 70 –8 0–8 0– ns Bank to Bank Delay Time tRRD 1 6–2 0–2 0– n s CAS to CAS delay time (same bank) tCCD 1–1–1– C L K

HYS64(72)V4200/8220GU SDRAM-Modules Semiconductor Group 9 Refresh Cycle Refresh Period (4096 cycles)tREF –6 4–6 4–6 4 m s 8) Self Refresh Exit Time tSREX 1 0–1 0–1 0– n s 9) Read Cycle Data Out Hold Time tOH 3–3 3– n s 4) Data Out to Low Impedance tLZ 0–0 0– n s Data Out to High Impedance tHZ 3 8 31 031 0 n s 10) DQM Data Out Disable LatencytDQZ –2–2–2 C L K Write Cycle Data input to Precharge (write recovery) tDPL 2 –2– 2 – CLK Data In to Active/refresh tDAL 5 –5– 5 – CLK DQM Write Mask Latency tDQW 0–0–0– C L K Parameter Symbol Limit Values Unit Note PC100-222 -8B PC100-323 -10 PC66

HYS64(72)V4200/8220GU SDRAM-Modules Semiconductor Group 10 Notes: 1. These parameters depend on the cycle rate. These values are measured at 100 MHz for -8 and -8B and at 66 MHz for -10 modules. Input signals are changed once during tck, excepts for ICC6 and for standby currents when tck=infinity. All values are shown per memory component. 2. These parameters are measured with continous data stream during read access and all DQ toggling. CL=3 and BL=4 assumed and the VDDQ current is excluded. 3. All AC characteristics are shown for device level. An initial pause of 100µs is required after power-up, then a Precharge All Banks command must be given followed by 8 Auto Refresh (CBR) cycles before the Mode Register Set Operation can begin. 4. AC timing tests have V il = 0.4 V and Vih = 2.4 V with the timing referenced to the 1.4 V crossover point. The transition time is measured between Vih and Vil. All AC measurements assume tT=1ns with the AC output load circuit show. Specified tac and toh parameters are measured with a 50 pF only, without any resistive termination and with a input signal of 1V / ns edge rate between 0.8V and 2.0 V. 5. If clock rising time is longer than 1ns, a time (t T/2 -0.5) ns has to be added to this parameter. 6. Rated at 1.5 V 7. If tT is longen than 1 ns, a time (tT -1) ns has to be added to this parameter. 8. Any time that the refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh commands must be given to “wake-up“ the device. 9. Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after CKE returns high. Self Refresh Exit is not complete until a time period equal to tRC is satisfied once the Self Refresh Exit command is registered. 10.Referenced to the time which the output achieves the open circuit condition, not to output voltage levels. 1.4V 1.4V tSETUP tHOLD tAC tAC tLZ tOH tHZ CLOCK INPUT OUTPUT 50 pF I/O Z=50 Ohm + 1.4 V

50 Ohm

2.4 V 0.4 V tT fig.1 tCH tCL 50 pF I/O Measurement conditions for tac and toh

HYS64(72)V4200/8220GU SDRAM-Modules Semiconductor Group 11 A serial presence detect storage device - E2PROM - is assembled onto the module. Information about the module configuration, speed, etc. is written into the E2PROM device during module production using a serial presence detect protocol ( I2C synchronous 2-wire bus) SPD-Table for PC100 modules: Byte# Description SPD Entry Value Hex 4Mx64 4Mx64 -8B 4Mx72 8Mx64 8Mx64 -8B 8Mx72

0 Number of SPD bytes 128 80 80 80 80 80 80

1 Total bytes in Serial PD 256 08 08 08 08 08 08

2 M e m o r y T y p e S D R A M 0 40 40 40 40 40 4

3 Number of Row Addresses (wit-

hout BS bits) 12 0C 0C 0C 0C 0C 0C

4 Number of Column Addresses

(for 16 SDRAM) 8 0 80 80 80 80 80 8

5 N u m b e r o f D I M M B a n k s 1 / 2 0 10 10 10 20 20 2

6 Module Data Width 64 40 40 48 40 40 48

7 Module Data Width (cont’d) 0 00 00 00 00 00 00

8 Module Interface Levels LVTTL 01 01 01 01 01 01

9 SDRAM Cycle Time at CL=3 10.0 ns A0 A0 A0 A0 A0 A0

10 SDRAM Access time from Clock

at CL=3 6.0 ns 60 60 60 60 60 60 11 Dimm Config (Error Det/Corr.) none 00 00 02 00 00 02

12 Refresh Rate/Type Self-Refresh,

15.6µs 80 80 80 80 80 80 1 3 S D R A M w i d t h , P r i m a r y x 1 6 1 0 1 0 1 0 1 0 1 0 1 0

14 Error Checking SDRAM data

n/a / x8 00 00 08 00 00 08

15 Minimum clock delay for back-to-

back random column address t ccd = 1 C L K 0 10 10 10 10 10 1

16 Burst Length supported 1, 2, 4, 8 & full

17 Number of SDRAM banks 4 04 04 04 04 04 04

18 Supported CAS Latencies CL = 2 & 3 06 06 06 06 06 06

1 9 C S L a t e n c i e s C S l a t e n c y = 0 0 10 10 10 10 10 1 2 0 W E L a t e n c i e s W L = 0 0 10 10 10 10 10 1

21 SDRAM DIMM module attributes non buffered/

non reg. 00 00 00 00 00 00

22 SDRAM Device Attributes :Gene-

V c c t o l + / - 1 0 % 0 60 60 60 60 60 6

23 Minimum Clock Cycle Time at

CAS Latency = 2 10.0 / 12.0ns A0 C0 A0 A0 C0 A0

24 Maximum data access time from

Clock for CL=2 6.0 / 7.0ns 60 70 60 60 70 60

25 Minimum Clock Cycle Time at CL

= 1 not supported FF FF FF FF FF FF

26 Maximum Data Access Time

from Clock at CL=1 not supported FF FF FF FF FF FF

27 Minimum Row Precharge Time 20 / 30 ns 14 1E 14 14 1E 14

HYS64(72)V4200/8220GU SDRAM-Modules Semiconductor Group 12 Byte# Description SPD Entry Value Hex 4Mx64 4Mx64 -8B 4Mx72 8Mx64 8Mx64 -8B 8Mx72

28 Minimum Row Active to Row

29 Minimum RAS to CAS delay

30 Minimum RAS pulse width tRAS 45 ns 2D 2D 2D 2D 2D 2D

31 Module Bank Density (per bank) 32 MByte 08 08 08 08 08 08

32 SDRAM input setup time 2 ns 20 20 20 20 20 20

33 SDRAM input hold time 1 ns 10 10 10 10 10 10

34 SDRAM data input setup time 2 ns 20 20 20 20 20 20

35 SDRAM data input hold time 1 ns 10 10 10 10 10 10

62-61 Superset information (may be used in future) FF FF FF FF FF FF 6 2 S P D R e v i s i o n R e v i s i o n 1 . 2 1 21 21 21 21 21 2

63 Checksum for bytes 0 - 62 D7 15 E9 D8 16 EA

Manufacturers information (optio- nal) (FFh if not used) XX XX XX XX XX XX 126 Max. Frequency Specification 100 MHz 64 64 64 64 64 64 127 100 Mhz support details AF AD AF FF FD FF 128+ Unused storage locations FF FF FF FF FF FF

HYS64(72)V4200/8220GU SDRAM-Modules Semiconductor Group 13 SPD-Table for PC66 modules: Byte# Description SPD Entry Value Hex 4Mx64 -10 4Mx72 -10 8Mx64 -10 8Mx72 -10

0 Number of SPD bytes 128 80 80 80 80

1 Total bytes in Serial PD 256 08 08 08 08

2 Memory Type SDRAM 04 04 04 04

3 Number of Row Addresses (without BS bits) 12 0C 0C 0C 0C

(for x16 SDRAM) 8 0 80 80 80 8

5 Number of DIMM Banks 1 / 2 01 01 02 02

6 Module Data Width 64 40 48 40 48

7 Module Data Width (cont’d) 0 00 00 00 00

8 Module Interface Levels LVTTL 01 01 01 01

9 SDRAM Cycle Time at CL=3 10.0 ns A0 A0 A0 A0 10 SDRAM Access time from Clock at CL=3 7.0 ns 70 70 70 70 11 Dimm Config (Error Det/Corr.) none 00 02 00 02 15.6µs 80 80 80 80

13 SDRAM width, Primary x16 10 10 10 10

14 Error Checking SDRAM data width n/a / x8 00 08 00 08

15 Minimum clock delay for back-to-back ran-

t ccd = 1 C L K 0 10 10 10 1

17 Number of SDRAM banks 4 04 04 04 04

18 Supported CAS Latencies CL = 2 & 3 06 06 06 06

19 CS Latencies CS latency = 0 01 01 01 01

20 WE Latencies WL = 0 01 01 01 01

non reg. 00 00 00 00

22 SDRAM Device Attributes :General Vcc tol +/- 10% 06 06 06 06

23 Minimum Clock Cycle Time at CAS Latency

= 2 15.0 ns F0 F0 F0 F0

24 Maximum data access time from Clock for

CL=2 8.0 ns 80 80 80 80

25 Minimum Clock Cycle Time at CL = 1 not supported FF FF FF FF

26 Maximum Data Access Time from Clock at

CL=1 not supported FF FF FF FF

27 Minimum Row Precharge Time 24 ns 18 18 18 18

28 Minimum Row Active to Row Active delay

HYS64(72)V4200/8220GU SDRAM-Modules Semiconductor Group 14 SPD cont’d: Byte# Description SPD Entry Value Hex 4Mx64 4Mx72 8Mx72 8Mx72

29 Minimum RAS to CAS delay tRCD 24 ns 18 18 18 18

30 Minimum RAS pulse width tRAS 60 ns 3C 3C 3C 3C

31 Module Bank Density (per bank) 32 MByte 08 08 08 08

32 SDRAM input setup time 2.5 ns 25 25 25 25

33 SDRAM input hold time 1 ns 10 10 10 10

34 SDRAM data input setup time 2.5 ns 25 25 25 25

35 SDRAM data input hold time 1 ns 10 10 10 10

32-61 Superset information (may be used in future) FF FF FF FF

63 Checksum for bytes 0 - 62 7C 8E 7D 8F

Manufacturers information (optional) (FFh if not used) XX XX XX XX 126 Max. Frequency Specification 66 MHz 66 66 66 66

127 Support details AF AF FF FF

128+ Unused storage locations FF FF FF FF

HYS64(72)V4200/8220GU SDRAM-Modules Semiconductor Group 15 L-DIM-168-31 SDRAM DIMM Module package 133,35 1 84 17,7810 11 40 41 3,0 127,35 168124 125 66,68 42,18 4,0 6,35 2,0 3,125 Detail B 6,35 2,0 3,125 Detail A Detail C 2,54 min. 1,27 1,0 + 0.5- A B C x) on ECC modules only +-0,2 0,15 94 95 DM168-31.WM F 29.31 1,27+ 0.1-