PC100-222-620

HYS64-72V2200GU-8 SIEMENS | Alldatasheet

Document overview

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Technical content

3.3V 2M x 64/72-Bit 1 BANK SDRAM Module 3.3V 4M x 64/72-Bit 2 BANK SDRAM Module 168 pin unbuffered DIMM Modules HYS64/72V2200GU-8/-10 HYS64/72V4220GU-8/-10

• 168 Pin PC100 and PC66 compatible unbuffered 8 Byte Dual-In-Line SDRAM Modules for PC main memory applications
• 1 bank 2M x 64, 2M x 72 and 2 bank 4M x 64, 4M x 72 organisation
• Optimized for byte-write non-parity or ECC applications
• JEDEC standard Synchronous DRAMs (SDRAM)
• Fully PC board layout compatible to INTEL’s Rev. 1.0 module specification
• SDRAM Performance:
• Programmed Latencies :
• Single +3.3V(± 0.3V ) power supply
• Programmable CAS Latency, Burst Length and Wrap Sequence (Sequential & Interleave)
• Auto Refresh (CBR) and Self Refresh
• Decoupling capacitors mounted on substrate
• All inputs, outputs are LVTTL compatible
• Serial Presence Detect with E2PROM
• Utilizes 2M x 8 SDRAMs in TSOPII-44 packages
• 4096 refresh cycles every 64 ms
• 133,35 mm x 31.75 mm x 4,00 mm card size with gold contact pads -8 -8-3 -10 Units fCK Clock frequency (max.) 100 100 66 MHz tAC Clock access time 6 6 8 ns Product Speed CL tRCD tRP -8 PC100 2 2 2 -8-3 PC100 3 2 3 -10 PC66 2 2 2 1 6.98

HYS64(72)V2200/4220GU-8/-10 SDRAM-Modules Semiconductor Group 2 The HYS64(72)2200 and HYS64(72)4220 are industry standard 168-pin 8-byte Dual in-line Memory Modules (DIMMs) which are organised as 2M x 64, 2M x 72 in 1 bank and 4M x 64 and 4M x 72 in two banks high speed memory arrays designed with Synchronous DRAMs (SDRAMs) for non-parity and ECC applications. The DIMMs use -8 speed sort 2M x 8 SDRAM devices in TSOP44 packages to meet the PC100 requirement. Modules which use -10 parts are suitable for PC66 applications only. Decoupling capacitors are mounted on the PC board. The PC board design is according to INTEL’s PC SDRAM Rev.1.0 module specification. The DIMMs have a serial presence detect, implemented with a serial E 2PROM using the two pin I2C protocol. The first 128 bytes are utilized by the DIMM manufacturer and the second 128 bytes are available to the end user. All SIEMENS 168-pin DIMMs provide a high performance, flexible 8-byte interface in a 133,35 mm long footprint, with 1,25“ ( 31,75 mm) height

Ordering Information

Address Format: Type Ordering Code Package Descriptions Module Height HYS 64V2200GU-8 PC100-222-620 L-DIM-168-29 100 Mhz 2M x 64 1 bank SDRAM module 1,25“ HYS 72V2200GU-8 PC100-222-620 L-DIM-168-29 100 MHz 2M x 72 1 bank SDRAM module 1,25“ HYS 64V4220GU-8 PC100-222-620 L-DIM-168-29 100 Mhz 4M x 64 2 bank SDRAM module 1,25“ HYS 72V4220GU-8 PC100-222-620 L-DIM-168-29 100 Mhz 4M x 72 2 bank SDRAM module 1,25“ HYS 64V2200GU-8-3 PC100-323-620 L-DIM-168-29 100 Mhz 2M x 64 1 bank SDRAM module 1,25“ HYS 72V2200GU-8-3 PC100-323-620 L-DIM-168-29 100 MHz 2M x 72 1 bank SDRAM module 1,25“ HYS 64V4220GU-8-3 PC100-323-620 L-DIM-168-29 100 Mhz 4M x 64 2 bank SDRAM module 1,25“ HYS 72V4220GU-8-3 PC100-323-620 L-DIM-168-29 100 Mhz 4M x 72 2 bank SDRAM module 1,25“ HYS 64V2200GU-10 PC66-222-920 L-DIM-168-29 66 Mhz 2M x 64 1 bank SDRAM module 1,25“ HYS 72V2200GU-10 PC66-222-920 L-DIM-168-29 66 MHz 2M x 72 1 bank SDRAM module 1,25“ HYS 64V4220GU-10 PC66-222-920 L-DIM-168-29 66 Mhz 4M x 64 2 bank SDRAM module 1,25“ HYS 72V4220GU-10 PC66-222-920 L-DIM-168-29 66 Mhz 4M x 72 2 bank SDRAM module 1,25“ A0-A10 Address Inputs CLK0 - CLK3 Clock Input BA Bank Address DQMB0 - DQMB7 Data Mask DQ0 - DQ63 Data Input/Output CS0 - CS3 Chip Select CB0-CB7 Check Bits (x72 organisation only) Vcc Power (+3.3 Volt) RAS Row Address Strobe Vss Ground CAS Column Address Strobe SCL Clock for Presence Detect WE Read / Write Input SDA Serial Data Out for Presence Detect CKE0, CKE1 Clock Enable N.C. No Connection Part Number Rows Columns Banks Refresh Period Interval 2M x 64 HYS 64V2200GU 11 9 1 4k 64 ms 15,6 µs 2M x 72 HYS 72V2200GU 11 9 1 4k 64 ms 15,6 µs 4M x 64 HYS 64V4220GU 11 9 1 4k 64 ms 15,6 µs 4M x 72 HYS 72V4220GU 11 9 1 4k 64 ms 15,6 µs

HYS64(72)V2200/4220GU-8/-10 SDRAM-Modules Semiconductor Group 3 Pin Configuration Note : Pinnames in brackets are for the x72 ECC versions PIN # Symbol PIN # Symbol PIN # Symbol PIN # Symbol

1 VSS 43 VSS 85 VSS 127 VSS

2 DQ0 44 DU 86 DQ32 128 CKE0

3 DQ1 45 CS2 87 DQ33 129 CS3

4 DQ2 46 DQMB2 88 DQ34 130 DQMB6

5 DQ3 47 DQMB3 89 DQ35 131 DQMB7

6 VCC 48 DU 90 VCC 132 NC

7 DQ4 49 VCC 91 DQ36 133 VCC

8 DQ5 50 NC 92 DQ37 134 NC

9 DQ6 51 NC 93 DQ38 135 NC

10 DQ7 52 NC (CB2) 94 DQ39 136 CB6

11 DQ8 53 NC (CB3) 95 DQ40 137 CB7

12 VSS 54 VSS 96 VSS 138 VSS

13 DQ9 55 DQ16 97 DQ41 139 DQ48

14 DQ10 56 DQ17 98 DQ42 140 DQ49

15 DQ11 57 DQ18 99 DQ43 141 DQ50

16 DQ12 58 DQ19 100 DQ44 142 DQ51

17 DQ13 59 VCC 101 DQ45 143 VCC

18 VCC 60 DQ20 102 VCC 144 DQ52

19 DQ14 61 NC 103 DQ46 145 NC

20 DQ15 62 DU 104 DQ47 146 DU

21 NC (CB0) 63 CKE1 105 NC (CB4) 147 NC

22 NC (CB1) 64 VSS 106 NC (CB5) 148 VSS

23 VSS 65 DQ21 107 VSS 149 DQ53

24 NC 66 DQ22 108 NC 150 DQ54

25 NC 67 DQ23 109 NC 151 DQ55

26 VCC 68 VSS 110 VCC 152 VSS

27 WE 69 DQ24 111 CAS 153 DQ56

28 DQMB0 70 DQ25 112 DQMB4 154 DQ57

29 DQMB1 71 DQ26 113 DQMB5 155 DQ58

30 CS0 72 DQ27 114 CS1 156 DQ59

31 DU 73 VCC 115 RAS 157 VCC

32 VSS 74 DQ28 116 VSS 158 DQ60

33 A0 75 DQ29 117 A1 159 DQ61

34 A2 76 DQ30 118 A3 160 DQ62

35 A4 77 DQ31 119 A5 161 DQ63

36 A6 78 VSS 120 A7 162 VSS

37 A8 79 CLK2 121 A9 163 CLK3

38 A10 80 NC 122 BA 164 NC

39 NC 81 WP 123 NC 165 SA0

40 VCC 82 SDA 124 VCC 166 SA1

41 VCC 83 SCL 125 CLK1 167 SA2

42 CLK0 84 VCC 126 NC 168 VCC

HYS64(72)V2200/4220GU-8/-10 SDRAM-Modules Semiconductor Group 4 Block Diagram for 2M x 64/72 SDRAM DIMM modules (HYS64/72V2200GU) CS WE DQM DQ0-DQ7 CS WE DQM DQ0-DQ7 CS WE DQM DQ0-DQ7 CS WE DQM DQ0-DQ7 CS WE DQM DQ0-DQ7 CS WE DQM DQ0-DQ7 CS WE DQM DQ0-DQ7 CS WE DQM DQ0-DQ7 CS WE DQM DQ0-DQ7 WE CS0 DQMB0 DQ(7:0) DQMB1 DQ(15:8) CB(7:0) DQMB2 DQ(23:16) DQMB3 DQ(31:24) DQMB4 DQ(39:32) DQMB5 DQ(47:40) DQMB6 DQ(55:48) DQMB7 DQ(63:56) A0-A10,BA VCC VSS D0 - D7,(D8) C0-C7,(C8) WP SDASA0 SA1 SA2 E2PROM (256wordx8bit) SA0 SA1 SA2 D0 - D7,(D8) D0 - D7,(D8) D0 - D7,(D8) D0 - D7,(D8) D0 - D7,(D8) RAS CAS CKE0 Note: D8 is only used in the x72 ECC version CS2 47k Clock Wiring CLK0 4 SDRAM+3.3pF 5 SDRAM CLK1 Termination Termination CLK2 4 SDRAM+3.3pF 4 SDRAM+3.3pF CLK3 Termination Termination 2M x 64 2M x 72 SCL SCL

HYS64(72)V2200/4220GU-8/-10 SDRAM-Modules Semiconductor Group 5 Block Diagram for 4M x 64/72 SDRAM DIMM modules (HYS64/72V4220GU) CS DQM DQ0-DQ7 CS DQM DQ0-DQ7 CS DQM DQ0-DQ7 D16 CS DQM DQ0-DQ7 CS DQM DQ0-DQ7 CS1 CS0 DQMB0 DQ(7:0) DQMB1 DQ(15:8) CB(7:0) DQMB2 DQ(23:16) DQMB3 DQ(31:24) A0-A10,BA VDD VSS D0 - D15,(D16,D17) C0-C31,(C32..C35) E2PROM (256wordx8bit) D0 - D15,(D16,D17) D0 - D7,(D8) D0 - D15,(D16,D17) D0 - D7,(D16) RAS , CAS, WE CKE0 Note: D16 & D17 is only used in the x72 ECC version and all resistor values are 10 Ohms except otherwise noted. CS2 CS DQM DQ0-DQ7 CS DQM DQ0-DQ7 CS DQM DQ0-DQ7 D17 CS DQM DQ0-DQ7 D10 CS DQM DQ0-DQ7 D11 CS DQM DQ0-DQ7 CS DQM DQ0-DQ7 CS DQM DQ0-DQ7 CS DQM DQ0-DQ7 DQMB4 DQ(39:32) DQMB5 DQ(47:40) DQMB6 DQ(55:48) DQMB7 DQ(63:56) CS DQM DQ0-DQ7 D13 CS DQM DQ0-DQ7 D12 CS DQM DQ0-DQ7 D14 CS DQM DQ0-DQ7 D15 CS3 D9 - D15,(D17)CKE1 VDD 10k WP SDASA0 SA1 SA2 SA0 SA1 SA2 47k Clock Wiring CLK0 4 SDRAM+3.3pF 5 SDRAM CLK1 4 SDRAM+3.3pF 5 SDRAM CLK2 4 SDRAM+3.3pF 4 SDRAM+3.3pF CLK3 4 SDRAM+3.3pF 4 SDRAM+3.3pF 4M x 64 4M x 72 SCL SCL

HYS64(72)V2200/4220GU-8/-10 SDRAM-Modules Semiconductor Group 6 DC Characteristics TA = 0 to 70 °C; VSS = 0 V; VDD,V DDQ = 3.3 V ± 0.3 V Capacitance TA = 0 to 70 °C; VDD = 3.3 V ± 0.3 V, f = 1 MHz Parameter Symbol Limit Values Unit min. max. Input high voltage VIH 2.0 Vcc+0.3 V Input low voltage VIL – 0.5 0.8 V Output high voltage (IOUT = – 2.0 mA) VOH 2.4 – V Output low voltage (IOUT = 2.0 mA) VOL – 0.4 V Input leakage current, any input (0 V < VIN < 3.6 V, all other inputs = 0 V) II(L) – 40 40 µA Output leakage current (DQ is disabled, 0 V < VOUT < VCC ) IO(L) – 40 40 µA Parameter Symbol Limit Values Unit max. 2Mx64 max. 2Mx72 max. 4Mx64 max. 4Mx72 Input capacitance (A0 to A10, BA, RAS, CAS, WE) C I1 45 55 80 90 pF Input capacitance (CS0 -CS3 ) C I2 20 25 30 35 pF Input capacitance (CLK0 - CLK3) C ICL 22 38 22 38 pF Input capacitance (CKE0, CKE1) C I3 22 38 50 55 pF Input capacitance (DQMB0 - DQMB7) C I4 13 13 20 20 pF Input / Output capacitance (DQ0-DQ63,CB0-CB7) C IO 13 12 20 20 pF Input Capacitance (SCL,SA0-2) C sc 8888 p F Input/Output Capacitance C sd 10 10 10 10 pF

HYS64(72)V2200/4220GU-8/-10 SDRAM-Modules Semiconductor Group 7 Standby and Refresh Currents (Ta = 0 to 70oC, VCC = 3.3V ± 0.3V) 1) Parameter Symbol Test Condition X64 X72 Note max. Operating Current Icc1 Burst length = 4, CL=3 trc>=trc(min.), tck>=tck(min.), Io=0 mA 2 bank interleave operation 800 900 mA 1,2 Precharged Standby Current in Power Down Mode Icc2P CKE<=VIL(max), tck>=tck(min.) 24 27 mA Icc2PS CKE<=VIL(max), tck=infinite 16 18 mA Precharged Standby Current in Non- power Down Mode Icc2N CKE>=VIH(min), tck>=tck (min.), input changed once in 3 cycles 160 180 mA CS = High Icc2NS CKE>=VIH(min), tck=infinite, no input change 80 90 mA Active Standby Current in Power Down Mode Icc3P CKE<=VIL(max), tck>=tck(min.) 24 27 mA Icc3PS CKE<=VIL(max), tck=infinite 16 18 mA Active Standby Current in Non- power Down Mode Icc3N CKE>=VIH(min), tck>=tck (min.) input changed one time 200 225 mA CS = High Icc3NS CKE=>VIH(min),tck=infinite, no input change 120 135 mA Burst Operating Current Icc4 Burst length = full page, trc = infinite, CL = 3, tck>=tck (min.), Io = 0 mA 2 banks activated 760 855 mA 1,2 Auto (CBR) Refresh Current Icc5 trc>=trc(min) 720 810 mA 1,2 Self Refresh Current Icc6 CKE=<0,2V 16 18 mA 1,2

HYS64(72)V2200/4220GU-8/-10 SDRAM-Modules Semiconductor Group 8 AC Characteristics 3)4) TA = 0 to 70 °C; VSS = 0 V; VCC = 3.3 V ± 0.3 V, tT = 1 ns Parameter Symbol Limit Values Unit Note PC100 2-2-2 -8-3 PC100 3-2-3 -10 PC66 2-2-2 Clock and Clock Enable Clock Cycle Time CAS Latency = 3 CAS Latency = 2 tCK ns ns System Frequency CAS Latency = 3 CAS Latency = 2 fCK 100 100 100 100 100 MHz MHz Clock Access Time CAS Latency = 3 CAS Latency = 2 tAC ns ns 4,5) Clock High Pulse Width tCH 3–3– 3 . 5 – n s 6) Clock Low Pulse Width tCL 3–3– 3 . 5 – n s 6) Input Setup time tCS 2–2–3– n s 7) Input Hold Time tCH 1–1–1– n s 7) CKE Setup Time (Power down mode) tCKSP 2.5 – 2.5 – 3 – ns 8) CKE Setup Time (Self Refresh Exit) tCKSR 8–8–8– n s 9) Transition time (rise and fall)tT 1–1–1– n s Common Parameters RAS to CAS delay tRCD 20 – 20 – 30 – ns Cycle Time tRC 70 120k 70 120k 75 120k ns Active Command Period tRAS 45 – 45 – 45 – ns Precharge Time tRP 20 – 30 – 30 – ns Bank to Bank Delay Time tRRD 16 – 20 – 20 – ns CAS to CAS delay time (same bank) tCCD 1–1–1– C L K

HYS64(72)V2200/4220GU-8/-10 SDRAM-Modules Semiconductor Group 9 Refresh Cycle Self Refresh Exit Time tSREX 10 – 10 – 10 – ns 9) Refresh Period (4096 cycles)tREF 64 – 64 – 64 – ms 8) Read Cycle Data Out Hold Time tOH 3–3–3– n s 4) Data Out to Low Impedance Time tLZ 0–0–0– n s Data Out to High Impedance Time tHZ 393939 n s 10) DQM Data Out Disable Latency tDQZ 2–2–2– C L K Write Cycle Data input to Precharge (write recovery) tDPL 2–2–2 – CLK Data In to Active/refresh tDAL 5–5–5 – CLK 11) DQM Write Mask Latency tDQW 0–0–0– C L K Parameter Symbol Limit Values Unit Note PC100 2-2-2 -8-3 PC100 3-2-3 -10 PC66 2-2-2

HYS64(72)V2200/4220GU-8/-10 SDRAM-Modules Semiconductor Group 10 Notes: 1. The specified values are valid when addresses are changed no more than once during tck(min.) and when No Operation commands are registered on every rising clock edge during tRC(min). Values are shown per module bank. 2. The specified values are valid when data inputs (DQ’s) are stable during tRC(min.). 3. All AC characteristics are shown for device level. An initial pause of 100µs is required after power-up, then a Precharge All Banks command must be given followed by 8 Auto Refresh (CBR) cycles before the Mode Register Set Operation can begin. 4. AC timing tests have V il = 0.4 V and Vih = 2.4 V with the timing referenced to the 1.4 V crossover point. The transition time is measured between Vih and Vil. All AC measurements assume tT=1ns with the AC output load circuit show. Specified tac and toh parameters are measured with a 50 pF only, without any resistive termination and with a input signal of 1V / ns edge rate between 0.8V and 2.0 V. 5. If clock rising time is longer than 1ns, a time (t T/2 -0.5) ns has to be added to this parameter. 6. Rated at 1.5 V 7. If t T is longen than 1 ns, a time (tT -1) ns has to be added to this parameter. 8. Any time that the refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh commands must be given to “ wake-up“ the device. 9. Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after CKE returns high. Self Refresh Exit is not complete until a time period equal to tRC is satisfied once the Self Refresh Exit command is registered. 10.Referenced to the time which the output achieves the open circuit condition, not to output voltage levels. 11.t DAL is equivalent to tDPL + tRP . 1.4V 1.4V tSETUP tHOLD tAC tAC tLZ tOH tHZ CLOCK INPUT OUTPUT 50 pF I/O Z=50 Ohm + 1.4 V

50 Ohm

2.4 V 0.4 V tT fig.1 tCH tCL 50 pF I/O Measurement conditions for tac and toh

HYS64(72)V2200/4220GU-8/-10 SDRAM-Modules Semiconductor Group 11 A serial presence detect storage device - E2PROM - is assembled onto the module. Information about the module configuration, speed, etc. is written into the E2PROM device during module production using a serial presence detect protocol ( I2C synchronous 2-wire bus) SPD-Table: Byte# Description SPD Entry Value Hex 2Mx64 2Mx72 4Mx64 4Mx72

0 Number of SPD bytes 128 80 80 80 80

1 Total bytes in Serial PD 256 08 08 08 08

2 Memory Type SDRAM 04 04 04 04

3 Number of Row Addresses (without BS bits) 11 0B 0B 0B 0B

4 Number of Column Addresses

(for x8 SDRAM) 9 0 90 90 90 9

5 Number of DIMM Banks 1 / 2 01 01 02 02

6 Module Data Width 64 / 72 40 48 40 48

7 Module Data Width (cont’d ) 0 0 00 00 00 0

8 Module Interface Levels LVTTL 01 01 01 01

9 SDRAM Cycle Time at CL=3 10.0 ns A0 A0 A0 A0 10 SDRAM Access time from Clock at CL=3 6.0 ns 60 60 60 60 11 Dimm Config (Error Det/Corr.) none / ECC 00 02 00 02

12 Refresh Rate/Type Self-Refresh,

15.6µs 80 80 80 80

13 SDRAM width, Primary x8 08 08 08 08

14 Error Checking SDRAM data width n/a / x8 00 08 00 08

15 Minimum clock delay for back-to-back ran-

t ccd = 1 CLK 01 01 01 01

16 Burst Length supported 1, 2, 4, 8 & full page 8F 8F 8F 8F

17 Number of SDRAM banks 2 02 02 02 02

18 Supported CAS Latencies CAS

lat. = 2 & 3 06 06 06 06

19 CS Latencies CS latency = 0 01 01 01 01

20 WE Latencies Write latency = 0 01 01 01 01

21 SDRAM DIMM module attributes non buffered/non

reg. 00 00 00 00

22 SDRAM Device Attributes :General Vcc tol +/- 10% 06 06 06 06

23 Min. Clock Cycle Time at CAS Latency = 2 10.0 ns A0 A0 A0 A0 24 Max. data access time from Clock for CL=2 6.0 ns 60 60 60 60

25 Minimum Clock Cycle Time at CL = 1 not supported FF FF FF FF

26 Maximum Data Access Time from Clock at

CL=1 not supported FF FF FF FF

27 Minimum Row Precharge Time 20 ns 14 14 14 14

28 Minimum Row Active to Row Active delay

HYS64(72)V2200/4220GU-8/-10 SDRAM-Modules Semiconductor Group 12 SPD-Table (cont’d): Byte# Description SPD Entry Value Hex 2Mx64 2Mx72 4Mx64 4Mx72

29 Minimum RAS to CAS delay tRCD 20 ns 14 14 14 14

30 Minimum RAS pulse width tRAS 45 ns 2D 2D 2D 2D

31 Module Bank Density (per bank) 16 MByte 04 04 04 04

32 SDRAM input setup time 2 ns 20 20 20 20

33 SDRAM input hold time 1 ns 10 10 10 10

34 SDRAM data input setup time 2 ns 20 20 20 20

35 SDRAM data input hold time 1 ns 10 10 10 10

36-61 Superset information (may be used in future) FF FF FF FF

63 Checksum for bytes 0 - 62 C9 DB CA DC

Manufacturers information (optional) (FFh if not used) XX XX XX XX

126 Frequency Specification 100 MHz 64 64 64 64

127 Details of 100 MHz Support AF AF FF FF

128+ Unused storage locations FF FF FF FF

HYS64(72)V2200/4220GU-8/-10 SDRAM-Modules Semiconductor Group 13 SPD-Table: Byte# Description SPD Entry Value Hex 2Mx64 -8-3 2Mx72 -8-3 4Mx64 -8-3 4Mx72 -8-3 (for x8 SDRAM) 9 0 90 90 90 9 9 SDRAM Cycle Time at CL=3 10.0 ns A0 A0 A0 A0 10 SDRAM Access time from Clock at CL=3 6.0 ns 60 60 60 60 11 Dimm Config (Error Det/Corr.) none / ECC 00 02 00 02 15.6µs 80 80 80 80 t ccd = 1 CLK 01 01 01 01 18 Supported CAS Latencies CAS lat. = 2 & 3 06 06 06 06 reg. 00 00 00 00 23 Min. Clock Cycle Time at CAS Latency = 2 10.0 ns A0 A0 A0 A0 24 Max. data access time from Clock for CL=2 7.0 ns 70 70 70 70 CL=1 not supported FF FF FF FF

27 Minimum Row Precharge Time 30 ns 1E 1E 1E 1E

HYS64(72)V2200/4220GU-8/-10 SDRAM-Modules Semiconductor Group 14 SPD-Table (cont’d): Byte# Description SPD Entry Value Hex 2Mx64 -8-3 2Mx72 -8-3 4Mx64 -8-3 4Mx72 -8-3 36-61 Superset information (may be used in future) FF FF FF FF

63 Checksum for bytes 0 - 62 E7 F9 E8 FA

Manufacturers information (optional) (FFh if not used) XX XX XX XX

127 Details of 100 MHz Support AD AD FD FD

128+ Unused storage locations FF FF FF FF

HYS64(72)V2200/4220GU-8/-10 SDRAM-Modules Semiconductor Group 15 SPD-Table: Byte# Description SPD Entry Value Hex 2Mx64 -10 2Mx72 -10 4Mx64 -10 4Mx72 -10 (for x8 SDRAM) 9 0 90 90 90 9 9 SDRAM Cycle Time at CL=3 10.0 ns A0 A0 A0 A0 10 SDRAM Access time from Clock at CL=3 8.0 ns 80 80 80 80 11 Dimm Config (Error Det/Corr.) none / ECC 00 02 00 02 15.6µs 80 80 80 80 t ccd = 1 CLK 01 01 01 01 18 Supported CAS Latencies CAS lat. = 2 & 3 06 06 06 06 reg. 00 00 00 00 23 Min. Clock Cycle Time at CAS Latency = 2 15.0 ns F0 F0 F0 F0 24 Max. data access time from Clock for CL=2 9.0 ns 90 90 90 90 CL=1 not supported FF FF FF FF

HYS64(72)V2200/4220GU-8/-10 SDRAM-Modules Semiconductor Group 16 SPD-Table (cont’d): Byte# Description SPD Entry Value Hex 2Mx64 -10 2Mx72 -10 4Mx64 -10 4Mx72 -10

29 Minimum RAS to CAS delay tRCD 30 ns 1E 1E 1E 1E

32 SDRAM input setup time 3 ns 30 30 30 30

34 SDRAM data input setup time 3 ns 30 30 30 30

36-61 Superset information (may be used in future) FF FF FF FF

63 Checksum for bytes 0 - 62 A1 B3 A2 B4

Manufacturers information (optional) (FFh if not used) XX XX XX XX

126 Frequency Specification 66 MHz 66 66 66 66

127 Details AF AF FF FF

128+ Unused storage locations FF FF FF FF

HYS64(72)V2200/4220GU-8/-10 SDRAM-Modules Semiconductor Group 17 L-DIM-168-29 SDRAM DIMM Module package 133,35 1 84 17,7810 11 40 41 3,0 127,35 168124 125 66,68 42,18 4,0 6,35 2,0 3,125 Detail B 6,35 2,0 3,125 Detail A Detail C 2,54 min. 1,27 1,0 + 0.5- A B C x) on ECC modules only +-0,2 0,15 DM168-29.WMF 31.75 94 95 RADIUS 1.27 + 0.10 D Detail D 4.45 8.25 2.26