ATF16V8B ATMEL | Alldatasheet
Document overview
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Technical content
Features
- Industry-standard Architecture – Emulates Many 20-pin PALs® – Low-cost Easy-to-use Software Tools High-speed Electrically-erasable Programmable Logic Devices – 10 ns Maximum Pin-to-pin Delay Several Power Saving Options CMOS and TTL Compatible Inputs and Outputs – Input and I/O Pull-up Resistors Advanced Flash Technology – Reprogrammable – 100% Tested High-reliability CMOS Process – 20 Year Data Retention – 100 Erase/Write Cycles – 2,000V ESD Protection – 200 mA Latchup Immunity Commercial, and Industrial Temperature Ranges Dual-in-line and Surface Mount Packages in Standard Pinouts PCI-compliant Green Package Options (Pb/Halide-free/RoHS Compliant) Available 1. Description The ATF16V8B is a high-performance CMOS (electricallyerasable) programmable logic device (PLD) that utilizes Atmel’s pr oven electrically-erasable Flash memory technology. All speed ranges are specified over the full 5V ± 10% range for industrial temperature ranges, and 5V ± 5% for commercial temperature ranges. Several low-power options allow selection of the best solution for various types of power-limited applications. Each of these options significantly reduces total system power and enhances system reliability. The ATF16V8Bs incorporate a superset of the generic architectures, which allows direct replacement of the 16R8 family and most 20-pin combinatorial PLDs. Eight out- puts are each allocated eight product terms. Three different modes of operation, configured automatically with software, allow highly complex logic functions to be realized. Device I CC, Standby I CC, Active ATF16V8B 50 mA 55 mA ATF16V8BQ 35 mA 40 mA ATF16V8BQL 5 mA 20 mA High- performance EE PLD ATF16V8B ATF16V8BQ ATF16V8BQL 0364J–PLD–7/05
0364J–PLD–7/05 ATF16V8B/BQ/BQL 3. Absolute Maximum Ratings* Maximum Ratings” may cause permanent dam- age to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note: 1. Minimum voltage is -0.6V DC, which may under- shoot to -2.0V for pulses of less than 20 ns. Maximum output pin voltage is V CC + 0.75V DC, which may overshoot to 7.0V for pulses of less than 20 ns. oC to +150oC Voltage on Any Pin with Voltage on Input Pins with Respect to Ground (1) Programming Voltage with (1) 4. DC and AC Operating Conditions Commercial Industrial Operating Temperature (Ambient) 0 oC - 70oC- 4 0 oC - 85oC VCC Power Supply 5V ± 5% 5V ± 10%
0364J–PLD–7/05 ATF16V8B/BQ/BQL Note: 1. Not more than one output at a time should be shorted. Duration of short circuit test should not exceed 30 sec.
4.1 DC Characteristics
Symbol Parameter Condition Min Typ Max Units IIL Input or I/O Low Leakage Current 0 ≤ VIN ≤ VIL(Max) -35 -100 µA IIH Input or I/O High Leakage Current 3.5 ≤ VIN ≤ VCC 10 µA ICC Power Supply Current, Standby VCC = Max, VIN = Max, Outputs Open B-10 Com. 55 85 mA Ind. 55 95 mA B-15 Com. 50 75 mA B-15 Ind. 50 80 mA BQ-10 Com. 35 55 mA BQL-15 Com. 5 10 mA BQL-15 Ind. 5 15 mA I CC2 Clocked Power Supply Current VCC = Max, Outputs Open, f = 15 MHz B-10 Com. 60 90 mA Ind. 60 100 mA B-15 Com. 55 85 mA B-15 Ind. 55 95 mA BQ-10 Com. 40 55 mA BQL-15 Com. 20 35 mA BQL-15 Ind. 20 40 mA I OS (1) Output Short Circuit Current VOUT = 0.5 V -130 mA VIL Input Low Voltage -0.5 0.8 V VIH Input High Voltage 2.0 V CC+0.75 V VOL Output High Voltage VIN = VIH or VIL, VCC = Min IOL = -24 mA Com., Ind. 0.5 V VOH Output High Voltage VIN = VIH or VIL, VCC = Min IOH = -4.0 mA 2.4 V
0364J–PLD–7/05 ATF16V8B/BQ/BQL
4.2 AC Waveforms (1)
specified. Note: 1. See ordering information for valid part numbers and speed grades.
4.3 AC Characteristics (1)
-10 -15 UnitsMin Max Min Max tPD Input or Feedback to Non-Registered Output 8 outputs switching 31 031 5 ns tCF Clock to Feedback 6 8 ns tCO Clock to Output 2 7 2 10 ns tS Input or Feedback Setup Time 7.5 12 ns tH Hold Time 0 0 ns tP Clock Period 12 16 ns tW Clock Width 6 8 ns fMAX External Feedback 1/(tS + tCO)6 8 4 5 M H z Internal Feedback 1/(tS + tCF)7 4 5 0 M H z No Feedback 1/(tP)8 3 6 2 M H z tEA Input to Output Enable — Product Term 3 10 3 15 ns tER Input to Output Disable — Product Term 2 10 2 15 ns tPZX OE pin to Output Enable 2 10 2 15 ns tPXZ OE pin to Output Disable 1.5 10 1.5 15 ns
0364J–PLD–7/05 ATF16V8B/BQ/BQL
4.4 Input Test Waveforms
4.4.1 Input Test Waveforms and Measurement Levels
tR, tF < 5 ns (10% to 90%)
4.4.2 Output Test Loads (Commercial)
CL includes Test fixture and Probe capacitance
4.5 Pin Capacitance
Note: 1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested. Table 4-1. Pin Capacitance (f = 1 MHz, T = 25°C(1)) Typ Max Units Conditions CIN 58 p F V IN = 0V COUT 68 p F V OUT = 0V
0364J–PLD–7/05 ATF16V8B/BQ/BQL
4.6 Power-up Reset
The registers in the ATF16V8Bs are designed to reset during power-up. At a point delayed slightly from VCC crossing VRST, all registers will be reset to the low state. As a result, the regis- tered output state will always be high on power-up. This feature is critical for state machine initialization. However, due to the asynchronous nature of reset and the uncertainty of how V CC actually rises in the system, the following conditions are required: 1. The V CC rise must be monotonic, 2. After reset occurs, all input and feedback setup times must be met before driving the clock pin high, and 3. The clock must remain stable during t PR. Figure 4-1. Power-up Reset Waveforms
4.7 Preload of Registered Outputs
The ATF16V8B’s registers are provided with circuitry to allow loading of each register with either a high or a low. This feature will simplify testing since any state can be forc ed into the registers to control test sequencing. A JEDEC file with preload is generated when a source file with vec- tors is compiled. Once downloaded, the JEDEC file preload sequence will be done automatically by most of the approved programmers after the programming. 5. Security Fuse Usage A single fuse is provided to prevent unauthorized copying of the ATF16V8B fuse patterns. Once programmed, fuse verify and preload are inhibited. However, the 64-bit User Signature remains accessible. The security fuse should be programmed last, as its effect is immediate. Table 4-2. Power-up Reset Parameters Parameter Description Typ Max Units tPR Power-up Reset Time 600 1,000 ns VRST Power-up Reset Voltage 3.8 4.5 V
0364J–PLD–7/05 ATF16V8B/BQ/BQL in the following pages. The user can download the listed subset device JEDEC programming file to the PLD programmer, and the ATF16V8B can be configured to act like the chosen device. Check with your programmer manufacturer for this capability. Unused product terms are automatically disabled by the compiler to decrease power consump- tion. A security fuse, when programmed, protects the content of the ATF16V8B. Eight bytes (64 fuses) of User Signature are accessible to the user for purposes such as storing project name, part number, revision, or date. The User Signature is accessible regardless of the state of the security fuse. 10. Software Support Atmel-WinCUPL is a free tool, available on Atmel’s web site and can be used to design in all members of the Atmel ATF16V8B family of SPLDs. Table 10-1 lists popular compilers with the appropriate device mnemonics Note: 1. Only applicable for version 3.4 or lower. 11. Macrocell Configuration Software compilers support the three different OMC modes as different device types. Most com- pilers have the ability to automatically select the device type, generally based on the register usage and output enable (OE) usage. Register us age on the device forces the software to choose the registered mode. All combinatorial ou tputs with OE controlled by the product term will force the software to c hoose the complex mode. The softw are will choose the simple mode only when all outputs are dedicated combinatorial without OE control. The different device types can be used to override the automatic device sele ction by the software. For further details, refer to the compiler software manuals. When using compiler software to configure the device, the user must pay special attention to the following restrictions in each mode. In registered mode pin 1 and pin 11 are permanently configured as clock and output enable, respectively. These pins cannot be configured as dedicated inputs in the registered mode. In complex mode pin 1 and pin 11 become dedicated inputs and use the feedback paths of pin 19 and pin 12 respectively. Because of this feedback path usage, pin 19 and pin 12 do not have the feedback option in this mode. In simple mode all feedback paths of the output pins are routed via the adjacent pins. In doing so, the two inner most pins (pins 15 and 16) will not have the feedback option as these pins are always configured as dedicated combinatorial output. Table 10-1. Compiler Mode Selection Registered Complex Simple Auto Select ABEL, Atmel-ABEL P16V8R P16V8C P16V8AS P16V8 CUPL, Atmel-WinCUPL G16V8MS G16V8MA G16V8AS G16V8 LOG/iC GAL16V8_R(1) GAL16V8_C7(1) GAL16V8_C8(1) GAL16V8 OrCAD-PLD “Registered” “Complex” “Simple” GAL16V8A PLDesigner P16V8R P16V8C P16V8C P16V8A Tango-PLD G16V8R G16V8C G16V8AS G16V8
0364J–PLD–7/05 ATF16V8B/BQ/BQL
11.1 ATF16V8B R egistered Mode
PAL Device Emulation/PAL Replacement. The registered mode is used if one or more regis- ters are required. Each macrocell can be configured as either a registered or combinatorial output or I/O, or as an input. For a registered output or I/O, the output is enabled by the OE pin, and the register is clocked by the CLK pin. Ei ght product terms are allocated to the sum term. For a combinatorial output or I/O, the output enable is controlled by a product term, and seven product terms are allocated to the sum term. When the macrocell is configured as an input, the output enable is permanently disabled. Any register usage will make the compiler select this mode. The following registered devices can be emulated using this mode: 16R8 16RP8 16R6 16RP6 16R4 16RP4 Figure 11-1. Registered Configuration for Registered Mode(1)(2) Notes: 1. Pin 1 controls common CLK for the r egistered outputs. Pin 11 controls common OE for the reg- istered outputs. Pin 1 and Pin 11 are permanently configured as CLK and OE. 2. The development software configures all the arch itecture control bits and checks for proper pin usage automatically. Figure 11-2. Combinatorial Configuration for Registered Mode(1)(2) Notes: 1. Pin 1 and Pin 11 are permanently configured as CLK and OE . 2. The development software configures all the arch itecture control bits and checks for proper pin usage automatically.
0364J–PLD–7/05 ATF16V8B/BQ/BQL Figure 11-3. Registered Mode Logic Diagram
0364J–PLD–7/05 ATF16V8B/BQ/BQL
11.2 ATF16V8B Complex Mode
PAL Device Emulation/PAL Replacement. In the complex mode, combinatorial output and I/O functions are possible. Pins 1 and 11 are regular inputs to the array. Pins 13 through 18 have pin feedback paths back to the AND-array, which makes full I/O capability possible. Pins 12 and 19 (outermost macrocells) are output s only. They do not have input capability. In this mode, each macrocell has seven product terms going to the sum term and one product term enabling the output. Combinatorial applications with an OE requirement will make the compiler select this mode. The following devices can be emulated using this mode: 16L8 16H8 16P8 Figure 11-4. Complex Mode Option
0364J–PLD–7/05 ATF16V8B/BQ/BQL Figure 11-5. Complex Mode Logic Diagram
0364J–PLD–7/05 ATF16V8B/BQ/BQL
11.3 ATF16V8B Simple Mode
PAL Device Emulation/PAL Replacement. In the Simple Mode, 8 product terms are allocated to the sum term. Pins 15 and 16 (center macrocells) are permanently configured as combinato- rial outputs. Other macrocells can be either inputs or combinatorial outputs with pin feedback to the AND-array. Pins 1 and 11 are regular inputs. The compiler selects this mode when all outputs are combinatorial without OE control. The fol- lowing simple PALs can be emulated using this mode: 10L8 10H8 10P8 12L6 12H6 12P6 14L4 14H4 14P4 16L2 16H2 16P2 Figure 11-6. Simple Mode Option Note: * Pins 15 and 16 are always enabled.
0364J–PLD–7/05 ATF16V8B/BQ/BQL Figure 11-7. Simple Mode Logic Diagram
0364J–PLD–7/05 ATF16V8B/BQ/BQL 12. Test Characterization Data SUPPL Y CURRENT vs. INPUT FREQUENCY ATF16V8B/BQ (VCC = 5V, TA = 25C) I C C m A 0 25 50 75 100 FREQUENCY (MHz) ATF16V8B ATF16V8BQ SUPPL Y CURRENT vs. SUPPL Y VOLTAGE ATF16V8B/BQ (TA = 25C) I C C m A SUPPL Y VOLTAGE (V) ATF16V8B ATF16V8BQ OUTPUT SOURCE CURRENT vs. SUPPL Y VOLTAGE (TA = 25C) -24 -22 -20 -18 -16 -14 -12 -10 I O H m A SUPPL Y VOLTAGE (V) SUPPL Y CURRENT vs. INPUT FREQUENCY ATF16V8BL/BQL (VCC = 5V, TA = 25C) I C C m A 0 2 04 06 08 0 1 0 0 FREQUENCY (MHz) ATF16V8B ATF16V8BQL
0364J–PLD–7/05 ATF16V8B/BQ/BQL NORMALIZED TPD vs. SUPPL Y VOL TA GE (TA=25°C) 0.7 0.85 1.15 1.3 SUPPL Y VOL TA GE (V) N O R M T P D ATF16V8B/BQ ATF16V8BQL NORMALIZED TCO vs. SUPPL Y VOLTAGE(TA=25°C) 0.7 0.85 1.15 1.3 SUPPL Y VOLTAGE (V) N O R M T C O ATF16V8B/BQ ATF16V8BQL
0364J–PLD–7/05 ATF16V8B/BQ/BQL
0364J–PLD–7/05 ATF16V8B/BQ/BQL 13. ATF16V8B Ordering Information Note: The last time buy date is Sept. 30, 2005 for shaded parts.
13.3 Using “C” Product for Industrial
To use commercial product for Industrial temperature ranges, down-grade one speed grade from the “I” to the “C” device (7 ns “C” = 10 ns “I”) and de-rate power by 30%.
13.1 ATF16V8B Standar d Package Options
(ns) tS (ns) tCO (ns) Ordering Code Package Operation Range 10 7.5 7 ATF16V8B-10JC ATF16V8B-10PC 20J 20P3 20S 20X Commercial (0°C to 70°C) ATF16V8B-10SC ATF16V8B-10XC ATF16V8B-10JI ATF16V8B-10PI ATF16V8B-10SI ATF16V8B-10XI 20J 20P3 20S 20X Industrial (-40°C to 85°C) 15 12 10 ATF16V8B-15JC ATF16V8B-15PC ATF16V8B-15SC 20J 20P3 20S 20X Commercial (0°C to 70°C) ATF16V8B-15XC ATF16V8B-15JI ATF16V8B-15PI ATF16V8B-15SI 20J 20P3 20S 20X Industrial (-40°C to 85°C) ATF16V8B-15XI
13.2 ATF16V8B Green Package Options (Pb/Halide-free/RoHS Compliant)
(ns) tS (ns) tCO (ns) Ordering Code Package Operation Range 10 7.5 7 ATF16V8B-10JU 20J Industrial (-40°C to 85°C)15 12 10 ATF16V8B-15JU ATF16V8B-15PU ATF16V8B-15SU ATF16V8B-15XU 20J 20P3 20S 20X Package Type 20J 20-lead, Plastic J-leaded Chip Carrier (PLCC) 20P3 20-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 20S 20-lead, 0.300" Wide, Plastic Gull-wing Small Outline (SOIC) 20X 20-lead, 4.4 mm Wide, Plastic Thin Shrink Small Outline (TSSOP)
0364J–PLD–7/05 ATF16V8B/BQ/BQL 14. ATF16V8BQ/BQL Ordering Information Note: The last time buy date is Sept. 30, 2005 for shaded parts.
14.3 Using “C” Product for Industrial
To use commercial product for Industrial temperature ranges, down-grade one speed grade from the “I” to the “C” device (7 ns “C” = 10 ns “I”) and de-rate power by 30%.
14.1 ATF16V8BQ and ATF16V8BQ L Ordering Information
(ns) tS (ns) tCO (ns) Ordering Code Package Operation Range 10 7.5 7 ATF16V8BQ-10JC 20J 20P3 20S 20X Commercial (0°C to 70°C) ATF16V8BQ-10PC ATF16V8BQ-10SC ATF16V8BQ-10XC 15 12 10 ATF16V8BQL-15JC ATF16V8BQL-15PC ATF16V8BQL-15SC ATF16V8BQL-15XC 20J 20P3 20S 20X Commercial (0°C to 70°C) ATF16V8BQL-15JI ATF16V8BQL-15PI ATF16V8BQL-15SI ATF16V8BQL-15XI 20J 20P3 20S 20X Industrial (-40°C to 85°C)
14.2 ATF16V8BQ and ATF16V8BQL Gr een Package Options (Pb/Halide-free/RoHS Compliant)
(ns) tS (ns) tCO (ns) Ordering Code Package Operation Range 15 12 10 ATF16V8BQL-15JU ATF16V8BQL-15PU ATF16V8BQL-15SU ATF16V8BQL-15XU 20J 20P3 20S 20X Industrial (-40°C to 85°C) Package Type 20J 20-lead, Plastic J-leaded Chip Carrier (PLCC) 20P3 20-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 20S 20-lead, 0.300" Wide, Plastic Gull-Wing Small Outline (SOIC) 20X 20-lead, 4.4 mm Wide, Plastic Thin Shrink Small Outline (TSSOP)
0364J–PLD–7/05 ATF16V8B/BQ/BQL 15. Packaging Information 15.1 20J – PLCC
2325 Orchard Parkway
San Jose, CA 95131R TITLE DRAWING NO. REV. Notes: 1. This package conforms to JEDEC reference MS-018, Variation AA. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010"(0.254 mm) per side. Dimension D1 and E1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. 3. Lead coplanarity is 0.004" (0.102 mm) maximum. A 4.191 – 4.572 A1 2.286 – 3.048 A2 0.508 – – D 9.779 – 10.033 D1 8.890 – 9.042 Note 2 E 9.779 – 10.033 E1 8.890 – 9.042 Note 2 D2/E2 7.366 – 8.382 B 0.660 – 0.813 B1 0.330 – 0.533 e 1.270 TYP COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE 1.14(0.045) X 45˚ PIN NO. 1 IDENTIFIER 1.14(0.045) X 45˚ 0.51(0.020)MAX 0.318(0.0125) 0.191(0.0075) 45˚ MAX (3X) A D2/E2 B e E1 E D 20J, 20-lead, Plastic J-leaded Chip Carrier (PLCC) B20J 10/04/01
0364J–PLD–7/05 ATF16V8B/BQ/BQL 15.2 20P3 – PDIP San Jose, CA 95131 TITLE DRAWING NO. R REV. 20P3, 20-lead (0.300"/7.62 mm Wide) Plastic Dual Inline Package (PDIP) D20P3 1/23/04 PIN B E C L SEATING PLANE A D e eB eC COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE A – – 5.334 A1 0.381 – – D 24.892 – 26.924 Note 2 E 7.620 – 8.255 E1 6.096 – 7.112 Note 2 B 0.356 – 0.559 B1 1.270 – 1.551 L 2.921 – 3.810 C 0.203 – 0.356 eB – – 10.922 eC 0.000 – 1.524 e 2.540 TYP Notes: 1. This package conforms to JEDEC reference MS-001, Variation AD. 2. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 mm (0.010").
0364J–PLD–7/05 ATF16V8B/BQ/BQL 15.3 20S – SOIC San Jose, CA 95131 TITLE DRAWING NO. R REV. 20S, 20-lead, 0.300" Body, Plastic Gull Wing Small Outline (SOIC) B20S 10/23/03 7.60 (0.2992) 7.40 (0.2914) 0.51(0.020) 0.33(0.013) 10.65 (0.419) 10.00 (0.394) PIN 1 ID 1.27 (0.050) BSC 13.00 (0.5118) 12.60 (0.4961) 0.30(0.0118) 0.10 (0.0040) 2.65 (0.1043) 2.35 (0.0926) 0º ~ 8º 1.27 (0.050) 0.40 (0.016) 0.32 (0.0125) 0.23 (0.0091) PIN 1 Dimensions in Millimeters and (Inches). Controlling dimension: Inches. JEDEC Standard MS-013
0364J–PLD–7/05 ATF16V8B/BQ/BQL 15.4 20X – TSSOP San Jose, CA 95131 TITLE DRAWING NO. R REV. 20X, (Formerly 20T), 20-lead, 4.4 mm Body Width, Plastic Thin Shrink Small Outline Package (TSSOP) C20X 10/23/03 6.60 (.260) 0.65 (.0256) BSC 0.20 (0.008) 0.09 (0.004) 0.15 (0.006) 0.05 (0.002) INDEX MARK 6.50 (0.256) 6.25 (0.246) SEATING PLANE 4.50 (0.177) 4.30 (0.169) PIN 0.75 (0.030) 0.45 (0.018) 0º ~ 8º 0.30 (0.012) 0.19 (0.007) Dimensions in Millimeters and (Inches). Controlling dimension: Millimeters. JEDEC Standard MO-153 AC
0364J–PLD–7/05 ATF16V8B/BQ/BQL 16. Revision History 16.1 0364J 1. ATF16V8B-25 JC/PC/SC/XC/JI/PI/SI/XI were obseleted in August 1999 ATF16V8BQL-25 JC/PC/SC/XC/JI/PI/SI/XI were obseleted in August 1999 These devices were removed from Section 13. ”ATF16V8B Ordering Information” on page 19 and Section 14. ”ATF16V8BQ/BQL Ordering Information” on page 20. 2. Green Package options added in 2005.
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