VX-724 VECTRON | Alldatasheet
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Vectron Interna/g415onal • 267 Lowell Road, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • h/g425p://www.vectron.com Page 1 of 9 Features Applica/g415ons VX-724 Features Applica/g415ons Descrip/g415on VX-724 Quad Frequency HPLL VCXO The VX-724 is a quad frequency voltage controlled crystal oscillator, VCXO, based upon Vectron’s HPLL high performance phase locked loop frequency mul/g415plier ASIC that combines key digital synthesis techniques with VI’s proven core analog technology blocks. A standard low frequency crystal provides the reference to the frac/g415onal-n synthesizer so that virtually any frequency between 10MHz and 1200 MHz can be factory programmed allowing quick turn manufacturing. The VX-724 has a 2 bit hardware Frequency Select func/g415on that provides one of four condi/g415ons: Frequency 1, Frequency 2, Frequency 3, or Frequency 4. Industry Standard Package, 5.0 x 7.0 x 1.8 mm• HPLL High Performance PLL ASIC • Ji/g425er < 500 fs-rms (12 kHz to 20 MHz)• Four Output Frequencies from 10 MHz to 1200 MHz• Spurious Suppression, 70 dBc Typical• 2.5V or 3.3V Supply Voltage• LVCMOS, LVPECL or LVDS Output Configura/g415ons• Output Enable • Compliant to EC RoHS Direc/g415ve• PLL circuits for clock smoothing and frequency transla/g415on Descrip/g415on Standard 1-2-4 Gigabit Fibre Channel•
10 Gigabit Fibre Channel•
10GbE LAN / WAN• Synchronous Ethernet• OC-192• SONET / SDH• INCITS 352-2002 INCITS 364-2003 IEEE 802.3ae ITU-T G.8262 ITU-T G.709 GR-253-CORE Issue4 Block Diagram VDD COutput Output Vc OE Gnd XTAL LVCMOS LVPECL LVDS HPLL Figure 1 - Block Diagram FS[1] FS[0] Rev2: 14 November 2012
Vectron Interna/g415onal • 267 Lowell Road, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • h/g425p://www.vectron.com Page 2 of 9 Electrical Performance Parameter Test Conditions Symbol Min Typ Max Units Supply Voltage1 3.3V Op/g415on 2.5V Op/g415on VDD 2.97 2.25 3.3 2.5 3.63 2.75 V Current LVCMOS LVDS LVPECL IDD - 120 108 130 mA Opera/g415ng Temperature 1, 3 TOP -40 - +85 °C Output Enable (OE) V IH 0.75 x VDD -- VVIL - - 0.5 Frequency Select (FS[1], FS[2]) V IH 0.75 x VDD -- VVIL - - 0.5 Frequency Nominal Frequency1 LVPECL/LVDS LVCMOS fN 10 1200 160 MHz Absolute Pull Range 1, 2, 3 VC = 0.1xVDD to 0.9xVDD APR ±50 - - ppm Linearity 2, 4 20% to 80% full output Lin - - ±10 % Gain Transfer 2, 10 to 90% of VDD KV - +100 - ppm/V Temperature Stability 1, 6 TA = -40 to +85°C fSTAB - ±20 - ppm Outputs LVPECL Output mid-level V O VDD-1.42 - VDD-1.25 V swing (diff) V OD 1.1 - 1.9 V PP LVDS Output mid-level V O 1.4 1.6 1.8 V swing (diff) V OD 300 450 600 mV PP LVCMOS Output V OH 0.9 x VDD -V DD V VOL - - 0.1 x V DD V Rise/Fall Time (20/80%)2,5 LVPECL/LVDS LVCMOS with CL = 15 pF tR/tf 350 1.2 ps ns Symmetry 2,3 LVPECL: VDD-1.3 V (diff) LVDS: 1.6 V (diff) LVCMOS: V DD/2 SYM 45 50 55 % Spurious Suppression 6 65 70 - dBc Ji/g425er 6 (Performance Op/g415on N) 12 kHz to 20 MHz фJ - - 1000 fs-rms Ji/g425er 6 (Performance Op/g415on A) 12 kHz to 20 MHz фJ - - 500 fs-rms Control Voltage Input Impedance (Output Enabled) 6 ZC 500 - - kΩ Modula/g415on Bandwidth BW - 10.0 - kHz Control Voltage Tuning Range V C 0- V DD V VX-724 Quad Frequency HPLL VCXO See Standard Frequencies and Ordering Informa/g415on (Pg 8).1] Parameters are tested with produc/g415on test circuit (See Figure 2 for LVCMOS, Figure 3 for LVPECL and figure 4 for LVDS).2] Parameters are tested at ambient temperature with test limits guard-banded for specified opera/g415ng temperature.3] Measured as the maximum devia/g415on from the best straight-line fit, per MIL-0-55310.4] Parameters are described with waveform diagram below (Figure 5).5] Not tested in produc/g415on, guaranteed by design, verified at qualifica/g415on.6] Performance Specifica/g415ons Rev2: 14 November 2012
Vectron Interna/g415onal • 267 Lowell Road, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • h/g425p://www.vectron.com Page 6 of 9 Reliability VI qualification includes aging at various extreme temperatures, shock and vibration, temperature cycling, and IR reflow simulation. The VX-724 family is capable of meeting the following qualification tests: Environmental Compliance Parameter Conditions Mechanical Shock MIL-STD-883, Method 2002 Mechanical Vibration MIL-STD-883, Method 2007 Solderability MIL-STD-883, Method 2003 Gross and Fine Leak MIL-STD-883, Method 1014 Resistance to Solvents MIL-STD-883, Method 2016 Moisture Sensitivity Level IPC/JEDEC J-STD-020, MSL1 Handling Precautions ESD Ratings Model Minimum Conditions Human Body Model 1000V MIL-STD-883, Method 3015 Charged Device Model 900V JEDEC, JESD22-C101 Machine Model 200 V JEDEC, JESD22-A115-A Reflow Profile (IPC/JEDEC J-STD-020) Parameter Symbol Value PreHeat Time t S 60 sec Min, 180 sec Max Ramp Up R UP 3 °C/sec Max Time Above 217 °C t L 60 sec Min, 150 sec Max Time To Peak Temperature T AMB-P 480 sec Max Time at 260 °C t P 20 sec Min, 40 sec Max Ramp Down R DN 6 °C/sec Max Although ESD protection circuitry has been designed into the VX-724 proper precautions should be taken when handling and mounting. VI employs a human body model (HBM) and a charged-device model (CDM) for ESD susceptibility testing and design protection evaluation. The device has been qualified to meet the JEDEC standard for Pb-Free assembly. The temperatures and time intervals listed are based on the Pb-Free small body requirements. The temperatures refer to the topside of the package, measured on the package body surface. The VX-724 device is hermetically sealed so an aqueous wash is not an issue. Terminal Plating: Electrolytic Ni > 1.9μm Electrolytic Au > 0.7μm VX-724 Quad Frequency HPLL VCXO Rev2: 14 November 2012
Vectron Interna/g415onal • 267 Lowell Road, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • h/g425p://www.vectron.com Page 7 of 9 Outline & Marking Diagram Frequency Select FS(1) Pin 7 FS(0) Pin 8 Fout 0 0 F1
01 F 2
10 F 3
11 F 4
Tape & Reel (EIA-481-2-A) Tape Dimensions (mm) Reel Dimensions (mm) Dimension W F Do Po P1 A B C D N W1 W2 # Per ReelTolerance Typ Typ Typ Typ Typ Typ Min Typ Min Min Typ Max 1:Output Enable is internally pulled to VDD with a 30 kΩ resistor. If op/g415on C is selected, OE must be pulled low by the user with a LVCMOS logic device or a 3 kΩ resistor to ground. 2: FS1 and FS0 are internally pulled to V DD with a 30 kΩ resistor Suggested Pad Layout Output Enable Option Voltage Level Result A H Output Enable L Output Disable C H Ouput Disable L Output Enable VX-724 Quad Frequency HPLL VCXO Y = Year WW = Week C = Op/g415on Codes F1F2F3F4 = Frequencies (See Ordering Info) mm [inch] Pin Out Pin Symbol Function
1 VC Control Voltage
2 OE Output Enable 1
3 GND Case and Electrical Ground
4 Output Output
5 COutput
(N/A for LVCMOS) Complementary Output (N/C for LVCMOS) VCC Power Supply Voltage
7 FS[1] Frequency Select MSB2
8 FS[0] Frequency Select LSB2
Rev2: 14 November 2012
Vectron Interna/g415onal • 267 Lowell Road, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • h/g425p://www.vectron.com Page 8 of 9 Standard Factory Configurable Frequencies (MHz) Standard Frequency Table VX-724 Quad Frequency HPLL VCXO Rev2: 14 November 2012
Vectron Interna/g415onal • 267 Lowell Road, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • h/g425p://www.vectron.com Page 9 of 9 VX-724 Quad Frequency HPLL VCXO Disclaimer Vectron Interna/g415onal reserves the right to make changes to the product(s) and or informa/g415on contained herein without no/g415ce. No liability is assumed as a result of their use or applica- /g415on. No rights under any patent accompany the sale of any such product(s) or informa/g415on. For Addi/g415onal Informa/g415on, Please Contact USA: Vectron Interna/g415onal
267 Lowell Road
Hudson, NH 03051 Tel: 1.888.328.7661 Fax: 1.888.329.8328 Europe: Vectron Interna/g415onal Landstrasse, D-74924 Neckarbischofsheim, Germany Tel: +49 (0) 3328.4784.17 Fax: +49 (0) 3328.4784.30 Asia: Vectron Interna/g415onal
1589 Century Avenue, the 19th Floor
Cham/g415me Interna/g415onal Financial Center Shanghai, China Tel: 86.21.6081.2888 Fax: 86.21.6163.3598 Ordering Informa/g415on VX - 724 - E C E - K E A N - F1F2F3F4 Product Family VX: VCXO Package 724: 5 x 7 x 1.8 mm Quad Frequency Input E: 3.3 V H: 2.5 V Output A: LVCMOS C: LVPECL D: LVDS Opera/g415ng Temperature E: -40 to 85 °C F1, F2, F3, F4 (See Frequency Table)Stability X: Standard E: ±20ppm Temperature Stability Enable/Disable A: Enable High C: Enable Low Absolute Pull Range K: ± 50 ppm Example: VX-724-ECE-KXAN-P2P4PBP5 Other (Future Use) N: Standard Rev2: 14 November 2012