OP-01 CALOGIC | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 4
Technical content
. nernsenreo perati mplifier CORPORATION Techical Gaces teats 7 echnical Canesiiagts (415) 830-0829 ce FEATURES DESCRIPTION @ Internally Compensated protection. Its use as a direct replacement for 741 operation amplifier results in significant performance enhancement without the need for circuit redesign. Military temperature APPLICATIONS devices, OP-01 and OP-01G, are available in 8-pin hermetic © D/A Converters packages. Commercial temperature range devices, OP-01C © Pin-for-Pin High-Performance 741 Replacement and OP-01H, are also available in 8-pin plastic DIP packages. © Fast Inverting Amplifier ORDERING INFORMATIONt PACKAGE Ta=25°C HERMETIC HERMETIC PLASTIC PLASTIC OPERATING AVosMAX —TO-99 DIP DIP SOIC.“ TEMPERATURE (mv) 8-PIN SPIN &-PIN _&-PIN RANGE ~ 0.7 OPOW* = OPO1Z" MIL
07 OPO1JH OPO1HZ OPO1HP OPO1HS: COM
5.0 OPO1GJ* OP0IGZ" MIL
5.0 OPO1CS _OPOICZ _OPOICP_OPOICS com
*For devices processed in total compliance to MIL-STD-883, add /883 after part number. Consult factory for 883 data sheet. +All commercial and industrial temperature range parts are available with burn-in, Pin Connections (Top View) 8 NC. BAL 1 V4 BAL [1 | 8) N.C -IN 2 V+ 4 _ “ qo fs ms v- BAL +IN3 5 BAL e
4 V-(CASE) EPOXY MINI-DIP (P-Suffix)
TO-99 (J-Suffix) 8-PIN HERMETIC DIP (Z-Suffix) 8-PIN PLASTIC SOIC (S-Suffix)
CORPORATION: a ABSOLUTE MAXIMUM RATINGS (Note 2) NOTES: Total Supply Voltage, OP-01, OP-01H, OP-O1N, OP-O1NT, 1. See table for maximum ambient temperature rating and derating factor. MAXIMUM AMBIENT DERATE ABOVE Operating Temperature Range 2, Absolut ratings apply to both packaged parts and DICE, unte: OP-01, OP-OIG «=... 85°C 0 $125°C — atherwise noted. *aged pars and ICs, unless OP-O1H, OP-O1C 00... eee eee eee ees OFC to +70°C 3, For supply voltages less than +15V, the maximum input voltage is the Storage Temperature Range Simplified Schematic Diagram oV+ fy a8 ‘9 a1 a -IN ~ — G20 +N of OT a co | tan ast} 28pF arg © OUTPUT [Ra | are Os, 6 Q10 oi RS R2 RS R7 RS © BALANCE © BALANCE Ove *Q1, Q2, Q3, AND Q4 FORM A THERMALLY CROSS-COUPLED QUAD. 5, 05’, 06, AND Q6' COMPRISE A SIMILAR ‘THERMALLY CROSS-COUPLED QUAD. Die Dimensions and Pad Connections T Pree in =n 1. BALANCE 2 os 2. (-) INPUT L lh 3, (+) INPUT 4.V- | val 5. BALANCE w 6. OUTPUT ' =La| 7+ : Calogte a ft DIE SIZE 0.063x0.047 inch, 2961 sq. mils (1.6x1.194mm, 1.91 sq. mm)
‘CORPORATION ELECTRICAL CHARACTERISTICS at Vg =+15V, Ta =25°C, unless otherwise noted. ‘OP-01, OP-01H OP-01G, OP-01C Input Offset Voltage Vos Aig <20k0. - 03 07 = 2.0 5.0 mv Input Offset Current los = 0s 20 — 20 20 nA Input Bias Current Ip =_ 18 30 - 25 100 nA Input Voltage Range IVR #1200 41300 412 £13 - Vv ‘Common-Mode Rejection Ratio CMRR —_Vom= + 10V, Rg<20k0 ae 0 80 100 = 68 Power Supply Rejection Ratio PSRR Vs = +5V to +20V, Rg <20k9 - 10 60 - 100, 150 aVIV Output Votage Swing Yo Aisa zo fio — fo feo v Large-Signal Voltage Gain Avo FL >2k0, Vo= + 10V 50 100 — 2 75 = vimv Power Consumption Pg Vout =0 -= 50 90 -= 50 90 mw Settling Time to 0.1% (Summing Node Error) ts Ay = —1 (Notes 1, 2), Vin=5V - 0.7 1.0 =-= O7 1.0 ws ‘Slew Rate (Notes 2, 3) sR Ay = - 1, Rg = 3k to 5k0 12 18 - 12 18 - Vins Large-Signal Bandwidth (Notes 3, 4) 160 250 — 160 250 = kHz ‘Smali-Signal Bandwidth (Notes 3, 4) 15 25 — 18 25 MHz Risetime t Ay=—1, Vin=5OmV - 150 - =- 150 - ns Qverohoot NOTES: 1. RL =25kM; Cy =S0pF. See Settling Time Test Circuit 3. See applications information. 2. Sample Tested 4, Guaranteed by design. ELECTRICAL CHARACTERISTICS at Vs = +15V, —55°C <Ta < +125°C for OP-01, OP-01G and 0°C <Ta< +70°C for OP-O1H, OP-01C, unless otherwise noted. OP-01, OP-O1H OP-01G, OP-01C Input Offset Voltage Vos Rg s20k0 = 04 1.0 = 3.0 60 mv Input Offset Current los - 1 4 - 4 40 nA Input Bias Current A = 3050 = 50 200 nA Input Voltage Range IVR +10 £13 - +10 +13 = dB Common-Mode Rejection Ratio CMRR Vom = + 10V, Rg <20ko 85 110 -= 80 100 - Vv Power Supply Rejection Ratio PSRR Vs = + 5V to + 20V, Rg <20k0 fod 10 60 - 100 150 Viv Large-Signal Voltage Gain Avo RL >2k9, Vo= +10V 30 60 = 18 50 = Vimv | Output vorage Sting No Raa ive iso — two io — v | Offset Voltage Drift (Note 1) TCVos_ _Ags5k2 = 2 8 = 5 20 BVIeC NOTE: 1, Sample Tested
‘CORPORATION a TIM! T CIRCUIT SETTLING: ETES cul . a Fast Inverting Amplifier Settling time may be measured using the circuit shown below. This circuit incorporates the “false sum node” technique to produce accurate, repeatable results. For a SV input step, 0.1% Rin Re settling will be achieved when the false sum node settles to Vino within +2.5mV of its final value. The oscilloscope used for observation of the false sum node should have wide bandwidth, Rs fast overload recovery time, and be used with a low capacity 2 probe (<10pF, including strays). A Tektronix 7504 scope with a A 7AM1 probe or equivalent is suggested. The pulse generator baal 6 should have a 50@ output impedance and be capable of a 5V * 3 ° rise time in <20ns with ringing less than 2.5mV after 0.5ys. Measurements to 0.1% require Rix to equal Rr within 0.01%; Re and Re are used as trimming resistors to achieve this Rp Reo = Rst Rin ll Re matching. FOR Ay =-1, Reg >3.3k2 Rp = Reg We TOSCOPEC w= 1OpF | g@ ——— ° a Offset Nulling Circuit RS. wale ro ee en Yon ikea 180 | He deem gose ate weut mo oureur ° Bh | am ON Ar Love 2 oy 71 6 LL Ly ro) 2 ; = 3 5 | Rr}, AC our s10% a 4 ti tl" “1 - ~ av 7 o APPLICATIONS INFORMATION The OP-01 incorporates an internal feed-forward compensation 3.3k2 to assure stability in all closed-loop gain configurations network to provide fast slewing and settling times in all inverting including unity gain. Should Riy||Rr <3.3k0, a resistor (Rs) and moderate-to-high-gain noninverting applications. Unity- may be placed between the inverting input and the sum node gain bandwidth is a function of the total equivalent source to provide the required resistance. (See Fast inverting Amplifier resistance seen by the inverting terminal. Proper choice of this Diagram.) Lower values to total equivalent resistance may be resistance will allow the user to maximize bandwidth while used to improve bandwidth in higher closed-loop gain assuring proper stability. The equivalent-inverting-terminal- configurations. resistance is defined as Ryy||Rr, and it must be greater than cal 237 Whitney Place Information furnished by Calogicis believed to be accurate and reliable. Fremont, CA 94539 However, no responsibility is assumed for its use; nor for any infringement of ‘commoRAnON (418) 656-2900 Crd WA R patents or other rights of third parties which may result from its use. No license TLX: 6771346 is granted by implication or otherwise under any patent or patent rights of FAX: (415) 651-1076 Calogic.