NPE405H AMCC | Alldatasheet

Document overview

  • Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
  • PDF pages: 70

Technical content

Revision 1.01 – April 18, 2007 AMCC Proprietary DS2011 1 NPe405H PowerNP NPe405H Embedded Processor Data Sheet

FEATURES

  • P o w e r N P™ technology using an AMCC Pow- erPC® 405 32-bit RISC processor core operat- ing up to 266 MHz
  • PC-133 synchronous DRAM (SDRAM) inter- face - 32-bit interface for non-ECC applications - 40-bit interface serves 32 bits of data plus 8 check bits for ECC applications
  • External bus for peripheral devices - Flash and ROM interface - Direct support for 8-, or 16-, or 32-bit SRAM and external peripherals - Up to 8 devices - External mastering supported
  • DMA support for external peripherals, internal UARTs and memory - Scatter-gather chaining supported - Four channels
  • PCI Revision 2.2 compliant interface (32-bit, up to 66MHz) - Asynchronous PCI bus interface - Internal PCI bus arbiter which can be dis- abled for use with an external arbiter
  • Four 10/100 Ethernet MACs supporting up to four external PHYs via MII, RMII, or SMII inter- faces
  • HDLC interface with 32 channels through two ports at up to 4.096 Mbps each or 8.192 Mbps for a single port
  • HDLC interface with 8 channels through 8 ports at 2.048 Mbps maximum
  • Programmable interrupt controller - Seven external and 49 internal - Edge triggered or level-sensitive - Positive or negative active - Non-critical or critical interrupt to processor core - Programmable critical interrupt priority ordering - Programmable critical interrupt vector
  • Programmable timers
  • Two serial ports (16550 compatible UART)
  • One IIC interface
  • General Purpose I/O (GPIO) available
  • Supports JTAG for board level testing
  • Internal processor local bus (PLB) runs at SDRAM interface frequency
  • Supports PowerPC processor boot from PCI memory
  • User accessible performance counters

DESCRIPTION

Designed specifically to address embedded applica- tions, the NPe405H provides a high-performance, low- power solution that interfaces to a wide range of peripherals by incorporating on-chip power manage- ment features and lower power dissipation requirements. This chip contains a high-performance RISC proces- sor core, SDRAM controller, PCI bus bridge, Ethernet EMACs, HDLC controllers, ex ternal bus controller for ROM, Flash, and peripherals, DMA with scatter-gather support, serial ports, IIC interface, and general pur- pose I/O. Technology: CMOS SA-12E 0.25 µm (0.18 µm L eff) Package: 35mm, 580-ball enhanced plastic ball grid array (E-PBGA) Power (typical): 2.3W at 133MHz, 2.9W at 200MHz, 3.4W at 266MHz

NPe405H – PowerNP NPe405H Embedded Processor

2 DS2011 AMCC Proprietary

Revision 1.01 – April 18, 2007 Data Sheet TABLE OF CONTENTS

NPe405H – PowerNP NPe405H Embedded Processor Revision 1.01 – April 18, 2007 AMCC Proprietary DS2011 3 Data Sheet

4 DS2011 AMCC Proprietary

NPe405H – PowerNP NPe405H Embedded Processor Revision 1.01 – April 18, 2007 AMCC Proprietary DS2011 5 Data Sheet ORDERING, PVR, AND JTAG INFORMATION This section provides the part numbering nomenclature for the NPe405H. For availability, contact your local AMCC sales office. The part number contains a part modifier. This modifier provides for identification of future enhancements (for example, higher performance). Each part number also contains a revision code. This refers to the die mask revision number and is specified in the part numbering scheme for identification purposes only. The PVR (Processor Version Register) is software accessible and contains additional information about the revi- sion level of the part. Refer to the NPe405H User’s Manual for details on the register content. AMCC Part Number Key Product Name Order Part Number1 Processor Frequency Package Rev Level PVR Value JTAG ID NPe405H NPe405H-3BA133C 133MHz 35mm, 580 E-PBGA A 0x41410140 0x04267049 NPe405H NPe405H-3BA133CZ 133MHz 35mm, 580 E-PBGA A 0x41410140 0x04267049 NPe405H NPe405H-3BA200C 200MHz 35mm, 580 E-PBGA A 0x41410140 0x04267049 NPe405H NPe405H-3BA200CZ 200MHz 35mm, 580 E-PBGA A 0x41410140 0x04267049 NPe405H NPe405H-3BA266C 266MHz 35mm, 580 E-PBGA A 0x41410140 0x04267049 NPe405H NPe405H-3BA266CZ 266MHz 35mm, 580 E-PBGA A 0x41410140 0x04267049 Note 1: Z at the end of the Order Part Number indicates a tape and reel shipping package. Otherwise, the chips are shipped in a tray. AMCC Part Number NPe405H-3BA200Cx Package (E-PBGA) Processor SpeedGrade 3 Reliability Operational Case Temperature Range Revision Level Shipping Package Blank = Tray Z = Tape and reel (-40°C to +85°C) 200MHz 266MHz 133MHz

6 DS2011 AMCC Proprietary

Figure 1. NPe405H Embedded Controller Functional Block Diagram generate complex ASICs using IBM CoreConnect™ Bus Architecture.

66 MHz max (async)

accessed by software running on the NPe405H processor through the use of mtdcr and mfdcr commands. Table 1. System Address Map 4GB Total System Memory

  1. When external peripheral bus boot is selected, peripheral bank 0 is automatically configured at reset to the address range li sted above.
  2. If PCI boot is selected, a PLB-to-PCI mapping is automatically configured at reset to the address range listed above.
  3. After the boot process, software may reassign the boot memory regions for other uses.
  4. All address ranges not listed above are reserved.

8 DS2011 AMCC Proprietary

Table 2. DCR Address Map 4KB Device Configuration Register

  1. DCR address space is addressable with up to 10 bits (1024 or 1K unique addresses). Each unique address represents a single 32 -bit (word) register, or 1 kiloword (KW) (which

NPe405H – PowerNP NPe405H Embedded Processor Revision 1.01 – April 18, 2007 AMCC Proprietary DS2011 9 Data Sheet PLB TO PCI BRIDGE The PLB to PCI bridge provides a mechanism for connecti ng PCI devices to the processor, peripherals, and mem- ory. This interface is PCI Specification rev 2.2 compliant. Features include:

  • Internal PCI bus arbiter for up to six external devices at PCI bus speeds up to 66MHz. Internal arbiter use is optional and can be disabled for systems which employ an external arbiter.
  • PCI bus frequency up to 66MHz - Asynchronous operation from 1/8 PLB frequency to 66MHz maximum
  • 32-bit PCI Address/Data Bus
  • Power Management: - PCI Bus Power Management v1.1 compliant
  • Buffering between PLB and PCI: - PCI Target 64-byte write post buffer - PCI Target 96-byte read prefetch buffer - PLB Slave 32-byte write post buffer - PLB Slave 64-byte read prefetch buffer
  • Error tracking/status
  • Supports PCI Target side configuration
  • Supports processor access to all PCI address spaces: - Single-byte PCI I/O reads and writes - PCI memory single-beat and prefetch-burst reads and single-beat writes - Single-byte PCI configuration reads and writes (type 0 and type 1) - PCI interrupt acknowledge - PCI special cycle
  • Supports PCI target access to all PLB address spaces
  • Supports PowerPC processor boot from PCI memory

NPe405H – PowerNP NPe405H Embedded Processor

10 DS2011 AMCC Proprietary

Revision 1.01 – April 18, 2007 Data Sheet SDRAM MEMORY CONTROLLER The NPe405H Memory Controller provides a low latency access path to SDRAM memory. The memory controller supports four logical banks. Up to 256MB per bank are supported, for a maximum of 1GB total. Memory access and refresh timing, address and bank sizes, and memory addressing modes are programmable. Features include:

  • 11x8 to 13x11 row-column address modes (2- and 4-bank devices supported)
  • Memory bus operates at same frequency as PLB
  • 32-bit memory interface support
  • Programmable address range for each bank of memory - 4GB address space
  • Industry standard 168-pin DIMMS are supported (some configurations)
  • 200 MHz NPe405H supports up to 1 00 MHz memory with PC100 support
  • 266 MHz NPe405H supports up to 1 33 MHz memory with PC133 support
  • 4MB to 256MB per bank
  • Programmable timing
  • Auto refresh
  • Page Mode Accesses with up to 4 open pages
  • Power Management (self-refresh)
  • Error Checking and Correction (ECC) support - Standard single error correct, double error detect coverage - Aligned nibble error detect - Address error logging EXTERNAL BUS CONTROLLER (EBC)
  • Supports eight ROM, EPROM, SRAM, Flash, and Slave Peripheral I/O banks supported
  • Up to 66.66MHz operation
  • Burst and non-burst devices
  • 8-, 16-, 32-bit byte-addressable data bus width support
  • Latch data on Ready, Synchronous or Asynchronous
  • Programmable 2K clock-cycle time- out counter with disable for Ready
  • Programmable access timing per device - 0–255 wait states for non-bursting devices - 0 –31 Burst Wait States for first access and up to 7 Wait States for subsequent accesses - Programmable chip select assertion/negation relative to driving address bus - Programmable output and write-enable assertion/negation relative to assertion of chip select
  • Programmable address mapping
  • Peripheral device wait via “Ready”
  • External master interface - Write posting from external master - Read prefetching on PLB for external master reads - Bursting capable from external master - Allows external master access to all non-EBC PLB slaves - External master can control EBC slaves for own access and control

NPe405H – PowerNP NPe405H Embedded Processor Revision 1.01 – April 18, 2007 AMCC Proprietary DS2011 11 Data Sheet DMA CONTROLLER

  • Supports the following transfers: - Memory-to-memory transfers - Buffered peripheral to memory transfers - Buffered memory to peripheral transfers
  • Four channels
  • Scatter/Gather capability for programming multiple DMA operations
  • 8-, 16-, 32-bit peripheral support (OPB and external bus attached)
  • 32-bit addressing
  • Address increment or decrement
  • Internal 32-byte data buffering capability
  • Supports internal and external peripherals
  • Support for memory mapped peripherals
  • Support for peripherals running on slower frequency buses SERIAL INTERFACE
  • Two 8-pin UART interfaces provided
  • Selectable internal or external serial clock to allow wide range of baud rates
  • Register compatibility with NS16550 register set
  • Complete status reporting capability
  • Transmitter and receiver are each buffered with 16-byte FIFOs when in FIFO mode
  • Fully programmable serial-interface characteristics
  • Supports DMA using internal DMA engine IIC BUS INTERFACE
  • Compliant with Phillips® Semiconductors I 2C Specification, dated 1995
  • Operation at 100kHz or 400kHz
  • 8 - b i t d a t a
  • 10- or 7-bit address
  • Slave transmitter and receiver
  • Master transmitter and receiver
  • Multiple bus masters
  • Supports fixed V DD IIC interface
  • Two independent 4 x 1 byte data buffers
  • One programmable interrupt request signal
  • Provides full management of all IIC bus protocol
  • Programmable error recovery IIC EEPROM CONTROLLER Supports setting of processor configuration from serial EEPROM during system reset.

NPe405H – PowerNP NPe405H Embedded Processor

12 DS2011 AMCC Proprietary

Revision 1.01 – April 18, 2007 Data Sheet HDLCEX INTERFACE

  • 32-channel HDLC controller
  • Two full-duplex Pulse Code Modulation (PCM) Highway po rts at speeds up to 4.096 Mbps per port or 8.192 Mbps when using a single port
  • Supports HDLC protocol as well as a Transparent mode
  • For a single channel per port, autonomous management of I-Frames and S-Frames of the Normal Response mode (NRM) protocol on one channel per port. U-frames are handled by software.
  • Supports software emulation of NRM on all channels HDLCMP INTERFACE
  • HDLC controller provides eight full-duplex serial ports
  • Up to 2.048Mbps data rate
  • Supports HDLC protocol as well as a Transparent mode
  • Software emulation of NRM GENERAL PURPOSE IO (GPIO) CONTROLLER
  • Two GPIO controllers - 32-signal system GPIO (GPIO0) - 32-signal communications GPIO (GPIO1)
  • Most GPIOs are pin-shared with other functions. Config uration registers are provided to determine whether a particular pin that has GPIO capabilities acts as a GPIO or is used for another purpose. Both GPIO func- tions have 32 I/Os.
  • Each GPIO output is separately programmable to emulate an open-drain driver (drives to zero, three-stated if output bit is 1) UNIVERSAL INTERRUPT CONTROLLER (UIC) Two cascaded Universal Interrupt Controllers (UICs) pr ovide the control, status, and communications necessary for the interrupt sources and the PowerPC processor. Features include:
  • Seven external and 49 internal interrupts
  • Edge triggered or level-sensitive
  • Positive or negative active
  • Selectable non-critical or critical interrupt requests to the PPC405 processor core
  • Programmable critical interrupt priority ordering
  • Programmable critical interrupt vector generation for reduced latency interrupt handling

NPe405H – PowerNP NPe405H Embedded Processor Revision 1.01 – April 18, 2007 AMCC Proprietary DS2011 13 Data Sheet 10/100 MBPS ETHERNET MAC

  • Four units capable of full- and half-duplex, 10 Mbps or 100 Mbps operation
  • Integrated ZMII Bridge supports use of MII, SMII or RMII connections to external PHYs (PHYs not included on chip) - Reduced Media Independent Interface (RMII) or Serial Media Independent Interface (SMII) for one to four PHY applications - Media Independent Interface (MII) for single or dual PHY applications
  • Dedicated media access layer (MAL) provides DMA support JTAG
  • IEEE 1149.1 Test Access Port
  • Debugger support
  • JTAG boundary scan support (BSDL file available) PERFORMANCE COUNTERS A series of software accessible PLB transaction event counters that can be used to analyze PLB performance.

14 DS2011 AMCC Proprietary

35 MM, 580-BALL E-PBGA PACKAGE

Figure 2. 35mm, 580-Ball E-PBGA Package Note: All dimensions are in mm.

0.60 Solder Ball

the signals in the indicated interface group begin. Table 3. Signals Listed Alphabetically (Sheet 1 of 17)

16 DS2011 AMCC Proprietary

Table 3. Signals Listed Alphabetically (Sheet 2 of 17)

Table 3. Signals Listed Alphabetically (Sheet 3 of 17)

18 DS2011 AMCC Proprietary

Table 3. Signals Listed Alphabetically (Sheet 4 of 17)

Table 3. Signals Listed Alphabetically (Sheet 5 of 17)

20 DS2011 AMCC Proprietary

Table 3. Signals Listed Alphabetically (Sheet 6 of 17)

Table 3. Signals Listed Alphabetically (Sheet 7 of 17)

22 DS2011 AMCC Proprietary

least significant bit (lsb) on this bus. Table 3. Signals Listed Alphabetically (Sheet 8 of 17)

  1. MemData00 is the most significant bit (msb).
  2. MemData31 is the least significant bit (lsb)

Table 3. Signals Listed Alphabetically (Sheet 9 of 17)

24 DS2011 AMCC Proprietary

Table 3. Signals Listed Alphabetically (Sheet 10 of 17)

Table 3. Signals Listed Alphabetically (Sheet 11 of 17)

26 DS2011 AMCC Proprietary

Table 3. Signals Listed Alphabetically (Sheet 12 of 17)

Table 3. Signals Listed Alphabetically (Sheet 13 of 17)

28 DS2011 AMCC Proprietary

Table 3. Signals Listed Alphabetically (Sheet 14 of 17)

Table 3. Signals Listed Alphabetically (Sheet 15 of 17)

30 DS2011 AMCC Proprietary

Table 3. Signals Listed Alphabetically (Sheet 16 of 17)

Table 3. Signals Listed Alphabetically (Sheet 17 of 17)

32 DS2011 AMCC Proprietary

Table 4. Signals Listed by Ball Assignment (Sheet 1 of 9) for an indication of all signals on the pin.

Table 4. Signals Listed by Ball Assignment (Sheet 2 of 9) for an indication of all signals on the pin.

34 DS2011 AMCC Proprietary

Table 4. Signals Listed by Ball Assignment (Sheet 3 of 9) for an indication of all signals on the pin.

Table 4. Signals Listed by Ball Assignment (Sheet 4 of 9) for an indication of all signals on the pin.

36 DS2011 AMCC Proprietary

Table 4. Signals Listed by Ball Assignment (Sheet 5 of 9) for an indication of all signals on the pin.

Table 4. Signals Listed by Ball Assignment (Sheet 6 of 9) for an indication of all signals on the pin.

38 DS2011 AMCC Proprietary

Table 4. Signals Listed by Ball Assignment (Sheet 7 of 9) for an indication of all signals on the pin.

Table 4. Signals Listed by Ball Assignment (Sheet 8 of 9) for an indication of all signals on the pin.

40 DS2011 AMCC Proprietary

Table 4. Signals Listed by Ball Assignment (Sheet 9 of 9) for an indication of all signals on the pin.

chip to offer a richer pin selection than would otherwise be possible. EBC in the NPe405H. In this example, the pins are also bidirectional, serving as both inputs and outputs. use of these pins for strapping is not considered multiplexing since the strapping function is not programmable. Table 5. Pin Summary

NPe405H – PowerNP NPe405H Embedded Processor

42 DS2011 AMCC Proprietary

Revision 1.01 – April 18, 2007 Data Sheet Pull-up and Pull-down Resistors Pull-up and pull-down resistors are used for strapping during reset and to retain unused or undriven inputs in an appropriate state. The recommended pull-up value of 3kΩ to +3.3V (10kΩ to +5V can be used on 5V tolerant I/Os) and pull-down value of 1kΩ to GND, applies only to individually terminated signals. To prevent possible damage to the device, I/Os capable of becoming outputs must never be tied together and terminated through a common resistor. If your system-level test methodology permits, i nput-only signals can be connected together and terminated through either a common resistor or directly to +3.3V or GND. When a resistor is used, its value must ensure that the grouped I/Os reach a valid logic zero or logic one stat e when accounting for the total input current into the NPe405H. Unused I/Os Strapping of some pins may be necessary when they are unused. Although the NPe405H requires only the pull-up and pull-down terminations as specified in the “Signal Functional Description” on page 43, good design practice is to terminate all unused inputs or to configure I/Os such th at they always drive. If unused, the peripheral, SDRAM, and PCI buses should be configured and terminated as follows:

  • Peripheral interface—PerAddr00:31, PerData00:31, and all of the control signals are driven by default. Ter- minate PerReady high and PerError low.
  • SDRAM—Program SDRAM0_CFG[EMDULR]=1 and SDRAM0_CFG[DCE]=1. This causes the NPe405H to actively drive all of the SDRAM address, data, and control signals.
  • PCI—Configure the PCI controller to park on the bus and actively drive PCIAD31:0, PCIC3:0[BE3:0 ], and the remaining PCI control signals by doing the following: - Strap the NPe405H to disable the internal PCI arbiter. - Individually connect PCISErr, PCIPErr, PCITRDY, and PCIStop through 3.3kΩ resistors to +3.3V. - Terminate PCIReq1:5 to +3.3V. - Terminate PCIReq0[Gnt] to GND. External Peripheral Bus Control Signals All external peripheral bus control signals (PerCS0: 7, PerR/W, PerWBE0:3, PerOE, PerWE, PerBLast, HoldAck, ExtAck) are set to the high-impedance state when ExtReset =0. In addition, as detailed in the PowerNP NPe405H Embedded Processor User’s Manual , the peripheral bus controller can be programmed via EBC0_CFG to float some of these control signals between transactions or when an external master owns the peripheral bus. As a result, a pull-up resistor should be added to those contro l signals where an undriven state may affect any devices receiving that particular signal. The following table lists all of the I/O signals provided by the NPe405H. Please see “Signals Listed Alphabetically” on page 15 for the pin number to which each signal is a ssigned. In cases where a multiplexed signal (indicated by the square brackets) is shown without the other signals that are assigned to that pin, you can see what the other signals are by referring to the same table.

Table 6. Signal Functional Description (Sheet 1 of 9)

  1. Receiver input has hysteresis.
  2. Must pull up. See “Pull-up and Pull-down Resistors” on page 42 for recommended termination values.
  3. Must pull down. See “Pull-up and Pull-down Resistors” on page 42 for recommended termination values.
  4. If not used, must pull up.
  5. If not used, must pull down.
  6. Strapping input during reset; pull up or pull down as required.
  7. Pull-up may be required. See “External Peripheral Bus Control Signals” on page 42.

is responsible for driving PCIParity on the next PCI bus clock. The target of the current PCI transaction drives PCITRDY. and command encoding and claims the transaction. Used for reporting data parity errors on PCI transactions. data in which bad parity is detected.

44 DS2011 AMCC Proprietary

Management Data Clock. The MDClk is sourced to the PHY. respect to this clock (MII, RMII, and SMII). transfer control and status information (MII, RMII, and SMII). Table 6. Signal Functional Description (Sheet 2 of 9)

  1. Receiver input has hysteresis.
  2. Must pull up. See “Pull-up and Pull-down Resistors” on page 42 for recommended termination values.
  3. Must pull down. See “Pull-up and Pull-down Resistors” on page 42 for recommended termination values.
  4. If not used, must pull up.
  5. If not used, must pull down.
  6. Strapping input during reset; pull up or pull down as required.
  7. Pull-up may be required. See “External Peripheral Bus Control Signals” on page 42.

Transmit Enable. This signal is driven by EMAC2 to the PHY. is synchronous with PHYTxClk (MII 0[RMII 0]). asynchronous signal (MII 0). Carrier sense data valid ([RMII 0]). Table 6. Signal Functional Description (Sheet 3 of 9)

  1. Receiver input has hysteresis.
  2. Must pull up. See “Pull-up and Pull-down Resistors” on page 42 for recommended termination values.
  3. Must pull down. See “Pull-up and Pull-down Resistors” on page 42 for recommended termination values.
  4. If not used, must pull up.
  5. If not used, must pull down.
  6. Strapping input during reset; pull up or pull down as required.
  7. Pull-up may be required. See “External Peripheral Bus Control Signals” on page 42.

46 DS2011 AMCC Proprietary

the frame reception (MII 0). Reference Clock [RMII and SMII]. asynchronous signal ([MII 1]). synchronous with PHY1RxClk ([RMII 3]). Carrier Sense Data Valid ([RMII 2]). Receive Data Valid ([MII 1]). Carrier Sense Data Valid ([RMII 3]).

  1. MemAddr00 is the most significant bit (msb).
  2. MemData31 is the least significant bit (lsb).
  3. MemAddr12 is the most significant bit (msb).
  4. MemAddr00 is the least significant bit (lsb).

Table 6. Signal Functional Description (Sheet 4 of 9)

  1. Receiver input has hysteresis.
  2. Must pull up. See “Pull-up and Pull-down Resistors” on page 42 for recommended termination values.
  3. Must pull down. See “Pull-up and Pull-down Resistors” on page 42 for recommended termination values.
  4. If not used, must pull up.
  5. If not used, must pull down.
  6. Strapping input during reset; pull up or pull down as required.
  7. Pull-up may be required. See “External Peripheral Bus Control Signals” on page 42.

be repowered by a PLL or zero-delay buffer. mode, otherwise used by external master. Note: PerData00 is the most significant bit (msb) on this bus. byte on each data transfer, allowing partial word transactions. when external bus master owns the external interface. enables the peripherals to drive the bus. read from memory, low indicates a write to memory. indicate the direction of transfer. Table 6. Signal Functional Description (Sheet 5 of 9)

  1. Receiver input has hysteresis.
  2. Must pull up. See “Pull-up and Pull-down Resistors” on page 42 for recommended termination values.
  3. Must pull down. See “Pull-up and Pull-down Resistors” on page 42 for recommended termination values.
  4. If not used, must pull up.
  5. If not used, must pull down.
  6. Strapping input during reset; pull up or pull down as required.
  7. Pull-up may be required. See “External Peripheral Bus Control Signals” on page 42.

48 DS2011 AMCC Proprietary

using the DMA0_POL register. to active-high using the DMA0_POL register. a system reset, the default mode of the signals is active-low. Table 6. Signal Functional Description (Sheet 6 of 9)

  1. Receiver input has hysteresis.
  2. Must pull up. See “Pull-up and Pull-down Resistors” on page 42 for recommended termination values.
  3. Must pull down. See “Pull-up and Pull-down Resistors” on page 42 for recommended termination values.
  4. If not used, must pull up.
  5. If not used, must pull down.
  6. Strapping input during reset; pull up or pull down as required.
  7. Pull-up may be required. See “External Peripheral Bus Control Signals” on page 42.

allowable internally generated baud rates are not satisfactory. Table 6. Signal Functional Description (Sheet 7 of 9)

  1. Receiver input has hysteresis.
  2. Must pull up. See “Pull-up and Pull-down Resistors” on page 42 for recommended termination values.
  3. Must pull down. See “Pull-up and Pull-down Resistors” on page 42 for recommended termination values.
  4. If not used, must pull up.
  5. If not used, must pull down.
  6. Strapping input during reset; pull up or pull down as required.
  7. Pull-up may be required. See “External Peripheral Bus Control Signals” on page 42.

50 DS2011 AMCC Proprietary

Table 6. Signal Functional Description (Sheet 8 of 9)

  1. Receiver input has hysteresis.
  2. Must pull up. See “Pull-up and Pull-down Resistors” on page 42 for recommended termination values.
  3. Must pull down. See “Pull-up and Pull-down Resistors” on page 42 for recommended termination values.
  4. If not used, must pull up.
  5. If not used, must pull down.
  6. Strapping input during reset; pull up or pull down as required.
  7. Pull-up may be required. See “External Peripheral Bus Control Signals” on page 42.

P09-P14 are also thermal balls. Table 6. Signal Functional Description (Sheet 9 of 9)

  1. Receiver input has hysteresis.
  2. Must pull up. See “Pull-up and Pull-down Resistors” on page 42 for recommended termination values.
  3. Must pull down. See “Pull-up and Pull-down Resistors” on page 42 for recommended termination values.
  4. If not used, must pull up.
  5. If not used, must pull down.
  6. Strapping input during reset; pull up or pull down as required.
  7. Pull-up may be required. See “External Peripheral Bus Control Signals” on page 42.

52 DS2011 AMCC Proprietary

  1. For a chip mounted on a JEDEC 2S2P card without a heat sink.
  2. For a chip mounted on a card with at least one signal and two power planes, the following relationships exist:

a. Case temperature, TC, is measured at top center of case surface with device soldered to circuit board. b. TA = TC – P×θCA, where TA is ambient temperature and P is power consumption. c. TCMax = TJMax – P×θJC, where TJMax is maximum junction temperature and P is power consumption. Table 7. Absolute Maximum Ratings permanent damage to the device.

  1. All voltages are specified with respect to ground (GND).
  2. AV DD should be derived from VDD using the following circuit:

Table 8. Package Thermal Specifications

Table 9. Recommended DC Operating Conditions conditions can affect device reliability.

  1. PCI drivers meet PCI specifications.

54 DS2011 AMCC Proprietary

5 V-TOLERANT I/O INPUT CURRENT

Figure 3. 5V-Tolerant I/O Input Current Table 10. Input Capacitance

85°C with the 50pF test load shown in the figure at right. Table 11. DC Electrical Characteristics

  1. Maximum power is characterized at V DD=2.7V, OVDD=3.6V, TC=85×C, across the silicon process (worse case to best case), while running an application designed to maximize power

56 DS2011 AMCC Proprietary

Figure 4. Clocking Waveform Table 12. Clocking Specifications

  1. If HDLCEX is not used, the maximum OPB frequency is 66.66MHz.

NPe405H – PowerNP NPe405H Embedded Processor Revision 1.01 – April 18, 2007 AMCC Proprietary DS2011 57 Data Sheet SPREAD SPECTRUM CLOCKING Care must be taken when using a spread spectrum clock generator (SSCG) with the NPe405H. This controller uses a PLL for clock generation inside the chip. The accu racy with which the PLL follows the SSCG is referred to as tracking skew. The PLL bandwidth and phase angle deter mine how much tracking skew there is between the SSCG and the PLL for a given frequency deviation and modulation frequency. When using an SSCG with the NPe405H the following conditions must be met:

  • The frequency deviation must not violate the minimum clock cycle time. Therefore, when operating the NPe405H with one or more internal clocks at their maximum supported frequency, the SSCG can only lower the frequency.
  • The maximum frequency deviation cannot exceed −3%, and the modulation frequency cannot exceed 40kHz. In some cases, on-board NPe405H peripherals impose more stringent requirements (see Note 1).
  • Use the peripheral bus clock (PerClk) for logic that is synchronous to the peripheral bus since this clock tracks the modulation.
  • Use the SDRAM MemClkOut since it also tracks the modulation. Please refer to the application note Using a Spread Spectrum Clock Generator with the PowerPC 405GP for addi- tional details. This application note is available on the AMCC web site at http://www.amcc.com. Notes: 1. The serial port baud rates are synchronous to the modulated clock. The serial port has a tolerance of approx- imately 1.5% on baud rate before framing errors begin to occur. The 1.5% tolerance assumes that the connected device is running at precise baud rates. If an external serial clock is used the baud rate is unaf- fected by the modulation. 2. Ethernet operation is unaffected. 3. IIC operation is unaffected. 4. The PCI clock specification for 66MHz a llows a maximum frequency deviation of −1% at a modulation between 30kHz and 33kHz. PCI asynchronous mode is unaffected. Caution: It is up to the system designer to ensure that any SSCG used with the NPe405H meets the above requirements and does not adversely affect other aspects of the system.

58 DS2011 AMCC Proprietary

Table 13. Peripheral Interface Clock Timings

  1. In asynchronous PCI mode the minimum PCIClk frequency is 1/8 the PLB Clock. Refer to the NPe405H User’s Manual for more infor mation.

60 DS2011 AMCC Proprietary

Table 14. I/O Specifications—All (Sheet 1 of 2)

  1. PCI timings are for asynchronous operation up to 66MHz. PCI output hold time requirement is 1ns for 66MHz and 2ns for

Table 14. I/O Specifications—All (Sheet 2 of 2)

  1. PCI timings are for asynchronous operation up to 66MHz. PCI output hold time requirement is 1ns for 66MHz and 2ns for

62 DS2011 AMCC Proprietary

Table 15. I/O Specifications—133 and 200MHz (Sheet 1 of 3)

  1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard.
  2. The SDRAM command interface is configurable through SDRAM0_TR[LDF] to provide a 2 to 4 cycle delay before the

command is used by SDRAM. Output times in table are in cycle 1.

  1. SDRAM I/O timings are specified relative to a MemClkOut terminated in a lumped 10pF load.
  2. SDRAM interface hold times are guaranteed at the NPe405H package pin. System designers must use the NPe405H IBIS

the relative delays on clock wiring do not exceed the delays on other SDRAM signal wiring.

  1. PerClk rising edge at package pin with a 10pF load trails the internal PLB clock by approximately 0.8ns.

1 OPB Clock

Table 15. I/O Specifications—133 and 200MHz (Sheet 2 of 3)

  1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard.
  2. The SDRAM command interface is configurable through SDRAM0_TR[LDF] to provide a 2 to 4 cycle delay before the

command is used by SDRAM. Output times in table are in cycle 1.

  1. SDRAM I/O timings are specified relative to a MemClkOut terminated in a lumped 10pF load.
  2. SDRAM interface hold times are guaranteed at the NPe405H package pin. System designers must use the NPe405H IBIS

the relative delays on clock wiring do not exceed the delays on other SDRAM signal wiring.

  1. PerClk rising edge at package pin with a 10pF load trails the internal PLB clock by approximately 0.8ns.

64 DS2011 AMCC Proprietary

Table 15. I/O Specifications—133 and 200MHz (Sheet 3 of 3)

  1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard.
  2. The SDRAM command interface is configurable through SDRAM0_TR[LDF] to provide a 2 to 4 cycle delay before the

command is used by SDRAM. Output times in table are in cycle 1.

  1. SDRAM I/O timings are specified relative to a MemClkOut terminated in a lumped 10pF load.
  2. SDRAM interface hold times are guaranteed at the NPe405H package pin. System designers must use the NPe405H IBIS

the relative delays on clock wiring do not exceed the delays on other SDRAM signal wiring.

  1. PerClk rising edge at package pin with a 10pF load trails the internal PLB clock by approximately 0.8ns.

Table 16. I/O Specifications—266MHz (Sheet 1 of 3)

  1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard.
  2. The SDRAM command interface is configurable through SDRAM0_TR[LDF] to provide a 2 to 4 cycle delay before the

command is used by SDRAM. Output times in table are in cycle 1.

  1. SDRAM I/O timings are specified relative to a MemClkOut terminated in a lumped 10pF load.
  2. SDRAM interface hold times are guaranteed at the NPe405H package pin. System designers must use the NPe405H IBIS

the relative delays on clock wiring do not exceed the delays on other SDRAM signal wiring.

  1. PerClk rising edge at package pin with a 10pF load trails the internal PLB clock by approximately 0.8ns.

66 DS2011 AMCC Proprietary

Table 16. I/O Specifications—266MHz (Sheet 2 of 3)

  1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard.
  2. The SDRAM command interface is configurable through SDRAM0_TR[LDF] to provide a 2 to 4 cycle delay before the

command is used by SDRAM. Output times in table are in cycle 1.

  1. SDRAM I/O timings are specified relative to a MemClkOut terminated in a lumped 10pF load.
  2. SDRAM interface hold times are guaranteed at the NPe405H package pin. System designers must use the NPe405H IBIS

the relative delays on clock wiring do not exceed the delays on other SDRAM signal wiring.

  1. PerClk rising edge at package pin with a 10pF load trails the internal PLB clock by approximately 0.8ns.

Table 16. I/O Specifications—266MHz (Sheet 3 of 3)

  1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard.
  2. The SDRAM command interface is configurable through SDRAM0_TR[LDF] to provide a 2 to 4 cycle delay before the

command is used by SDRAM. Output times in table are in cycle 1.

  1. SDRAM I/O timings are specified relative to a MemClkOut terminated in a lumped 10pF load.
  2. SDRAM interface hold times are guaranteed at the NPe405H package pin. System designers must use the NPe405H IBIS

the relative delays on clock wiring do not exceed the delays on other SDRAM signal wiring.

  1. PerClk rising edge at package pin with a 10pF load trails the internal PLB clock by approximately 0.8ns.

68 DS2011 AMCC Proprietary

The following describes the method by which initial chip settings are established when a system reset occurs. ing normal operation. The following table lists the strapping pins along with their functions and strapping options. default values are covered in detail in the PowerNP NPe405H Network Processor User’s Manual. Table 17. Strapping Pin Assignments

NPe405H – PowerNP NPe405H Embedded Processor Revision 1.01 – April 18, 2007 AMCC Proprietary DS2011 69 Data Sheet DOCUMENT REVISION HISTORY Revision Date Description 1.01 04/18/07 Updated SDRAM and MDIO timing in Tables 15 and 16. 1.00 07/29/04 Initial Release

NPe405H – PowerNP NPe405H Embedded Processor

70 DS2011 AMCC Proprietary

Revision 1.01 – April 18, 2007 Data Sheet Applied Micro Circuits Corporation 6290 Sequence Dr., San Diego, CA 92121 Phone: (858) 450-9333 — (800) 755-2622 — Fax: (858) 450-9885 http://www.amcc.com AMCC reserves the right to make changes to its products, its datasheets, or related documentation, without notice and war- rants its products solely pursuant to its terms and conditions of sale, only to substantially co mply with the latest available datasheet. Please consult AMCC’s Term and Conditions of Sale for its warranties and other terms, conditions and limitations. AMCC may discontinue any semiconductor product or service wi thout notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information is current. AMCC does not assume any lia- bility arising out of the application or use of any product or circuit described herein, neither does it convey any license under its patent rights nor the rights of others. AMCC reserves the ri ght to ship devices of higher gr ade in place of those of lower grade. AMCC SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. AMCC is a registered Trademark of Applied Micro Circuits Corporation. Copyright © 2007 Applied Micro Circuits Corporation.