IA186EB INNOVASIC | Alldatasheet
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IA186EB/IA188EB Data Sheet 8-Bit/16-Bit Microcontrollers July 10, 2011 IA211080314-13 http://www.Innovasic.com UNCONTROLLED WHEN PRINTED OR COPIED Customer Support: Page 1 of 85 1-888-824-4184 IA186EB/IA188EB 8-Bit/16-Bit Microcontrollers Data Sheet
IA186EB/IA188EB Data Sheet 8-Bit/16-Bit Microcontrollers July 10, 2011 IA211080314-13 http://www.Innovasic.com UNCONTROLLED WHEN PRINTED OR COPIED Customer Support: Page 2 of 85 1-888-824-4184 Copyright 2011 by Innovasic Semiconductor, Inc. Published by Innovasic Semiconductor, Inc.
3737 Princeton Drive NE, Suite 130, Albuquerque, NM 87107
MILES™ is a trademark Innovasic Semiconductor, Inc. Intel is a registered trademark of Intel Corporation
IA186EB/IA188EB Data Sheet 8-Bit/16-Bit Microcontrollers July 10, 2011 IA211080314-13 http://www.Innovasic.com UNCONTROLLED WHEN PRINTED OR COPIED Customer Support: Page 3 of 85 1-888-824-4184 TABLE OF CONTENTS
IA186EB/IA188EB Data Sheet 8-Bit/16-Bit Microcontrollers July 10, 2011 IA211080314-13 http://www.Innovasic.com UNCONTROLLED WHEN PRINTED OR COPIED Customer Support: Page 4 of 85 1-888-824-4184
IA186EB/IA188EB Data Sheet 8-Bit/16-Bit Microcontrollers July 10, 2011 IA211080314-13 http://www.Innovasic.com UNCONTROLLED WHEN PRINTED OR COPIED Customer Support: Page 7 of 85 1-888-824-4184 1. Introduction The Innovasic Semiconductor IA186EB and IA188EB microcontrollers are form, fit, and function replacements for the original Intel® 80C186EB, 80C188EB, 80L186EB, and 80L188EB 16-bit high-integration embedded processors. These devices are produced using Innovasic’s Managed IC Lifetime Extension System (MILES™). This cloning technology, which produces replacement ICs beyond simple emulations, ensures complete compatibility with the original device, including any ―undocumented features.‖ Additionally, the MILES process captures the clone design in such a way that production of the clone can continue even as silicon technology advances. The IA186EB and IA188EB microcontrollers replace the obsolete Intel 80C186EB and 80C188EB devices, allowing users to retain existing board designs, software compilers/assemblers, and emulation tools, thereby avoiding expensive redesign efforts.
1.1 General Description
The Innovasic Semiconductor IA186EB and IA188EB microcontrollers are an upgrade for the 80C186EB/80C188EB microcontroller designs with integrated peripherals to provide increased functionality and reduce system costs. The IA186EB and IA188EB devices are designed to satisfy requirements of embedded products designed for telecommunications, office automation and storage, and industrial controls. The IA186EB and IA188EB microcontrollers have a set of base peripherals beneficial to many embedded applications and include a standard numeric interface, an interrupt control unit, a chip- select unit, a DRAM refresh control unit, a power management unit, and three 16-bit timer/counters. The IA186EB and IA188EB microcontrollers are capable of operating at 5.0 or 3.3 volts. This datasheet discusses both modes of operation. Where applicable, characteristics specific to either 3.3 or 5.0 volt operation are identified separately throughout this datasheet. Additionally, the IA186EB and IA188EB include two integrated serial ports that support both synchronous and asynchronous communications, simplifying inter-processor and display communications. The IA186EB and IA188EB also have an enhanced chip-select unit and two multiplexed I/O ports. The enhanced chip-select unit offers 10 general chip selects, each with the ability to address up to 1 Mbyte. This enhanced unit enables memory-bank switching to expand the IA186EB/IA188EB 1 Mbyte address space. The I/O ports allow for basic functions such as scanning keypads for input. The ports can also be used to control system power consumption, disabling unneeded components. The serial ports, I/O capabilities, and enhanced chip selects make the IA186EB/IA188EB an excellent processor for portable data acquisition or communication applications.
IA186EB/IA188EB Data Sheet 8-Bit/16-Bit Microcontrollers July 10, 2011 IA211080314-13 http://www.Innovasic.com UNCONTROLLED WHEN PRINTED OR COPIED Customer Support: Page 8 of 85 1-888-824-4184
1.2 Features
The primary features of the IA186EB and IA188EB microcontrollers are as follows: Low-Power Operating Modes – Idle (freezes CPU clocks; peripherals are kept active) – Power-Down (freezes all internal clocks) Low-Power CPU Core (static) Direct Addressing Capability – Memory: 1 Mbyte – I/O: 64 Kbyte I/O Ports – 2 each, 8-Bit – Multiplexed Clock Generator Chip Selects – 10 each, Programmable – Integral Wait-State Generator Memory Refresh Control Unit Interrupt Controller, Programmable Counter/Timers – 3 each, 16-Bit – Programmable Serial Channels – 2 each, UARTs – Integral Baud Rate Generator Operating Frequency (system clock input) – 50 MHz @ 5V – 32 MHz @ 3.3V Chapter 4, Functional Description, provides details of the IA186EB and IA188EB microcontrollers, including the features listed above.
IA186EB/IA188EB Data Sheet 8-Bit/16-Bit Microcontrollers July 10, 2011 IA211080314-13 http://www.Innovasic.com UNCONTROLLED WHEN PRINTED OR COPIED Customer Support: Page 9 of 85 1-888-824-4184 2. Packaging, Pin Descriptions, and Physical Dimensions Information on the packages and pin descriptions for the IA186EB and the IA188EB is provided separately. Refer to sections, figures, and tables for information on the device of interest.
2.1 Packages and Pinouts
The Innovasic Semiconductor IA186EB and IA188EB microcontroller is available in the following packages: 84-Pin Plastic Leaded Chip Carrier (PLCC), equivalent to original PLCC package 80-Pin Plastic Quad Flat Pack (PQFP), equivalent to original PQFP package 80-Pin Low-Profile Quad Flat Pack (LQFP), equivalent to original SQFP package
2.1.1 IA186EB 84 PLCC Package
pinout is provided in Table 1. Figure 1. IA186EB 84-Pin PLCC Package Diagram
Table 1. IA186EB 84-Pin PLCC Pin Listing
1 Vcc 22 Vss 43 Vss 64 Vcc
2 Vss 23 Vcc 44 clkout 65 Vss
2.1.2 IA188EB 84 PLCC Package
pinout is provided in Table 2. Figure 2. IA188EB 84-Pin PLCC Package Diagram
Table 2. IA188EB 84-Pin PLCC Pin Listing
2.1.3 PLCC Physical Dimensions
The physical dimensions for the 84 PLCC are as shown in Figure 3. Figure 3. 84-Pin PLCC Physical Package Dimensions inches (0.002 inches per side). those stated in this drawing.
2.1.4 IA186EB 80 PQFP Package
pinout is provided in Table 3. Figure 4. IA186EB 80-Pin PQFP Package Diagram
Table 3. IA186EB 80-Pin PQFP Pin Listing
13 Vcc 33 Vss 53 Vss 73 Vss
14 Vss 34 Vcc 54 Vcc 74 clkout
2.1.5 IA188EB 80 PQFP Package
pinout is provided in Table 4. Figure 5. IA188EB 80-Pin PQFP Package Diagram
Table 4. IA188EB 80-Pin PQFP Pin Listing
2.1.6 PQFP Physical Dimensions
The physical dimensions for the 80 PQFP are as shown in Figure 6. Figure 6. 80-Pin PQFP Physical Package Dimensions
- Dimension D1 and E1 do not include mold protrusion.
- Dimension b does not include dambar protrusion.
2.1.7 IA186EB 80 LQFP Package
pinout is provided in Table 5. Figure 7. IA186EB 80-Pin LQFP Package Diagram
Table 5. IA186EB 80-Pin LQFP Pin Listing
10 Vss 30 Vss 50 Vcc 70 Vss
11 Vcc 31 clkout 51 Vss 71 Vcc
2.1.8 IA188EB 80 LQFP Package
pinout is provided in Table 6. Figure 8. IA188EB 80-Pin LQFP Package Diagram
Table 6. IA188EB 80-Pin LQFP Pin Listing
2.1.9 LQFP Physical Dimensions
The physical dimensions for the 80 LQFP are as shown in Figure 9. Figure 9. 80-Pin LQFP Physical Package Dimensions
- Exact shape of each corner is optional.
- Controlling dimension: mm.
- To be determined at seating plane C.
- Dimensions D1 and E1 do not include
dimensions including mold mismatch.
- Dimension b does not include dambar
on the lower radius of the foot.
- Exact shape of each corner is
- These dimensions apply to the flat
- A1 is defined as the distance from the
2.2 IA186EB Pin/Signal Descriptions
Table 7. IA186EB Pin/Signal Descriptions 16-bit data are present on these lines.
Table 7. IA186EB Pin/Signal Descriptions (Continued) ale ale 6 75 38 address latch enable. Output. Active High. the upper half of the data bus. Note: bhe_n is multiplexed with refresh_n.
cts0_n cts0_n 51 38 1 clear to send, Serial Port 0. Input. Active Low. transmission from Serial Port 0 is inhibited. cts1_n p2.4/cts1_n 56 43 6 clear to send, Serial Port 1. Input. Active Low. transmission from Serial Port 1 is inhibited. bidirectional buffers in a buffered system.
space programmed for that output. hlda hlda 12 1 44 hold acknowledge. Output. Active High. a HOLD request (see next table entry). master to drive the signals directly.
nmi nmi 17 5 48 non-maskable interrupt. Input. Active High. ONCE Mode is used for device testing. pins are placed in a high-impedance state.
is connected between this pin and the clkin pin. ONCE mode, oscout does not float. general-purpose output line. as a general-purpose I/O line. general-purpose output line. general-purpose output line.
pdtmr pdtmr 36 24 67 power-down timer. Input/Output (push-pull). assertion of the resin_n input). reset (i.e., the assertion resin_n). pereq pereq 39 NA NA numerics coprocessor external request. Input. pending. This applies to the PLCC only. being accessed onto the data bus. Chip-Select Unit is configured to ignore ready.
rxd0 rxd0 53 40 3 Receive (rx) data, Serial Port 0. Input/Output. This pin is the serial data input for Serial Port 0. data transmission (txd0 becomes the clock). rxd1 p2.0/rxd1 57 44 7 Receive (rx) data, Serial Port 1. Input/Output. This pin is the serial data input for Serial Port 1. data transmission (txd1 becomes the clock). indicates that Serial Port 1 requires service. used either as clock input or a control signal. used either as clock input or a control signal.
pin is the serial data output for Serial Port 0. functions as an output for data transmission). pin is the serial data output for Serial Port 1. functions as an output for data transmission). connected to a vss board plane.
2.3 IA188EB Pin/Signal Descriptions
are provided in the ―Pin‖ column. Table 8. IA188EB Pin/Signal Descriptions data are present on these lines. ale ale 6 75 38 address latch enable. Output. Active High.
Table 8. IA188EB Pin/Signal Descriptions (Continued) cts0_n cts0_n 51 38 1 clear to send, Serial Port 0. Input. Active Low. transmission from Serial Port 0 is inhibited. cts1_n p2.4/cts1_n 56 43 6 clear to send, Serial Port 1. Input. Active Low. transmission from Serial Port 1 is inhibited. bidirectional buffers in a buffered system.
space programmed for that output. hlda hlda 12 1 44 hold acknowledge. Output. Active High. a HOLD request (see next table entry). bus master to drive the signals directly. inta0_n int2/inta0_n 33 21 64 interrupt acknowledge 0. Output. Active Low. on the int0 pin (see previous table entry).
lcs_n lcs_n 29 17 60 lower chip select. Input/Output. Active Low. nmi nmi 17 5 48 non-maskable interrupt. Input. Active High. ONCE Mode is used for device testing. placed in a high-impedance state. ONCE mode, oscout does not float.
general-purpose output line. as a general-purpose I/O line. general-purpose output line. general-purpose output line.
pdtmr pdtmr 36 24 67 Power-down timer. Input/Output (push-pull). assertion of the resin_n input). reset (i.e., the assertion resin_n). being accessed onto the data bus. Chip-Select Unit is configured to ignore ready.
rxd0 rxd0 53 40 3 Receive (rx) data, Serial Port 0. Input/Output. This pin is the serial data input for Serial Port 0. data transmission (txd0 becomes the clock). rxd1 p2.0/rxd1 57 44 7 Receive (rx) data, Serial Port 1. Input/Output. This pin is the serial data input for Serial Port 1. data transmission (txd1 becomes the clock). indicates that Serial Port 1 requires service. used either as clock input or a control signal. used either as clock input or a control signal.
pin is the serial data output for Serial Port 0. functions as an output for data transmission). pin is the serial data output for Serial Port 1. functions as an output for data transmission). connected to a vss board plane.
- Maximum Ratings, Thermal Characteristics, and DC Parameters
Table 9. IA186EB and IA188EB Absolute Maximum Ratings Table 10. IA186EB and IA188EB Thermal Characteristics
Table 11. IA186EB and IA188EB DC Parameters Operating temperature is -40°C to +85°C.
IA186EB/IA188EB Data Sheet 8-Bit/16-Bit Microcontrollers July 10, 2011 IA211080314-13 http://www.Innovasic.com UNCONTROLLED WHEN PRINTED OR COPIED Customer Support: Page 44 of 85 1-888-824-4184 4. Functional Description
4.1 Device Architecture
Architecturally, the IA186EB and IA188EB microcontrollers include the following functional modules: Bus Interface Unit Clock Generator Interrupt Control Unit Timer/Counter Unit Serial Communications Unit Chip-Select Unit I/O Port Unit Refresh Control Unit Power Management Unit A functional block diagram of the IA186EB/IA188EB is shown in Figure 10. Descriptions of the functional modules are provided in the following subsections.
4.1.1 Bus Interface Unit
The IA186EB/IA188EB bus controller that generates local bus control signals and uses a hold/hlda protocol to share the local bus with other bus masters. The bus controller generates 20 address bits, read and write control signals, and bus-cycle status information. A ready input is used to extend a bus cycle beyond the minimum four clock cycles.
Figure 10. IA186EB/IA188EB Functional Block Diagram
4.1.2 Clock Generator
The IA186EB/IA188EB uses an on-chip clock generator to supply internal and external clocks. The clock generator makes use of a crystal oscillator and includes a divide-by-two counter. network (B), or it can be driven by an external clock source (C). Figure 11. Clock Circuit Connection Options
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4.1.3 Interrupt Control Unit
The IA186EB/IA188EB can receive interrupts from a number of sources, both internal and external. The interrupt control unit serves to merge these requests on a priority basis, for individual service by the CPU. Each interrupt source can be independently masked by the Interrupt Control Unit (ICU) or all interrupts can be globally masked by the CPU. Internal interrupt sources include the Timers and Serial Channel 0. External interrupt sources come from the five input pins int0–int4. The NMI interrupt pin is not controlled by the ICU and is passed directly to the CPU. Although the Timer and Serial channel each have only one request input to the ICU, separate vector types are generated to service individual interrupts within the Timer and Serial channel units.
4.1.4 Timer/Counter Unit
The IA186EB/IA188EB Timer/Counter Unit (TCU) provides three 16-bit programmable timers. Two of these are highly flexible and are connected to external pins for control or clocking. A third timer is not connected to any external pins and can only be clocked internally. However, it can be used to clock the other two timer channels. The TCU can be used to count external events, time external events, generate non-repetitive waveforms, and generate timed interrupts, etc.
4.1.5 Serial Communications Unit
The Serial Control Unit (SCU) of the IA186EB/IA188EB contains two independent channels. Each channel is identical in operation except that only Channel 0 is supported by the integrated interrupt controller (Channel 1 has an external interrupt pin). Each channel has its own baud rate generator that is independent of the Timer/Counter Unit, and can be internally or externally clocked at up to one half the IA186EB/IA188EB operating frequency. Independent baud rate generators are provided for each of the serial channels. For the asynchronous modes, the generator supplies an 8x baud clock to both the receive and transmit register logic. A 1x baud clock is provided in the synchronous mode.
4.1.6 Chip-Select Unit
The IA186EB/IA188EB Chip-Select Unit (CSU) integrates logic that provides up to ten programmable chip-selects to access both memories and peripherals. In addition, each chip select can be programmed to automatically insert additional clocks (wait-states) into the current bus cycle and automatically terminate a bus cycle independent of the condition of the ready input pin.
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4.1.7 I/O Port Unit
The I/O Port Unit (IPU) on the IA186EB/IA188EB supports two 8-bit channels of input, output, or input/output operation. Port 1 is multiplexed with the chip select pins and is output only. Most of Port 2 is multiplexed with the serial channel pins.
4.1.8 Refresh Control Unit
The Refresh Control Unit (RCU) automatically generates a periodic memory read bus cycle to keep dynamic or pseudo-static memory refreshed. A 9-bit counter controls the number of clocks between refresh requests. A 12-bit address generator is maintained by the RCU and is presented on the a1–a12 address lines during the refresh bus cycle. Address Bits [a13–a19] are programmable to allow the refresh address block to be located on any 8-Kbyte boundary.
4.1.9 Power Management Unit
The IA186EB/IA188EB Power Management Unit (PMU) is provided to control the power consumption of the device. The PMU provides three power modes: Active, Idle, and Powerdown. Active Mode indicates that all units on the IA186EB/IA188EB are functional and the device consumes maximum power (depending on the level of peripheral operation). Idle Mode freezes the clocks of the execution and bus units at a logic zero state (all peripherals continue to operate normally). The Powerdown mode freezes all internal clocks at a logic zero level and disables the crystal oscillator. All internal registers hold their values provided VCC is maintained. Current consumption is reduced to just transistor junction leakage.
4.2 Peripheral Architecture
The IA186EB/IA188EB has integrated several common system peripherals with a CPU core to create a compact, yet powerful system. The integrated peripherals are designed to be flexible and provide logical interconnections between supporting units (e.g., the interrupt control unit supports interrupt requests from the timer/counters or serial channels). The list of integrated peripherals includes: 7-Input Interrupt Control Unit 3-Channel Timer/Counter Unit 2-Channel Serial Communications Unit 10-Output Chip-Select Unit I/O Port Unit Refresh Control Unit
space on any 256-byte address boundary. Table 12 provides a list of the registers associated with the PCB. Table 12. Peripheral Control Block Registers
Table 12. Peripheral Control Block Registers (Continued) established a value between 0x0000 and 0x0002, depending on the revision of the part.
4.3 Reference Documents
and Tables 15 and 16. Relative timing characteristics are provided in Figure 14 and Table 17. Instruction Execution Times. at 100C and 4.75V; Rev. 2 was tested at 100C and 4.5V. Figure 12. AC Input Characteristics
For specific 5.0- and 3.3-volt characteristics, refer to Tables 13 and 14, respectively. Table 13. AC Input Characteristics for 5.0-Volt Operation Table 14. AC Input Characteristics for 3.3-Volt Operation Figure 13. AC Output Characteristics For specific 5.0- and 3.3-volt characteristics, refer to Tables 15 and 16, respectively.
Table 15. AC Output Characteristics for 5.0-Volt Operation Table 16. AC Output Characteristics for 3.3-Volt Operation
Figure 14. Relative Timing Characteristics For specific relative timing characteristics, refer to Table 17.
Table 17. Relative Timing Characteristics
5.1 AC Test Conditions
measured at the VCC/2 crossing point unless otherwise specified. Figure 15. AC Test Load
5.2 Clock Input and Clock Output Timing Characteristics
Tables 18 and 19, respectively. Figure 16. Clock Input and Clock Output Timing Characteristics Table 18. Clock Input and Clock Output Timing Characteristics for 5.0-Volt Operation
1 TCKIN clkin Period 20 ∞ ns –
2 TCHCK clkin High
3 TCLCK clkin Low
4 TCKLH clkin Rise
1 5 ns Only required to guarantee ICC.
5 TCKHL clkin Fall
1 5 ns Only required to guarantee ICC.
6 TCICO clkin to clkout
0 11.5 ns Specified for a 50-pF load.
7 TCLCL clkout Period – 2TCKIN ns –
8 TCHCL clkout High
9 TCCCH clkout Low
10 TCH1CH2 clkout Rise
1 6 ns Specified for a 50-pF load.
11 TCL2CL1 clkout Fall
1 6 ns Specified for a 50-pF load.
Table 19. Clock Input and Output Characteristics for 3.3-Volt Operation
1 TC clkin Period 30 ∞ ns –
2 TCH clkin High
3 TCL clkin Low Time 15 ∞ ns Measure for VIH for high time, NIL for low
4 TCR clkin Rise
limits are bounded for TC, TCH and TCL. limits are bounded for TC, TCH and TCL.
6 XTCD clkin to clkout
0 14.5 ns Specified for a 50-pF load.
7 T clkout Period – 2TC ns –
8 TPH clkout High
9 TPL clkout Low
10 TPR clkout Rise
1 6 ns Specified for a 50-pF load.
11 TPF clkout Fall
1 6 ns Specified for a 50-pF load.
5.3 Serial Port Mode 0 Timing Characteristics
Serial Port Mode 0 timing characteristics are illustrated in Figure 17 and collected in Table 20. Figure 17. Serial Port Mode 0 Timing Characteristics Table 20. Serial Port Mode 0 Timing Characteristics
Figure 18. Cold Reset Timing
Figure 19. Warm Reset Timing
Figure 20. Read, Fetch, and Refresh Cycle Timing
Figure 21. Write Cycle Timing
Figure 22. Halt Cycle Timing
Figure 23. Interrupt Acknowledge (inta1_n, inta0_n) Cycle Timing
Figure 24. hold/hlda Timing
Figure 25. Refresh During Hold Acknowledge Timing
Figure 26. Ready Timing
- Instruction Execution Times
Table 21. Instruction Set Timing
Table 21. Instruction Set Timing (Continued)
Table 22. Innovasic Part Number Cross-Reference for the PLCC
Table 23. Innovasic Part Number Cross-Reference for the PQFP
Table 24. Innovasic Part Number Cross-Reference for the LQFP
the identified problem has been provided where possible.
9.1 Summary
Table 25 presents a summary of errata. Table 25. Summary of Errata
1 Alternate Mode (TxCON[1] == 1) for timer 0 and 1 has some functional
2 When the extension byte (mod field) is set to ―11,‖ some instructions will
3 When the chip is put in SFNM mode for INT0 or INT1, the LVL bit is
automatically set for those interrupts.
7 Bound instruction uses bad data when index addresses are on odd
8 Pin LOCK_n does not have an internal pullup and will float during reset
9 The Relocation Register (RELREG, PCB offset 0xA8) can only be modified
10 When the timer compare register for any of the timers is set to x0000, the
IA186EB/IA188EB Data Sheet 8-Bit/16-Bit Microcontrollers July 10, 2011 IA211080314-13 http://www.Innovasic.com UNCONTROLLED WHEN PRINTED OR COPIED Customer Support: Page 78 of 85 1-888-824-4184 Errata No. Problem Ver. 0 Ver. 2 12 Illegal serial port modes do not match OEM part. Exists Exists 13 Non-maskable interrupt (NMI) can be pre-empted by maskable interrupt. Exists Exists 14 Ready signal may not be recognized in bus cycles with zero wait states. Exists Exists
9.2 Detail
Errata No. 1 Problem: Alternate Mode (TxCON[1] == 1) for timer 0 and 1 has some functional issues. Description: TxOUT will continuously toggle at 1/2 CLKOUT regardless of count register values. The maxcount compare will not work. The live count will compare against TxCMPA and TxCMPB in alternate cycles. This could cause a compare (and the associated interrupt, or switch the intended compare, or stop counting altogether) to occur early or not at all. The TxOUT pin may start in the wrong state if the user writes to TxCON register Bit [12]. When in retrigger mode, Timer 1 will not function correctly. Input pulses on T0IN will cause counter to begin counting. Workaround: None.
IA186EB/IA188EB Data Sheet 8-Bit/16-Bit Microcontrollers July 10, 2011 IA211080314-13 http://www.Innovasic.com UNCONTROLLED WHEN PRINTED OR COPIED Customer Support: Page 79 of 85 1-888-824-4184 Errata No. 2 Problem: When the extension byte (mod field) is set to ―11,‖ some instructions will cause the CPU to hang. Description: Although there are faster versions of each instruction (these are not commonly used by compilers), the following instructions will cause the CPU to hang when the extension byte (mod field) is set to ―11‖: 8D (LEA) 8F (POP memory) C6 (MOV immediate8 to memory/register) C7 (MOV immediate16 to memory/register) FE (PUSH memory) FF (PUSH memory) Workaround: Substitute instructions in the following table. Instruction Workaround 8D (LEA) Use MOV register (89 or 8B) 8F (POP memory) Use POP register (0101_0xxx) C6 (MOV immediate8 to memory/register) Use MOV immediate8 to register (1011_0xxx) C7 (MOV immediate16 to memory/register) Use MOV immediate16 to register (1011_1xxx) FE (PUSH memory) Use PUSH register (0101_0xxx) FF (PUSH memory) Use PUSH register (0101_0xxx) Errata No. 3 Problem: When the chip is put in SFNM mode for INT0 or INT1, the LVL bit is automatically set for those interrupts. Workaround: None.
IA186EB/IA188EB Data Sheet 8-Bit/16-Bit Microcontrollers July 10, 2011 IA211080314-13 http://www.Innovasic.com UNCONTROLLED WHEN PRINTED OR COPIED Customer Support: Page 80 of 85 1-888-824-4184 Errata No. 4 Problem: Timer 2 will stop or not start counting. Description: Writing a logic ―1‖ to unused bits in the timer control register can cause the timer to stop counting or to never start counting. Workaround: Do not write a logic ―1‖ to any unused or reserved bits in the timer control register. Errata No. 5 Problem: Write does not occur when counter is actively counting. Description: If a timer incremented its count register to the currently active compare register during a write to that count register, the write would not occur. Workaround: Do not write count register while that counter is actively counting. Errata No. 6 Problem: Program Counter can become corrupted if an interrupt occurs. Description: If an interrupt occurs during the decode stage of a TEST instruction using an opcode of the form 1111_0111_1100_0xxx, the Program Counter could become corrupted upon returning from the interrupt handler. Workaround: None. Errata No. 7 Problem: Bound instruction uses bad data when index addresses are on odd boundary in memory. Description: BOUND instruction will use bad data if index address LSB is a ―1‖ in memory. Workaround: None.
IA186EB/IA188EB Data Sheet 8-Bit/16-Bit Microcontrollers July 10, 2011 IA211080314-13 http://www.Innovasic.com UNCONTROLLED WHEN PRINTED OR COPIED Customer Support: Page 81 of 85 1-888-824-4184 Errata No. 8 Problem: Pin LOCK_n does not have an internal pullup. Description: Because Pin LOCK_n does not have an internal pullup, it will float during reset and bus hold. Workaround: An external pullup may be necessary if there is high external load on the signal. Errata No. 9 Problem: The Relocation Register (RELREG, PCB offset 0xA8) can only be modified by an 8-bit write. Description: The Relocation Register (RELREG, PCB offset 0xA8) can only be modified by an 8-bit write. A 16-bit write will have no effect. The 186 EB is unaffected. Workaround: Use an 8-bit access to affect the RELREG register. Errata No. 10 Problem: When the timer compare register for any of the timers is set to x0000, the max count is xFFFF instead of x10000 as in the OEM part. Description: The timer output will change one count earlier than it should when the max count is set to x0000. Workaround: The workaround is application dependent. Please contact Innovasic Technical Support if this erratum is an issue. Errata No. 11 Problem: NMI cannot bring chip out of powerdown mode. Description: Only a reset brings the part out of powerdown after a HLT instruction is executed with the PWRDN bit set in the PWRCON register. Workaround: Use IDLE instead of PWRDN.
IA186EB/IA188EB Data Sheet 8-Bit/16-Bit Microcontrollers July 10, 2011 IA211080314-13 http://www.Innovasic.com UNCONTROLLED WHEN PRINTED OR COPIED Customer Support: Page 82 of 85 1-888-824-4184 Errata No. 12 Problem: Illegal serial port modes do not match OEM part. Description: If the mode bits of the serial control register (S1CON, S0CON) are set to an illegal encoding (0x5, 0x6, or 0x7), the Innovasic part acts as though it were in mode 4. The OEM part acts as if it were in mode 1. Workaround: Use a valid encoding for serial mode. Errata No. 13 Problem: Non-maskable interrupt (NMI) can be pre-empted by maskable interrupt. Description: When instruction execution unit is in Decode state for 2 or more consecutive cycles and an NMI is recognized, it could be pre-empted by a maskable interrupt. Workaround: None. Errata No. 14 Problem: Ready signal may not be recognized in bus cycles with zero wait states. Description: When a chip select is set to use the ready signal to extend a bus cycle that normally has no wait states (Start register bits 3-0 == 0000), the ready signal may not be recognized in time to extend the bus cycle. Workaround: Set wait states to 1 or more if using ready to extend bus cycles.
IA186EB/IA188EB Data Sheet 8-Bit/16-Bit Microcontrollers July 10, 2011 IA211080314-13 http://www.Innovasic.com UNCONTROLLED WHEN PRINTED OR COPIED Customer Support: Page 83 of 85 1-888-824-4184
Revision History
Table 26 presents the sequence of revisions to document IA211080314. Table 26. Revision History a8‖ in Figures 26 and 27. Errata No. 4 added. version of the 188EB in the 80-pin LQFP package. Added two errata for Version 2 of the device.
IA186EB/IA188EB Data Sheet 8-Bit/16-Bit Microcontrollers July 10, 2011 IA211080314-13 http://www.Innovasic.com UNCONTROLLED WHEN PRINTED OR COPIED Customer Support: Page 84 of 85 1-888-824-4184 Date Revision Description Page(s) September 4, 2009 08 Added a note to Table 12 regarding the Step ID register. 50 February 25, 2011 09 Elimination of pages with SnPb lead plating options 74-76 March 23, 2011 10 Updated Instruction Set Timing Table to incorporate DIV and IDIV values. 70 June 12, 2011 11 Added Errata 11 and 12. 77, 78, 81 July 5, 2011 12 Added Errata 13. 78, 82 July 10, 2011 13 Added Errata 14. 78, 82
IA186EB/IA188EB Data Sheet 8-Bit/16-Bit Microcontrollers July 10, 2011 IA211080314-13 http://www.Innovasic.com UNCONTROLLED WHEN PRINTED OR COPIED Customer Support: Page 85 of 85 1-888-824-4184 10. For Additional Information The Innovasic Semiconductor IA186EB and IA188EB microcontrollers are form, fit, and function replacements for the original Intel® 80C186EB, 80C188EB, 80L186EB, and 80L188EB 16-bit high-integration embedded processors. The Innovasic Support Team wants our information to be complete, accurate, useful, and easy to understand. Please feel free to contact our experts at Innovasic at any time with suggestions, comments, or questions. Innovasic Support Team
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