N25Q128A11B1241F

N25Q128A11B1241F MICRON | Alldatasheet

Document overview

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• PDF pages: 185

Technical content

Datasheet sections

• 1 Description
• 2 Signal descriptions
• 2.1 Serial data output (DQ1)
• 2.2 Serial data input (DQ0)
• 2.3 Serial Clock (C)
• 2.4 Chip Select (S)
• 2.5 Hold (HOLD) or Reset (Reset)
• 2.6 Write protect/enhanced program supply voltage (W
• 2.7 V CC supply voltage
• 2.8 V SS ground
• 3 SPI Modes
• 4 SPI Protocols
• 4.1 Extended SPI protocol
• 4.2 Dual I/O SPI (DIO-SPI) protocol
• 4.3 Quad SPI (QIO-SPI) protocol
• 5 Operating features
• 5.1 Extended SPI Protocol Operating features
• 5.1.1 Read Operations
• 5.1.2 Page programming
• 5.1.3 Dual input fast program
• 5.1.4 Dual Input Extended Fast Program
• 5.1.5 Quad Input Fast Program
• 5.1.6 Quad Input Extended Fast Pr ogram
• 5.1.7 Subsector erase, sector erase and bulk erase
• 5.1.8 Polling during a write, pr ogram or erase cycle
• 5.1.9 Active power and standby power modes
• 5.1.10 Hold (or Reset) cond ition
• 5.2 Dual SPI (DIO-SPI) Protocol
• 5.2.1 Multiple Read Identification

Datasheet sections

• 6.4.1 Quad Input Command VECR<7>
• 6.4.2 Dual Input Command VECR<6>
• 6.4.3 Reset/Hold disable VECR<4>
• 6.4.4 Accelerator pin enable: QIO-SPI pr otocol / QIFP/QIEFP VECR<3>
• 6.4.5 Output Driver Strength VECR<2:0>
• 6.5 Flag Status Register
• 6.5.1 P/E Controller Status bit
• 6.5.2 Erase Suspend Status bit
• 6.5.3 Erase Status bit
• 6.5.4 Program Status bit
• 6.5.5 VPP Status bit
• 6.5.6 Program Suspend Status bit
• 6.5.7 Protection Status bit
• 7 Protection modes
• 7.1 SPI Protocol-related protections
• 7.2 Specific hardware and software protection
• 8 Memory organization
• 9 Instructions
• 9.1 Extended SPI Instructions
• 9.1.1 Read Identification (RDID)
• 9.1.2 Read Data Bytes (READ)
• 9.1.3 Read Data Bytes at Higher Speed (FAST_READ)
• 9.1.4 Dual Output Fast Read (DOFR)
• 9.1.5 Dual I/O Fast Read
• 9.1.6 Quad Output Fast Read
• 9.1.7 Quad I/O Fast Read
• 9.1.8 Read OTP (ROTP)
• 9.1.9 Write Enable (WREN)
• 9.1.10 Write Disable (WRDI)
• 9.1.11 Page Program (PP)
• 9.1.12 Dual Input Fast Program (DIF P)
• 9.1.13 Dual Input Extended Fast Program
• 9.1.14 Quad Input Fast Program
• 9.1.15 Quad Input Extended Fast Program

Datasheet sections

• 9.2.17 Read Flag Status Register
• 9.2.18 Clear Flag Status Register
• 9.2.19 Read NV Configuration Register
• 9.2.20 Write NV Configuration Register
• 9.2.21 Read Volatile Configuration Register
• 9.2.22 Write Volatile Configuration Register
• 9.2.23 Read Volatile Enhanced Configuration Re gister
• 9.2.24 Write Volatile Enhanced Configuration Re gister
• 9.2.25 Deep Power-down (DP)
• 9.2.26 Release from Deep Power- down (RDP)
• 9.3 QIO-SPI Instructions
• 9.3.1 Multiple I/O Read Identification (MIORDID)
• 9.3.2 Quad Command Fast Read (QCFR)
• 9.3.3 Read OTP (ROTP)
• 9.3.4 Write Enable (WREN)
• 9.3.5 Write Disable (WRDI)
• 9.3.6 Quad Command Page Program (QCPP)
• 9.3.7 Program OTP instruction (POTP)
• 9.3.8 Subsector Erase (SSE)
• 9.3.9 Sector Erase (SE)
• 9.3.10 Bulk Erase (BE)
• 9.3.11 Program/Erase Suspend
• 9.3.12 Program/Erase Resume
• 9.3.13 Read Status Register (RDSR)
• 9.3.14 Write status register (WRSR)
• 9.3.15 Read Lock Register (RDLR)
• 9.3.16 Write to Lock Register (WRLR)
• 9.3.17 Read Flag Status Register
• 9.3.18 Clear Flag Status Register
• 9.3.19 Read NV Configuration Register
• 9.3.20 Write NV Configuration Register
• 9.3.21 Read Volatile Configuration Register
• 9.3.22 Write Volatile Configuration Register
• 9.3.23 Read Volatile Enhanced Configuration Re gister
• 9.3.24 Write Volatile Enhanced Configuration Re gister
• 9.3.25 Deep Power-down (DP)
• 9.3.26 Release from Deep Power- down (RDP)

Features

„ SPI-compatible serial bus interface „ 108 MHz (maximum) clock frequency „ 1.7 V to 2 V single supply voltage „ Supports legacy SPI protocol and new Quad I/O or Dual I/O SPI protocol „ Quad/Dual I/O instructions resulting in an equivalent clock frequency up to 432 MHz: „ XIP mode for all three protocols – Configurable via volatile or non-volatile registers (enabling the memory to work in XiP mode directly after power on) „ Program/Erase suspend instructions „ Continuous read of entire memory via single instruction: –F a s t R e a d – Quad or Dual Output Fast Read – Quad or Dual I/O Fast Read „ Flexible to fit application: – Configurable numb er of dummy cycles – Output buffer configurable – Fast POR instruction: to speed up power on phase – Reset function available upon customer request „ 64-byte user-lockable, one-time programmable (OTP) area „ Erase capability – Subsector (4-Kbyte) granularity in the 8 boot sectors (bottom or top parts). – Sector (64-Kbyte) granularity „ Write protections – Software write protection applicable to every 64-Kbyte sector (volatile lock bit) – Hardware write protection: protected area size defined by five non-volatile bits (BP0, BP1, BP2, BP3 and TB bit) – Additional smart protections available upon customer request „ Deep Power-down mode: 5 µA (typical) „ Electronic signature – JEDEC standard two-byte signature (BB18h) – Additional 2 Extended Device ID (EDID) bytes to identify device factory options – Unique ID code (UID) with 14 bytes read- only, available upon customer request „ 100,000 + program/erase cycles per sector „ More than 20 years data retention „ Packages – RoHS compliant VDFPN8 (F8) 8 × 6 mm (MLP8) SO16 (SF) 300 mils width TBGA24 (12) 6 x 8 mm www.numonyx.com

N25Q128 - 1.8 V Contents 6.2.1 Dummy clock cycle NV configuration bits (NVCR bits from 15 to 12) . . 37 6.2.3 Output Driver Strength NV configuratio n bits (NVCR bits from 8 to 6) . . 38 6.3.1 Dummy clock cycle Volatile Configurat ions bits (VCR bits from 7 to 4) . 40

N25Q128 - 1.8 V Contents

N25Q128 - 1.8 V Contents

Table 35. VDFPN8 (MLP8) 8-lead very thin dual flat package no lead,

Description N25Q128 - 1.8 V

1 Description

The N25Q128 is a 128 Mbit (16Mb x 8) serial Flash memory, with advanced write protection mechanisms. It is accessed by a high speed SPI-compatible bus and features the possibility to work in XIP (“eXecute in Place”) mode. The N25Q128 supports innovative, high-performance quad/dual I/O instructions, these new instructions allow to double or quadruple the transfer bandwidth for read and program operations. Furthermore the memory can be operated with 3 different protocols: „ Standard SPI (Extended SPI protocol) „ Dual I/O SPI „ Quad I/O SPI The Standard SPI protocol is enriched by the new quad and dual instructions (Extended SPI protocol). For Dual I/O SPI (DIO-SPI) all the instructions codes, the addresses and the data are always transmitted across two data lines. For Quad I/O SPI (QIO-SPI) the instructions codes, the addresses and the data are always transmitted across four data lines thus enabling a tremendous improvement in both random access time and data throughput. The memory can work in “XIP mode”, that means the device only requires the addresses and not the instructions to output the data. This mode dramatically reduces random access time thus enabling many applications requiring fast code execution without shadowing the memory content on a RAM. The XIP mode can be used with QIO-SPI, DIO-SPI, or Extended SPI protocol, and can be entered and exited using different dedicated instructions to allow maximum flexibility: for applications required to enter in XIP mode right after power up of the device, this can be set as default mode by using dedicated Non Volatile Register (NVR) bits. It is also possible to reduce the power on sequence time with the Fast POR (Power on Reset) feature, enabling a reduction of the latency time before the first read instruction can be performed. Another feature is the ability to pause and resume program and erase cycles by using dedicated Program/Erase Suspend and Resume instructions. The N25Q128 memory offers the following additional Features to be configured by using the Non Volatile Configuration Register (NVCR) for default /Non-Volatile settings or by using the Volatile and Volatile Enhanced Configuration Registers for Volatile settings: „ the number of dummy cycles for fast read instructions (single, dual and, quad I/O) according to the operating frequency „ the output buffer impedance „ the type of SPI protocol (extended SPI, DIO-SPI or QIO-SPI) „ the required XIP mode „ Fast or standard POR sequence „ the Hold (Reset) functionality enabling/disabling The memory is organized as 248 (64-Kbyte) main sectors, in products with Bottom or Top architecture there are 8 64-Kbyte boot sectors, and each boot sector is further divided into 16 4-Kbyte subsectors (128 subsectors in total). The boot sectors can be erased a 4-Kbyte subsector at a time or as a 64-Kbyte sector at a time. The entire memory can be also erased at a time or by sector.

Kbyte (sector granularity) for volatile protections. Numonyx Sales office for more information. Figure 1. Logic diagram Table 1. Signal names

1. Provides dual and quad I/O for Extended SPI protocol instructio ns, dual I/O for Dual I/O SPI protocol instructions, and quad

I/O for Quad I/O SPI protocol instructions.

1. Provides dual and quad instruction input for Extended SPI protocol, dual instruction input for Dual I/O SPI protocol, and

quad instruction input for Quad I/O SPI protocol.

1. Provides quad I/O for Extended SPI protocol instructions, and quad I/O for Quad I/O SPI protocol instructions.
2. Reset functionality available with a dedicated part number. See Section 16: Ordering information.

Figure 4. BGA connections

1. See Figure 116.: TBGA - 6 x 8 mm, 24-ball, mechanical package outline.

Signal descriptions N25Q128 - 1.8 V

2 Signal descriptions

2.1 Serial data output (DQ1)

This output signal is used to transfer data serially out of the device. Data are shifted out on the falling edge of Serial Clock (C). When used as an Input, It is latched on the rising edge of the Serial Clock (C). In the Extended SPI protocol, during the Quad and Dual Input Fast Program (QIFP, DIFP) instructions and during the Quad and Dual Input Extended Fast Program (QIEFP, DIEFP) instructions, pin DQ1 is used also as an input. In the Dual I/O SPI protocol (DIO-SPI) the DQ1 pin always acts as an input/output. In the Quad I/O SPI protocol (QIO-SPI) the DQ1 pin always acts as an input/output, with the exception of the Program or Erase cycle performed with the Enhanced Program Supply Voltage (VPP). In this case the device temporarily goes in Extended SPI protocol. The protocol then becomes QIO-SPI as soon as the VPP pin voltage goes low.

2.2 Serial data input (DQ0)

This input signal is used to transfer data serially into the device. It receives instructions, addresses, and the data to be programmed. Values are latched on the rising edge of Serial Clock (C). Data are shifted out on the falling edge of the Serial Clock (C). In the Extended SPI protocol, during the Quad and Dual Output Fast Read (QOFR, DOFR) and the Quad and Dual Input/Output Fast Read (QIOFR, DIOFR) instructions, pin DQ0 is also used as an input/output. In the DIO-SPI protocol the DQ0 pin always acts as an input/output. In the QIO-SPI protocol, the DQ0 pin always acts as an input/output, with the exception of the Program or Erase cycle performed with the VPP. In this case the device temporarily goes in Extended SPI protocol. Then, the protocol returns to QIO-SPI as soon as the VPP pin voltage goes low.

2.3 Serial Clock (C)

This input signal provides the timing for the serial interface. Instructions, addresses, or data present at serial data input (DQ0) are latched on the rising edge of Serial Clock (C). Data are shifted out on the falling edge of the Serial Clock (C).

2.4 Chip Select (S )

When this input signal is high, the device is deselected and serial data output (DQ1) is at high impedance. Unless an internal program, erase or write status register cycle is in progress, the device will be in the standby power mode (this is not the deep power-down mode). Driving Chip Select (S ) low enables the device, placing it in the active power mode. After power-up, a falling edge on Chip Select (S) is required prior to the start of any instruction.

N25Q128 - 1.8 V Signal descriptions

2.5 Hold (HOLD ) or Reset (Reset)

The Hold (HOLD) signal is used to pause any serial communications with the device without deselecting the device. Reset functionality is present instead of Hold in devices with a dedicated part number. See Section 16: Ordering information. During Hold condition, the Serial Data output (DQ1) is in high impedance, and Serial Data input (DQ0) and Serial Clock (C) are Don't Care. To start the Hold condition, the device must be selected, with Chip Select (S) driven Low. For devices featuring Reset instead of Hold functionality, the Reset (Reset) input provides a hardware reset for the memory. When Reset (Reset) is driven High, the memory is in the normal operating mode. When Reset (Reset) is driven Low, the memory will enter the Reset mode. In this mode, the output is high impedance. Driving Reset (Reset) Low while an internal operation is in progress will affect this operation (write, program or erase cycle) and data may be lost. In the Extended SPI protocol, during the QOFR, QIOFR, QIFP and the Quad Extended Fast Program (QIEFP) instructions, the Hold (Reset) / DQ3 is used as an input/output (DQ3 functionality). In QIO-SPI, the Hold (Reset) / DQ3 pin acts as an I/O (DQ3 functionality), and the HOLD (Reset) functionality disabled when the device is selected. When the device is deselected (S signal is high), in parts with Reset functionality, it is possible to reset the device unless this functionality is not disabled by mean of dedicated registers bits. The HOLD (Reset) functionality can be disabled using bit 3 of the NVCR or bit 4 of the VECR.

Signal descriptions N25Q128 - 1.8 V

2.6 Write protect/enhanced program supply voltage (W/VPP),

W/VPP/DQ2 can be used as: „ A protection control input. „ A power supply pin. „ I/O in Extended SPI protocol quad instructions and in QIO-SPI protocol instructions. When the device is operated in Extended SPI protocol with single or dual instructions, the two functions W or VPP are selected by the voltage range applied to the pin. If the W/VPP input is kept in a low voltage range (0 V to VCC) the pin is seen as a control input. This input signal is used to freeze the size of the area of memory that is protected against program or erase instructions (as specified by the values in the BP[0:3] bits of the Status Register. (See Table 3.: Status register format). If VPP is in the range of VPPH, it acts as an additional power supply during the Program or Erase cycles (See Table 29.: Operating conditions). In this case VPP must be stable until the Program or Erase algorithm is completed. During the Extended SPI protocol, the QOFR and QIOFR instructions, and the QIO-SPI protocol instructions, the pin W /VPP/DQ2 is used as an input/output (DQ2 functionality). Using the Extended SPI protocol the QIFP, QIEFP and the QIO-SPI Program/Erase instructions, it is still possible to use the VPP additional power supply to speed up internal operations. However, to enable this possibility it is necessary to set bit 3 of the Volatile Enhanced Configuration Register to 0. In this case the W/VPP/DQ2 pin is used as an I/O pin until the end of the instruction sequence. After the last input data is shifted in, the application should apply VPP voltage to W/VPP/DQ2 within 200 ms to speed up the internal operations. If the VPP voltage is not applied within 200 ms the Program/Erase operations start with standard speed. The default value of the VECR bit 3 is 1, and the VPP functionality for Quad I/O modify instruction is disabled.

2.7 V CC supply voltage

VCC is the supply voltage.

2.8 V SS ground

VSS is the reference for the VCC supply voltage.

3 SPI Modes

output data is available from the falling edge of Serial Clock (C). Figure 5. Bus master and memory devices on the SPI bus

master leaves the SPI bus in high impedance. Figure 6. Extended SPI protocol example

N25Q128 - 1.8 V SPI Protocols

4 SPI Protocols

The N25Q128 memory can work with 3 different Serial protocols: „ Extended SPI protocol. „ Dual I/O SPI (DIO-SPI) protocol. „ Quad I/O SPI (QIO-SPI) protocol. It is possible to choose among the three protocols by means of user volatile or non-volatile configuration bits.It's not possible to mix Extended SPI, DIO-SPI, and QIO-SPI protocols. The device can operate in XIP mode in all 3 protocols.

4.1 Extended SPI protocol

This is an extension of the standard (legacy) SPI protocol. Instructions are transmitted on a single data line (DQ0), while addresses and data are transmitted by one, two or four data lines (DQ0, DQ1, W /VPP(DQ2) and HOLD / (DQ3) according to the instruction. When used in the Extended SPI protocol, these devices can be driven by a micro controller in either of the two following modes: „ CPOL=0, CPHA=0 „ CPOL=1, CPHA=1 Please refer to the SPI modes for a detailed description of these two modes

4.2 Dual I/O SPI (DIO-SPI) protocol

Dual I/O SPI (DIO-SPI) protocol: instructions, addresses and I/O data are always transmitted on two data lines (DQ0 and DQ1). Also when in DIO-SPI mode, the device can be driven by a micro controller in either of the two following modes: „ CPOL= 0, CPHA= 0 „ CPOL= 1, CPHA= 1 Please refer to the SPI modes for a detailed description of these two modes. Note: Extended SPI protocol Dual I/O instructions allow only address and data to be transmitted over two data lines. However, DIO-SPI allows instructions, addresses, and data to be transmitted on two data lines. This mode can be set using two ways „ Volatile: by setting bit 6 of the VECR to 0. The device enters DIO-SPI protocol immediately after the Write Enhanced Volatile Configuration Register sequence completes. The device returns to the default working mode (defined by NVCR) on power on. „ Default/ Non-Volatile: This is default mode on power-up. By setting bit 2 of the NVCR to 0. The device enters DIO-SPI protocol on the subsequent power-on. After all subsequent power-on sequences, the device still starts in DIO-SPI protocol unless bit 2 of NVCR is set to 1 (default value, corresponding to Extended SPI protocol) or bit 3 of NVCR is set to 0 (corresponding to QIO-SPI protocol).

SPI Protocols N25Q128 - 1.8 V

4.3 Quad SPI (QIO-SPI) protocol

Quad SPI (QIO-SPI) protocol: instructions, addresses, and I/O data are always transmitted on four data lines DQ0, DQ1, W/VPP(DQ2), and HOLD / (DQ3). The exception is the Program/Erase cycle performed with the VPP , in which case the device temporarily goes to Extended SPI protocol. Going temporarily into Extended SPI protocol allows the application either to: „ check the polling bits: WIP bit in the Status Register or Program/Erase Controller bit in the Flag Status Register „ perform Program/Erase suspend functions. Note: As soon as the VPP pin voltag e goes low, the protocol returns to the QIO-SPI protocol. In QIO-SPI protocol the W and HOLD/ (RESET) functionality is disabled when the device is selected (S signal low). When used in the QIO-SPI mode, these devices can be driven by a micro controller in either of the two following modes: „ CPOL=0, CPHA=0 „ CPOL=1, CPHA=1 Please refer to the SPI modes for a detailed description of the 2 modes. Note: In the Extended SPI protocol only Address and data are allowed to be transmitted on 4 data lines, However in QIO-SPI protocol, the address, data and instructions are transmitted across 4 data lines. This working mode is set in either bit 7 of the Volatile Enhanced Configuration Register (VECR) or in bit 3 of the Non Volatile Configuration Register (NVCR). This mode can be set using two ways „ Volatile: by setting bit 7 of the VECR to 0, the device enters QIO-SPI protocol immediately after the Write Enhanced Volatile Configuration Register sequence completes. The device returns to the default working protocol (defined by the NVCR) on the next power on. „ Default/ Non- Volatile: This is default protocol on power up. By setting bit 3 of the NVCR to 0, the device enters QIO-SPI protocol on the subsequent power-on. After all subsequent power-on sequences, the device still starts in QIO-SPI protocol unless bit 3 of the NVCR is set to 1 (default value, corresponding to Extended SPI mode).

N25Q128 - 1.8 V Operating features

5 Operating features

5.1 Extended SPI Protoc ol Operating features

5.1.1 Read Operations

To read the memory content in Extended SPI protocol different instructions are available: READ, Fast Read, Dual Output Fast Read, Dual Input Output Fast Read, Quad Output Fast Read and Quad Input Output Fast read, allowing the application to choose an instruction to send addresses and receive data by one, two or four data lines. Note: In the Extended SPI protocol the instruction co de is always sent on one data line (DQ0): to use two or four data lines the user must use either the DIO-SPI or the QIO-SPI protocol respectively. For fast read instructions the number of dummy clock cycles is configurable by using VCR bits [7:4] or NVCR bits [15:12]. After a successful reading instruction a reduced tSHSL equal to 20 ns is allowed to further improve random access time (in all the other cases tSHSL should be at least 50 ns). See Table 33.: AC Characteristics.

5.1.2 Page programming

To program one data byte, two instructions are required: write enable (WREN), which is one byte, and a page program (PP) sequence, which consists of four bytes plus data. This is followed by the internal program cycle (of duration tPP). To spread this overhead, the page program (PP) instruction allows up to 256 bytes to be programmed at a time (changing bits from ‘1’ to ‘0’), provided that they lie in consecutive addresses on the same page of memory. For optimized timings, it is recommended to use the page program (PP) instruction to program all consecutive targeted bytes in a single sequence versus using several page program (PP) sequences with each containing only a few bytes (see Section 5.2.3: Page programming and Table 33: AC Characteristics).

5.1.3 Dual input fast program

The dual input fast program (DIFP) instruction makes it possible to program up to 256 bytes using two input pins at the same time (by changing bits from ‘1’ to ‘0’). For optimized timings, it is recommended to use the DIFP instruction to program all consecutive targeted bytes in a single sequence rather using several DIFP sequences each containing only a few bytes (see Section 9.1.12: Dual Input Fast Program (DIFP)).

5.1.4 Dual Input Extended Fast Program

The Dual Input Extended Fast Program (DIEFP) instruction is an enhanced version of the Dual Input Fast Program instruction, allowing to transmit address across two data lines. For optimized timings, it is recommended to use the DIEFP instruction to program all consecutive targeted bytes in a single sequence rather than using several DIEFP sequences, each containing only a few bytes.

Operating features N25Q128 - 1.8 V

5.1.5 Quad Input Fast Program

The Quad Input Fast Program (QIFP) instruction makes it possible to program up to 256 bytes using 4 input pins at the same time (by changing bits from 1 to 0). For optimized timings, it is recommended to use the QIFP instruction to program all consecutive targeted bytes in a single sequence rather than using several QIFP sequences each containing only a few bytes.

5.1.6 Quad Input Ex tended Fast Program

The Quad Input Extended Fast Program (QIEFP) instruction is an enhanced version of the Quad Input Fast Program instruction, allowing parallel input on the 4 input pins, including the address being sent to the device. For optimized timings, it is recommended to use the QIEFP instruction to program all consecutive targeted bytes in a single sequence rather than using several QIEFP sequences each containing only a few bytes.

5.1.7 Subsector erase, se ctor erase and bulk erase

The page program (PP) instruction allows bits to be reset from ‘1’ to’0’. In order to do this the bytes of memory need to be erased to all 1s (FFh). This can be achieved as follows: „ a subsector at a time, using the subsector erase (SSE) instruction (only available on the 8 boot sectors at the bottom or top addressable area of a device with a dedicated part number); See Section 16: Ordering information; „ a sector at a time, using the sector erase (SE) instruction; „ throughout the entire memory, using the bulk erase (BE) instruction. This starts an internal erase cycle (of duration tSSE, tSE or tBE). The erase instruction must be preceded by a write enable (WREN) instruction.

5.1.8 Polling during a write, program or erase cycle

A further improvement in the time to Write Status Register (WRSR), POTP, PP, DIFP,DIEFP ,QIFP, QIEFP or Erase (SSE, SE or BE) can be achieved by not waiting for the worst case delay (tW, tPP , tSSE, tSE, or tBE). The application program can monitor if the required internal operation is completed, by polling the dedicated register bits to establish when the previous Write, Program or Erase cycle is complete. The information on the memory being in progress for a Program, Erase, or Write instruction can be checked either on the Write In Progress (WIP) bit of the Status Register or in the Program/Erase Controller bit of the Flag Status Register. Note: The Program/Erase Controller bit is the opposite state of the WIP bit in the Status Register. In the Flag Status Register additional information can be checked, as eventual Program/Erase failures by mean of the Program or erase Error bits.

5.1.9 Active power and standby power modes

When Chip Select (S) is Low, the device is selected, and in the active power mode.

5.1.10 Hold (or Reset) condition

write status register, program or erase cycle that is currently in progress. Serial Clock (C) is Low (as shown in Figure 7). Low (this is shown in Figure 7). input (DQ0) and Serial Clock (C) are don’t care. from the moment of entering the hold condition. the device from going back to the hold condition. Figure 7. Hold condition activation Section 16: Ordering information. the lock bits are reset to 0 after a Reset Low pulse.

Table 2. Device Status after Reset Low Pulse Note: 1 S remains Low while Reset is Low. (DQ3 functionality) during Quad Instructions: QOFR, QIOFR,QIFP and QIEFP. The Hold/Reset feature can be disabled by using of the bit 4 of the VECR.

N25Q128 - 1.8 V Operating features

5.2 Dual SPI (DIO-SPI) Protocol

In the Dual SPI (DIO-SPI) protocol all the instructions, addresses and I/O data are transmitted on two data lines. All the functionality available in the Extended SPI protocol is also available in the DIO-SPI protocol. The DIO-SPI instructions are comparable with the Extended SPI instructions; however, in DIO-SPI, the instructions are multiplexed on the two data lines, DQ0 and DQ1. The only exceptions are the READ, Quad Read, and Program instructions, which are not available in DIO-SPI protocol, and the RDID instruction, which is replaced in the DIO-SPI protocol by the Multiple I/O Read Identification (MIORDID) instruction. The Multiple I/O Read Identification Instruction reads just the standard SPI electronic ID (3 bytes), while the Extended SPI protocol RDID instruction allows access to the UID bytes. To help the application code port from Extended SPI to DIO-SPI protocol, the instructions available in the DIO-SPI protocol have the same operation code as the Extended SPI protocol, the only exception being the MIORDID instruction.

5.2.1 Multiple Read Identification

The Multiple I/O Read Identification (MIORDID) instruction is available to read the device electronic ID.With respect to the RDID instruction of the Extended SPI protocol, the output data, shifted out on the 2 data lines DQ0 and DQ1. Since the read ID instruction in the DIO-SPI protocol is limited to 3 bytes of the standard electronic ID, the UID bytes are not read with the MIORDID instruction

5.2.2 Dual Command Fast reading

Reading the memory data multiplexing the instruction, the addresses and the output data on 2 data lines can be achieved in DIO-SPI protocol by mean of the Dual Command Fast Read instruction, that has 3 instruction codes (BBh, 3Bh and 0Bh) to help the application code porting from Extended SPI protocol to DIO-SPI protocol. Of course quad and single I/O Read instructions are not available in DIO-SPI mode. For Dual Command fast read instructions the number of dummy clock cycles is configurable by using VCR bits [7:4] or NVCR bits [15:12]. After a successful reading instruction, a reduced tSHSL equal to 20ns is allowed to further improve random access time (in all the other cases tSHSL should be at least 50 ns). See Table 33.: AC Characteristics.

5.2.3 Page programming

Programming the memory by transmitting the instruction, addresses and the output data on 2 data lines can be achieved in DIO-SPI protocol by using the Dual Command Page Program instruction, that has 3 instruction codes (D2h, A2h and 02h) to help port from Extended SPI protocol to DIO-SPI protocol Quad and single input Program instructions are not available in DIO-SPI mode.

Operating features N25Q128 - 1.8 V The DIO-SPI protocol is similar to the Extended SPI protocol i.e., to program one data byte two instructions are required: „ Write Enable (WREN), which is one byte, and a „ Dual Command Page Program (DCPP) sequence, which consists of four bytes plus data. This is followed by the internal Program cycle (of duration tPP). To spread this overhead, the Dual Command Page Program (DCPP) instruction allows up to 256 bytes to be programmed at a time (changing bits from 1 to 0), provided that they are consecutive addresses on the same page of memory. For optimized timings, it is recommended to use the DCPP instruction to program all consecutive targeted bytes in a single sequence versus using several DCPP sequences with each containing only a few bytes. See Table 33.: AC Characteristics.

5.2.4 Subsector Erase, Sect or Erase and Bulk Erase

Similar to the Extended SPI protocol, in the DIO-SPI protocol to erase the memory bytes to all 1s (FFh) the Subsector Erase (SSE), the Sector Erase (SE) and the Bulk Erase (BE) instructions are available. These instructions start an internal Erase cycle (of duration tSSE, tSE or tBE). The Erase instruction must be preceded by a Write Enable (WREN) instruction. Subsector Erase is only available on the 8 Bottom (Top) boot sectors, and is not available in uniform architecture parts

5.2.5 Polling during a Write, Program or Erase cycle

Similar to the Extended SPI protocol, in the DIO-SPI protocol it is possible to monitor if the internal write, program or erase operation is completed, by polling the dedicated register bits by using the Read Status Register (RDSR) or Read Flag Status Register (RFSR) instructions, the only obvious difference is that instruction codes, addresses and output data are transmitted across two data lines.

5.2.6 Read and Modify registers

Similar to the Extended SPI protocol, the only obvious difference is that instruction codes, addresses and output data are transmitted across two data lines

5.2.7 Active Power and Standby Power modes

Similar to the Extended SPI protocol, when Chip Select (S) is Low, the device is selected, and in the Active Power mode. When Chip Select (S) is High, the device is deselected, but could remain in the Active Power mode until all internal cycles have completed (Program, Erase, Write Cycles). The device then goes in to the Standby Power mode. The device consumption drops to ICC1.

5.2.8 HOLD (or Reset) condition

The HOLD (or Reset i.e. for parts having the reset functionality instead of hold pin) signal has exactly the same behavior in DIO-SPI protocol as do in Extended SPI protocol, so please refer to section 5.1.10, Hold (or Reset) condition” in the Extend SPI protocol section for further details.

N25Q128 - 1.8 V Operating features

5.3 Quad SPI (QIO-SPI)Protocol

In the Quad SPI (QIO-SPI) protocol all the Instructions, addresses and I/O data are transmitted on four data lines, with the exception of the polling instructions performed during a Program or Erase cycle performed with VPP, in this case the device temporarily goes in Extended SPI protocol. The protocol again becomes QIO-SPI as soon as the VPP voltage goes low. All the functionality available in the Extended SPI protocol are also available in the QIO-SPI mode, with equivalent instruction transmitted on the 4 data lines DQ0, DQ1, DQ2 and DQ3. The exceptions are the READ, Dual Read and Dual Program instructions, that are not available in QIO-SPI protocol, and the RDID instruction, that is replaced in the QIO-SPI protocol by the Multiple I/O Read Identification (MIORDID) instruction. The Multiple I/O Read Instruction reads just the standard SPI electronic ID (3 bytes), while with the Extended SPI protocol RDID instruction is possible to access also the UID bytes. To help the application code port from Extended SPI to QIO-SPI protocol, the instructions available in the QIO-SPI protocol have the same operation code as in the Extended SPI protocol, the only exception is the MIORDID instruction.

5.3.1 Multiple Read Identification

The Multiple I/O Read Identification (MIORDID) instruction is available to read the device electronic ID. With respect to the RDID instruction of the Extended SPI protocol, the output data, shifted out on the 4 data lines DQ0, DQ1, DQ2 and DQ3. Since in the QIO-SPI protocol the Read ID instruction is limited to 3 bytes of the standard electronic ID, the UID bytes are not read with the MIORDID instruction.

5.3.2 Quad Command Fast reading

The Array Data can be read by the Quad Command Fast Read instruction using 3 instructions (EBh, 6Bh and 0Bh) to help the application code port from Extended SPI protocol to DIO-SPI protocol. The instruction, address and output data are transmitted across 4 data lines. The Dual and Single I/O Read instructions are not available in QIO-SPI protocol.

5.3.3 QUAD Command Page programming

The memory can be programmed in QIO-SPI protocol by the Quad Command Page Program instruction using (02h, 12h and 32h). The instruction, address and input data are transmitted across 4 data lines The Dual and Single I/O Program instructions are not available in QIO-SPI protocol Programming the memory by multiplexing the instruction, the addresses and the output data on 4 wires can be achieved in QIO-SPI protocol by mean of the Quad Command Page Program instruction, that has 3 instruction codes (02h, 12h and 32h) to help the application code porting from Extended SPI protocol to QIO-SPI protocol. Similar to the Extended SPI protocol in the QIO-SPI protocol, to program one data byte two instructions are required: „ Write Enable (WREN), which is one byte, and „ Quad Command Page Program (QCPP) sequence, which consists of instruction (one byte), address (3 bytes) and input data.

Operating features N25Q128 - 1.8 V This is followed by the internal Program cycle (of duration tPP). To spread this overhead, the Quad Command Page Program (QCPP) instruction allows up to 256 bytes to be programmed at a time (changing bits from 1 to 0), provided that they are in consecutive addresses on the same page of memory. For optimized timings, it is recommended to use the QCPP instruction to program all consecutive targeted bytes in a single sequence versus using several QCPP sequences with each containing only a few bytes. See Table 33.: AC Characteristics. The QCPP instruction is transmitted across 4 data lines except when VPP is raised to VPPH. The VPP can be raised to VPPH to decrease programming time (provided that the bit 3 of the VECR has been set to 0 in advance). When bit 3 of VECR is set to 0 after the Quad Command Page Program instruction sequence has been received, the memory temporarily goes in Extended SPI protocol, and is possible to perform polling instructions (checking the WIP bit of the Status Register or the Program/Erase Controller bit of the Flag Status Register) or Program/Erase Suspend instruction even if DQ2 is temporarily used in this VPP functionality. The memory automatically comes back in QIO-SPI protocol as soon as the VPP pin goes Low.

5.3.4 Subsector Erase, Sect or Erase and Bulk Erase

Similar to the Extended SPI protocol, Subsector Erase (SSE)(1), the Sector Erase (SE) and the Bulk Erase (BE) instructions are used to erase the memory in the QIO-SPI protocol. These instructions start an internal Erase cycle (of duration tSSE, tSE or tBE). The Erase instruction must be preceded by a Write Enable (WREN) instruction. The erase instructions are transmitted across 4 data lines unless the VPP is raised to VPPH. The VPP can be raised to VPPH to decrease erasing time, provided that the bit 3 of the VECR has been set to 0 in advance. In this case, after the erase instruction sequence has been received, the memory temporarily goes in extended SPI protocol, and it is possible to perform polling instructions (checking the WIP bit of the Status Register or the Program/Erase Controller bit of the Flag Status Register) or Program/Erase Suspend instruction even if DQ2 is temporarily used in this VPP functionality. The memory automatically comes back in QIO-SPI protocol as soon as the VPP pin goes Low. Note: Subsector Erase is only available on the 8 Bottom (Top) boot sectors, and is not available in uniform architecture parts

5.3.5 Polling during a Write, Program or Erase cycle

It is possible to check if the internal write, program or erase operation is completed, by polling the dedicated register bits of the Read Status Register (RDSR) or Read Flag Status Register (FSR). When the Program or Erase cycle is performed with the VPP, the device temporarily goes in single I/O SPI mode. The protocol became again QIO-SPI as soon as the VPP pin voltage goes low.

N25Q128 - 1.8 V Operating features

5.3.6 Read and Modify registers

The read and modify register instructions are available and behave in QIO-SPI protocol exactly as they do in Extended SPI protocol, the only difference is that instruction codes, addresses and output data are transmitted across 4 data lines.

5.3.7 Active Power and Standby Power modes

Exactly as in Extended SPI protocol, when Chip Select (S) is Low, the device is selected, and in the Active Power mode. When Chip Select (S) is High, the device is deselected, but could remain in the Active Power mode until all internal (Program, Erase, Write) Cycles have completed. The device then goes in to the Standby Power mode. The device consumption drops to ICC1.

5.3.8 HOLD (or Reset) condition

The HOLD (Hold) feature (or Reset feature, for parts having the reset functionality instead of hold) is disabled in QIO-SPI protocol when the device is selected: the Hold (or Reset)/ DQ3 pin always behaves as an I/O pin (DQ3 function) when the device is deselected. For parts with reset functionality, it is still possible to reset the memory when it is deselected (C signal high).

5.3.9 VPP pin Enhanced Supply Voltage feature

It is possible in the QIO-SPI protocol to use the VPP pin as an enhanced supply voltage, but the intention to use VPP as accelerated supply voltage must be declared by setting bit 3 of the VECR to 0. In this case, to accelerate the Program cycle the VPP pin must be raised to VPPH after the device has received the last data to be programmed within 200ms. If the VPP is not raised within 200ms, the program operation starts with the standard internal cycle speed as if the Vpp high voltage were not used, and a flag error appears on Flag Status Register bit 3".

Volatile and Non Volatile Registers N25Q128 - 1.8 V

6 Volatile and Non Volatile Registers

The device features many different registers to store, in volatile or non volatile mode, many parameters and operating configurations: „ Legacy SPI Status Register „ 3 configuration registers: – Non Volatile Configuratio n Register (NVCR), 16 bits – Volatile Configuration Register (VCR), 8 bits – Volatile Enhanced Configuration Register (VECR), 8 bits The Non Volatile Configuration Register (NVCR) affects the memory configuration starting from the successive power-on. It can be used to make the memory start in a determined condition. The VCR and VECR affect the memory configuration after every execution of the related Write Volatile configuration Register (WRVCR) and Write Enhanced Volatile Configuration register (WRVECR) instructions. These instructions overwrite the memory configuration set at POR by NVCR. As described in Figure 8.: Non Volatile and Volatile configuration Register Scheme, the working condition of the memory is set by an internal configuration register, which is not accessible by the user. The working parameters of the internal configuration register are loaded from the NVCR during the boot phase of the device. In this sense the NVCR can be seen as having the default settings of the memory. During the normal life of the application, every time a write volatile or enhanced volatile configuration register instruction is performed, the new configuration parameters set in the volatile registers are also copied in the internal configuration register, thus instantly affecting the memory behavior. Please note that on the next power on the memory will start again in the working protocol set by the Non Volatile Register parameters.

Figure 8. Non Volatile and Volatile configuration Register Scheme detecting possible errors or a Program/Erase internal cycle in progress. protocols (Extended SPI, DIO-SPI, and QIO-SPI). cycles. See Table 33.: AC Characteristics.

6.1 Legacy SPI Status Register

is available in all the 3 protocols (Extended SPI, DIO-SPI, and QIO-SPI).

6.1.1 WIP bit

Status Register, Program or Erase cycle. 0 indicates no cycle is in progress.

6.1.2 WEL bit

Program or Erase instruction is accepted.

6.1.3 BP3, BP2, BP1, BP0 bits

6.1.4 TB bit

(WRSR) instruction provided that the Write Enable (WREN) instruction has been issued. Table 3. Status register format

N25Q128 - 1.8 V Volatile and Non Volatile Registers The Top/Bottom (TB) bit is used in conjunction with the Block Protect (BP3, BP2, BP1, BP0) bits to determine if the protected area defined by the Block Protect bits starts from the top or the bottom of the memory array: „ When TB is reset to '0' (default value), the area protected by the Block Protect bits starts from the top of the memory array. „ When TB is set to '1', the area protected by the Block Protect bits starts from the bottom of the memory array. The TB bit cannot be written when the SRWD bit is set to '1' and the W pin is driven Low.

6.1.5 SRWD bit

The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write Protect (W/VPP) signal. The Status Register Write Disable (SRWD) bit and the Write Protect (W/VPP) signal allow the device to be put in the hardware protected mode (when the Status Register Write Disable (SRWD) bit is set to '1', and Write Protect ((W/VPP) is driven Low). In this mode, the non-volatile bits of the Status Register (TB, BP3, BP2, BP1, BP0) become read-only bits and the Write Status Register (WRSR) instruction is no longer accepted for execution.

6.2 Non Volatile Configuration Register

The Non Volatile Configuration Register (NVCR) bits affects the default memory configuration after power-on. It can be used to make the memory start in the configuration to fit the application requirements. The device is delivered with Non Volatile Configuration Register (NVCR) bits all erased to 1 (FFFFh). The purpose of the NVCR is to define the default memory settings after the power-on sequence related to many features: „ The number of dummy clock cycle for fast read instructions, „ XIP mode configurations, „ output driver strengths, „ fast POR sequence, „ Reset (or Hold) disabling „ Multiple I/O protocol enabling. The NVCR can be read by the Read Non Volatile Configuration Register (RDNVCR) instruction and written by the Write Non Volatile Configuration Register (WRNVCR) in all the 3 available SPI protocols. See the sections that follow as well as Table 4.: Non-Volatile Configuration Register.

Table 4. Non-Volatile Configuration Register

0000 As '1111'

000 XIP for SIO Read

001 XIP for DOFR

010 XIP for DIOFR

011 XIP for QOFR

100 XIP for QIOFR

111 XIP disabled (default)

6.2.1 Dummy clock cycle NV configurat ion bits (NVCR bits from 15 to 12)

the dummy clock cycle number) to optimize the fast read instructions performance. number is not sufficient for the operating frequency, the memory reads wrong data. Table 5. Maximum allowed frequency (MHz)

0 Enabled POR phase < 100us only read available

1 Disabled (default) POR phase ~ 700us all instructions

1. All values are guaranteed by characterization and not 100% tested in production.

Volatile and Non Volatile Registers N25Q128 - 1.8 V

6.2.2 XIP NV configuration bits (NVCR bits from 11 to 9)

The bits from 11 to 9 of the Non Volatile Configuration register store the default settings for the XIP operation, allowing the memory to start working directly on the required XIP mode after successive POR sequence: the device then accepts only address on one, two, or four wires (skipping the instruction) depending on the NVCR XIP bits settings. The default settings for the XIP bits of the NVCR enable the memory to start working in Extended SPI mode after the POR sequence (XIP directly after POR is disabled).

6.2.3 Output Driver Strengt h NV configuration bits (NVCR bits from 8 to 6)

The bits from 8 to 6 of the Non Volatile Configuration register store the default settings for the output driver strength, enabling to optimize the impedance at Vcc/2 output voltage for the specific application. The default values of Output Driver Strength bits of the NVCR set the output impedance at Vcc/2 equal to 30 Ohms.

6.2.4 Fast POR NV confi guration bit (NVCR bit 5)

The bit 5 of the NVCR enables the FAST POR sequence to speed up the application boot phase before the first READ instruction: if enabled, the FAST POR allows to perform the first read operation after less than 100us. Please note that this timing is valid only for the reading operations: if a modify instruction is then required, after the first WREN instruction the complete POR phase will be performed, resulting in latency time between the WREN and the receiving of the modify instruction (~500us). During this latency time, when the power on second phase is running, no instruction will be accepted except the standard polling instructions either on the Flag Status register or in the Status Register. The default values of Fast POR bit of the NVCR is set to disable the Fast POR feature, in this case the POR sequence requires the standard value of ~500us and after the first WREN instruction no relevant latency time is needed.

6.2.5 Hold (Reset) disable NV configuration bit (NVCR bit 4)

The Hold (RESET) disable bit can be used to disable the Hold (Reset) functionality of the Hold (Reset) / DQ3 pin as described in Table 4.: Non-Volatile Configuration Register. This feature can be useful to avoid accidental Hold or Reset condition entries in applications that never require the Hold (Reset) functionality. The default values of Hold (Reset) bit of the NVCR is set to enable the Hold (Reset) functionality. Note: Reset functionality is available instead of Hold in devices with a dedicated part number. See Section 16: Ordering information.

6.2.6 Quad Input NV conf iguration bit (NVCR bit 3)

The Quad Input NV configuration bit can be used to make the memory start working in QIO- SPI protocol directly after the power on sequence. The products are delivered with this set to 1, making the memory default in Extended SPI protocol, if the application sets this bit to 0 the device will enter in QIO-SPI protocol right after the next power on. Please note that in case both QIO-SPI and DIO-SPI are enabled (both bit 3 and bit 2 of the Non Volatile Configuration Register set to 0), the memory will work in QIO-SPI.

N25Q128 - 1.8 V Volatile and Non Volatile Registers

6.2.7 Dual Input NV conf iguration bit (NVCR bit 2)

The Dual Input NV configuration bit can be used to make the memory start working in DIO- SPI protocol directly after the power on sequence. The products are delivered with this set to 1, making the memory default in Extended SPI protocol, if the application sets this bit to 0 the device will enter in QIO-SPI protocol right after the next power on. Please note that in case both QIO-SPI and DIO-SPI are enabled (both bit 3 and bit 2 of the Non Volatile Configuration Register set to 0), the memory will work in QIO-SPI.

6.3 Volatile Configuration Register

The Volatile Configuration Register (VCR) affects the memory configuration after every execution of Write Volatile Configuration Register (WRVCR) instruction: this instruction overwrite the memory configuration set at POR by the Non Volatile Configuration Register (NVCR). Its purpose is to define the dummy clock cycles number and to make the device ready to enter in the required XIP mode.

6.3.1 Dummy clock cycle Vola tile Configurations bits (VCR bits from 7 to 4)

the fast read instructions performance. Table 6. Volatile Configuration Register

0 Ready to enter XIP mode To make the data on DQ0 during the first

1 XIP disabled (default)

N25Q128 - 1.8 V Volatile and Non Volatile Registers

6.3.2 XIP Volatile Confi guration bits (VCR bit 3)

The bit 3 of the Volatile Configuration Register is the XIP enabling bit, this bit must be set to 0 to enable the memory working on XIP mode. For devices with a feature set digit equal to 2 or 4 in the part number (Basic XiP), this bit is always Don't Care, and it is possible to operate the memory in XIP mode without setting it to 0. See Section 16: Ordering information.

6.4 Volatile Enhanced Configuration Register

The Volatile Enhanced Configuration Register (VECR) affects the memory configuration after every execution of Write Volatile Enhanced Configuration Register (WRVECR) instruction: this instruction overwrite the memory configuration set during the POR sequence by the Non Volatile Configuration Register (NVCR). Its purpose is: „ enabling of QIO-SPI protocol and DIO-SPI protocol Warning: WARNING: in case of both QIO-SPI and DIO-SPI enabled, the memory works in QIO-SPI „ HOLD (Reset) functionality disabling „ To enable the VPP functionality in Quad I/O modify operations „ To define output driver strength (3 bit)

6.4.1 Quad Input Command VECR<7>

0 (in this case the memory start working in DIO-SPI mode). VECR set to 0), the memory will work in QIO-SPI.

6.4.2 Dual Input Command VECR<6>

VECR are set to 0), the memory will work in QIO-SPI. Table 7. Volatile Enhanced Configuration Register

0 Enabled

1 Disabled (default)

0 Disabled

1 Enabled (default)

0 Enabled The bit must be considered in case of

N25Q128 - 1.8 V Volatile and Non Volatile Registers

6.4.3 Reset/Hold disable VECR<4>

The Hold (RESET) disable bit can be used to disable the Hold (Reset) functionality of the Hold (Reset) / DQ3 pin right after the Write Volatile Enhanced Configuration Register (WVECR) instruction. This feature can be useful to avoid accidental Hold or Reset condition entries in applications that never require the Hold (Reset) functionality. If this bit is set to 0 the Hold (Reset) functionality is disabled, it is possible to enable it back by setting this bit to Please note that after the next power on the Hold (Reset) functionality will be enabled again unless the bit 4 of the Non Volatile Configuration Register is set to 0. Note: Reset functionality is available instead of Hold in devices with a dedicated part number. See Section 16: Ordering information.

6.4.4 Accelerator pin enable: QIO- SPI protocol / QIFP/QIEFP VECR<3>

The bit 3 of the Volatile Enhanced Configuration Register determines whether it is possible to use the Vpp accelerating voltage to speed up the internal modify operation with the Quad program and erase instructions (both in Extended or QIO-SPI protocols). To use the Vpp voltage with the Quad I/O modify instructions, this bit must be set to 0. The default value is 1, in which case the Vpp pin functionality is disabled in all Quad I/O operations: both in Extended SPI and QIO-SPI protocols. If the Volatile Enhanced Configuration Register bit 3 is set to 0, using the QIO-SPI protocol, after a Quad Command Page Program instruction or an Erase instruction is received (with all input data in the Program case) and the memory is de-selected, the protocol temporarily switches to Extended SPI protocol until Vpp passes from Vpph to normal I/O value (this transition is mandatory to come back to QIO-SPI protocol), to enable the possibility to perform polling instructions (to check if the internal modify cycle is finished by means of the WIP bit of the Status Register or of the Program/Erase controller bit of the Flag Status register) or Program/Erase Suspend instruction even if the DQ2 pin is temporarily used in his Vpp functionality. If the Volatile Enhanced Configuration Register bit 3 is set to 0, after any quad modify instruction (both in Extended SPI protocol and QIO-SPI protocol), there is a maximum allowed time-out of 200 ms after the last instruction input is received and the memory is de- selected to raise the Vpp signal to Vpph; otherwise, the modify instruction starts at normal speed, without the Vpph enhancement, and a flag error appears on Flag Status Register bit

6.4.5 Output Driver Strength VECR<2:0>

The bits from 2 to 0 of the VECR set the value of the output driver strength, enabling to optimize the impedance at Vcc/2 output voltage for the specific application as described in Table 7.: Volatile Enhanced Configuration Register. The default values of Output Driver Strength is set by the dedicated bits of the Non Volatile Configuration Register (NVCR), the parts are delivered with the output impedance at Vcc/2 equal to 30 Ohms.

Volatile and Non Volatile Registers N25Q128 - 1.8 V

6.5 Flag Status Register

The Flag Status Register is a powerful tool to investigate the status of the device, checking information regarding what is actually doing the memory and detecting possible error conditions. The Flag status register is composed by 8 bit.Three bits (Program/Erase Controller bit, Erase Suspend bit and Program Suspend bit) are a “Status Indicator bit”, they are set and reset automatically by the memory. Four bits (Erase error bit, Program error bit, VPP 1 to 0 error bit and Protection error bit) are “Error Indicators bits”, they are set by the memory when some program or erase operation fails or the user tries to perform a forbidden operation. The user can clear the Error Indicators bits by mean of the Clear Flag Status Register (CLFSR) instruction. All the Flag Status Register bits can be read by mean of the Read Status Register (RFSR) instruction.

6.5.1 P/E Controll er Status bit

device is ready to process a new command. finished, both on the Flag Status register bit 7 or on WIP bit of the Status Register.

6.5.2 Erase Suspend Status bit

that an Erase operation has been suspended or is going to be suspended. complete the operation before entering the Suspend Mode.

6.5.3 Erase Status bit

failure or a protection error when an erase operation is issued. failed to verify that it has correctly erased. The Erase Status bit should be read once the P/E Controller Status bit is High. Table 8. Flag Status Register

7 P/E Controller (not WIP) Status

6 Erase Suspend Status

5 Erase Error

4 Program Error

3 VPP Error

2 Program Suspend Status

1 Protection Error

0 RESERVED

Volatile and Non Volatile Registers N25Q128 - 1.8 V The Erase Status bit is related to all possible erase operations: Sector Erase, Sub Sector Erase, and Bulk Erase in all the three available protocols (SPI, DIO-SPI and QIO-SPI). Once the bit 5 is set High, it can only be reset Low (FSR<5>=0) by a Clear Flag Status Register command (CLFSR). If set High it should be reset before a new Erase command is issued; otherwise the new command will appear to fail.

6.5.4 Program Status bit

The bit 4 of the Flag Status Register represents the Program Status bit. It indicates: „ a Program failure „ an attempt to program a '1' on '0' when VPP=VPPH (only when the pattern is a multiple of 64 bits, otherwise this bit is "Don't care"). „ a protection error when a program is issued When the Program Status bit is High (FSR<4>=1) after a Program failure that means that the P/E Controller has applied the maximum pulses number to the bytes and it still failed to verify that the required data have been correctly programmed. After an attempt to program '1' on '0', the FSR<4> only goes High (FSR<4>=1) if VPP=VPPH and the data pattern is a multiple of 64 bits: if VPP is not VPPH, FSR<4> remains Low and the attempt is not shown while if VPP is equal to VPPh but the pattern is not a 64 bits multiple the bit 4 is Don't Care. The Program Status bit should be read once the P/E Controller Status bit is High. The Program Status bit is related to all possible program operations in the Extended SPI protocol: Page Program, Dual and Quad Input Fast Program, Dual and Quad Input Extended Fast Program, and OTP Program. The Program Status bit is related to the following program operations in the DIO-SPI and QIO-SPI protocols: Dual and Quad Command Page program and OTP program. Once the bit is set High, it can only be reset Low (FSR<4>=0) by a Clear Flag Status Register command (CLFSR). If set High it should be reset before a new Program command is issued, otherwise the new command will appear to fail.

6.5.5 VPP Status bit

The bit 3 of the Flag Status Register represents the VPP Status bit. It indicates an invalid voltage on the VPP pin during Program and Erase operations. The VPP pin is sampled at the beginning of a Program or Erase operation. If VPP becomes invalid during an operation, that is the voltage on VPP pin is below the VPPH Voltage (9V), the VPP Status bit goes High (FSR<3>=1) and indeterminate results can occur. Once set High, the VPP Status bit can only be reset Low (FSR<3>=0) by a Clear Flag Status Register command (CLFSR). If set High it should be reset before a new Program or Erase command is issued, otherwise the new command will appear to fail.

6.5.6 Program Suspend Status bit

The bit 2 of the Flag Status register represents the Program Suspend Status bit, It indicates that an Program operation has been suspended or is going to be suspended.

N25Q128 - 1.8 V Volatile and Non Volatile Registers The bit is set (FSR<2>=1) within the Erase Suspend Latency time, that is as soon as the Program/Erase Suspend command (PES) has been issued, therefore the device may still complete the operation before entering the Suspend Mode. The Program Suspend Status should be considered valid when the P/E Controller bit is high (FSR<7>=1). When a Program/Erase Resume command (PER) is issued the Program Suspend Status bit returns Low (FSR<2>=0)

6.5.7 Protection Status bit

The bit 1 of the Flag Status Register represents the Protection Status bit. It indicates that an Erase or Program operation has tried to modify the contents of a protected array sector, or that a modify operation has tried to access to a locked OTP space. The Protection Status bit is related to all possible protection violations as follows: „ The sector is protected by Software Protection Mode 1 (SPM1) Lock registers, „ The sector is protected by Software Protection Mode 2 (SPM2) Block Protect Bits (standard SPI Status Register), „ An attempt to program OTP when locked, „ A Write Status Register command (WRSR) on STD SPI Status Register when locked by the SRWD bit in conjunction with the Write Protect (W/VPP) signal (Hardware Protection Mode). Once set High, the Protection Status bit can only be reset Low (FSR<1>=0) by a Clear Flag Status Register command (CLFSR). If set High it should be reset before a new command is issued, otherwise the new command will appear to fail.

Protection modes N25Q128 - 1.8 V

7 Protection modes

There are protocol-related and specific hardware and software protection modes. They are described below.

7.1 SPI Protocol-related protections

This applies to all three protocols. The environments where non-volatile memory devices are used can be very noisy. No SPI device can operate correctly in the presence of excessive noise. To help combat this, the N25Q128 features the following data protection mechanisms: „ Power On Reset and an internal timer (tPUW) can provide protection against inadvertent changes while the power supply is outside the operating specification. „ Program, Erase, and Write Status Register instructions are checked to ensure the instruction includes a number of clock pulses that is a multiple of a byte before they are accepted for execution. „ All instructions that modify data must be preceded by a Write Enable (WREN) instruction to set the Write Enable Latch (WEL) bit. This bit is returned to its reset state by the following events (in Extended SPI protocol mode): –P o w e r - u p – Write Disable (WRDI) instruction completion – Write Status Register (W RSR) instruction completion – Write to Lock Register (W RLR) instruction completion – Program OTP (POTP) instruction completion – Page Program (PP) instruction completion – Dual Input Fast Program (DIFP) instruction completion – Dual Input Extended Fast Program (DIEFP) instruction completion – Quad Input Fast Program (QIFP) instruction completion – Quad Input Extended Fast Progra m (QIEFP) instruction completion – Subsector Erase (SSE) instruction completion – Sector Erase (SE) instruction completion – Bulk Erase (BE) instruction completion This bit is also returned to its reset state after all the analogous events in DIO-SPI and QIO- SPI protocol modes.

7.2 Specific hardware and software protection

There are two software protected modes, SPM1 and SPM2, that can be combined to protect the memory array as required. The SPM2 can be locked by hardware with the help of the W input pin. SPM1 The first software protected mode (SPM1) is managed by specific Lock Registers assigned to each 64 Kbyte sector.

Write to Lock Register (WRLR) instructions. protected by the Lock Register, and may be modified. '0', the Write Lock and Lock Down bits can be changed. The definition of the Lock Register bits is given in Table 9: Lock Register out. only. See Section 16: Ordering information. BP2, BP1, BP0) and the Status Register Write Disable bit (SRWD) are protected. Table 9. Software protection truth table (Sectors 0 to 255, 64 Kbyte)

00 Sector unprotected from Program/Erase/Write operations, protection status

01 Sector protected from Program/Erase/Write operations, protection status

10 Sector unprotected from Program/Erase/Write operations. Sector protection status cannot be changed except by a power-up. 11 Sector protected from Program/Erase/Write operations. Sector protection status cannot be changed except by a power-up.

Table 10. Protected area sizes (TB bit = 0)

„ Uniform version, 64 KB uniform sectors without any boot sectors and subsectors. Table 11. Protected area sizes (TB bit = 1)

8 Memory organization

Erase is allowed on the 8 boot sectors (for devices with bottom or top architecture). Figure 9. Block diagram

256 Byte

64 OTP bytes

Table 12. Memory organization (uniform) (page 1 of 8)

255 FF0000 FFFFFF

254 FE0000 FEFFFF

253 FD0000 FDFFFF

252 FC0000 FCFFFF

251 FB0000 FBFFFF

250 FA0000 FAFFFF

249 F90000 F9FFFF

248 F80000 F8FFFF

247 F70000 F7FFFF

246 F60000 F6FFFF

245 F50000 F5FFFF

244 F40000 F4FFFF

243 F30000 F3FFFF

242 F20000 F2FFFF

241 F10000 F1FFFF

240 F00000 F0FFFF

239 EF0000 EFFFFF

238 EE0000 EEFFFF

237 ED0000 EDFFFF

236 EC0000 ECFFFF

235 EB0000 EBFFFF

234 EA0000 EAFFFF

233 E90000 E9FFFF

232 E80000 E8FFFF

231 E70000 E7FFFF

230 E60000 E6FFFF

229 E50000 E5FFFF

228 E40000 E4FFFF

227 E30000 E3FFFF

226 E20000 E2FFFF

225 E10000 E1FFFF

224 E00000 E0FFFF

223 DF0000 DFFFFF

222 DE0000 DEFFFF

221 DD0000 DDFFFF

220 DC0000 DCFFFF

219 DB0000 DBFFFF

218 DA0000 DAFFFF

217 D90000 D9FFFF

216 D80000 D8FFFF

215 D70000 D7FFFF

214 D60000 D6FFFF

213 D50000 D5FFFF

212 D40000 D4FFFF

211 D30000 D3FFFF

210 D20000 D2FFFF

209 D10000 D1FFFF

208 D00000 D0FFFF

207 CF0000 CFFFFF

206 CE0000 CEFFFF

205 CD0000 CDFFFF

204 CC0000 CCFFFF

203 CB0000 CBFFFF

202 CA0000 CAFFFF

201 C90000 C9FFFF

200 C80000 C8FFFF

199 C70000 C7FFFF

198 C60000 C6FFFF

197 C50000 C5FFFF

196 C40000 C4FFFF

195 C30000 C3FFFF

194 C20000 C2FFFF

193 C10000 C1FFFF

192 C00000 C0FFFF

191 BF0000 BFFFFF

190 BE0000 BEFFFF

189 BD0000 BDFFFF

188 BC0000 BCFFFF

187 BB0000 BBFFFF

Table 12. Memory organization (uniform) (page 2 of 8)

186 BA0000 BAFFFF

185 B90000 B9FFFF

184 B80000 B8FFFF

183 B70000 B7FFFF

182 B60000 B6FFFF

181 B50000 B5FFFF

180 B40000 B4FFFF

179 B30000 B3FFFF

178 B20000 B2FFFF

177 B10000 B1FFFF

176 B00000 B0FFFF

175 AF0000 AFFFFF

174 AE0000 AEFFFF

173 AD0000 ADFFFF

172 AC0000 ACFFFF

171 AB0000 ABFFFF

170 AA0000 AAFFFF

169 A90000 A9FFFF

168 A80000 A8FFFF

167 A70000 A7FFFF

166 A60000 A6FFFF

165 A50000 A5FFFF

164 A40000 A4FFFF

163 A30000 A3FFFF

162 A20000 A2FFFF

161 A10000 A1FFFF

160 A00000 A0FFFF

Table 12. Memory organization (uniform) (page 3 of 8)

Table 12. Memory organization (uniform) (page 4 of 8)

Table 12. Memory organization (uniform) (page 5 of 8)

Table 12. Memory organization (uniform) (page 6 of 8)

15 F0000 FFFFF

14 E0000 EFFFF

13 D0000 DFFFF

12 C0000 CFFFF

Table 12. Memory organization (uniform) (page 7 of 8)

11 B0000 BFFFF

10 A0000 AFFFF

Table 13. Memory organization (bottom) (page 1 of 9) Table 12. Memory organization (uniform) (page 8 of 8)

Table 13. Memory organization (bottom) (page 2 of 9)

Table 13. Memory organization (bottom) (page 3 of 9)

Table 13. Memory organization (bottom) (page 4 of 9)

Table 13. Memory organization (bottom) (page 5 of 9)

Table 13. Memory organization (bottom) (page 6 of 9)

Table 13. Memory organization (bottom) (page 7 of 9)

Table 13. Memory organization (bottom) (page 8 of 9)

15 F000 FFFF

00 F F F

Table 14. Memory organization (top)

127 FFF000 FFFFFF

112 FF0000 FF0FFF

111 FEF000 FEFFFF

96 FE0000 FE0FFF

95 FDF000 FDFFFF

80 FD0000 FD0FFF

79 FCF000 FCFFFF

64 FC0000 FC0FFF

63 FBF000 FBFFFF

48 FB0000 FB0FFF

47 FAF000 FAFFFF

32 FA0000 FA0FFF

31 F9F000 F9FFFF

16 F90000 F90FFF

15 F8F000 F8FFFF

0 F80000 F80FFF

Table 13. Memory organization (bottom) (page 9 of 9)

Instructions N25Q128 - 1.8 V

9 Instructions

The device can work in three different protocols: Extended SPI, DIO-SPI and QIO-SPI. Each protocol has a dedicated instruction set, and each instruction set features the same functionality: „ Read, program and erase the memory and the 64 byte OTP area, „ Suspend and resume the program or erase operations, „ Read and modify all the registers and to read the device ID: please note that in this case there is a small functionality difference among the single and the multiple I/O read ID instructions. See Section 9.2.1: Multiple I/O Read Identification protocol and Section 9.3.1: Multiple I/O Read Identification (MIORDID). The application can choose in every time of the device life which protocol to use by setting the dedicated bits either in the Non Volatile Configuration Register or the Volatile Enhanced Configuration Register. Note: In multiple SPI protocols, all instructions, addresses, and data are parallel on two lines (DIO- SPI protocol) or four lines (QIO-SPI protocol). All instructions, addresses and data are shifted in and out of the device, most significant bit first. Serial Data input(s) is (are) sampled on the first rising edge of Serial Clock (C) after Chip Select (S ) is driven Low. Then, the one-byte instruction code must be shifted in to the device, most significant bit first, on Serial Data input(s), each bit being latched on the rising edges of Serial Clock (C). Instruction code is shifted into the device just on DQ0 in Extended SPI protocol, on DQ0 and DQ1 in DIO-SPI protocol and on DQ0, DQ1, DQ2, and DQ3 in QIO-SPI protocol. In standard mode every instruction sequence starts with a one-byte instruction code. Depending on the instruction, this might be followed by address bytes, or by data bytes, or by both or none. In XIP modes only read operation and exit XIP mode can be performed, and to read the memory content no instructions code are needed: the device directly receives addresses and after a configurable number of dummy clock cycle it outputs the required data.

9.1 Extended SP I Instructions

In Extended SPI protocol instruction set the instruction code is always shifted into the device just on DQ0 pin, while depending on the instruction addresses and input/output data can run on single, two or four wires. In the case of a Read Instructions Data Bytes (READ), Read Data Bytes at Higher Speed (FAST_READ), Dual Output Fast Read (DOFR), Dual Input/Output Fast Read (DIOFR), Quad Output Fast Read (QOFR), Quad Input/Output Fast Read (QIOFR), Read OTP (ROTP), Read Lock Registers (RDLR), Read Status Register (RDSR), Read Flag Status Register (RFSR), Read NV Configuration Register (RDNVCR), Read Volatile Configuration Register (RDVCR), Read Volatile Enhanced Configuration Register (RDVECR) and Read Identification (RDID) instruction, the shifted-in instruction sequence is followed by a data-out sequence. Chip Select (S ) can be driven High after any bit of the data-out sequence is being shifted out.

N25Q128 - 1.8 V Instructions In the case of a Page Program (PP), Program OTP (POTP), Dual Input Fast Program (DIFP), Dual Input Extended Fast Program (DIEFP), Quad Input Fast Program (QIFP), Quad Input Extended Fast Program (QIEFP), Subsector Erase (SSE), Sector Erase (SE), Bulk Erase (BE), Write Status Register (WRSR), Clear Flag Status Register (CLFSR), Write to Lock Register (WRLR), Write Configuration Register (WRVCR), Write Enhanced Configuration Register (WRVECR), Write NV Configuration Register (WRNVCR), Write Enable (WREN) or Write Disable (WRDI) instruction, Chip Select (S) must be driven High exactly at a byte boundary, otherwise the instruction is rejected, and is not executed. That is, Chip Select (S) must driven High when the number of clock pulses after Chip Select (S) being driven Low is an exact multiple of eight. All attempts to access the memory array are ignored during: – Write Status Register cycle – Write Non Volatile Configuration Register – Program cycle – Erase cycle The following continue unaffected, with one exception: – Internal Write Status Register cycle, – Write Non Volatile Configuration Register, – Program cycle, – Erase cycle The only exception is the Program/Erase Suspend instruction (PES), that can be used to pause all the program and the erase cycles except for: – Program OTP (POTP), – Bulk Erase, – Write Non Volatile Configuration Register. The suspended program or erase cycle can be resumed by the Program/Erase Resume instruction (PER). During the program/erase cycles, the polling instructions (both on the Status register and on the Flag Status register) are also accepted to allow the application to check the end of the internal modify cycles. Note: These polling instruct ions don't affect the internal cycles performing.

Table 15. Instruction set: extended SPI protocol (page 1 of 2)

9.1.1 Read Identification (RDID)

requests, the devices are shipped with all the CFD bytes programmed to zero (00h). not decoded, and has no effect on the cycle that is in progress. bit is shifted out during the falling edge of Serial Clock (C). The instruction sequence is shown in Figure 10. any time during data output. Table 15. Instruction set: extended SPI protocol (page 2 of 2)

Figure 10. Read identification instruction and data-out sequence

9.1.2 Read Data Bytes (READ)

maximum frequency fR, during the falling edge of Serial Clock (C). to be continued indefinitely. any effects on the cycle that is in progress. Table 16. Read Identification data-out sequence Table 17. Extended Device ID table (first byte)

Figure 11. Read Data Bytes instruction and data-out sequence

9.1.3 Read Data Bytes at Higher Speed (FAST_READ)

A0) and a dummy byte, each bit being latched-in during the rising edge of Serial Clock (C). maximum frequency fC, during the falling edge of Serial Clock (C). 000000h, allowing the read sequence to be continued indefinitely.

Figure 12. Read Data Bytes at Higher Speed instruction and data-out sequence

9.1.4 Dual Output Fast Read (DOFR)

during the falling edge of Serial Clock (C). memory can, therefore, be read with a single Dual Output Fast Read (DOFR) instruction. the read sequence can be continued indefinitely.

Figure 13. Dual Output Fast Read instruction sequence

9.1.5 Dual I/O Fast Read

Figure 14. Dual I/O Fast Read instruction sequence

9.1.6 Quad Output Fast Read

Fast Read (DOFR) instruction. HOLD/DQ3 (1) at a maximum frequency fC, during the falling edge of Serial Clock (C). The instruction sequence is shown in Figure 15. single Quad Output Fast Read (QOFR) instruction. the read sequence can be continued indefinitely.

Section 16: Ordering information. Figure 15. Quad Input/Output Fast Read instruction sequence

9.1.7 Quad I/O Fast Read

/VPP/DQ2 and pin HOLD/DQ3 (1)) instead of only one. Section 16: Ordering information.

Figure 16. Quad Input/ Output Fast Read instruction sequence

9.1.8 Read OTP (ROTP)

bit is latched in on the rising edge of Serial Clock (C). Then the memory contents at that address are shifted out on Serial Data output (DQ1). (C). The instruction sequence is shown in Figure 17. having any effect on the cycle that is in progress.

Figure 17. Read OTP instruction and data-out sequence

9.1.9 Write Enable (WREN)

The Write Enable (WREN) instruction (Figure 8) sets the Write Enable Latch (WEL) bit. Register (WRNVCR) instruction. instruction code, and then driving Chip Select (S) High.

respect to the Status Register WIP bit. Figure 18. Write Enable instruction sequence

9.1.10 Write Disable (WRDI)

The Write Disable (WRDI) instruction (Figure 9) resets the Write Enable Latch (WEL) bit. instruction code, and then driving Chip Select (S) High.

Figure 19. Write Disable instruction sequence

9.1.11 Page Program (PP)

decoded, the device sets the Write Enable Latch (WEL).

Instructions N25Q128 - 1.8 V same page (from the address whose 8 least significant bits (A7-A0) are all zero). Chip Select (S) must be driven Low for the entire duration of the sequence. If more than 256 bytes are sent to the device, previously latched data are discarded and the last 256 data bytes are guaranteed to be programmed correctly within the same page. If less than 256 data bytes are sent to device, they are correctly programmed at the requested addresses without having any effects on the other bytes of the same page. For optimized timings, it is recommended to use the Page Program (PP) instruction to program all consecutive targeted bytes in a single sequence versus using several Page Program (PP) sequences with each containing only a few bytes. See Table 33.: AC Characteristics. Chip Select (S) must be driven High after the eighth bit of the last data byte has been latched in, otherwise the Page Program (PP) instruction is not executed. As soon as Chip Select (S) is driven High, the self-timed Page Program cycle (whose duration is top) is initiated. While the Page Program cycle is in progress, the Status Register and the Flag Status Register may be read to check if the internal modify cycle is finished. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. A Page Program (PP) instruction applied to a page which is protected by the Block Protect (BP3,BP2, BP1, BP0 and TB) bits is not executed. Page Program cycle can be paused by mean of Program/Erase Suspend (PES) instruction and resumed by mean of Program/Erase Resume (PER) instruction.

Figure 20. Page Program instruction sequence

9.1.12 Dual Input Fast Program (DIFP)

compared to the Page Program (PP) instruction. must be driven Low for the entire duration of the sequence. addresses without having any effects on the other bytes in the same page.

Table 33.: AC Characteristics. latched in, otherwise the Dual Input Fast Program (DIFP) instruction is not executed. Block Protect (BP3, BP2, BP1, BP0 and TB) bits is not executed. instruction and resumed by mean of Program/Erase Resume (PER) instruction. Figure 21. Dual Input Fast Program instruction sequence

9.1.13 Dual Input Extended Fast Program

pin DQ1) instead of only one. Figure 22. Dual Input Extended Fast Program instruction sequence

9.1.14 Quad I nput Fast Program

must be driven Low for the entire duration of the sequence.

addresses without having any effects on the other bytes in the same page. Table 33.: AC Characteristics. latched in, otherwise the Quad Input Fast Program (QIFP) instruction is not executed. Block Protect (BP3, BP2, BP1, BP0 and TB) bits is not executed. (PES) instruction and resumed by mean of Program/Erase Resume (PER) instruction. Figure 23. Quad Input Fast Program instruction sequence

9.1.15 Quad Input Ex tended Fast Program

(pin DQ0, pin DQ1, pin W/VPP/DQ2 and pin HOLD/DQ3) instead of only one.

Figure 24. Quad Input Extended Fast Program instruction sequence

9.1.16 Program OTP instruction (POTP)

instruction has been decoded, the device sets the Write Enable Latch (WEL) bit. latched in, otherwise the Program OTP instruction is not executed. once all 65 bytes have been latched in, any following byte will be discarded. „ When bit 0 of byte 64 = '1', the 64 bytes of the OTP memory array can be programmed. cannot be programmed anymore.

Once a bit of the OTP memory has been programmed to '0', it can no longer be set to '1'. memory array become read-only in a permanent way. progress is rejected without having any effect on the cycle that is in progress. Figure 25. Program OTP instruction sequence

Figure 26. How to permanently lock the OTP bytes

9.1.17 Subsector Erase (SSE)

Select (S) must be driven Low for the entire duration of the sequence. unspecified time before the cycle is complete, the Write Enable Latch (WEL) bit is reset. progress, is rejected without having any effects on the cycle that is in progress. boot sectors with subsectors) is rejected without having any effects on the device.

Figure 27. Subsector Erase instruction sequence

9.1.18 Sector Erase (SE)

can be accepted, a Write Enable (WREN) instruction must previously have been executed. driven Low for the entire duration of the sequence. time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. (BP3, BP2, BP1, BP0 and TB) bits is not executed. and resumed by mean of Program/Erase Resume (PER) instruction.

24 Bit Address

Figure 28. Sector Erase instruction sequence

9.1.19 Bulk Erase (BE)

(WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL). entire duration of the sequence. completed, the Write Enable Latch (WEL) bit is reset. bits are 0. The Bulk Erase (BE) instruction is ignored if one, or more, sectors are protected. Figure 29. Bulk Erase instruction sequence

9.1.20 Program/Erase Suspend

Input Extended Page program can be suspended and erased. The Suspended state is reset if a power-off is performed or after resume. sector outputs Don't Care data. on this sector outputs Don't Care data. another Program/Erase Resume Instruction is need to resume also the former one. Table 18. Suspend Parameters

Note: The device can be in only one state at a time, such as Standby, Program, Erase, and so on.

9.1.21 Program/Erase Resume

required to continue performing the suspended Program or Erase sequence. Program/Erase Resume instruction until the Program or Erase sequence is completed. Table 19. Operations Allowed / Disallowed During Device States

1. The Read operation is accepted but the data output is not guaranetted until the program or erase has completed.

9.1.22 Read Status Register (RDSR)

Status Register continuously, as shown here. Figure 30. Read Status Register instruction sequence

9.1.23 Write status register (WRSR)

the device sets the write enable latch (WEL). followed by the instruction code and the data byte on serial data input (DQ0). Chip Select (S) must be driven High after the eighth bit of the data byte has been latched in. cycle is completed, the write enable latch (WEL) is reset.

Figure 31. Write Status Register instruction sequence The protection features of the device are summarized in Table 8. of the whether Write Protect (W/VPP) is driven High or Low. Status Register, are also hardware protected against data modification. (BP3, BP2, BP1, BP0) bits of the Status Register, can be used.

9.1.24 Read Lock Register (RDLR)

any time during data output. progress, is rejected without having any effects on the cycle that is in progress. Figure 32. Read Lock Register instruction and data-out sequence Table 20. Protection modes

1. As defined by the values in the Block Protect (TB, BP3, BP2, BP1, BP0) bits of the Status Register, as shown in Table 3:

9.1.25 Write to Lo ck Register (WRLR)

device sets the Write Enable Latch (WEL). Enable Latch (WEL) bit is reset after a delay time less than tSHSL minimum value. progress, is rejected without having any effects on the cycle that is in progress. Figure 33. Write to Lock Register instruction sequence Table 21. Lock Register out (1) Lock Down bit it cannot be cleared to ‘0’, except by a power-up. ‘0’ The Write Lock and Lock Down bits can be changed by writing new values to them. memory contents will not be changed.

1. Values of (b1, b0) after power-up are defined in Section 7: Protection modes.

9.1.26 Read Flag Status Register

Register continuously, as shown here. Figure 34. Read Flag Status Register instruction sequence

9.1.27 Clear Flag Status Register

will be unchanged after this command is executed. Table 22. Lock Register in (1)

1. Values of (b1, b0) after power-up are defined in Section 7: Protection modes.

Figure 35. Clear Flag Status Register instruction sequence

9.1.28 Read NV C onfiguration Register

Configuration Register to be read. Figure 36. Read NV Configurati on Register instruction sequence

9.1.29 Write NV C onfiguration Register

Chip Select (S) must be driven High after the 16th bit of the data bytes has been latched in. If not, the Write Non Volatile Configuration register (WRNVCR) instruction is not executed.

cycle (whose duration is tnvcr) is initiated. completed. When the cycle is completed, the write enable latch (WEL) is reset. Non-Volatile Configuration Register. Figure 37. Write NV Configuratio n Register instruction sequence

9.1.30 Read Volatile Configuration Register

Configuration Register to be read. See Table 6.: Volatile Configuration Register.

Figure 38. Read Volatile Configuration Register instruction sequence

9.1.31 Write Volatile Configuration Register

has been decoded and executed, the device sets the write enable latch (WEL). required because a WREN instruction gets the device out from the Fast POR state. Chip Select (S) must be driven High after the eighth bit of the data byte has been latched in. If not, the Write Volatile Configuration register (WRVCR) instruction is not executed. When the new data are latched, the write enable latch (WEL) is reset. instruction is received by the device.

Figure 39. Write Volatile Configuration Register instruction sequence

9.1.32 Read Volatile Enha nced Configuration Register

Volatile Configuration Register to be read. Figure 40. Read Volatile Enhanced Configuration Register instruction sequence

9.1.33 Write Volatile Enha nced Configuration Register

Chip Select (S) must be driven High after the eighth bit of the data byte has been latched in. When the new data are latched, the write enable latch (WEL) is reset. Table 7.: Volatile Enhanced Configuration Register. the instruction is received by the device. Figure 41. Write Volatile Enhanced Configuration Register instruction sequence

9.1.34 Deep Power-down (DP)

ignores all Write, Program and Erase instructions. ICC2, as specified in Table 32).

powers up in the Standby Power mode. the entire duration of the sequence. The instruction sequence is shown in Figure 42. to ICC2 and the Deep Power-down mode is entered. progress, is rejected without having any effects on the cycle that is in progress. Figure 42. Deep Power-down instruction sequence

9.1.35 Release from Deep Power-down (RDP)

takes the device out of the Deep Power-down mode. driven Low for the entire duration of the sequence. The instruction sequence is shown in Figure 43. Low, cause the instruction to be rejected, and not executed. device waits to be selected, so that it can receive, decode and execute instructions. cycle is in progress, is rejected without having any effects on the cycle that is in progress.

Figure 43. Release from Deep Power-down instruction sequence

9.2 DIO-SPI Instructions

Select (S) can be driven High after any bit of the data-out sequence is being shifted out. these polling instructions don't affect the internal cycles performing.

Table 23. Instruction set: DIO-SPI protocol

2) SSE is only available in devices with Bottom or Top architecture.

9.2.1 Multiple I/O Read Identification protocol

instruction can not read the Unique ID code (UID) (17 bytes). Section 9.1.1: Read Identification (RDID). and DQ0. Each two bits are shifted out during the falling edge of Serial Clock (C). any time during data output. Figure 44. Multiple I/O Read Identification instruction and data-out sequence DIO-

9.2.2 Dual Command Fast Read (DCFR)

protocol, please refer to Section 9.1.5: Dual I/O Fast Read for further details. Figure 45. Dual Command Fast Read instruction and data-out sequence DIO-SPI

9.2.3 Read OTP (ROTP)

address and output data are all parallelized on the two pins DQ0 and DQ1. the internal reading operation.

Figure 46. Read OTP instruction and data-out sequence DIO-SPI

9.2.4 Write Enable (WREN)

The Write Enable (WREN) instruction sets the Write Enable Latch (WEL) bit. Figure 47. Write Enable instruction sequence DIO-SPI

9.2.5 Write Disable (WRDI)

The Write Disable (WRDI) instruction resets the Write Enable Latch (WEL) bit.

Figure 48. Write Disable instruction sequence DIO-SPI

9.2.6 Dual Command Page Program (DCPP)

porting from Extended SPI protocol to DIO-SPI protocol. Fast Program for further details. Figure 49. Dual Command Page Program instruction sequence DSP , 02h

Figure 50. Dual Command Page Program instruction sequence DSP , A2h Figure 51. Dual Command Page Program instruction sequence DSP , D2h

9.2.7 Program OTP instruction (POTP)

(WREN) instruction must previously have been executed. refer to Section 9.1.16: Program OTP instruction (POTP) for further details.

Figure 52. Program OTP instruction sequence DIO-SPI

9.2.8 Subsector Erase (SSE)

accepted, a Write Enable (WREN) instruction must previously have been executed. Figure 53. Subsector Erase instruction sequence DIO-SPI

9.2.9 Sector Erase (SE)

can be accepted, a Write Enable (WREN) instruction must previously have been executed. Figure 54. Sector Erase instruction sequence DIO-SPI

9.2.10 Bulk Erase (BE)

Enable (WREN) instruction must previously have been executed. Extended SPI protocol, please refer to Section 9.1.19: Bulk Erase (BE) for further details.

Figure 55. Bulk Erase instruction sequence DIO-SPI

9.2.11 Program/Erase Suspend

register, and Program OTP cannot be suspended. instruction of the Extended SPI protocol. Figure 56. Program/Erase Suspend instruction sequence DIO-SPI

9.2.12 Program/Erase Resume

required to continue performing the suspended Program or Erase sequence.

Figure 57. Program/Erase Resume instruction sequence DIO-SPI

9.2.13 Read Status Register (RDSR)

Register (RDSR) for further details. Figure 58. Read Status Register instruction sequence DIO-SPI

9.2.14 Write status register (WRSR)

protocol, please refer to Section 9.1.23: Write status register (WRSR) for further details. Figure 59. Write Status Register instruction sequence DIO-SPI

9.2.15 Read Lock Register (RDLR)

The Read Lock Register instructions is used to read the lock register content. Read Lock Register (RDLR) for further details. Figure 60. Read Lock Register instruction and data-out sequence DIO-SPI

9.2.16 Write to Lo ck Register (WRLR)

Write to Lock Register (WRLR) for further details.

Figure 61. Write to Lock Register instruction sequence DIO-SPI

9.2.17 Read Flag Status Register

Status Register for further details. Figure 62. Read Flag Status Register instruction sequence DIO-SPI

9.2.18 Clear Flag Status Register

will be unchanged after this command is executed. Figure 63. Clear Flag Status Register instruction sequence DIO-SPI

9.2.19 Read NV C onfiguration Register

Configuration Register to be read. Figure 64. Read NV Configuration Re gister instruction sequence DIO-SPI

9.2.20 Write NV C onfiguration Register

enable (WREN) instruction must previously have been executed. Section 9.1.29: Write NV Configuration Register for further details. Figure 65. Write NV Configuration Register instruction sequence DIO-SPI

9.2.21 Read Volatile Configuration Register

Configuration Register to be read. See Table 6.: Volatile Configuration Register.

Figure 66. Read Volatile Configuration Register instruction sequence DIO-SPI

9.2.22 Write Volatile Configuration Register

POR state (See Section 11.1: Fast POR). Write Volatile Configuration Register for further details. Figure 67. Write Volatile Configurati on Register instruction sequence DIO-SPI

9.2.23 Read Volatile Enha nced Configuration Register

Volatile Configuration Register to be read. Figure 68. Read Volatile Enhanced Configuration Register instruction sequence

9.2.24 Write Volatile Enha nced Configuration Register

device out from the Fast POR state (See Section 11.1: Fast POR). Section 9.1.33: Write Volatile Enhanced Configuration Register for further details.

Figure 69. Write Volatile Enhanced Configuration Register instruction sequence

9.2.25 Deep Power-down (DP)

Figure 70. Deep Power-down instruction sequence

9.2.26 Release from Deep Power-down (RDP)

takes the device out of the Deep Power-down mode. Release from Deep Power-down instruction sequence. Figure 71. Release from Deep Power-down instruction sequence

9.3 QIO-SPI Instructions

instruction (erase and program) performed with the VPP=VPPh. Select (S) can be driven High after any bit of the data-out sequence is being shifted out. High exactly at a byte boundary, otherwise the instruction is rejected, and is not executed.

but the Program OTP (POT), Bulk Erase (BE) and Write Non Volatile Configuration Register. instructions don't affect the internal cycles performing. Table 24. Instruction set: QIO-SPI protocol (page 1 of 2)

1) The number of Dummy Clock cycles is configurable by the user.

9.3.1 Multiple I/O Read Identification (MIORDID)

instruction can not read the Unique ID code (UID) (17 bytes). any time during data output. Table 24. Instruction set: QIO-SPI protocol (page 2 of 2)

Figure 72. Multiple I/O Read Identification instruction and data-out sequence QIO-

9.3.2 Quad Command Fast Read (QCFR)

protocol to QIO-SPI protocol. Extended SPI protocol, please refer to Section 9.1.7: Quad I/O Fast Read for further details.

Figure 75. Quad Command Fast Read instruction and data-out sequence QSP , EBh

9.3.3 Read OTP (ROTP)

address and output data are all parallelized on the four pins DQ0, DQ1, DQ2 and DQ3.

Figure 76. Read OTP instruction and data-out sequence QIO-SPI

9.3.4 Write Enable (WREN)

SPI protocol, please refer to Section 9.1.9: Write Enable (WREN) for further details. Figure 77. Write Enable instruction sequence QIO-SPI

9.3.5 Write Disable (WRDI)

The Write Disable (WRDI) instruction resets the Write Enable Latch (WEL) bit. Figure 78. Write Disable instruction sequence QIO-SPI

9.3.6 Quad Command Page Program (QCPP)

code porting from Extended SPI protocol to QIO-SPI protocol. Fast Program for further details.

Figure 81. Quad Command Page Program instruction sequence QIO-SPI, 32h

9.3.7 Program OTP instruction (POTP)

(WREN) instruction must previously have been executed. please refer to Section 9.1.16: Program OTP instruction (POTP) for further details.

Figure 82. Program OTP instruction sequence QIO-SPI

9.3.8 Subsector Erase (SSE)

previously have been executed. Erase (SSE) for further details.

Figure 83. Subsector Erase instruction sequence QIO-SPI

9.3.9 Sector Erase (SE)

can be accepted, a Write Enable (WREN) instruction must previously have been executed. Figure 84. Sector Erase instruction sequence QIO-SPI

9.3.10 Bulk Erase (BE)

Enable (WREN) instruction must previously have been executed. Figure 85. Bulk Erase instruction sequence QIO-SPI

9.3.11 Program/Erase Suspend

Configuration register and Program OTP can not be suspended. Suspend for further details.

Figure 86. Program/Erase Suspend instruction sequence QIO-SPI

9.3.12 Program/Erase Resume

required to continue performing the suspended Program or Erase sequence.

Figure 87. Program/Erase Resume instruction sequence QIO-SPI

9.3.13 Read Status Register (RDSR)

The Read Status Register (RDSR) instruction allows the Status Register to be read. Read Status Register (RDSR) for further details.

Figure 88. Read Status Register instruction sequence QIO-SPI

9.3.14 Write status register (WRSR)

Figure 89. Write Status Register instruction sequence QIO-SPI

9.3.15 Read Lock Register (RDLR)

The Read Lock Register instructions is used to read the lock register content. Section 9.1.24: Read Lock Register (RDLR) for further details.

Figure 90. Read Lock Register instruction and data-out sequence QIO-SPI

9.3.16 Write to Lo ck Register (WRLR)

Section 9.1.25: Write to Lock Register (WRLR) for further details.

Figure 91. Write to Lock Register instruction sequence QIO-SPI

9.3.17 Read Flag Status Register

Section 9.1.26: Read Flag Status Register for further details.

Figure 92. Read Flag Status Register instruction sequence QIO-SPI

9.3.18 Clear Flag Status Register

will be unchanged after this command is executed.

Figure 93. Clear Flag Status Register instruction sequence QIO-SPI

9.3.19 Read NV C onfiguration Register

Configuration Register to be read.

Figure 94. Read NV Configuration Re gister instruction sequence QIO-SPI

9.3.20 Write NV C onfiguration Register

enable (WREN) instruction must previously have been executed. refer to Section 9.1.29: Write NV Configuration Register for further details.

Figure 95. Write NV Configuration Register instruction sequence QIO-SPI

9.3.21 Read Volatile Configuration Register

Configuration Register to be read.

Figure 96. Read Volatile Configuration Register instruction sequence QIO-SPI

9.3.22 Write Volatile Configuration Register

POR state (See Section 11.1: Fast POR). Section 9.1.31: Write Volatile Configuration Register for further details.

Figure 97. Write Volatile Configuration Register instruction sequence QIO-SPI

9.3.23 Read Volatile Enha nced Configuration Register

Volatile Configuration Register to be read.

Figure 98. Read Volatile Enhanced Configuration Register instruction sequence

9.3.24 Write Volatile Enha nced Configuration Register

device out from the Fast POR state (See Section 11.1: Fast POR).

Figure 99. Write Volatile Enhanced Configuration Register instruction sequence

9.3.25 Deep Power-down (DP)

Extended SPI protocol. The instruction sequence is shown in Figure 100. Figure 100. Deep Power-down instruction sequence

9.3.26 Release from Deep Power-down (RDP)

SPI protocol. The instruction sequence is shown in Figure 101. Figure 101. Deep Power-down instruction sequence

N25Q128 - 1.8 V XIP Operations

10 XIP Operations

XIP (eXecution in Place) mode is available in each protocol: Extended SPI, DIO-SPI, and QIO-SPI. XIP mode allows the memory to be read simply by sending an address to the device and then receiving the data on one, two, or four pins in parallel, depending on the customer requirements. It offers maximum flexibility to the application, saves instruction overhead, and allows a dramatic reduction to the Random Access time. You can enable XIP mode in two ways: „ Using the Volatile Configuration Register: this is dedicated to applications that boot in SPI mode (Extended SPI, DIO-SPI or QIO-SPI) and then during the application life need to switch to XIP mode to directly execute some code in the flash. „ Using the Non Volatile Configuration Register: this is dedicated to applications that need to boot directly in XIP mode. Setting to 0 the bit 3 of the Volatile Configuration Register the device is ready to enter in XIP mode right after the next fast read instruction (by 1, 2 or 4 pin). While acting on the Non Volatile Configuration Register (bit 11 to bit 9, depending on which XIP type is required, single, dual or quad I/O) the memory enters in the selected XIP mode only after the next power-on sequence. The Non Volatile Configuration Register XIP configuration bits allows the memory to start directly in the required XIP mode (Single, Dual or Quad) after the power on. The XIP mode status must be confirmed forcing the XIP confirmation bit to "0", the XIP confirmation bit is the value on the DQ0 pin during the first dummy clock cycle after the address in XIP reading instruction. Forcing the bit "1" on DQ0 during the first dummy clock cycle after the address (XIP Confirmation bit) the memory returns in the previous standard read mode, that means it will codify as an instruction code the next byte received on the input pin(s) after the next chip select. Instead, if the XIP mode is confirmed (by forcing the XIP confirmation bit to 0), after the device next de-selection and selection cycle, the memory codify the first 3 bytes received on the inputs pin(s) as a new address. Besides not confirming the XIP mode during the first dummy clock cycle, it is possible to exit the XIP mode by mean of a dedicated rescue sequence. Note: For devices with a feature set digit equal to 2 or 4 in the part number (Basic XiP), it is not necessary to set the Volatile Configuration Register bit 3 to enter XIP mode: it is possible to enter XIP mode directly by setting XIP Confirmation bit to 1 during the first dummy clock cycle after a fast read instruction.See Section 16: Ordering information.

Figure 102. N25Q128 Read functionality Flow Chart

10.1 Enter XIP mode by setting the Non Volatile Configuration

Figure 103. XIP mode di rectly after power on mode and return to standard read mode. Table 25. NVCR XIP bi ts setting example

10.2 Enter XIP mode by setting the Volatile Configuration Register

(either Single, Dual or Quad) is needed once to start the XIP Reading. instruction code, and after the dummy clock cycles (configurable) directly outputs the data. Read instruction, as described in Table 26.: VCR XIP bits setting example. clock cycle after a fast read instruction. See Section 16: Ordering information. Table 26. VCR XIP bits setting example

Figure 104. XiP: enter by VCR 2/2 (Q IOFR in normal SPI protocol example) mode and return to standard read mode.

10.3 XIP mode hold and exit

bit to be sent to the memory on DQ0 during the first dummy clock cycle. means codifying the first byte after the next chip select as an instruction code. addresses is always Don't Care. after the addresses are always Don't Care. deselected. See Section 16: Ordering information.

XIP Operations N25Q128 - 1.8 V

10.4 XIP Memory reset after a controller reset

If during the application life the system controller is reset during operation, and the device features the RESET functionality (in devices with a dedicated part number), and the feature has not been disabled, after the controller resets, the memory returns to POR state and there is no issue. See Section 16: Ordering information. In all the other cases, it is possible to exit the memory from the XIP mode by sending the following rescue sequence at the first chip selection after a system reset: DQ0= '1' for: 7 clock cycles within S low (S becomes high before 8th clock cycle) + 13 clock cycles within S low (S becomes high before 14th clock cycle) + 25 clock cycles within S low (S becomes high before 26th clock cycle) The global effect is only to exit from XIP without any other reset.

N25Q128 - 1.8 V Power-up and power-down

11 Power-up and power-down

At power-up and power-down, the device must not be selected (that is Chip Select (S) must follow the voltage applied on VCC) until VCC reaches the correct value: „ VCC(min) at power-up, and then for a further delay of tVSL „ VSS at power-down A safe configuration is provided in Section 3: SPI Modes. To avoid data corruption and inadvertent write operations during power-up, a Power On Reset (POR) circuit is included. The logic inside the device is held reset while VCC is less than the Power On Reset (POR) threshold voltage, VWI - all operations are disabled, and the device does not respond to any instruction. Moreover, the device ignores the Write Enable (WREN) instruction and all the modify instructions until a time delay of tPUW has elapsed after the moment that VCC rises above the VWI threshold. However, the correct operation of the device is not guaranteed if, by this time, VCC is still below VCC(min). No Write Status Register, Program or Erase instructions should be sent until the later of: „ tPUW after VCC has passed the VWI threshold „ tVSL after VCC has passed the VCC(min) level These values are specified in Table 27.: Power-up timing and VWI threshold. If the time, tVSL, has elapsed, after VCC rises above VCC(min), the device can be selected for READ instructions even if the tPUW delay has not yet fully elapsed. After power-up, the device is in the following state: „ The device is in the Standby Power mode (not the Deep Power-down mode) „ The Write Enable Latch (WEL) bit is reset „ The Write In Progress (WIP) bit is reset „ The Lock Registers are configured as: (Write Lock bit, Lock Down bit) = (0,0). Normal precautions must be taken for supply line decoupling, to stabilize the VCC supply. Each device in a system should have the VCC line decoupled by a suitable capacitor close to the package pins (generally, this capacitor is of the order of 100 nF). At power-down, when VCC drops from the operating voltage, to below the Power On Reset (POR) threshold voltage, VWI, all operations are disabled and the device does not respond to any instruction (the designer needs to be aware that if power-down occurs while a Write, Program or Erase cycle is in progress, some data corruption may result). VPPH must be applied only when VCC is stable and in the VCC(min) to VCC(max) voltage range.

N25Q128 - 1.8 V Power-up and power-down

11.1 Fast POR

The Fast POR feature is available to speed up the power-on sequence for applications that only require reading the memory after the power on sequence (no modify instructions). If enabled, the Fast POR allows read operations and Volatile Configuration Register and Volatile Enhanced Configuration Register modifications after less than 100us, providing a substantially faster application boot phase. In any case, even if the Fast POR sequence is selected, it is still possible to execute a modify instruction (erase or program) issuing a WREN instruction. In this case the device will have a latency time (~500us) after the first WREN instruction to complete POR sequence. During this latency time, when the power on second phase is running, no instruction will be accepted except for the polling instruction. During the power on second phase, both WEL & WIP bits are set to 1. At the end of POR sequence only the WEL bit is still set to 1. To select or deselect the Fast POR feature, a Write non Volatile Configuration Register (WRNVCR) instruction is needed to properly set the dedicated bit (bit 5) of the Non Volatile Configuration Register.

11.2 Rescue sequence in case of power loss during WRNVCR

If a power loss occurs during a Write Non Volatile Configuration Register instruction, after the next power on the device could eventually wake up in a not determined state, for example a not required protocol or XIP mode. In that case a particular rescue sequence must be used to recover the device at a fixed state (Extended SPI protocol without XIP) until the next power up. Then to fix the problem definitively is recommended to run the Write Non Volatile configuration Register again. The rescue sequence is composed of two parts that have to be run in the correct order. During all the sequence the TSHSL must be 50ns at least. The sequence is: DQ0 (PAD DATA) equal to '1' for: 7 clock cycles within S low (S becomes high before 8th clock cycle) + 13 clock cycles within S low S becomes high before 14th clock cycle) + 25 clock cycles within S low (S becomes high before 26th clock cycle) To exit from XIP. DQ0 (PAD DATA) and DQ3 (PAD HOLD) equal to '1' for: 8 clock cycles within S low (S becomes high before 9th clock cycle) to force Normal SPI protocol.

12 Initial delivery state

contains FFh). The Status Register contains 00h (all Status Register bits are 0).

13 Maximum rating

Table 28. Absolute maximum ratings

1. Compliant with JEDEC Std. J-STD-020C (for small body, Sn-Pb or Pb assembly), the Numonyx

Substances (RoHS) 2002/95/EU.

1. Avoid applying VPP H to the W/VPP pin during Bulk Erase.

14 DC and AC parameters

match the measurement conditions when relying on the quoted parameters. 1) Output Buffers are configurable by user. Figure 107. AC measurement I/O waveform Table 29. Operating conditions Table 30. AC measurement conditions Table 31. Capacitance (1)

1. Sampled only, not 100% tested, at T A=25 °C and a frequency of 54 MHz.

Table 32. DC Characteristics

108 MHz 18 mA

108 MHz 20 mA

Note: The AC Characteristi cs data is preliminary. Table 33. AC Characteristics (page 1 of 2)

Figure 108. Reset AC waveforms: program or erase cycle is in progress See Table 34.: Reset Conditions.

1. tCH + tCL must be greater than or equal to 1/ fC.
2. Typical values given for TA = 25 °C
3. Value guaranteed by characterization, not 100% tested in production.
4. Expressed as a slew-rate.
5. Only applicable as a constraint for a WRSR instruction when SRWD is set to '1'.
6. VPPH should be kept at a valid level until the program or eras e operation has completed and its result (success or failure)

is known. Avoid applying VPPH to the W/VPP pin during Bulk Erase.

1. When using the page program (PP) instruction to program consecutive bytes, optimized timings are obtained with one
2. int(A) corresponds to the upper integer part of A. For example int(12/8) = 2, int(32/8) = 4 int(15.3) =16.

Table 33. AC Characteristics (page 2 of 2)

Figure 109. Serial input timing Table 34. Reset Conditions DIFP, QIEFP, QIFP, SE, BE, PER, PES.

1. All values are guaranteed by characteri zation and not 100% tested in production.
2. The device reset is possible but not guaranteed if tRLRH < 50 ns.

conditions are also marked on the inner box label. Figure 114. VDFPN8 (MLP8) 8-lead very thin dual flat package no lead,

1. The circle in the top view of the package indicates the position of pin 1.
2. D2 Max must not exceed (D – K – 2 × L).

Figure 115. SO16 wide - 16-lead plastic sm all outline, 300 mils body width, package Table 36. SO16 wide - 16-lead plastic small outline, 300 mils body width,

Figure 116. TBGA - 6 x 8 mm, 24-ball, mechanical package outline

Table 37. TBGA 6x8 mm 24-ball package dimensions

contact your nearest Numonyx Sales Office. Table 38. Ordering information scheme

1. Additional secure options are available upon customer request.

Note: Packing information details: E= tray, F= ta pe-n-reel, G= tube (16th digit of part number). Table 39. Valid Order Information Line Items

Table 40. Document revision history 12-Feb-2010 1.0 Initial public release.