MT48LC128M4A2

MT48LC128M4A2 MICRON | Alldatasheet

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ADVANCE‡ ‡ PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S PRODUCTION DATA SHEET SPECIFICATIONS. 512Mb: x4, x8, x16 SDRAM 512Mb: x4, x8, x16 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. 512MSDRAM_D.p65 – Rev. D; Pub 1/02 ©2000, Micron Technology, Inc. KEY TIMING PARAMETERS SPEED CLOCK ACCESS TIME SETUP HOLD GRADE FREQUENCY CL = 2* CL = 3* TIME TIME -7E 143 MHz – 5.4ns 1.5ns 0.8ns -75 133 MHz – 5.4ns 1.5ns 0.8ns -7E 133 MHz 5.4ns – 1.5ns 0.8ns -75 100 MHz 6ns – 1.5ns 0.8ns

128 Meg x 4 64 Meg x 8 32 Meg x 16

Configuration 32 Meg x 4 x 4 banks 16 Meg x 8 x 4 banks 8 Meg x 16 x 4 banks Refresh Count 8K 8K 8K Row Addressing 8K (A0–A12) 8K (A0–A12) 8K (A0–A12) Bank Addressing 4 (BA0, BA1) 4 (BA0, BA1) 4 (BA0, BA1) Column Addressing 4K (A0–A9, A11, A12) 2K (A0–A9, A11) 1K (A0–A9) SYNCHRONOUS DRAM MT48LC128M4A2 – 32 Meg x 4 x 4 banks MT48LC64M8A2 – 16 Meg x 8 x 4 banks MT48LC32M16A2 – 8 Meg x 16 x 4 banks For the latest data sheet, please refer to the Micron Web site: www.micron.com/dramds Pin Assignment (Top View) 54-Pin TSOP

FEATURES

• PC100- and PC133-compliant  Fully synchronous; all signals registered on positive edge of system clock  Internal pipelined operation; column address can be changed every clock cycle  Internal banks for hiding row access/precharge  Programmable burst lengths: 1, 2, 4, 8, or full page  Auto Precharge, includes CONCURRENT AUTO PRECHARGE, and Auto Refresh Modes  Self Refresh Mode  64ms, 8,192-cycle refresh  LVTTL-compatible inputs and outputs  Single +3.3V ±0.3V power supply OPTIONS MARKING  Configurations

128 Meg x 4 (32 Meg x 4 x 4 banks) 128M4

64 Meg x 8 (16 Meg x 8 x 4 banks) 64M8

32 Meg x 16 (8 Meg x 16 x 4 banks) 32M16

 WRITE Recovery ( tWR) tWR = “2 CLK”1 A2  Plastic Package – OCPL 2 54-pin TSOP II (400 mil) TG  Timing (Cycle Time) 7.5ns @ CL = 2 (PC133) -7E 7.5ns @ CL = 3 (PC133) -75  Self Refresh Standard None Low power L  Operating Temperature Commercial (0 oC to +70oC) None NOTE: 1. Refer to Micron Technical Note TN-48-05. 2. Off-center parting line. Part Number Example: MT48LC32M16A2TG-75 NOTE: The # symbol indicates signal is active LOW. A dash (–) indicates x8 and x4 pin function is same as x16 pin function. VDD DQ0 VDDQ DQ1 DQ2 VssQ DQ3 DQ4 V DDQ DQ5 DQ6 VssQ DQ7 V DD DQML WE# CAS# RAS# CS# BA0 BA1 A10 V DD Vss DQ15 VssQ DQ14 DQ13 V DDQ DQ12 DQ11 VssQ DQ10 DQ9 V DDQ DQ8 Vss NC DQMH CLK CKE A12 A11 Vss x8x16 x16x8 x4x4 DQ0 NC DQ1 NC DQ2 NC DQ3 NC NC NC NC DQ0 NC NC NC DQ1 NC NC DQ7 NC DQ6 NC DQ5 NC DQ4 NC DQM NC NC DQ3 NC NC NC DQ2 NC DQM *CL = CAS (READ) latency 512Mb SDRAM PART NUMBERS PART NUMBER ARCHITECTURE MT48LC128M4A2TG 128 Meg x 4 MT48LC64M8A2TG 64 Meg x 8 MT48LC32M16A2TG 32 Meg x 16

512Mb: x4, x8, x16 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. 512MSDRAM_D.p65 – Rev. D; Pub 1/02 ©2000, Micron Technology, Inc. 512Mb: x4, x8, x16 SDRAM ADVANCE page, with a burst terminate option. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst se- quence. The 512Mb SDRAM uses an internal pipelined archi- tecture to achieve high-speed operation. This architec- ture is compatible with the 2 n rule of prefetch architec- tures, but it also allows the column address to be changed on every clock cycle to achieve a high-speed, fully ran- dom access. Precharging one bank while accessing one of the other three banks will hide the precharge cycles and provide seamless, high-speed, random-access operation. The 512Mb SDRAM is designed to operate at 3.3V. An auto refresh mode is provided, along with a power-sav- ing, power-down mode. All inputs and outputs are LVTTL- compatible. SDRAMs offer substantial advances in DRAM operat- ing performance, including the ability to synchronously burst data at a high data rate with automatic column- address generation, the ability to interleave between in- ternal banks to hide precharge time and the capability to randomly change column addresses on each clock cycle during a burst access. GENERAL DESCRIPTION The 512Mb SDRAM is a high-speed CMOS, dynamic random-access memory containing 536,870,912 bits. It is internally configured as a quad-bank DRAM with a syn- chronous interface (all signals are registered on the posi- tive edge of the clock signal, CLK). Each of the x4’s 134,217,728-bit banks is organized as 8,192 rows by 4,096 columns by 4 bits. Each of the x8’s 134,217,728-bit banks is organized as 8,192 rows by 2,048 columns by 8 bits. Each of the x16’s 134,217,728-bit banks is organized as 8,192 rows by 1,024 columns by 16 bits. Read and write accesses to the SDRAM are burst ori- ented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an AC- TIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA0, BA1 select the bank; A0-A12 select the row). The address bits registered coincident with the READ or WRITE command are used to select the starting column location for the burst access. The SDRAM provides for programmable READ or WRITE burst lengths of 1, 2, 4, or 8 locations, or the full

512Mb: x4, x8, x16 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. 512MSDRAM_D.p65 – Rev. D; Pub 1/02 ©2000, Micron Technology, Inc. 512Mb: x4, x8, x16 SDRAM ADVANCE TABLE OF CONTENTS I Timing Waveforms Reads Writes

512Mb: x4, x8, x16 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. 512MSDRAM_D.p65 – Rev. D; Pub 1/02 ©2000, Micron Technology, Inc. 512Mb: x4, x8, x16 SDRAM ADVANCE FUNCTIONAL BLOCK DIAGRAM

128 Meg x 4 SDRAM

RAS# CAS# ROW- ADDRESS MUX CLK CS# WE# CKE CONTROL LOGIC COLUMN- ADDRESS COUNTER/ LATCH MODE REGISTER COMMAND DECODE A0-A12, BA0, BA1 DQM13 ADDRESS REGISTER15 4096 (x4) 8192 I/O GATING DQM MASK LOGIC READ DATA LATCH WRITE DRIVERS COLUMN DECODER BANK0 MEMORY ARRAY (8,192 x 4,096 x 4) BANK0 ROW- ADDRESS LATCH DECODER 8192 SENSE AMPLIFIERS BANK CONTROL LOGIC DQ0- DQ3 DATA INPUT REGISTER DATA OUTPUT REGISTER BANK1 BANK2 BANK3 1 1 REFRESH COUNTER

512Mb: x4, x8, x16 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. 512MSDRAM_D.p65 – Rev. D; Pub 1/02 ©2000, Micron Technology, Inc. 512Mb: x4, x8, x16 SDRAM ADVANCE FUNCTIONAL BLOCK DIAGRAM

64 Meg x 8 SDRAM

RAS# CAS# ROW- ADDRESS MUX CLK CS# WE# CKE CONTROL LOGIC COLUMN- ADDRESS COUNTER/ LATCH MODE REGISTER COMMAND DECODE A0-A12, BA0, BA1 DQM13 ADDRESS REGISTER15 2048 (x8) 8192 I/O GATING DQM MASK LOGIC READ DATA LATCH WRITE DRIVERS COLUMN DECODER BANK0 MEMORY ARRAY (8,192 x 2,048 x 8) BANK0 ROW- ADDRESS LATCH DECODER 8192 SENSE AMPLIFIERS BANK CONTROL LOGIC DQ0- DQ7 DATA INPUT REGISTER DATA OUTPUT REGISTER BANK1 BANK2 BANK3 1 1 REFRESH COUNTER

512Mb: x4, x8, x16 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. 512MSDRAM_D.p65 – Rev. D; Pub 1/02 ©2000, Micron Technology, Inc. 512Mb: x4, x8, x16 SDRAM ADVANCE FUNCTIONAL BLOCK DIAGRAM

32 Meg x 16 SDRAM

RAS# CAS# ROW- ADDRESS MUX CLK CS# WE# CKE CONTROL LOGIC COLUMN- ADDRESS COUNTER/ LATCH MODE REGISTER COMMAND DECODE A0-A12, BA0, BA1 DQML, DQMH ADDRESS REGISTER15 1024 (x16) 8192 I/O GATING DQM MASK LOGIC READ DATA LATCH WRITE DRIVERS COLUMN DECODER BANK0 MEMORY ARRAY (8,192 x 1,024 x 16) BANK0 ROW- ADDRESS LATCH DECODER 8192 SENSE AMPLIFIERS BANK CONTROL LOGIC DQ0- DQ15 DATA INPUT REGISTER DATA OUTPUT REGISTER BANK1 BANK2 BANK3 2 2 REFRESH COUNTER

512Mb: x4, x8, x16 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. 512MSDRAM_D.p65 – Rev. D; Pub 1/02 ©2000, Micron Technology, Inc. 512Mb: x4, x8, x16 SDRAM ADVANCE PIN DESCRIPTIONS PIN NUMBERS SYMBOL TYPE DESCRIPTION 38 CLK Input Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the positive edge of CLK. CLK also increments the internal burst counter and controls the output registers. 37 CKE Input Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal. Deactivating the clock provides PRECHARGE POWER-DOWN and SELF REFRESH operation (all banks idle), ACTIVE POWER-DOWN (row active in any bank) or CLOCK SUSPEND operation (burst/access in progress). CKE is synchronous except after the device enters power-down and self refresh modes, where CKE becomes asynchronous until after exiting the same mode. The input buffers, including CLK, are disabled during power-down and self refresh modes, providing low standby power. CKE may be tied HIGH.

19 CS# Input Chip Select: CS# enables (registered LOW) and disables (registered HIGH)

the command decoder. All commands are masked when CS# is registered HIGH. CS# provides for external bank selection on systems with multiple banks. CS# is considered part of the command code. 18, 17, 16 RAS#, CAS#, Input Command Inputs: RAS#, CAS#, and WE# (along with CS#) define the WE# command being entered. 39 x4, x8: DQM Input Input/Output Mask: DQM is an input mask signal for write accesses and an output enable signal for read accesses. Input data is masked when 15, 39 x16: DQML, DQM is sampled HIGH during a WRITE cycle. The output buffers are DQMH placed in a High-Z state (two-clock latency) when DQM is sampled HIGH during a READ cycle. On the x4 and x8, DQML (Pin 15) is a NC and DQMH is DQM. On the x16, DQML corresponds to DQ0-DQ7 and DQMH corresponds to DQ8-DQ15. DQML and DQMH are considered same state when referenced as DQM. 20, 21 BA0, BA1 Input Bank Address Inputs: BA0 and BA1 define to which bank the ACTIVE, READ, WRITE, or PRECHARGE command is being applied. 23-26, 29-34, 22, 35, 36 A0 –A12 Input Address Inputs: A0-A12 are sampled during the ACTIVE command (row- address A0-A12) and READ/WRITE command (column-address A0-A9, A11, A12 [x4]; A0-A9, A11 [x8]; A0-A9 [x16]; with A10 defining auto precharge) to select one location out of the memory array in the respective bank. A10 is sampled during a PRECHARGE command to determine if all banks are to be precharged (A10 [HIGH]) or bank selected by (A10 [LOW]). The address inputs also provide the op-code during a LOAD MODE REGISTER command. 2, 4, 5, 7, 8, 10, 11, 13, 42, DQ0–DQ15 x16: I/O Data Input/Output: Data bus for x16 (4, 7, 10, 13, 15, 42, 45, 48, and 51 are 44, 45, 47, 48, 50, 51, 53 NCs for x8; and 2, 4, 7, 8, 10, 13, 15, 42, 45, 47, 48, 51, and 53 are NCs for x4). 2, 5, 8, 11, 44, 47, 50, 53 DQ0 –DQ7 x8: I/O Data Input/Output: Data bus for x8 (2, 8, 47, and 53 are NCs for x4). 5, 11, 44, 50 DQ0 –DQ3 x4: I/O Data Input/Output: Data bus for x4. 40 NC – No Connect: This pin should be left unconnected. 3, 9, 43, 49 V DDQ Supply DQ Power: Isolated DQ power to the die for improved noise immunity. 6, 12, 46, 52 V SSQ Supply DQ Ground: Isolated DQ ground to the die for improved noise immunity. 1, 14, 27 V DD Supply Power Supply: +3.3V ±0.3V. 28, 41, 54 V SS Supply Ground.

512Mb: x4, x8, x16 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. 512MSDRAM_D.p65 – Rev. D; Pub 1/02 ©2000, Micron Technology, Inc.

16 Meg x 8 x 4 banks, and 8 Meg x 16 x 4 banks) are quad-

column location for the burst access. command descriptions and device operation. any command other than a COMMAND INHIBIT or NOP. MAND INHIBIT or NOP commands should be applied. device in the all banks idle state. Figure 1. The Mode Register is programmed via the LOAD loading of the Mode Register. mand to generate arbitrary burst lengths. columns equal to the burst length is effectively selected. within the page if the boundary is reached.

512Mb: x4, x8, x16 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. 512MSDRAM_D.p65 – Rev. D; Pub 1/02 ©2000, Micron Technology, Inc. 512Mb: x4, x8, x16 SDRAM ADVANCE NOTE: 1. For full-page accesses: y = 4,096 (x4); y = 2,048 2. For a burst length of two, A1-A9, A11, A12 (x4); A1-A9, A11 (x8); or A1-A9 (x16) select the block- of-two burst; A0 selects the starting column within the block. 3. For a burst length of four, A2-A9, A11, A12 (x4); A2-A9, A11 (x8); or A2-A9 (x16) select the block- of-four burst; A0-A1 select the starting column within the block. 4. For a burst length of eight, A3-A9, A11, A12 (x4); A3-A9, A11 (x8); or A3-A9 (x16) select the block- of-eight burst; A0-A2 select the starting column within the block. 5. For a full-page burst, the full row is selected and A0-A9, A11, A12 (x4); A0-A9, A11 (x8); or A0-A9 (x16) select the starting column. 6. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. 7. For a burst length of one, A0-A9, A11, A12 (x4); A0-A9, A11 (x8); or A0-A9 (x16) select the unique column to be accessed, and Mode Register bit M3 is ignored. Table 1 Burst Definition M3 = 0 Reserved Reserved Reserved Full Page M3 = 1 Reserved Reserved Reserved Reserved Operating Mode Standard Operation All other states reserved Defined Burst Type Sequential Interleaved CAS Latency Reserved Reserved Reserved Reserved Reserved Reserved Burst Length Burst LengthCAS Latency BT A9 A7 A6 A5 A4 A3A8 A2 A1 A0 Mode Register (Mx) Address Bus 9 7 654 38 2 1 0 M6-M0M8 M7 Op Mode A10A11 1011 Reserved* WB Write Burst Mode Programmed Burst Length Single Location Access *Should program to ensure compatibility with future devices. A12 Figure 1 Mode Register Definition Burst Type Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit M3. The ordering of accesses within a burst is determined by the burst length, the burst type and the starting col- umn address, as shown in Table 1. Burst Starting Column Order of Accesses Within a Burst Length Address Type = Sequential Type = Interleaved 2 00 - 1 0 - 1 11 - 0 1 - 0 A1 A0 A2 A1 A0 Full n = A0-A11/9/8 Cn, Cn + 1, Cn + 2 Page Cn + 3, Cn + 4... Not Supported (y) (location 0-y) … Cn - 1, Cn…

512Mb: x4, x8, x16 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. 512MSDRAM_D.p65 – Rev. D; Pub 1/02 ©2000, Micron Technology, Inc. 512Mb: x4, x8, x16 SDRAM ADVANCE TRUTH TABLE 1 – COMMANDS AND DQM OPERATION (Note: 1) NAME (FUNCTION) CS# RAS# CAS# WE# DQM ADDR DQs NOTES COMMAND INHIBIT (NOP) H XXXX X X NO OPERATION (NOP) L H H H X X X ACTIVE (Select bank and activate row) L L H H X Bank/Row X 3 READ (Select bank and column, and start READ burst) L H L H L/H 8 Bank/Col X 4 WRITE (Select bank and column, and start WRITE burst) L H L L L/H 8 Bank/Col Valid 4 BURST TERMINATE L H H L X X Active PRECHARGE (Deactivate row in bank or banks) L L H L X Code X 5 AUTO REFRESH or SELF REFRESH L L L H X X X 6, 7 (Enter self refresh mode) LOAD MODE REGISTER L L L L X Op-Code X 2 Write Enable/Output Enable –––– L – Active 8 Write Inhibit/Output High-Z –––– H – High-Z 8 following the Operation section; these tables provide current state/next state information. COMMANDS Truth Table 1 provides a quick reference of available commands. This is followed by a written description of each command. Three additional Truth Tables appear NOTE: 1. CKE is HIGH for all commands shown except SELF REFRESH. 2. A0-A11 define the op-code written to the Mode Register, and A12 should be driven LOW. 3. A0-A12 provide row address, and BA0, BA1 determine which bank is made active. 4. A0-A9, A11, A12 (x4); A0-A9, A11 (x8); or A0-A9 (x16) provide column address; A10 HIGH enables the auto precharge feature (nonpersistent), while A10 LOW disables the auto precharge feature; BA0, BA1 determine which bank is being read from or written to. 5. A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: All banks precharged and BA0, BA1 are “Don’t Care.” 6. This command is AUTO REFRESH if CKE is HIGH; SELF REFRESH if CKE is LOW. 7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE. 8. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock delay).

512Mb: x4, x8, x16 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. 512MSDRAM_D.p65 – Rev. D; Pub 1/02 ©2000, Micron Technology, Inc. 512Mb: x4, x8, x16 SDRAM ADVANCE COMMAND INHIBIT The COMMAND INHIBIT function prevents new com- mands from being executed by the SDRAM, regardless of whether the CLK signal is enabled. The SDRAM is effec- tively deselected. Operations already in progress are not affected. NO OPERATION (NOP) The NO OPERATION (NOP) command is used to per- form a NOP to an SDRAM which is selected (CS# is LOW). This prevents unwanted commands from being regis- tered during idle or wait states. Operations already in progress are not affected. LOAD MODE REGISTER The Mode Register is loaded via inputs A0-A11 (A12 should be driven LOW.) See Mode Register heading in the Register Definition section. The LOAD MODE REGISTER command can only be issued when all banks are idle, and a subsequent executable command cannot be issued until tMRD is met. ACTIVE The ACTIVE command is used to open (or activate) a row in a particular bank for a subsequent access. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-A12 selects the row. This row remains active (or open) for accesses until a PRECHARGE command is issued to that bank. A PRECHARGE command must be issued before opening a different row in the same bank. READ The READ command is used to initiate a burst read access to an active row. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0- A9, A11, A12 (x4); A0-A9, A11 (x8); or A0-A9 (x16) selects the starting column location. The value on input A10 determines whether or not auto precharge is used. If auto precharge is selected, the row being accessed will be precharged at the end of the READ burst; if auto precharge is not selected, the row will remain open for subsequent accesses. Read data appears on the DQs subject to the logic level on the DQM inputs two clocks earlier. If a given DQM signal was registered HIGH, the corresponding DQs will be High-Z two clocks later; if the DQM signal was registered LOW, the DQs will provide valid data. WRITE The WRITE command is used to initiate a burst write access to an active row. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0- A9, A11, A12 (x4); A0-A9, A11 (x8); or A0-A9 (x16) selects the starting column location. The value on input A10 determines whether or not auto precharge is used. If auto precharge is selected, the row being accessed will be precharged at the end of the WRITE burst; if auto precharge is not selected, the row will remain open for subsequent accesses. Input data appearing on the DQs is written to the memory array subject to the DQM input logic level appearing coincident with the data. If a given DQM signal is registered LOW, the corresponding data will be written to memory; if the DQM signal is registered HIGH, the corresponding data inputs will be ignored, and a WRITE will not be executed to that byte/column location. PRECHARGE The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row access a specified time ( tRP) after the PRECHARGE command is issued. Input A10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs BA0, BA1 select the bank. Otherwise BA0, BA1 are treated as “Don’t Care.” Once a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued to that bank. AUTO PRECHARGE Auto precharge is a feature which performs the same individual-bank PRECHARGE function described above, without requiring an explicit command. This is accom- plished by using A10 to enable auto precharge in con- junction with a specific READ or WRITE command. A PRECHARGE of the bank/row that is addressed with the READ or WRITE command is automatically performed upon completion of the READ or WRITE burst, except in the full-page burst mode, where auto precharge does not apply. Auto precharge is nonpersistent in that it is either enabled or disabled for each individual READ or WRITE command. Auto precharge ensures that the precharge is initiated at the earliest valid stage within a burst. The user must not issue another command to the same bank until the precharge time ( tRP) is completed. This is determined as if an explicit PRECHARGE command was issued at the earliest possible time, as described for each burst type in the Operation section of this data sheet.

512Mb: x4, x8, x16 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. 512MSDRAM_D.p65 – Rev. D; Pub 1/02 ©2000, Micron Technology, Inc. 512Mb: x4, x8, x16 SDRAM ADVANCE BURST TERMINATE The BURST TERMINATE command is used to trun- cate either fixed-length or full-page bursts. The most recently registered READ or WRITE command prior to the BURST TERMINATE command will be truncated, as shown in the Operation section of this data sheet. AUTO REFRESH AUTO REFRESH is used during normal operation of the SDRAM and is analogous to CAS#-BEFORE-RAS# (CBR) REFRESH in conventional DRAMs. This command is nonpersistent, so it must be issued each time a refresh is required. All active banks must be PRECHARGED prior to issuing a AUTO REFRESH comand. The AUTO RE- FRESH command should not be issued until the mini- mum tRP has been met after the PRECHARGE command as shown in the operations section. The addressing is generated by the internal refresh controller. This makes the address bits “Don’t Care” during an AUTO REFRESH command. The 512Mb SDRAM requires 8,192 AUTO REFRESH cycles every 64ms ( tREF), regardless of width option. Providing a distributed AUTO REFRESH command every 7.81µs will meet the refresh requirement and ensure that each row is refreshed. Alter- natively, 8,192 AUTO REFRESH commands can be issued in a burst at the minimum cycle rate ( tRC), once every 64ms. SELF REFRESH The SELF REFRESH command can be used to retain data in the SDRAM, even if the rest of the system is powered down. When in the self refresh mode, the SDRAM retains data without external clocking. The SELF RE- FRESH command is initiated like an AUTO REFRESH command except CKE is disabled (LOW). Once the SELF REFRESH command is registered, all the inputs to the SDRAM become “Don’t Care” with the exception of CKE, which must remain LOW. Once self refresh mode is engaged, the SDRAM pro- vides its own internal clocking, causing it to perform its own AUTO REFRESH cycles. The SDRAM must remain in self refresh mode for a minimum period equal to tRAS and may remain in self refresh mode for an indefinite period beyond that. The procedure for exiting self refresh requires a se- quence of commands. First, CLK must be stable (stable clock is defined as a signal cycling within timing con- straints specified for the clock pin) prior to CKE going back HIGH. Once CKE is HIGH, the SDRAM must have NOP commands issued (a minimum of two clocks) for tXSR because time is required for the completion of any internal refresh in progress. Upon exiting the self refresh mode, AUTO REFRESH commands must be issued every 7.81µs or less as both SELF REFRESH and AUTO REFRESH utilize the row re- fresh counter.

512Mb: x4, x8, x16 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. 512MSDRAM_D.p65 – Rev. D; Pub 1/02 ©2000, Micron Technology, Inc. 512Mb: x4, x8, x16 SDRAM ADVANCE latencies of two and three; data element n + 3 is either the last of a burst of four or the last desired of a longer burst. The 512Mb SDRAM uses a pipelined architecture and therefore does not require the 2 n rule associated with a prefetch architecture. A READ command can be initiated Figure 7 Consecutive READ Bursts on any clock cycle following a previous READ command. Full-speed random read accesses can be performed to the same bank, as shown in Figure 8, or each subsequent READ may be performed to a different bank. DON’T CARENOTE: Each READ command may be to any bank. DQM is LOW. CLK DQ DOUT n T2T1 T4 T3 T6 T5T0 COMMAND ADDRESS READ NOP NOP NOP NOP BANK, COL n NOP BANK, COL b DOUT n + 1 DOUT n + 2 DOUT n + 3 DOUT b READ X = 1 cycle CAS Latency = 2 CLK DQ DOUT n T2T1 T4 T3 T6 T5T0 COMMAND ADDRESS READ NOP NOP NOP NOP BANK, COL n NOP BANK, COL b DOUT n + 1 DOUT n + 2 DOUT n + 3 DOUT b READ NOP X = 2 cycles CAS Latency = 3

512Mb: x4, x8, x16 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. 512MSDRAM_D.p65 – Rev. D; Pub 1/02 ©2000, Micron Technology, Inc. 512Mb: x4, x8, x16 SDRAM ADVANCE Figure 8 Random READ Accesses CLK DQ T2T1 T4 T3 T6 T5T0 COMMAND ADDRESS READ NOP NOP BANK, COL n DON’T CARE DOUT n DOUT a DOUT x DOUT m READ NOTE: Each READ command may be to any bank. DQM is LOW. READ READ NOP BANK, COL a BANK, COL x BANK, COL m CLK DQ DOUT n T2T1 T4 T3 T5T0 COMMAND ADDRESS READ NOP BANK, COL n DOUT a DOUT x DOUT m READ READ READ NOP BANK, COL a BANK, COL x BANK, COL m CAS Latency = 2 CAS Latency = 3

512Mb: x4, x8, x16 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. 512MSDRAM_D.p65 – Rev. D; Pub 1/02 ©2000, Micron Technology, Inc. 512Mb: x4, x8, x16 SDRAM ADVANCE Figure 11 READ to PRECHARGE A fixed-length READ burst may be followed by, or truncated with, a PRECHARGE command to the same bank (provided that auto precharge was not activated), and a full-page burst may be truncated with a PRECHARGE command to the same bank. The PRECHARGE command should be issued x cycles before the clock edge at which the last desired data element is valid, where x equals the CAS latency minus one. This is shown in Figure 11 for each possible CAS latency; data element n + 3 is either the last of a burst of four or the last desired of a longer burst. Following the PRECHARGE command, a subsequent command to the same bank cannot be issued until tRP is met. Note that part of the row precharge time is hidden during the access of the last data element(s). In the case of a fixed-length burst being executed to completion, a PRECHARGE command issued at the opti- mum time (as described above) provides the same op- DON’T CARE CLK DQ DOUT n T2T1 T4 T3 T6 T5T0 COMMAND ADDRESS READ NOP NOP NOP NOPNOP DOUT n + 1 DOUT n + 2 DOUT n + 3 PRECHARGE ACTIVE t RP NOTE: DQM is LOW. CLK DQ DOUT n T2T1 T4 T3 T6 T5T0 COMMAND ADDRESS READ NOP NOP NOP NOPNOP DOUT n + 1 DOUT n + 2 DOUT n + 3 PRECHARGE ACTIVE t RP X = 1 cycle CAS Latency = 2 CAS Latency = 3 X = 2 cycles BANK a, COL n BANK a, ROW BANK (a or all) BANK a, COL n BANK a, ROW BANK (a or all)

512Mb: x4, x8, x16 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. 512MSDRAM_D.p65 – Rev. D; Pub 1/02 ©2000, Micron Technology, Inc. 512Mb: x4, x8, x16 SDRAM ADVANCE Figure 12 Terminating a READ Burst eration that would result from the same fixed-length burst with auto precharge. The disadvantage of the PRECHARGE command is that it requires that the com- mand and address buses be available at the appropriate time to issue the command; the advantage of the PRECHARGE command is that it can be used to truncate fixed-length or full-page bursts. Full-page READ bursts can be truncated with the BURST TERMINATE command, and fixed-length READ bursts may be truncated with a BURST TERMINATE com- mand, provided that auto precharge was not activated. The BURST TERMINATE command should be issued x cycles before the clock edge at which the last desired data element is valid, where x equals the CAS latency minus one. This is shown in Figure 12 for each possible CAS latency; data element n + 3 is the last desired data ele- ment of a longer burst. CLK DQ DOUT n T2T1 T4 T3 T6 T5T0 COMMAND ADDRESS READ NOP NOP NOP NOP BANK, COL n NOP DOUT n + 1 DOUT n + 2 DOUT n + 3 BURST TERMINATE NOP DON’T CARENOTE: DQM is LOW. CLK DQ DOUT n T2T1 T4 T3 T6 T5T0 COMMAND ADDRESS READ NOP NOP NOP BANK, COL n NOP DOUT n + 1 DOUT n + 2 DOUT n + 3 BURST TERMINATE NOP X = 1 cycle CAS Latency = 2 CAS Latency = 3 X = 2 cycles

512Mb: x4, x8, x16 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. 512MSDRAM_D.p65 – Rev. D; Pub 1/02 ©2000, Micron Technology, Inc. 512Mb: x4, x8, x16 SDRAM ADVANCE TRUTH TABLE 2 – CKE (Notes: 1-4) CKEn-1 CKEn CURRENT STATE COMMAND n ACTIONn NOTES L L Power-Down X Maintain Power-Down Self Refresh X Maintain Self Refresh Clock Suspend X Maintain Clock Suspend L H Power-Down COMMAND INHIBIT or NOP Exit Power-Down 5 Self Refresh COMMAND INHIBIT or NOP Exit Self Refresh 6 Clock Suspend X Exit Clock Suspend 7 H L All Banks Idle COMMAND INHIBIT or NOP Power-Down Entry All Banks Idle AUTO REFRESH Self Refresh Entry Reading or Writing VALID Clock Suspend Entry H H See Truth Table 3 (page 28) NOTE: 1. CKE n is the logic state of CKE at clock edge n; CKEn-1 was the state of CKE at the previous clock edge. 2. Current state is the state of the SDRAM immediately prior to clock edge n. 3. COMMAND n is the command registered at clock edge n, and ACTION n is a result of COMMAND n. 4. All states and sequences not shown are illegal or reserved. 5. Exiting power-down at clock edge n will put the device in the all banks idle state in time for clock edge n + 1 (provided that tCKS is met). 6. Exiting self refresh at clock edge n will put the device in the all banks idle state once tXSR is met. COMMAND INHIBIT or NOP commands should be issued on any clock edges occurring during the tXSR period. A minimum of two NOP commands must be provided during tXSR period. 7. After exiting clock suspend at clock edge n, the device will resume operation and recognize the next command at clock edge n + 1.

512Mb: x4, x8, x16 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. 512MSDRAM_D.p65 – Rev. D; Pub 1/02 ©2000, Micron Technology, Inc. 512Mb: x4, x8, x16 SDRAM ADVANCE TRUTH TABLE 3 – CURRENT STATE BANK n - COMMAND TO BANK n (Notes: 1-6; notes appear below and on next page) CURRENT STATE CS# RAS# CAS# WE# COMMAND (ACTION) NOTES Any H X X X COMMAND INHIBIT (NOP/Continue previous operation) L H H H NO OPERATION (NOP/Continue previous operation) L L H H ACTIVE (Select and activate row) Idle L L L H AUTO REFRESH 7 LLLL LOAD MODE REGISTER 7 L L H L PRECHARGE 11 L H L H READ (Select column and start READ burst) 10 Row Active L H L L WRITE (Select column and start WRITE burst) 10 L L H L PRECHARGE (Deactivate row in bank or banks) 8 Read L H L H READ (Select column and start new READ burst) 10 (Auto L H L L WRITE (Select column and start WRITE burst) 10 Precharge L L H L PRECHARGE (Truncate READ burst, start PRECHARGE) 8 Disabled) L H H L BURST TERMINATE 9 Write L H L H READ (Select column and start READ burst) 10 (Auto L H L L WRITE (Select column and start new WRITE burst) 10 Precharge L L H L PRECHARGE (Truncate WRITE burst, start PRECHARGE) 8 Disabled) L H H L BURST TERMINATE 9 NOTE: 1. This table applies when CKE n-1 was HIGH and CKE n is HIGH (see Truth Table 2) and after tXSR has been met (if the previous state was self refresh). 2. This table is bank-specific, except where noted, i.e., the current state is for a specific bank and the commands shown are those allowed to be issued to that bank when in that state. Exceptions are covered in the notes below. 3. Current state definitions: Idle: The bank has been precharged, and tRP has been met. Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses are in progress. Read: A READ burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. 4. The following states must not be interrupted by a command issued to the same bank. COMMAND INHIBIT or NOP commands, or allowable commands to the other bank should be issued on any clock edge occurring during these states. Allowable commands to the other bank are determined by its current state and Truth Table 3, and according to Truth Table 4. Precharging: Starts with registration of a PRECHARGE command and ends when tRP is met. Once tRP is met, the bank will be in the idle state. Row Activating: Starts with registration of an ACTIVE command and ends when tRCD is met. Once tRCD is met, the bank will be in the row active state. Read w/Auto Precharge Enabled: Starts with registration of a READ command with auto precharge enabled and ends when tRP has been met. Once tRP is met, the bank will be in the idle state. Write w/Auto Precharge Enabled: Starts with registration of a WRITE command with auto precharge enabled and ends when tRP has been met. Once tRP is met, the bank will be in the idle state.

512Mb: x4, x8, x16 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. 512MSDRAM_D.p65 – Rev. D; Pub 1/02 ©2000, Micron Technology, Inc. 512Mb: x4, x8, x16 SDRAM ADVANCE NOTE (continued): 5. The following states must not be interrupted by any executable command; COMMAND INHIBIT or NOP commands must be applied on each positive clock edge during these states. Refreshing: Starts with registration of an AUTO REFRESH command and ends when tRC is met. Once tRC is met, the SDRAM will be in the all banks idle state. Accessing Mode Register: Starts with registration of a LOAD MODE REGISTER command and ends when tMRD has been met. Once tMRD is met, the SDRAM will be in the all banks idle state. Precharging All: Starts with registration of a PRECHARGE ALL command and ends when tRP is met. Once tRP is met, all banks will be in the idle state. 6. All states and sequences not shown are illegal or reserved. 7. Not bank-specific; requires that all banks are idle. 8. May or may not be bank-specific; if all banks are to be precharged, all must be in a valid state for precharging. 9. Not bank-specific; BURST TERMINATE affects the most recent READ or WRITE burst, regardless of bank. 10. READs or WRITEs listed in the Command (Action) column include READs or WRITEs with auto precharge enabled and READs or WRITEs with auto precharge disabled. 11. Does not affect the state of the bank and acts as a NOP to that bank.

512Mb: x4, x8, x16 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. 512MSDRAM_D.p65 – Rev. D; Pub 1/02 ©2000, Micron Technology, Inc. 512Mb: x4, x8, x16 SDRAM ADVANCE TRUTH TABLE 4 – CURRENT STATE BANK n - COMMAND TO BANK m (Notes: 1-6; notes appear below and on next page) CURRENT STATE CS# RAS# CAS# WE# COMMAND (ACTION) NOTES Any H X X X COMMAND INHIBIT (NOP/Continue previous operation) L H H H NO OPERATION (NOP/Continue previous operation) Idle XXXX Any Command Otherwise Allowed to Bank m Row L L H H ACTIVE (Select and activate row) Activating, L H L H READ (Select column and start READ burst) 7 Active, or L H L L WRITE (Select column and start WRITE burst) 7 Precharging L L H L PRECHARGE Read L L H H ACTIVE (Select and activate row) (Auto L H L H READ (Select column and start new READ burst) 7, 10 Precharge L H L L WRITE (Select column and start WRITE burst) 7, 11 Disabled) L L H L PRECHARGE 9 Write L L H H ACTIVE (Select and activate row) (Auto L H L H READ (Select column and start READ burst) 7, 12 Precharge L H L L WRITE (Select column and start new WRITE burst) 7, 13 Disabled) L L H L PRECHARGE 9 Read L L H H ACTIVE (Select and activate row) (With Auto L H L H READ (Select column and start new READ burst) 7, 8, 14 Precharge) L H L L WRITE (Select column and start WRITE burst) 7, 8, 15 L L H L PRECHARGE 9 Write L L H H ACTIVE (Select and activate row) (With Auto L H L H READ (Select column and start READ burst) 7, 8, 16 Precharge) L H L L WRITE (Select column and start new WRITE burst) 7, 8, 17 L L H L PRECHARGE 9 NOTE: 1. This table applies when CKE n-1 was HIGH and CKE n is HIGH (see Truth Table 2) and after tXSR has been met (if the previous state was self refresh). 2. This table describes alternate bank operation, except where noted; i.e., the current state is for bank n and the commands shown are those allowed to be issued to bank m (assuming that bank m is in such a state that the given command is allowable). Exceptions are covered in the notes below. 3. Current state definitions: Idle: The bank has been precharged, and tRP has been met. Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses are in progress. Read: A READ burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. Read w/Auto Precharge Enabled: Starts with registration of a READ command with auto precharge enabled, and ends when tRP has been met. Once tRP is met, the bank will be in the idle state. Write w/Auto Precharge Enabled: Starts with registration of a WRITE command with auto precharge enabled, and ends when tRP has been met. Once tRP is met, the bank will be in the idle state.

512Mb: x4, x8, x16 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. 512MSDRAM_D.p65 – Rev. D; Pub 1/02 ©2000, Micron Technology, Inc. 512Mb: x4, x8, x16 SDRAM ADVANCE NOTE (continued): 4. AUTO REFRESH, SELF REFRESH and LOAD MODE REGISTER commands may only be issued when all banks are idle. 5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current state only. 6. All states and sequences not shown are illegal or reserved. 7. READs or WRITEs to bank m listed in the Command (Action) column include READs or WRITEs with auto precharge enabled and READs or WRITEs with auto precharge disabled. 8. CONCURRENT AUTO PRECHARGE: Bank n will initiate the auto precharge command when its burst has been interrupted by bank m’s burst. 9. Burst in bank n continues as initiated. 10. For a READ without auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt the READ on bank n, CAS latency later (Figure 7). 11. For a READ without auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will interrupt the READ on bank n when registered (Figures 9 and 10). DQM should be used one clock prior to the WRITE command to prevent bus contention. 12. For a WRITE without auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt the WRITE on bank n when registered (Figure 17), with the data-out appearing CAS latency later. The last valid WRITE to bank n will be data-in registered one clock prior to the READ to bank m. 13. For a WRITE without auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will interrupt the WRITE on bank n when registered (Figure 15). The last valid WRITE to bank n will be data-in registered one clock prior to the READ to bank m. 14. For a READ with auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt the READ on bank n, CAS latency later. The PRECHARGE to bank n will begin when the READ to bank m is registered (Figure 24). 15. For a READ with auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will interrupt the READ on bank n when registered. DQM should be used two clocks prior to the WRITE command to prevent bus contention. The PRECHARGE to bank n will begin when the WRITE to bank m is registered (Figure 25). 16. For a WRITE with auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt the WRITE on bank n when registered, with the data-out appearing CAS latency later. The PRECHARGE to bank n will begin after tWR is met, where tWR begins when the READ to bank m is registered. The last valid WRITE to bank n will be data-in registered one clock prior to the READ to bank m (Figure 26). 17. For a WRITE with auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will interrupt the WRITE on bank n when registered. The PRECHARGE to bank n will begin after tWR is met, where tWR begins when the WRITE to bank m is registered. The last valid WRITE to bank n will be data registered one clock prior to the WRITE to bank m (Figure 27).

512Mb: x4, x8, x16 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. 512MSDRAM_D.p65 – Rev. D; Pub 1/02 ©2000, Micron Technology, Inc. 512Mb: x4, x8, x16 SDRAM ADVANCE DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS (Notes: 1, 5, 6; notes appear on page 35) (VDD, VDDQ = +3.3V ±0.3V) PARAMETER/CONDITION SYMBOL MIN MAX UNITS NOTES Supply Voltage V DD, VDDQ 3 3.6 V Input High Voltage: Logic 1; All inputs V IH 2V DD + 0.3 V 22 Input Low Voltage: Logic 0; All inputs V IL -0.3 0.8 V 22 Input Leakage Current: Any input 0V ≤ VIN ≤ VDD II -5 5 µA (All other pins not under test = 0V) Output Leakage Current: DQs are disabled; I OZ -5 5 µA 0V ≤ VOUT ≤ VDDQ Output Levels: V OH 2.4 – V2 6 Output High Voltage (IOUT = -4mA) Output Low Voltage (IOUT = 4mA) V OL – 0.4 V 26 ABSOLUTE MAXIMUM RATINGS* Voltage on VDD, VDDQ Supply Voltage on Inputs, NC or I/O Pins Operating Temperature, *Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. MAX IDD SPECIFICATIONS AND CONDITIONS (Notes: 1, 5, 6, 11, 13; notes appear on page 35) (V DD, VDDQ = +3.3V ±0.3V) PARAMETER/CONDITION SYMBOL -7E -75 UNITS NOTES Operating Current: Active Mode; I DD1 TBD TBD mA 3, 18, Burst = 1; READ or WRITE; tRC = tRC (MIN) 19, 29 Standby Current: Power-Down Mode; I DD2 TBD TBD mA 29 CKE = LOW; All banks idle Standby Current: Active Mode; CS# = HIGH; I DD3 TBD TBD mA 3, 12, CKE = HIGH; All banks active after tRCD met; 19, 29 No accesses in progress Operating Current: Burst Mode; Continuous burst; I DD4 TBD TBD mA 3, 18, READ or WRITE; All banks active 19, 29 Auto Refresh Current: tRFC = tRFC (MIN) I DD5 TBD TBD mA 3, 12, CS# = HIGH; CKE = HIGH 18, 19, tRFC = 7.81µs I DD6 TBD TBD mA 29,30 Self Refresh Current: CKE ≤ 0.2V Standard I DD7 TBD TBD mA 4 Low power (L) I DD7 TBD TBD mA

512Mb: x4, x8, x16 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. 512MSDRAM_D.p65 – Rev. D; Pub 1/02 ©2000, Micron Technology, Inc. 512Mb: x4, x8, x16 SDRAM ADVANCE CAPACITANCE (Note: 2; notes appear on page 35) PARAMETER SYMBOL MIN MAX UNITS Input Capacitance: CLK C I1 2.5 3.5 pF Input Capacitance: All other input-only pins C I2 2.5 3.8 pF Input/Output Capacitance: DQs C IO 4.0 6.0 pF AC CHARACTERISTICS -7E -75 PARAMETER SYMBOL MIN MAX MIN MAX UNITS NOTES Access time from CLK (pos. edge) CL = 3 tAC(3) 5.4 5.4 ns 27 CL = 2 tAC(2) 5.4 6 ns Address hold time tAH 0.8 0.8 ns Address setup time tAS 1.5 1.5 ns CLK high-level width tCH 2.5 2.5 ns CLK low-level width tCL 2.5 2.5 ns Clock cycle time CL = 3 tCK(3) 7 7.5 ns 23 CL = 2 tCK(2) 7.5 10 ns 23 CKE hold time tCKH 0.8 0.8 ns CKE setup time tCKS 1.5 1.5 ns CS#, RAS#, CAS#, WE#, DQM hold time tCMH 0.8 0.8 ns CS#, RAS#, CAS#, WE#, DQM setup time tCMS 1.5 1.5 ns Data-in hold time tDH 0.8 0.8 ns Data-in setup time tDS 1.5 1.5 ns Data-out high-impedance time CL = 3 tHZ(3) 5.4 5.4 ns 10 CL = 2 tHZ(2) 5.4 6 ns 10 Data-out low-impedance time tLZ 1 1 ns Data-out hold time (load) tOH 2.7 2.7 ns Data-out hold time (no load) tOHN 1.8 1.8 ns 28 ACTIVE to PRECHARGE command tRAS 37 120,000 44 120,000 ns ACTIVE to ACTIVE command period tRC 60 66 ns ACTIVE to READ or WRITE delay tRCD 15 20 ns Refresh period (8,192 rows) tREF 64 64 ms AUTO REFRESH period tRFC 66 66 ns PRECHARGE command period tRP 15 20 ns ACTIVE bank a to ACTIVE bank b command tRRD 14 15 ns Transition time tT 0.3 1.2 0.3 1.2 ns 7 WRITE recovery time tWR 1 CLK + 1 CLK + – 24 7ns 7.5ns 14 14 15 ns 25 Exit SELF REFRESH to ACTIVE command tXSR 67 75 ns 20 ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (Notes: 5, 6, 8, 9, 11; notes appear on page 35)

512Mb: x4, x8, x16 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. 512MSDRAM_D.p65 – Rev. D; Pub 1/02 ©2000, Micron Technology, Inc. 512Mb: x4, x8, x16 SDRAM ADVANCE AC FUNCTIONAL CHARACTERISTICS (Notes: 5, 6, 7, 8, 9, 11; notes appear on page 35) PARAMETER SYMBOL -7E -75 UNITS NOTES READ/WRITE command to READ/WRITE command tCCD 1 1 tCK 17 CKE to clock disable or power-down entry mode tCKED 1 1 tCK 14 CKE to clock enable or power-down exit setup mode tPED 1 1 tCK 14 DQM to input data delay tDQD 0 0 tCK 17 DQM to data mask during WRITEs tDQM 0 0 tCK 17 DQM to data high-impedance during READs tDQZ 2 2 tCK 17 WRITE command to input data delay tDWD 0 0 tCK 17 Data-in to ACTIVE command tDAL 4 5 tCK 15, 21 Data-in to PRECHARGE command tDPL 2 2 tCK 16, 21 Last data-in to burst STOP command tBDL 1 1 tCK 17 Last data-in to new READ/WRITE command tCDL 1 1 tCK 17 Last data-in to PRECHARGE command tRDL 2 2 tCK 16, 21 LOAD MODE REGISTER command to ACTIVE or REFRESH command tMRD 2 2 tCK 26 Data-out to high-impedance from PRECHARGE command CL = 3 tROH(3) 3 3 tCK 17 CL = 2 tROH(2) 2 2 tCK 17

512Mb: x4, x8, x16 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. 512MSDRAM_D.p65 – Rev. D; Pub 1/02 ©2000, Micron Technology, Inc. 512Mb: x4, x8, x16 SDRAM ADVANCE 13. I DD specifications are tested after the device is properly initialized. 14. Timing actually specified by tCKS; clock(s) specified as a reference only at minimum cycle rate. 15. Timing actually specified by tWR plus tRP; clock(s) specified as a reference only at minimum cycle rate. 16. Timing actually specified by tWR. 17. Required clocks are specified by JEDEC functional- ity and are not dependent on any timing param- eter. 18. The I DD current will increase or decrease in a proportional amount by the amount the frequency is altered for the test condition. 19. Address transitions average one transition every two clocks. 20. CLK must be toggled a minimum of two times during this period. 21. Based on tCK = 7.5ns for -75 and -7E. 22. VIH overshoot: VIH (MAX) = VDDQ + 2V for a pulse width ≤ 3ns, and the pulse width cannot be greater than one third of the cycle rate. V IL undershoot: VIL (MIN) = -2V for a pulse width ≤ 3ns. 23. The clock frequency must remain constant (stable clock is defined as a signal cycling within timing constraints specified for the clock pin) during access or precharge states (READ, WRITE, includ- ing tWR, and PRECHARGE commands). CKE may be used to reduce the data rate. 24. Auto precharge mode only. The precharge timing budget (tRP) begins 7.5ns/7ns after the first clock delay, after the last WRITE is executed. 25. Precharge mode only. 26. JEDEC and PC100, PC133 specify three clocks. 27. tAC for -75/-7E at CL = 3 with no load is 4.6ns and is guaranteed by design. 28. Parameter guaranteed by design. 29. For -75, CL = 3, tCK = 7.5ns; For -7E, CL = 2, tCK = 7.5ns 30. CKE is HIGH during refresh command period tRFC(MIN) else CKE is LOW . The IDD6 limit is actually a nominal value and does not result in a fail value. NOTES 1. All voltages referenced to V SS. 2. This parameter is sampled. V DD, VDDQ = +3.3V; f = 1 MHz, TA = 25°C; pin under test biased at 1.4V. 3. I DD is dependent on output loading and cycle rates.Specified values are obtained with minimum cycle time and the outputs open. 4. Enables on-chip refresh and address counters. 5. The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range (0°C ≤ T A ≤ 70°C) is ensured. 6. An initial pause of 100µs is required after power- up, followed by two AUTO REFRESH commands, before proper device operation is ensured. (V DD and VDDQ must be powered up simultaneously. V SS and VSSQ must be at same potential.) The two AUTO REFRESH command wake-ups should be repeated any time the tREF refresh requirement is exceeded. 7. AC characteristics assume tT = 1ns. 8. In addition to meeting the transition rate specifi- cation, the clock and CKE must transit between V IH and VIL (or between VIL and VIH) in a monotonic manner. 9. Outputs measured at 1.5V with equivalent load: Q 50pF 10. tHZ defines the time at which the output achieves the open circuit condition; it is not a reference to V OH or VOL. The last valid data element will meet tOH before going High-Z. 11. AC timing and I DD tests have V IL = 0V and VIH = 3V, with timing referenced to 1.5V crossover point. If the input transition time is longer than 1 ns, then the timing is referenced at V IL (MAX) and VIH (MIN) and no longer at the 1.5V crossover point. 12. Other input signals are allowed to transition no more than once every two clocks and are otherwise at valid V IH or VIL levels.

512Mb: x4, x8, x16 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. 512MSDRAM_D.p65 – Rev. D; Pub 1/02 ©2000, Micron Technology, Inc. 512Mb: x4, x8, x16 SDRAM ADVANCE -7E -75 SYMBOL* MIN MAX MIN MAX UNITS TIMING PARAMETERS -7E -75 SYMBOL* MIN MAX MIN MAX UNITS tAH 0.8 0.8 ns tAS 1.5 1.5 ns tCH 2.5 2.5 ns tCL 2.5 2.5 ns tCK (3) 7 7.5 ns tCK (2) 7.5 10 ns tCKH 0.8 0.8 ns INITIALIZE AND LOAD MODE REGISTER 2 *CAS latency indicated in parentheses. NOTE: 1. The Mode Register may be loaded prior to the AUTO REFRESH cycles if desired. 2. If CS is HIGH at clock high time, all commands applied are NOP, with CKE a “Don’t Care.” 3. JEDEC and PC100 specify three clocks. 4. Outputs are guaranteed High-Z after command is issued. 5. A12 should be a LOW at tP + 1. tCKS 1.5 1.5 ns tCMH 0.8 0.8 ns tCMS 1.5 1.5 ns tMRD3 22 tCK tRFC 66 66 ns tRP 15 20 ns tCH tCLtCK CKE CK COMMAND DQ BA0, BA1 BANK tRFC tMRD tRFC AUTO REFRESH AUTO REFRESH Program Mode Register 1, 3, 4 tCMHtCMS Precharge all banks tRP )tCKS Power-up: VDD and CLK stable T = 100µs MIN PRECHARGE NOP AUTO REFRESH NOPLOAD MODE REGISTER ACTIVENOP NOP NOP AUTO REFRESH ALL BANKS High-Z tCKH DQM/ DQML, DQMH ()() ()() ()() ()()()() NOP tCMHtCMS tCMHtCMS A0-A9, A11, A12 ROW tAH 5tAS CODE A10 ROW tAHtAS CODE ALL BANKS SINGLE BANK DON’T CARE UNDEFINED T0 T1 Tn + 1 To + 1 Tp + 1 Tp + 2 Tp + 3

512Mb: x4, x8, x16 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. 512MSDRAM_D.p65 – Rev. D; Pub 1/02 ©2000, Micron Technology, Inc. 512Mb: x4, x8, x16 SDRAM ADVANCE TIMING PARAMETERS -7E -75 SYMBOL* MIN MAX MIN MAX UNITS tAH 0.8 0.8 ns tAS 1.5 1.5 ns tCH 2.5 2.5 ns tCL 2.5 2.5 ns tCK (3) 7 7.5 ns NOTE: 1. Violating refresh requirements during power-down may result in a loss of data. POWER-DOWN MODE 1 tCH tCLtCK Two clock cycles CKE CLK DQ All banks idle, enter power-down mode Precharge all active banks Input buffers gated off while in power-down mode Exit power-down mode DON’T CARE tCKS tCKS COMMAND tCMHtCMS PRECHARGE NOP NOP ACTIVENOP All banks idle BA0, BA1 BANKBANK(S) High-Z tAHtAS tCKHtCKS DQM/ DQML, DQMH A0-A9, A11, A12 ROW ALL BANKS SINGLE BANK A10 ROW T0 T1 T2 Tn + 1 Tn + 2 *CAS latency indicated in parentheses. -7E -75 SYMBOL* MIN MAX MIN MAX UNITS tCK (2) 7.5 10 ns tCKH 0.8 0.8 ns tCKS 1.5 1.5 ns tCMH 0.8 0.8 ns tCMS 1.5 1.5 ns

512Mb: x4, x8, x16 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. 512MSDRAM_D.p65 – Rev. D; Pub 1/02 ©2000, Micron Technology, Inc. 512Mb: x4, x8, x16 SDRAM ADVANCE TIMING PARAMETERS -7E -75 SYMBOL* MIN MAX MIN MAX UNITS tAC (3) 5.4 5.4 ns tAC (2) 5.4 6 ns tAH 0.8 0.8 ns tAS 1.5 1.5 ns tCH 2.5 2.5 ns tCL 2.5 2.5 ns tCK (3) 7 7.5 ns tCK (2) 7.5 10 ns tCKH 0.8 0.8 ns CLOCK SUSPEND MODE 1 tCH tCLtCK tAC tLZ DQM/ DQML, DQMH CLK A0-A9, A11, A12 DQ BA0, BA1 A10 tOH DOUT m tAHtAS tAHtAS tAHtAS BANK tDH DOUT e tAC tHZ DOUT m + 1 COMMAND tCMHtCMS NOPNOP NOP NOPNOPREAD WRITE DON’T CARE CKE tCKS tCKH BANK COLUMN m tDS DOUT e + 1 NOP tCKHtCKS tCMHtCMS

2 COLUMN e2

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 NOTE: 1. For this example, the burst length = 2, the CAS latency = 3, and AUTO PRECHARGE is disabled. 2. x16: A11 and A12 = “Don’t Care” x8: A12 = “Don’t Care” *CAS latency indicated in parentheses. -7E -75 SYMBOL* MIN MAX MIN MAX UNITS tCKS 1.5 1.5 ns tCMH 0.8 0.8 ns tCMS 1.5 1.5 ns tDH 0.8 0.8 ns tDS 1.5 1.5 ns tHZ (3) 5.4 5.4 ns tHZ (2) 5.4 6 ns tLZ 1 1 ns tOH 2.7 2.7 ns

512Mb: x4, x8, x16 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. 512MSDRAM_D.p65 – Rev. D; Pub 1/02 ©2000, Micron Technology, Inc. 512Mb: x4, x8, x16 SDRAM ADVANCE AUTO REFRESH MODE tCH tCL tCK CKE CLK DQ tRFC RFC tRP COMMAND tCMHtCMS NOPNOP BANK ACTIVEAUTO REFRESH NOPNOPPRECHARGE Precharge all active banks AUTO REFRESH t High-Z BA0, BA1 BANK(S) tAHtAS tCKHtCKS NOP DQM / DQML, DQMH A0-A9, A11, A12 ROW ALL BANKS SINGLE BANK A10 ROW DON’T CARE T0 T1 T2 Tn + 1 To + 1 *CAS latency indicated in parentheses. -7E -75 SYMBOL* MIN MAX MIN MAX UNITS tCKH 0.8 0.8 ns tCKS 1.5 1.5 ns tCMH 0.8 0.8 ns tCMS 1.5 1.5 ns tRFC 66 66 ns tRP 15 20 ns TIMING PARAMETERS -7E -75 SYMBOL* MIN MAX MIN MAX UNITS tAH 0.8 0.8 ns tAS 1.5 1.5 ns tCH 2.5 2.5 ns tCL 2.5 2.5 ns tCK (3) 7 7.5 ns tCK (2) 7.5 10 ns

512Mb: x4, x8, x16 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. 512MSDRAM_D.p65 – Rev. D; Pub 1/02 ©2000, Micron Technology, Inc. 512Mb: x4, x8, x16 SDRAM ADVANCE TIMING PARAMETERS -7E -75 SYMBOL* MIN MAX MIN MAX UNITS tAH 0.8 0.8 ns tAS 1.5 1.5 ns tCH 2.5 2.5 ns tCL 2.5 2.5 ns tCK (3) 7 7.5 ns tCK (2) 7.5 10 ns tCKH 0.8 0.8 ns SELF REFRESH MODE tCH tCL tCK tRP CKE CLK DQ Enter self refresh modePrecharge all active banks tXSR CLK stable prior to exiting self refresh mode Exit self refresh mode (Restart refresh time base) DON’T CARE COMMAND tCMHtCMS AUTO REFRESHPRECHARGE NOP NOP or COMMAND INHIBIT BA0, BA1 BANK(S) High-Z tCKS AHAS AUTO REFRESH tRAS(MIN)1 tCKHtCKS DQM/ DQML, DQMH tt A0-A9, A11,A12 ALL BANKS SINGLE BANK A10 T0 T1 T2 Tn + 1 To + 1 To + 2 ( *CAS latency indicated in parentheses. -7E -75 SYMBOL* MIN MAX MIN MAX UNITS tCKS 1.5 1.5 ns tCMH 0.8 0.8 ns tCMS 1.5 1.5 ns tRAS 37 120,000 44 120,000 ns tRP 15 20 ns tXSR 67 75 ns NOTES: 1. No maximum time limit for Self Refresh. tRAS(MAX) applies to non-Self Refresh mode. 2. tXSR requires minimum of two clocks regardless of frequency or timing.

512Mb: x4, x8, x16 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. 512MSDRAM_D.p65 – Rev. D; Pub 1/02 ©2000, Micron Technology, Inc. 512Mb: x4, x8, x16 SDRAM ADVANCE TIMING PARAMETERS -7E -75 SYMBOL* MIN MAX MIN MAX UNITS tAC (3) 5.4 5.4 ns tAC (2) 5.4 6 ns tAH 0.8 0.8 ns tAS 1.5 1.5 ns tCH 2.5 2.5 ns tCL 2.5 2.5 ns tCK (3) 7 7.5 ns tCK (2) 7.5 10 ns tCKH 0.8 0.8 ns tCKS 1.5 1.5 ns READ – WITHOUT AUTO PRECHARGE 1 ALL BANKS tCH tCLtCK tAC tLZ tRP tRAS tRCD CAS Latency tRC DQM/ DQML, DQMH CKE CLK A0-A9, A11, A12 DQ BA0, BA1 A10 tOH DOUT m tCMHtCMS tAHtAS tAHtAS tAHtAS ROW ROW BANK BANK BANK ROW ROW BANK tHZ tOH DOUT m + 3 tAC tOH tAC tOH tAC DOUT m + 2DOUT m + 1 COMMAND tCMHtCMS PRECHARGENOPNOP NOPACTIVE NOP READ NOP ACTIVE DISABLE AUTO PRECHARGE SINGLE BANK DON’T CARE UNDEFINED tCKHtCKS COLUMN m2 T0 T1 T2 T4 T3 T5 T6 T7 T8 NOTE: 1. For this example, the burst length = 4, the CAS latency = 2, and the READ burst is followed by a “manual” PRECHARGE. 2. x16: A11 and A12 = “Don’t Care” x8: A12 = “Don’t Care” *CAS latency indicated in parentheses. -7E -75 SYMBOL* MIN MAX MIN MAX UNITS tCMH 0.8 0.8 ns tCMS 1.5 1.5 ns tHZ (3) 5.4 5.4 ns tHZ (2) 5.4 6 ns tLZ 1 1 ns tOH 2.7 2.7 ns tRAS 37 120,000 44 120,000 ns tRC 60 66 ns tRCD 15 20 ns tRP 15 20 ns

512Mb: x4, x8, x16 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. 512MSDRAM_D.p65 – Rev. D; Pub 1/02 ©2000, Micron Technology, Inc. 512Mb: x4, x8, x16 SDRAM ADVANCE TIMING PARAMETERS -7E -75 SYMBOL* MIN MAX MIN MAX UNITS tAC (3) 5.4 5.4 ns tAC (2) 5.4 6 ns tAH 0.8 0.8 ns tAS 1.5 1.5 ns tCH 2.5 2.5 ns tCL 2.5 2.5 ns tCK (3) 7 7.5 ns tCK (2) 7.5 10 ns tCKH 0.8 0.8 ns tCKS 1.5 1.5 ns READ – WITH AUTO PRECHARGE 1 ENABLE AUTO PRECHARGE tCH tCLtCK tAC tLZ tRP tRAS tRCD CAS Latency tRC DQM/ DQML, DQMH CKE CLK A0-A9, A11, A12 DQ BA0, BA1 A10 tOH DOUT m tCMHtCMS tAHtAS tAHtAS tAHtAS ROW ROW BANK BANK ROW ROW BANK DON’T CARE UNDEFINED tHZ tOH DOUT m + 3 tAC tOH tAC tOH tAC DOUT m + 2DOUT m + 1 COMMAND tCMHtCMS NOPNOP NOPACTIVE NOP READ NOP ACTIVENOP tCKHtCKS COLUMN m2 T0 T1 T2 T4 T3 T5 T6 T7 T8 NOTE: 1. For this example, the burst length = 4, and the CAS latency = 2. 2. x16: A11 and A12 = “Don’t Care” x8: A12 = “Don’t Care” *CAS latency indicated in parentheses. -7E -75 SYMBOL* MIN MAX MIN MAX UNITS tCMH 0.8 0.8 ns tCMS 1.5 1.5 ns tHZ (3) 5.4 5.4 ns tHZ (2) 5.4 6 ns tLZ 1 1 ns tOH 2.7 2.7 ns tRAS 37 120,000 44 120,000 ns tRC 60 66 ns tRCD 15 20 ns tRP 15 20 ns

512Mb: x4, x8, x16 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. 512MSDRAM_D.p65 – Rev. D; Pub 1/02 ©2000, Micron Technology, Inc. 512Mb: x4, x8, x16 SDRAM ADVANCE SINGLE READ – WITHOUT AUTO PRECHARGE 1 TIMING PARAMETERS -7E -75 SYMBOL* MIN MAX MIN MAX UNITS tAC (3) 5.4 5.4 ns tAC (2) 5.4 6 ns tAH 0.8 0.8 ns tAS 1.5 1.5 ns tCH 2.5 2.5 ns tCL 2.5 2.5 ns tCK (3) 7 7.5 ns tCK (2) 7.5 10 ns tCKH 0.8 0.8 ns tCKS 1.5 1.5 ns tCMH 0.8 0.8 ns tCMS 1.5 1.5 ns tHZ (3) 5.4 5.4 ns tHZ (2) 5.4 6 ns tLZ 1 1 ns tOH 2.7 2.7 ns tRAS 37 120,000 44 120,000 ns tRC 60 66 ns tRCD 15 20 ns tRP 15 20 ns *CAS latency indicated in parentheses. ALL BANKS tCH tCLtCK tAC tLZ tRP tRAS tRCD CAS Latency tRC tOH DOUT m tCMHtCMS tAHtAS tAHtAS tAHtAS ROW ROW BANK BANK(S) BANK ROW ROW BANK tHZ tCMHtCMS NOPNOPNOP PRECHARGEACTIVE NOP READ ACTIVE NOP DISABLE AUTO PRECHARGE SINGLE BANKS DON’T CARE UNDEFINED COLUMN m2 tCKHtCKS T0 T1 T2 T3 T4 T5 T6 T7 T8 DQM/ DQML, DQMH CKE CLK A0-A9, A11, A12 DQ BA0, BA1 A10 COMMAND -7E -75 SYMBOL* MIN MAX MIN MAX UNITS NOTE: 1. For this example, the burst length = 1, the CAS latency = 2, and the READ burst is followed by a “manual” PRECHARGE. 2. x16: A11 and A12 = “Don’t Care” x8: A12 = “Don’t Care”

512Mb: x4, x8, x16 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. 512MSDRAM_D.p65 – Rev. D; Pub 1/02 ©2000, Micron Technology, Inc. 512Mb: x4, x8, x16 SDRAM ADVANCE NOTE: 1. For this example, the burst length = 1, and the CAS latency = 2. 2. x16: A11 and A12 = “Don’t Care” x8: A12 = “Don’t Care” 3. READ command not allowed else tRAS would be violated *CAS latency indicated in parentheses. -7E -75 SYMBOL* MIN MAX MIN MAX UNITS tCMH 0.8 0.8 ns tCMS 1.5 1.5 ns tHZ (3) 5.4 5.4 ns tHZ (2) 5.4 6 ns tLZ 1 1 ns tOH 2.7 2.7 ns tRAS 37 120,000 44 120,000 ns tRC 60 66 ns tRCD 15 20 ns tRP 15 20 ns TIMING PARAMETERS -7E -75 SYMBOL* MIN MAX MIN MAX UNITS tAC (3) 5.4 5.4 ns tAC (2) 5.4 6 ns tAH 0.8 0.8 ns tAS 1.5 1.5 ns tCH 2.5 2.5 ns tCL 2.5 2.5 ns tCK (3) 7 7.5 ns tCK (2) 7.5 10 ns tCKH 0.8 0.8 ns tCKS 1.5 1.5 ns SINGLE READ – WITH AUTO PRECHARGE 1 ENABLE AUTO PRECHARGE tCH tCLtCK tRPtRAS tRCD CAS Latency tRC DQM/ DQML, DQMH CKE CLK A0-A9, A11 DQ BA0, BA1 A10 tCMHtCMS tAHtAS tAHtAS tAHtAS ROW ROW BANK BANK ROW ROW BANK DON’T CARE UNDEFINED tHZ tOH DOUT m tAC COMMAND tCMHtCMS NOP3 READACTIVE NOP NOP 3 ACTIVENOP tCKHtCKS COLUMN m2 T0 T1 T2 T4 T3 T5 T6 T7 T8 NOP NOP

512Mb: x4, x8, x16 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. 512MSDRAM_D.p65 – Rev. D; Pub 1/02 ©2000, Micron Technology, Inc. 512Mb: x4, x8, x16 SDRAM ADVANCE TIMING PARAMETERS -7E -75 SYMBOL* MIN MAX MIN MAX UNITS tAC (3) 5.4 5.4 ns tAC (2) 5.4 6 ns tAH 0.8 0.8 ns tAS 1.5 1.5 ns tCH 2.5 2.5 ns tCL 2.5 2.5 ns tCK (3) 7 7.5 ns tCK (2) 7.5 10 ns tCKH 0.8 0.8 ns tCKS 1.5 1.5 ns ALTERNATING BANK READ ACCESSES 1 ENABLE AUTO PRECHARGE tCH tCLtCK tAC tLZ DQM/ DQML, DQMH CLK A0-A9, A11, A12 DQ BA0, BA1 A10 tOH DOUT m tCMHtCMS tAHtAS tAHtAS tAHtAS ROW ROW ROW ROW DON’T CARE UNDEFINED tOH DOUT m + 3 tAC tOH tAC tOH tAC DOUT m + 2DOUT m + 1 COMMAND tCMHtCMS NOP NOPACTIVE NOP READ NOP ACTIVE tOH DOUT b tAC tAC READ ENABLE AUTO PRECHARGE ROW ACTIVE ROW BANK 0 BANK 0 BANK 3 BANK 3 BANK 0 CKE tCKHtCKS COLUMN m2 COLUMN b 2 T0 T1 T2 T4 T3 T5 T6 T7 T8 tRP - BANK 0 tRAS - BANK 0 tRCD - BANK 0 tRCD - BANK 0CAS Latency - BANK 0 tRCD - BANK 1 CAS Latency - BANK 1 t t RC - BANK 0 RRD NOTE: 1. For this example, the burst length = 4, and the CAS latency = 2. 2. x16: A11 and A12 = “Don’t Care” x8: A12 = “Don’t Care” *CAS latency indicated in parentheses. -7E -75 SYMBOL* MIN MAX MIN MAX UNITS tCMH 0.8 0.8 ns tCMS 1.5 1.5 ns tLZ 1 1 ns tOH 2.7 2.7 ns tRAS 37 120,000 44 120,000 ns tRC 60 66 ns tRCD 15 20 ns tRP 15 20 ns tRRD 14 15 ns

512Mb: x4, x8, x16 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. 512MSDRAM_D.p65 – Rev. D; Pub 1/02 ©2000, Micron Technology, Inc. 512Mb: x4, x8, x16 SDRAM ADVANCE TIMING PARAMETERS -7E -75 SYMBOL* MIN MAX MIN MAX UNITS tAC (3) 5.4 5.4 ns tAC (2) 5.4 6 ns tAH 0.8 0.8 ns tAS 1.5 1.5 ns tCH 2.5 2.5 ns tCL 2.5 2.5 ns tCK (3) 7 7.5 ns tCK (2) 7.5 10 ns tCKH 0.8 0.8 ns READ – FULL-PAGE BURST 1 NOTE: 1. For this example, the CAS latency = 2. 2. x16: A11 and A12 = “Don’t Care” x8: A12 = “Don’t Care” 3. Page left open; no tRP. *CAS latency indicated in parentheses. -7E -75 SYMBOL* MIN MAX MIN MAX UNITS tCKS 1.5 1.5 ns tCMH 0.8 0.8 ns tCMS 1.5 1.5 ns tHZ (3) 5.4 5.4 ns tHZ (2) 5.4 6 ns tLZ 1 1 ns tOH 2.7 2.7 ns tRCD 15 20 ns tCH tCL tCK tAC tLZ tRCD CAS Latency DQM/ DQML, DQMH CKE CLK A0-A9, A11, A12 DQ BA0, BA1 A10 tOH DOUT m tCMHtCMS tAHtAS tAHtAS tAC tOH DOUT m+1 ROW ROW tHZ tAC tOH DOUT m+1 tAC tOH DOUT m+2 tAC tOH DOUT m-1 tAC tOH Dout m Full-page burst does not self-terminate. Can use BURST TERMINATE command. Full page completed 1,024 (x16) locations within same row 2,048 (x8) locations within same row 4,096 (x4) locations within same row DON’T CARE UNDEFINED COMMAND tCMHtCMS NOPNOP NOPACTIVE NOP READ NOP BURST TERMNOP NOP NOP tAHtAS BANK BANK tCKHtCKS COLUMN m2 T0 T1 T2 T4 T3 T5 T6 Tn + 1 Tn + 2 Tn + 3 Tn + 4

512Mb: x4, x8, x16 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. 512MSDRAM_D.p65 – Rev. D; Pub 1/02 ©2000, Micron Technology, Inc. 512Mb: x4, x8, x16 SDRAM ADVANCE TIMING PARAMETERS -7E -75 SYMBOL* MIN MAX MIN MAX UNITS tAC (3) 5.4 5.4 ns tAC (2) 5.4 6 ns tAH 0.8 0.8 ns tAS 1.5 1.5 ns tCH 2.5 2.5 ns tCL 2.5 2.5 ns tCK (3) 7 7.5 ns tCK (2) 7.5 10 ns tCKH 0.8 0.8 ns READ – DQM OPERATION 1 tCH tCLtCK tRCD CAS Latency DQM/ DQML, DQMH CKE CLK A0-A9, A11, A12 DQ BA0, BA1 A10 tCMS ROW BANK ROW BANK DON’T CARE UNDEFINED tAC LZ DOUT m tOH DOUT m + 3DOUT m + 2 t tHZ LZt tCMH COMMAND NOPNOP NOPACTIVE NOP READ NOPNOP NOP tHZ tAC tOH tAC tOH tAHtAS tCMS tCMH tAHtAS tAHtAS tCKHtCKS ENABLE AUTO PRECHARGE DISABLE AUTO PRECHARGE COLUMN m2 T0 T1 T2 T4 T3 T5 T6 T7 T8 NOTE: 1. For this example, the burst length = 4, and the CAS latency = 2. 2. x16: A11 and A12 = “Don’t Care” x8: A12 = “Don’t Care” *CAS latency indicated in parentheses. -7E -75 SYMBOL* MIN MAX MIN MAX UNITS tCKS 1.5 1.5 ns tCMH 0.8 0.8 ns tCMS 1.5 1.5 ns tHZ (3) 5.4 5.4 ns tHZ (2) 5.4 6 ns tLZ 1 1 ns tOH 2.7 2.7 ns tRCD 15 20 ns

512Mb: x4, x8, x16 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. 512MSDRAM_D.p65 – Rev. D; Pub 1/02 ©2000, Micron Technology, Inc. 512Mb: x4, x8, x16 SDRAM ADVANCE WRITE – WITHOUT AUTO PRECHARGE 1 DISABLE AUTO PRECHARGE tCH tCLtCK tRP tRAS tRCD tRC DQM/ DQML, DQMH CKE CLK A0-A9, A11, A12 DQ BA0, BA1 A10 tCMHtCMS tAHtAS ROW BANK BANK ROW BANK t DON’T CARE DIN m tDHtDS DIN m + 1 DIN m + 2 DIN m + 3 COMMAND tCMHtCMS NOPNOP NOPACTIVE NOP WRITE PRECHARGE tAHtAS tAHtAS tDHtDS tDHtDS tDHtDS SINGLE BANK tCKHtCKS COLUMN m3 T0 T1 T2 T4 T3 T5 T6 T7 T8 T9 ROW BANK ROW ACTIVENOP WR NOP ALL BANKs NOTE: 1. For this example, the burst length = 4, and the WRITE burst is followed by a “manual” PRECHARGE. 2. 14ns to 15ns is required between <D IN m> and the PRECHARGE command, regardless of frequency. 3. x16: A11 and A12 = “Don’t Care” x8: A12 = “Don’t Care” *CAS latency indicated in parentheses. -7E -75 SYMBOL* MIN MAX MIN MAX UNITS tCMS 1.5 1.5 ns tDH 0.8 0.8 ns tDS 1.5 1.5 ns tRAS 37 120,000 44 120,000 ns tRC 60 66 ns tRCD 15 20 ns tRP 15 20 ns tWR 14 15 ns TIMING PARAMETERS -7E -75 SYMBOL* MIN MAX MIN MAX UNITS tAH 0.8 0.8 ns tAS 1.5 1.5 ns tCH 2.5 2.5 ns tCL 2.5 2.5 ns tCK (3) 7 7.5 ns tCK (2) 7.5 10 ns tCKH 0.8 0.8 ns tCKS 1.5 1.5 ns tCMH 0.8 0.8 ns

512Mb: x4, x8, x16 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. 512MSDRAM_D.p65 – Rev. D; Pub 1/02 ©2000, Micron Technology, Inc. 512Mb: x4, x8, x16 SDRAM ADVANCE TIMING PARAMETERS -7E -75 SYMBOL* MIN MAX MIN MAX UNITS tAH 0.8 0.8 ns tAS 1.5 1.5 ns tCH 2.5 2.5 ns tCL 2.5 2.5 ns tCK (3) 7 7.5 ns tCK (2) 7.5 10 ns tCKH 0.8 0.8 ns tCKS 1.5 1.5 ns tCMH 0.8 0.8 ns WRITE – WITH AUTO PRECHARGE 1 NOTE: 1. For this example, the burst length = 4. 2. x16: A11 and A12 = “Don’t Care” x8: A12 = “Don’t Care” *CAS latency indicated in parentheses. -7E -75 SYMBOL* MIN MAX MIN MAX UNITS tCMS 1.5 1.5 ns tDH 0.8 0.8 ns tDS 1.5 1.5 ns tRAS 37 120,000 44 120,000 ns tRC 60 66 ns tRCD 15 20 ns tRP 15 20 ns tWR 1 CLK + 1 CLK + – 7ns 7.5ns ENABLE AUTO PRECHARGE tCH tCLtCK tRP tRAS tRCD tRC DQM/ DQML, DQMH CKE CLK A0-A9, A11, A12 DQ BA0, BA1 A10 tCMHtCMS tAHtAS ROW ROW BANK BANK ROW ROW BANK tWR DON’T CARE DIN m tDHtDS DIN m + 1 DIN m + 2 DIN m + 3 COMMAND tCMHtCMS NOPNOP NOPACTIVE NOP WRITE NOP ACTIVE tAHtAS tAHtAS tDHtDS tDHtDS tDHtDS tCKHtCKS NOP NOP COLUMN m2 T0 T1 T2 T4 T3 T5 T6 T7 T8 T9

512Mb: x4, x8, x16 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. 512MSDRAM_D.p65 – Rev. D; Pub 1/02 ©2000, Micron Technology, Inc. 512Mb: x4, x8, x16 SDRAM ADVANCE TIMING PARAMETERS -7E -75 SYMBOL* MIN MAX MIN MAX UNITS tAH 0.8 0.8 ns tAS 1.5 1.5 ns tCH 2.5 2.5 ns tCL 2.5 2.5 ns tCK (3) 7 7.5 ns tCK (2) 7.5 10 ns tCKH 0.8 0.8 ns tCKS 1.5 1.5 ns tCMH 0.8 0.8 ns SINGLE WRITE – WITHOUT AUTO PRECHARGE 1 tCMS 1.5 1.5 ns tDH 0.8 0.8 ns tDS 1.5 1.5 ns tRAS 37 120,000 44 120,000 ns tRC 60 66 ns tRCD 15 20 ns tRP 15 20 ns tWR 14 15 ns *CAS latency indicated in parentheses. DISABLE AUTO PRECHARGE ALL BANKS tCH tCLtCK tRP tRAS tRCD tRC DQM/ DQML, DQMH CKE CLK A0-A9, A11, A12 DQ BA0, BA1 A10 tCMHtCMS tAHtAS ROW BANK BANK BANK ROW ROW BANK tWR DIN m tDHtDS COMMAND tCMHtCMS NOP4NOP4 PRECHARGEACTIVE NOP WRITE ACTIVENOP NOP tAHtAS tAHtAS SINGLE BANK tCKHtCKS COLUMN m3 T0 T1 T2 T4 T3 T5 T6 T7 T8 DON’T CARE -7E -75 SYMBOL* MIN MAX MIN MAX UNITS NOTE: 1. For this example, the burst length = 1, and the WRITE burst is followed by a “manual” PRECHARGE. 2. 14ns to 15ns is required between <D IN m> and the PRECHARGE command, regardless of frequency. 3. x16: A11 and A12 = “Don’t Care” x8: A12 = “Don’t Care” 4. PRECHARGE command not allowed else tRAS would be violated

512Mb: x4, x8, x16 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. 512MSDRAM_D.p65 – Rev. D; Pub 1/02 ©2000, Micron Technology, Inc. 512Mb: x4, x8, x16 SDRAM ADVANCE TIMING PARAMETERS -7E -75 SYMBOL* MIN MAX MIN MAX UNITS tAH 0.8 0.8 ns tAS 1.5 1.5 ns tCH 2.5 2.5 ns tCL 2.5 2.5 ns tCK (3) 7 7.5 ns tCK (2) 7.5 10 ns tCKH 0.8 0.8 ns tCKS 1.5 1.5 ns tCMH 0.8 0.8 ns SINGLE WRITE – WITH AUTO PRECHARGE 1 -7E -75 SYMBOL* MIN MAX MIN MAX UNITS NOTE: 1. For this example, the burst length = 1, and the WRITE burst is followed by a “manual” PRECHARGE. 2. 14ns to 15ns is required between <D IN m> and the PRECHARGE command, regardless of frequency. 3. x16: A11 and A12 = “Don’t Care” x8: A12 = “Don’t Care” 4. WRITE command not allowed else tRAS would be violated *CAS latency indicated in parentheses. ENABLE AUTO PRECHARGE tCH tCLtCK tRP tRAS tRCD3 tRC DQM/ DQML, DQMH CKE CLK A0-A9, A11, A12 DQ BA0, BA1 A10 tCMHtCMS tAHtAS ROW ROW BANK BANK ROW ROW BANK tWR2 DIN m COMMAND tCMHtCMS NOP4 NOP4 NOPACTIVE NOP 4 WRITE NOPACTIVE tAHtAS tAHtAS tDHtDS tCKHtCKS NOP NOP COLUMN m3 T0 T1 T2 T4 T3 T5 T6 T7 T8 T9 DON’T CARE tCMS 1.5 1.5 ns tDH 0.8 0.8 ns tDS 1.5 1.5 ns tRAS 37 120,000 44 120,000 ns tRC 60 66 ns tRCD 15 20 ns tRP 15 20 ns tWR 1 CLK + 1 CLK + ns 7ns 7ns

512Mb: x4, x8, x16 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. 512MSDRAM_D.p65 – Rev. D; Pub 1/02 ©2000, Micron Technology, Inc. 512Mb: x4, x8, x16 SDRAM ADVANCE TIMING PARAMETERS -7E -75 SYMBOL* MIN MAX MIN MAX UNITS tAH 0.8 0.8 ns tAS 1.5 1.5 ns tCH 2.5 2.5 ns tCL 2.5 2.5 ns tCK (3) 7 7.5 ns tCK (2) 7.5 10 ns tCKH 0.8 0.8 ns tCKS 1.5 1.5 ns tCMH 0.8 0.8 ns ALTERNATING BANK WRITE ACCESSES 1 tCH tCLtCKCLK DQ DON’T CARE DIN m tDHtDS DIN m + 1 DIN m + 2 DIN m + 3 COMMAND tCMHtCMS NOP NOPACTIVE NOP WRITE NOP NOP ACTIVE tDHtDS tDHtDS tDHtDS ACTIVE WRITE DIN b tDHtDS DIN b + 1 DIN b + 3 tDHtDS tDHtDS ENABLE AUTO PRECHARGE DQM/ DQML, DQMH A0-A9, A11, A12 BA0, BA1 A10 tCMHtCMS tAHtAS tAHtAS tAHtAS ROW ROW ROW ROW ENABLE AUTO PRECHARGE ROW ROW BANK 0 BANK 0 BANK 1 BANK 0 BANK 1 CKE tCKHtCKS DIN b + 2 tDHtDS COLUMN b 3COLUMN m3 tRP - BANK 0 tRAS - BANK 0 tRCD - BANK 0 t t RCD - BANK 0tWR - BANK 0 WR - BANK 1tRCD - BANK 1 t t RC - BANK 0 RRD T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 NOTE: 1. For this example, the burst length = 4. 2. Requires one clock plus time (7ns to 7.5ns) with auto precharge or 14ns to 15ns with PRECHARGE. 3. x16: A11 and A12 = “Don’t Care” x8: A12 = “Don’t Care” *CAS latency indicated in parentheses. -7E -75 SYMBOL* MIN MAX MIN MAX UNITS tCMS 1.5 1.5 ns tDH 0.8 0.8 ns tDS 1.5 1.5 ns tRAS 37 120,000 44 120,000 ns tRC 60 66 ns tRCD 15 20 ns tRP 15 20 ns tRRD 14 15 ns tWR Note 2 Note 2 ns

512Mb: x4, x8, x16 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. 512MSDRAM_D.p65 – Rev. D; Pub 1/02 ©2000, Micron Technology, Inc. 512Mb: x4, x8, x16 SDRAM ADVANCE TIMING PARAMETERS -7E -75 SYMBOL* MIN MAX MIN MAX UNITS tAH 0.8 0.8 ns tAS 1.5 1.5 ns tCH 2.5 2.5 ns tCL 2.5 2.5 ns tCK (3) 7 7.5 ns tCK (2) 7.5 10 ns tCKH 0.8 0.8 ns WRITE – FULL-PAGE BURST NOTE: 1. x16: A11 and A12 = “Don’t Care” x8: A12 = “Don’t Care” 2. tWR must be satisfied prior to PRECHARGE command. 3. Page left open; no tRP. *CAS latency indicated in parentheses. -7E -75 SYMBOL* MIN MAX MIN MAX UNITS tCKS 1.5 1.5 ns tCMH 0.8 0.8 ns tCMS 1.5 1.5 ns tDH 0.8 0.8 ns tDS 1.5 1.5 ns tRCD 15 20 ns tCH tCL tCK tRCD DQM/ DQML, DQMH CKE CLK A0-A9, A11, A12 BA0, BA1 A10 tCMS tAHtAS tAHtAS ROW ROW Full-page burst does not self-terminate. Can use BURST TERMINATE command to stop. 2, 3 Full page completed DON’T CARE COMMAND tCMHtCMS NOPNOP NOPACTIVE NOP WRITE BURST TERMNOP NOP DQ DIN m tDHtDS DIN m + 1 DIN m + 2 DIN m + 3 tDHtDS tDHtDS tDHtDS DIN m - 1 tDHtDS tAHtAS BANK BANK tCMH tCKHtCKS 1,024 (x16) locations within same row 2,048 (x8) locations within same row 4,096 (x4) locations within same row COLUMN m1 T0 T1 T2 T3 T4 T5 Tn + 1 Tn + 2 Tn + 3

512Mb: x4, x8, x16 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. 512MSDRAM_D.p65 – Rev. D; Pub 1/02 ©2000, Micron Technology, Inc. 512Mb: x4, x8, x16 SDRAM ADVANCE TIMING PARAMETERS -7E -75 SYMBOL* MIN MAX MIN MAX UNITS tAH 0.8 0.8 ns tAS 1.5 1.5 ns tCH 2.5 2.5 ns tCL 2.5 2.5 ns tCK (3) 7 7.5 ns tCK (2) 7.5 10 ns tCKH 0.8 0.8 ns WRITE – DQM OPERATION 1 tCH tCLtCK tRCD DQM/ DQML, DQMH CKE CLK A0-A9, A11, A12 DQ BA0, BA1 A10 tCMS tAHtAS ROW BANK ROW BANK ENABLE AUTO PRECHARGE DIN m + 3 tDHtDS DIN m DIN m + 2 tCMH COMMAND NOPNOP NOPACTIVE NOP WRITE NOPNOP DON’T CARE tCMS tCMH tDHtDStDHtDS tAHtAS tAHtAS DISABLE AUTO PRECHARGE tCKHtCKS COLUMN m2 T0 T1 T2 T3 T4 T5 T6 T7 NOTE: 1. For this example, the burst length = 4. 2. x16: A11 and A12 = “Don’t Care” x8: A12 = “Don’t Care” *CAS latency indicated in parentheses. -7E -75 SYMBOL* MIN MAX MIN MAX UNITS tCKS 1.5 1.5 ns tCMH 0.8 0.8 ns tCMS 1.5 1.5 ns tDH 0.8 0.8 ns tDS 1.5 1.5 ns tRCD 15 20 ns

512Mb: x4, x8, x16 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. 512MSDRAM_D.p65 – Rev. D; Pub 1/02 ©2000, Micron Technology, Inc. 512Mb: x4, x8, x16 SDRAM ADVANCE 54-PIN PLASTIC TSOP (400 mil) SEE DETAIL A .80 TYP 0.71 10.16 ±0.08 0.50 ±0.10 PIN #1 ID DETAIL A 22.22 ±0.08 0.375 ±0.075

1.2 MAX

0.10 0.25 11.76 ±0.10 0.80 TYP 0.15 +0.03 -0.02 0.10 +0.10 -0.05 GAGE PLANE NOTE: 1. All dimensions in millimeters. 2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side. 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992 Micron is a registered trademark and the Micron logo and M logo are trademarks of Micron Technology, Inc.