MV036F120M010-CB

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U G :003 vicorpow er.com A pplications E ngineering: 8 00 927 .947 4 Page 1 The Custom er E valuation B oards described in this docum ent are intended to acquaint you w ith the benefits and features of a Factorized Pow er A rchitecture (F P A TM ). They are not designed to be installed in end-use equipm ent. Please read this docum ent before setting up a Custom er Evaluation Board. During operation, the pow er devices and surrounding structures can be operated safely at high tem peratures.

• Rem ove pow er and use caution w hen connecting and disconnecting test probes and interface lines to avoid inadvertent short circuits and contact w ith hot surfaces.
• W hen testing electronic products alw ays use approved safety glasses. F ollow good laboratory practice and procedures. Introduction A F actorized Pow er A rchitecture offers a fundam entally new and im prove d approach to distributed pow er. F actorizing DC-DC pow er conversion into its basic functions – isolation and transform ation on the one hand and output voltage control and regulation on the other – and arranging those functions in a sequence m axim izes pow er system perform ance and cost effectiveness. VTM m odules put isolated current m ultiplication and voltage division directly at the Point of Load (PO L), and an upstream PRM non-isolated regulator controls the F actorized B us voltage supplied to the VTM to provide line and load regulation. W ith this architecture, the F actorized B us voltage can be relatively high; distribution losses can be m inim ized w ith narrow er copper traces; and the PRM m ay be located at any convenient location, either adjacent to or rem ote from the VTM . PRM s operate from a w ide variety of input sources to drive VTM s. VTM s are extrem ely fast and quiet and provide voltage division ratios as high as 32. VTM s enable the user to efficiently supply up to 100 A from each full VI Chip package at regulated output voltages as low as 0.8 Vdc or higher, as needed. W ith F PA , only a VTM is needed at the PO L. VTM s, unim peded by serial inductance, feature very high bandw idth and extrem ely fast transient response, allow ing energy to be stored efficiently at the relatively high F actorized B us voltage. W ithout bul k capacitors at the PO L, precious board real estate m ay be reclaim ed for essential functions. The density, efficiency, perform ance, cost-effectiveness, and architectural superiority of F PA m ake it the least intrusive form of distributed pow er and facilitate the developm ent of m ore advanced, com petitive products. The PRM m ay be used as a stan dalone non-isolated regulation stage, w hereas the VTM is intended to be used w ith a PRM . F or custom ers to evaluate these com ponents, special Custom er B oards are available. To obtain one of these boards, sim ply append the chosen PRM or VTM part num ber w ith "-CB ". PRM ® and VTM ® Custom er Evaluation Boards Contents Page Introduction 1 Board O verview 2 Recom m ended 3 H ardw are Initial Set U p 4 Baseline Test 4 Procedure VTM -CB 7 The D C-D C 8 Converter Chip Set O rdering 9 Inform ation U SER G U ID E | U G :003

U G :003 vicorpow er.com A pplications E ngineering: 8 00 927 .947 4 Page 2 Please take a closer look at the PRM -CB board. F igure 1 is a picture of a PRM -A L m ounted to the PRM -CB board. The board has several features that enable the user to fully explore the capabilities of the PRM -A L: Board O verview (reference the designators in the im age above) 1 Source voltage input points are designed to accom m odate #10 hardw are and Panduit ring lugs. B E CE RTA IN THA T THE PO LA RITY IS CO RRE CT B E F O RE A PPLYIN G PO W E R. 2 A uxiliary control (H01) - access points for PR, IL, TM , PC, and VH, (header show n installed). 3 Reference test point Signal G round (SG ).

4 A djustm ent potentiom eters for indicated function are used in conjunction w ith actuation of

corresponding sw itch in Item 5. 5 PRM port connections (sw itch bank and silk screen reference). a. Toggling the sw itch indicated PC to the O N position inhibits the PRM output. b. Toggling the sw itch indicated IL to the O N position enables an adjustable current lim it effected by varying the corresponding IL trim pot (Item 4). c. Toggling the sw itch indicated SC to the O N position enables adjustm ent of the output voltage dow n from the set point determ ined by the O S resistor by varying the corresponding SC trim pot (Item 4). - CA U TIO N : depending upon the initial output voltage set point determ ined by the O S resistor it is possible to trim the SC so low that the output shuts off. The m inim um output voltage per the data sheet is 26 Vdc. d. Toggling the sw itch indicated CD to the O N position places the PRM in A daptive Loop regulation m ode (for use w ith the VTM -CB ) from the Local Loop regulation m ode. (In Local Loop m ode the set voltage is regulated at the output term inals of the PRM .) A djusting the corresponding CD trim pot (Item 4) changes the gain of the loop to com pensate for different O S settings and/or interconnect resistive losses. e. Toggling the sw itch indicated O SV (O S Variable) to the O N position requires the sw itch indicated O SF (O S F ixed) be placed in the O F F position and allow s the PRM output set point to be varied w ithin the range specified on the data sheet. f. Toggling the sw itch indicated O SF to the O N position sets the output of the PRM to the nom inal value indicated on the data sheet. If this sw itch is in the O F F position and the O SV sw itch is also O F F, the unit w ill not function. g. IT IS B E ST TO SE T THE SW ITCH PO SITIO N A N D CO RRE SPO N DIN G TRIM PO T SE TTIN G S B E F O RE A PPLYIN G PO W E R TO THE B O A RD. Figure 1 PRM -A L m ounted to PRM -CB board

U G :003 vicorpow er.com A pplications E ngineering: 8 00 927 .947 4 Page 3

6 Test point for Secondary Control (SC)

7 O utput voltage points are designed to accom m odate #10 hardw are and Panduit ring lugs. 8 O utput connector (J01) for m ating w ith VTM -CB providing Vout and VC. A s show n on the schem atic (F igure 2) there are four pins dedicated to the + O ut, four for the -O ut, and tw o for the VC. E ach contact is rated for 3 A . The excess capacity afforded by these pins can facilitate testing m ultiple VTM -CB s from a single PRM -CB using an appropriate w iring harness and m ating connector. This m ay also be achieved using the large pads of Item 7 . 9 O utput scope jack (J02). Headers H01 and J01 are 0.100" spacing, 10 position fem ale, m anufactured by Sullins E lectronics and available from Digi-K ey as part # S5519-N D. B elow is the schem atic for this PCB . Double clicking the im age w ill launch A dobe A crobat to allow you a better view . Recom m ended H ardw are Q TY Description M anufacturer P/N 4 ring lug Panduit LCA S6 -10-L Kit # 26647 contains: 4 #10-32 screw 4 #10 flat w asher 4 #10 lock w asher 4 #10 hex nut A ll hardw are is stainless steel except the ring lug. K it # 26 6 47 is included w ith the Custom er E valuation B oard. Figure 2 PRM -CB schem atic diagram

U G :003 vicorpow er.com A pplications E ngineering: 8 00 927 .947 4 Page 4 Initial Set U p To test the PRM ® m ounted to the board it is necessary to configure the sw itch bank (Item 5) as show n on the silk screen in F igure 3. Placing the sw itch bank in this state connects a fixed resistor betw een O S and SG of the PRM that sets the output voltage of the PRM to the nom inal value indicated on its respective data sheet. Failure to configure the sw itch bank in this state prior to testing m ay result in im proper output or no output. Baseline Test Procedure - PRM -CB (Refer to F igure 3)

1.0 Recom m ended Equipm ent

1.1 DC pow er supply – 0-100 V; 500 W . 1.2 DC electronic load – pulse capable; 0-100 V; 100 A m inim um . 1.3 DM M . 1.4 O scilloscope. 1.5 A ppropriately sized interconnect cables. 1.6 F astening hardw are.

1.7 F an (if the PRM is to be operated for extended periods of tim e or at an elevated

am bient tem perature w e recom m end the supplied heat sink be installed). 1.8 Safety glasses. 1.9 Data sheet for the requisite PRM . Figure 3 PRM Custom er Board Layout sw itch reference (silk screen) sw itch bank (Item 5)

U G :003 vicorpow er.com A pplications E ngineering: 8 00 927 .947 4 Page 5

2.0 H ook U p

2.1 Connect the pow er supply + O ut lead to the + In term inal of the Custom er

E valuation B oard.

2.2 Connect the pow er supply –O ut lead to the –In term inal of the Custom er

E valuation B oard.

2.3 A high quality, low -noise pow er supply should be connected to these locations

2.4 Connect a lead betw een the + O ut of the Custom er E valuation B oard and + In

of the load.

2.5 Connect a lead betw een the –O ut of the Custom er E valuation B oard and –In

of the load. 2.6 Connections to these locations should be w ith short heavy gauge leads.

3.0 Verify Connections

4.0 Test Sequence

4.1 Have the latest version of the PRM ® data sheet in hand. 4.2 A ssure that the DC supply is set to 0 Vdc prior to turning the unit on. 4.3 Confirm that the sw itch bank is configured as show n in the silk screen on the board. 4.4 Turn on the DC supply.

4.5 M ake sure the DC load is set to constant current and at 0 A prior to turning

on the load. 4.6 Turn on the DC load. 4.7 Connect an oscilloscope to the test point provided to m onitor output voltage. M any types of scope probes m ay be directly connected to these points if the probe is equipped w ith a rem ovable plastic sheath. B e careful to avoid creating ground loops w hen m aking m easurem ents of this voltage and the input voltage. It is recom m ended that th e m easurem ents be m ade separately. Shorting the -input and -output of the PRM w ill defeat the PRM current lim it feature as the current shunt is in this path. 4.8 Turn on a fan if desired. 4.9 Raise the DC input voltage to the nom inal value indicated on the data sheet.

4.10 Verify no load operation by raising and low ering the input voltage through the entire

input voltage range. The output voltage should rem ain constant w ithin the tolerance indicated in the data sheet. 4.11 Re-establish the nom inal input voltage. 4.12 Slow ly increase the load current to full load w hile m onitoring the output voltage. The output voltage should rem ain w ithin the lim its specified in the appropriate PRM data sheet. 4.13 Return the load current to 0 A and decrease the input voltage to low line. 4.14 Repeat step 4.12. Depending upon the supply used and the source im pedance it m ay be necessary to adjust the input voltage to keep the input to the PRM at low line. 4.15 Return the load current to 0 A and increase the input voltage to high line. 4.16 Repeat step 4.12.

5.0 You have now verified the functionality of the PRM over the entire line and load

operating range.

6.0 D eviating from N om inal Settings

This board has provisions, as described in the B oard O verview section, to adjust the configuration of the PRM about the nom inal values. The data sheet for the PRM has equations and curves for determ ining the required resistor values needed for specific conditions. A pplications requiring output voltages other than the nom inal setting w ill need to have the new value set via the trim pots and respective sw itches. Reference Item s 4 and 5 of the B oard O verview and the schem atic show n in F igure 2.

6.1 A djust the PRM O utput Voltage Set Point

6 .1.1 M ake sure that the pow er is rem oved from the unit prior to m aking adjustm ent. 6 .1.2 U sing a DM M (set to m easure resistance), probe betw een SG (Item 3) and the pad labeled O S located next to the 5 k Ω trim pot R08 .

U G :003 vicorpow er.com A pplications E ngineering: 8 00 927 .947 4 Page 6 6 .1.3 A djust R08 such that the m eter reads ~ 200 Ω. This value added to the fixed resistor R07 should total ~ 2.3 k Ω. N ote: R07 is 1.7 k Ω on the boards w ith the M IL-CO TS PRM . 6 .1.4 O ne could also probe betw een SG and the O N side of sw itch O SV (#5) and set the total resistance show n to ~ 2.3 k Ω. 6 .1.5 M ove sw itch O SF (#6 ) to the O F F position. 6 .1.6 M ove sw itch O SV (#5) to the O N position. 6 .1.7 The unit is now ready to provide the desired output voltage set point. 6 .1.8 Pow ering the device on should yield a no-load output voltage of the nom inal specified value. 6 .1.9 The output voltage can now be set to the desired value by varying trim pot O S (R08 ). 6 .1.10 IT M A Y B E PO SSIB LE TO IN A DVE RTE N TLY TRIM THE O U TPU T TO O HIG H E N A B LIN G THE O VE RVO LTA G E PRO TE CTIO N CIRCU IT. If this happens, reduce the im pedance of 6 .1.11 The desired output voltage set point can also be achieved by using the equations in the data sheet and setting the total O S resistance (R07 + R08 ) to that value and then configuring the sw itches as above. 6 .1.12 B e certain to adhere to the pow er vs. output voltage curve in the data sheet to avoid over pow ering the device!

6.2 A djusting the Current Lim it

6 .2.1 Increasing the load beyond the rated m axim um m ay activate the PRM ’s internal current lim it (see data sheet for values) feature. Certain applications m ay require a low er lim it and for those situations w e offer the adjustm ent feature. 6 .2.2 Refer to the data sheet for the resistance vs. lim it curve for the desired lim it value. N ote: the IL values of resistors installed on this board (R01+ R02: 2 k Ω+ 100 k Ω) m ay not cover the entire range of the curve. 6 .2.3 The adjustable IL m ode is engaged by repositioning the IL sw itch (#2) from O F F to O N . (This m ay be done w hile the unit is pow ered.) 6 .2.4 A djusting the IL trim pot w ill reduce the current lim it from the factory preset lim its specified in the data sheet. It is not possible to increase this lim it beyond the factory settings. 6 .2.5 To reinstate the factory lim it return the IL sw itch to the O F F position.

6.3 Trim m ing the output voltage using SC

6 .3.1 O nce the output voltage has been determ ined and set using the O S resistors, it is still possible to trim the output dow n to 26 V using the SC control. A djusting the output in this m anner rather than m erely adjusting the output via the O S values provides im proved regulation. 6 .3.2 Depending upon the chosen initial output voltage determ ined by the O S resistors, the am ount of available adjustm ent m ight be very lim ited. E nabling SC adjustm ent by toggling the SC sw itch (#3) to the O N position m ay result in shut dow n. 6 .3.3 To avoid the situation described in 6 .3.2, set the SC trim pot R04 (100 k Ω) to its m axim um value prior to enabling the sw itch. 6 .3.4 The data sheet has an equation for calculating the appropriate resistor value for a trim m ed output voltage. This value w ould be the sum of fixed resistor R03 (5.11 k Ω) and the trim pot R04. R04 can be set using the test points provided locally, or the sum set using the SC and SG test points (Item s 3 and 6 ) w hen the SC sw itch is O N . 6.4 A ctivating A daptive Loop Regulation and Interconnect Com pensation CD . 6 .4.1 The CD sw itch (#4) and the associated fixed resistor R05 (20 Ω) and trim pot R06 (20 Ω) enable the PRM A daptive Loop regulation feature, w hich com pensates for the VTM output resistance induced voltage drop as the load current from the VTM is increased. 6 .4.2 This feature is intended to be used w ith m ating VTM -CB discussed in detail in the next section.

U G :003 vicorpow er.com A pplications E ngineering: 8 00 927 .947 4 Page 7 VTM -CB (F igure 4) The VTM ® m odule provides the isolation stage and the output voltage step dow n. W hen paired w ith the PRM the chip set form s a traditional DC-DC converter. The -CB board for the VTM is intended to be used in conjunction w ith the PRM -CB ; nevertheless, in order to test this standalone, it is possible to inject a VC pulse as specified in the data sheet to the exposed lead from the header corresponding to the VC pin. Refer to the board schem atic F igure 5 for the appropriate pin(s.) A n im pedance m easurem ent m ay prove just as expeditious. Board O verview

1 Source voltage input points (Item 1) are designed to accom m odate #10 hardw are and Panduit ring

lugs. B E CE RTA IN PO LA RITY IS CO RRE CT B E F O RE A PPLYIN G PO W E R. 2 Input connector J01 (Item 2) m ates w ith PRM -CB providing Vin and VC. A s can be seen from the follow ing schem atic there are four pins dedicated to the + In, four for the -In, and tw o for the VC. E ach contact is rated for 3 A . The excess capacity afforded by these pins can facilitate testing m ultiple VTM -CB s from a single PRM -CB using an appropriate w iring harness and m ating connector. This m ay also be achieved using the large pads of Item 1. N ote: There is a rem ovable m ale to m ale insert installed into this connector. This allow s the m ate to be either gender w hich m ay be im portant depending upon the availability of connectors. 3 The K elvin connection points for Vin and Vout (Item 3) are for use in efficiency m easurem ents. 4 The scope jack (Item 4) is used to view output voltage param eters.

5 O utput voltage points (Item 5) are designed to accom m odate #10 hardw are and Panduit

ring lugs. Figure 4 VTM -CB

vicorpow er.com A pplications E ngineering: 8 00 927 .947 4 Rev 1.1 Page 912/2013 F or exam ple, if a P048 F 048 T24A L-CB and a V048 F 120T025-CB are m ated as above, the input range to the pair is 36 – 7 5 Vdc and the output w ould be 12 Vdc at no load decreasing by Iout x Rout of the VTM ® as the load current increases. This Vout decrease is due to the sw itch bank being configured as show n in the silk screen. In this configuration, the PRM ® is set for Local Loop m ode as described in Section 5d. To provide for load regulation at the output of the VTM , the A daptive Loop regulation m ode should be engaged. To activate this feature of the PRM -A L, the sw itch indicated CD (sw itch #4) should be set to the O N position. The corresponding trim pot should be set to 19.2 Ω w hich w ill result in a total CD to SG resistance of 39.2 Ω. This is the optim al value for the nom inal PRM output voltage as set by the fixed O S resistor installed on the board and activated by the O SF (sw itch #6 ) in the O N position. B e certain to refer to the data sheets for the appropriate resistor values for your requirem ents. To validate the functionality of the A daptive Loop regulation, repeat the steps of 2.0 to 5.0 under the section B aseline Test Procedure - PRM -CB except in this instance the output connections are to be m ade to the VTM -CB output term inals. B oth the PRM and VTM data sheets should be in hand. The load current refers to the VTM output current ratings. B e certain to m ake the connections to the supply and load prior to m ating the boards to avoid stressing the connectors. The PRM A daptive Loop regulates the output of the VTM w ithout sense lines. The F actorized B us voltage (Vf) m ay be m oniored by using J02 on the PRM -CB board (Item 9) w hile increasing the load current. O bserve the Vf voltage increases w ith the load current, com pensating for the insertion loss due to the VTM output resistance. VTM output voltages, w hich deviate from the nom inal configuration, are available by changing the output set point of the PRM as described in section 6 of this docum ent and using the form ula described in the data sheet. O rdering Inform ation The PRM and VTM Custom er E valuation B oards are specified by add the suffix “-CB ” to the appropriate PRM or VTM m odel num ber. G o to http://w w w .vicorpow er.com /contact-us for ordering inform ation.