MTFC128AZAQHD-IT

MTFC64GAZAQHD-IT MICRON | Alldatasheet

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Features

CCM005-841846911-10476 Micron Technology, Inc. reserves the right to change products or specifications without notice. industrial_emmc_32_128gb_TLC_5_1_B.pdf - Rev. C 09/2021 EN © 2021 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice. Micron Confidential and Proprietary e.MMC Memory MTFC32GAZAQHD-WT, MTFC32GAZAQHD-IT, MTFC64GAZAQHD-WT, MTFC64GAZAQHD-IT, MTFC128GAZAQJP-IT Notes: 1. The JEDEC specification is available at www.jedec.org/sites/default/files/docs/JESD84-B5 1.pdf. 2. Operating temperature (TOPER) is the case surface temperature on the center/top of the package.

• MultiMediaCard (MMC) controller and NAND flash
• JEDEC/MMC standard version 5.1-compliant (JEDEC Standard No. JESD84-B51)1
• VCC: 2.7–3.6V
• VCCQ: 1.70–1.95V
• Storage temperature range: – WT: From –40°C to +85°C – IT: From –40°C to +95°C
• Advanced 12-signal interface
• ×1, ×4, and ×8 I/Os, selectable by host
• e.MMC I/F boot frequency: 0 to 52 MHz
• e.MMC I/F clock frequency: 0 to 200 MHz
• HS200/HS400 mode
• Command classes: Class 0 (basic); Class 2 (block read); Class 4 (block write); Class 5 (erase); Class 6 (write protection); Class 7 (lock card)
• Command queue
• BKOPS control
• Temporary write protection
• Boot operation (high-speed boot)
• Sleep mode
• Replay-protected memory block (RPMB)
• Hardware reset signal
• Multiple partitions with enhanced attribute
• Permanent and power-on write protection
• High-priority interrupt (HPI)
• Data strobe pin
• Field firmware update (FFU)
• Device health report
• Sleep notification
• Background operation
• Reliable write
• Discard and sanitize
• Power-off notification
• Backward compatible with previous MMC
• ECC and block management implemented
• Enhanced strobe
• Extended reflow capability
• Retention: – 1 year @55°C at maximum PE – 10 years @55°C at 10% of PE Options Marking
• Density – 32GB 32G – 64GB 64G – 128GB 128G
• NAND component – 256Gb AZ
• Controller AQ
• Packages – JEDEC-standard, RoHS-compliant – 153-ball VFBGA HD – 153-ball VFBGA JP
• Operating temperature range2 – From –25°C to +85°C WT – From –40°C to +95°C IT industrial_emmc_32_128gb_tlc_5_1_b.ditamap Page 1

CCM005-841846911-10476 Micron Technology, Inc. reserves the right to change products or specifications without notice. industrial_emmc_32_128gb_TLC_5_1_B.pdf - Rev. C 09/2021 EN © 2021 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32GB, 64GB, 128GB: Industrial e.MMC Part Numbering Information Micron® e.MMC memory devices are available in different configurations and densities. Figure 1: e.MMC Part Numbering Device Marking Due to the size of the package, the Micron-standard part number is not printed on the top of the device. Instead, an abbreviated device mark consisting of a 5-digit alphanumeric code is used. The abbreviated device marks are cross-referenced to the Micron part numbers at the FBGA Part Marking Decoder site: www.micron.com/decoder. Table 1: Ordering Information Base Part Number Density Package Shipping MTFC32GAZAQHD-WT MTFC32GAZAQHD-IT 32GB 153-ball VFBGA 11.5mm × 13mm × 0.9mm Tray Tape and reel MTFC64GAZAQHD-WT MTFC64GAZAQHD-IT 64GB 153-ball VFBGA 11.5mm × 13mm × 0.9mm Tray Tape and reel MTFC128GAZAQJP-IT 128GB 153-ball VFBGA 11.5mm × 13mm × 1.0mm Tray Tape and reel MT FC - Micron Technology Product Family FC = NAND Flash + controller NAND Density NAND Component Controller ID Production Status Blank = Production ES = Engineering sample Operating Temperature Range Special Options Package Codes xx xx xx xx xx xx All packages are Pb free xx industrial_emmc_32_128gb_tlc_5_1_b.ditamap Page 2

CCM005-841846911-10476 Micron Technology, Inc. reserves the right to change products or specifications without notice. industrial_emmc_32_128gb_TLC_5_1_B.pdf - Rev. C 09/2021 EN © 2021 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32GB, 64GB, 128GB: Industrial e.MMC e.MMC Performance Performance in the following tables are retrieved with these conditions: Bus in x8 I/O; Temperature 25°C; Sequential access of 512KB chunk; Cache on (write); Command queueing enabled with queue depth 32 commands. Additional performance data, such as system performance on a specific application board, is provided in a separate document upon customer request. e.MMC Current Consumption Current consumption in the following tables are retrieved with these conditions: Bus in x8 I/O; VCC = 3.6V and VCCQ = 1.95V; Temperature 25°C; Measurements done as average RMS current consumption; ICCQ in READ operation measurements with tester load disconnected. Note: 1. Command queueing enabled with queue depth 32 commands. Table 2: HS400 Performance Condition Typical Values Unit32GB 64GB 128GB Sequential write 100 215 215 MB/s Sequential read 300 320 320 MB/s Table 3: HS200 Performance Condition Typical Values Unit32GB 64GB 128GB Sequential write 100 140 140 MB/s Sequential read 175 175 175 MB/s Table 4: HS400 Current Consumption Condition Typical Values (ICC/ICCQ) Unit32GB 64GB 128GB Write1 50/110 50/110 50/110 mA Read1 50/190 50/190 50/190 mA Sleep (VCC off) 0/280 0/300 0/315 µA Auto standby 25/350 45/360 75/405 µA Table 5: HS200 Current Consumption Condition Typical Values (ICC/ICCQ) Unit32GB 64GB 128GB Write 40/105 40/105 40/105 mA Read 40/150 40/150 40/150 mA Sleep (VCC off) 0/280 0/300 0/315 µA industrial_emmc_32_128gb_tlc_5_1_b.ditamap Page 3

CCM005-841846911-10476 Micron Technology, Inc. reserves the right to change products or specifications without notice. industrial_emmc_32_128gb_TLC_5_1_B.pdf - Rev. C 09/2021 EN © 2021 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32GB, 64GB, 128GB: Industrial e.MMC Auto standby 25/350 45/360 75/405 µA Table 5: HS200 Current Consumption (Continued) Condition Typical Values (ICC/ICCQ) Unit32GB 64GB 128GB industrial_emmc_32_128gb_tlc_5_1_b.ditamap Page 4

CCM005-841846911-10476 Micron Technology, Inc. reserves the right to change products or specifications without notice. industrial_emmc_32_128gb_TLC_5_1_B.pdf - Rev. C 09/2021 EN © 2021 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32GB, 64GB, 128GB: Industrial e.MMC Important Notes and Warnings Important Notes and Warnings Micron Technology, Inc. ("Micron") reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions. This document supersedes and replaces all information supplied prior to the publication hereof. You may not rely on any information set forth in this document if you obtain the product described herein from any unauthorized distributor or other source not authorized by Micron. Automotive Applications. Products are not designed or intended for use in automotive applications unless specifi- cally designated by Micron as automotive-grade by their respective data sheets. Distributor and customer/distrib- utor shall assume the sole risk and liability for and shall indemnify and hold Micron harmless against all claims, costs, damages, and expenses and reasonable attorneys' fees arising out of, directly or indirectly, any claim of product liability, personal injury, death, or property damage resulting directly or indirectly from any use of non-automotive-grade products in automotive applications. Customer/distributor shall ensure that the terms and conditions of sale between customer/distributor and any customer of distributor/customer (1) state that Micron products are not designed or intended for use in automotive applications unless specifically designated by Micron as automotive-grade by their respective data sheets and (2) require such customer of distributor/customer to indemnify and hold Micron harmless against all claims, costs, damages, and expenses and reasonable attorneys' fees arising out of, directly or indirectly, any claim of product liability, personal injury, death, or property damage resulting from any use of non-automotive-grade products in automotive applications. Critical Applications. Products are not authorized for use in applications in which failure of the Micron component could result, directly or indirectly in death, personal injury, or severe property or environmental damage ("Critical Applications"). Customer must protect against death, personal injury, and severe property and environmental damage by incorporating safety design measures into customer's applications to ensure that failure of the Micron component will not result in such harms. Should customer or distributor purchase, use, or sell any Micron compo- nent for any critical application, customer and distributor shall indemnify and hold harmless Micron and its subsid- iaries, subcontractors, and affiliates and the directors, officers, and employees of each against all claims, costs, damages, and expenses and reasonable attorneys' fees arising out of, directly or indirectly, any claim of product liability, personal injury, or death arising in any way out of such critical application, whether or not Micron or its subsidiaries, subcontractors, or affiliates were negligent in the design, manufacture, or warning of the Micron product. Customer Responsibility. Customers are responsible for the design, manufacture, and operation of their systems, applications, and products using Micron products. ALL SEMICONDUCTOR PRODUCTS HAVE INHERENT FAILURE RATES AND LIMITED USEFUL LIVES. IT IS THE CUSTOMER'S SOLE RESPONSIBILITY TO DETERMINE WHETHER THE MICRON PRODUCT IS SUITABLE AND FIT FOR THE CUSTOMER'S SYSTEM, APPLICATION, OR PRODUCT. Customers must ensure that adequate design, manufacturing, and operating safeguards are included in customer's applications and products to eliminate the risk that personal injury, death, or severe property or envi- ronmental damages will result from failure of any semiconductor component. Limited Warranty. In no event shall Micron be liable for any indirect, incidental, punitive, special or consequential damages (including without limitation lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort, warranty, breach of contract or other legal theory, unless explicitly stated in a written agreement executed by Micron's duly autho- rized representative. industrial_emmc_32_128gb_tlc_5_1_b.ditamap Page 5

CCM005-841846911-10476 Micron Technology, Inc. reserves the right to change products or specifications without notice. industrial_emmc_32_128gb_TLC_5_1_B.pdf - Rev. C 09/2021 EN © 2021 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32GB, 64GB, 128GB: Industrial e.MMC General Description General Description Micron e.MMC is a communication and mass data storage device that includes a MultiMediaCard (MMC) interface, a NAND Flash component, and a controller on an advanced 12-signal bus, which is compliant with the MMC system specification. Its cost per bit, small package sizes, and high reliability make it an ideal choice for automotive applications, including information and entertainment, navi- gation tools, advanced driving assistance systems, and a variety of other industrial and portable prod- ucts. The nonvolatile e.MMC draws no power to maintain stored data, delivers high performance across a wide range of operating temperatures, and resists shock and vibration disruption. industrial_emmc_32_128gb_tlc_5_1_b.ditamap Page 6

CCM005-841846911-10476 Micron Technology, Inc. reserves the right to change products or specifications without notice. industrial_emmc_32_128gb_TLC_5_1_B.pdf - Rev. C 09/2021 EN © 2021 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32GB, 64GB, 128GB: Industrial e.MMC Signal Descriptions Signal Descriptions Note: 1. VSS and VSSQ are connected internally. Table 6: Signal Descriptions Symbol Type Description CLK Input Clock: Each cycle of the clock directs a transfer on the command line and on the data line(s). The fre- quency can vary between the minimum and the maximum clock frequency. RST_n Input Reset: The RST_n signal is used by the host for resetting the device, moving the device to the pre-idle state. By default, the RST_n signal is temporarily disabled in the device. The host must set ECSD register byte 162, bits[1:0] to 0x1 to enable this functionality before the host can use it. CMD I/O Command: This signal is a bidirectional command channel used for command and response trans- fers. The CMD signal has two bus modes: open-drain mode and push-pull mode (see Operating Modes). Commands are sent from the MMC host to the device, and responses are sent from the device to the host. DAT[7:0] I/O Data I/O: These are bidirectional data signals. The DAT signals operate in push-pull mode. By default, after power-on or assertion of the RST_n signal, only DAT0 is used for data transfer. The MMC controller can configure a wider data bus for data transfer either using DAT[3:0] (4-bit mode) or DAT[7:0] (8-bit mode). e·MMC includes internal pull-up resistors for data lines DAT[7:1]. Immedi- ately after entering the 4-bit mode, the device disconnects the internal pull-up resistors on the DAT[3:1] lines. Upon entering the 8-bit mode, the device disconnects the internal pull-ups on the DAT[7:1] lines. DS Output Data strobe: Generated by the device and used for data output and CRC status response output in HS400 mode. The frequency of this signal follows the frequency of CLK. For data output, each cycle of this signal directs two bits transfer (2x) on the data, one bit for the positive edge and the other bit for the negative edge. For CRC status response output, the CRC status is latched on the positive edge only, and is "Don't Care" on the negative edge. VSF[7:1] Input/out put Vendor specific function: VSF[7:1] must be left floating; Exposing VSF balls on test points is recom- mended. VCC Supply VCC: NAND Flash power supply. VCCQ Supply VCCQ: e·MMC controller core, e·MMC interface I/O, and NAND interface I/O power supply. VSS 1 Supply VSS: NAND interface I/O and NAND Flash ground connection. VSSQ 1 Supply VSSQ: e·MMC controller core and e·MMC interface ground connection. VDDIM Internal voltage node: At least a 0.1μF capacitor is required to connect VDDIM to ground. A 1μF capacitor is recommended. Do not tie to supply voltage or ground. NC – No connect: No internal connection is present. RFU – Reserved for future use: No internal connection is present. Leave it floating externally. industrial_emmc_32_128gb_tlc_5_1_b.ditamap Page 7

CCM005-841846911-10476 Micron Technology, Inc. reserves the right to change products or specifications without notice. industrial_emmc_32_128gb_TLC_5_1_B.pdf - Rev. C 09/2021 EN © 2021 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32GB, 64GB, 128GB: Industrial e.MMC 153-Ball Signal Assignments 153-Ball Signal Assignments Figure 2: 153 Ball (Top View, Ball Down) Notes: 1. Some previous versions of the JEDEC product or mechanical specification had defined reserved for future use (RFU) balls as no connect (NC) balls. NC balls assigned in the previous specifications could have been connected to ground on the system board. To enable new feature introduction, some of these balls are assigned as RFU in the v4.4 mechanical specification. Any new PCB footprint implementations should use the new ball assignments and leave the RFU balls floating on the system board. 2. VCC, VCCQ, VSS, and VSSQ balls must all be connected on the system board. A B C D E F G H J K L M N P A B C D E F G H J K L M N P Top View NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC DAT3 V DDIM NC NC NC NC NC NC NC NC NC V SSQ NC DAT0 DAT4 NC NC NC NC NC NC NC NC NC NC NC V CCQ DAT1 DAT5 V SSQ NC VCCQ VCCQ VSSQ DAT2 DAT6 NC RFU V CC VSS DS VSS RST_n CMD VSSQ VCCQ VSS DAT7 VCCQ VCC RFU CLK NC VSSQ RFU NC NC V SS RFU NC NC NC NC NC NC V SS NC NC NC NC NC NC VCC NC NC NC NC NC NC V SS VCC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC VSF2 VSF3VSF1 VSF4 VSF5 VSF6 VSF7 industrial_emmc_32_128gb_tlc_5_1_b.ditamap Page 8

CCM005-841846911-10476 Micron Technology, Inc. reserves the right to change products or specifications without notice. industrial_emmc_32_128gb_TLC_5_1_B.pdf - Rev. C 09/2021 EN © 2021 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32GB, 64GB, 128GB: Industrial e.MMC Package Dimensions Package Dimensions Figure 3: 153-Ball VFBGA – 11.5mm x 13.0mm x 0.9mm (Package Code: HD) Notes: 1. Dimensions are in millimeters. 2. The package height does not include room temperature warpage. 3. In the whole eMMC package area, solder mask is recommended to cover the via pad in the PCB in order to avoid possible contact with Ni/Au plated test pads on the eMMC package. The Ni/Au plated test pads are reserved for Micron internal use only. 0.213 ±0.04 0.8 ±0.1

6.5 CTR

11.5 ±0.1

0.5 TYP

13 ±0.1 (covered by SR) Seating plane 0.08 A 153X Ø0.357 ±0.05 Dimensions apply to solder balls post-reflow on Ø0.35 SMD ball pads. 1 3 5 7 92 4 6 8 1011 1312 14 56X Ø0.27 on 0.5 pitch. Ni/Au plated test pads. No solder balls. A industrial_emmc_32_128gb_tlc_5_1_b.ditamap Page 9

CCM005-841846911-10476 Micron Technology, Inc. reserves the right to change products or specifications without notice. industrial_emmc_32_128gb_TLC_5_1_B.pdf - Rev. C 09/2021 EN © 2021 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32GB, 64GB, 128GB: Industrial e.MMC Package Dimensions Figure 4: 153-Ball VFBGA – 11.5mm x 13.0mm x 1.0mm (Package Code: JP) Notes: 1. Dimensions are in millimeters. 2. The package height does not include room temperature warpage. 3. In the whole eMMC package area, solder mask is recommended to cover the via pad in the PCB in order to avoid possible contact with Ni/Au plated test pads on the eMMC package. The Ni/Au plated test pads are reserved for Micron internal use only. 0.213 ±0.04 0.9 ±0.1 11.5 ±0.1 13 ±0.1 (covered by SR) Seating plane 0.08 A 153X Ø0.357 ±0.05 Dimensions apply to solder balls post-reflow on Ø0.35 SMD ball pads. 1 3 5 7 92 4 6 8 1011 1312 14 56X Ø0.27 on 0.5 pitch. Ni/Au plated test pads. No solder balls. A industrial_emmc_32_128gb_tlc_5_1_b.ditamap Page 10

CCM005-841846911-10476 Micron Technology, Inc. reserves the right to change products or specifications without notice. industrial_emmc_32_128gb_TLC_5_1_B.pdf - Rev. C 09/2021 EN © 2021 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32GB, 64GB, 128GB: Industrial e.MMC Architecture Architecture Figure 5: e.MMC Functional Block Diagram Note: 1. VSS and VSSQ are internally connected. MMC Protocol Independent of NAND Flash Technology The MMC specification defines the communication protocol between a host and a device. The protocol is independent of the NAND flash features included in the device. The device has an intelli- gent on-board controller that manages the MMC communication protocol. The controller also handles block management functions such as logical block allocation and wear leveling. These management functions require complex algorithms and depend entirely on NAND flash technology (generation or memory cell type). The device handles these management functions internally, making them invisible to the host processor. Defect and Error Management Micron e.MMC incorporates advanced technology for defect and error management. If a defective block is identified, the device completely replaces it with a spare block. This process is invisible to the host and does not affect user-allocated data space. The device also includes a built-in error correction code (ECC) algorithm to ensure data integrity is maintained. To best implement these advanced technologies and ensure proper data loading and storage over the life of the device, the host must follow these precautions:

• Check the status after WRITE, READ, and ERASE operations.
• Avoid power-down during WRITE and ERASE operations. As best practice, Micron recommends the usage of Power Off Notification (PON) and refresh mecha- nism. RST_n CMD CLK VDDIM VCCM VCCQM DAT[7:0] VSS VSSQ MMC controller e.MMC NAND Flash Registers OCR CSD RCA CID ECSD DSR DS industrial_emmc_32_128gb_tlc_5_1_b.ditamap Page 11

CCM005-841846911-10476 Micron Technology, Inc. reserves the right to change products or specifications without notice. industrial_emmc_32_128gb_TLC_5_1_B.pdf - Rev. C 09/2021 EN © 2021 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32GB, 64GB, 128GB: Industrial e.MMC OCR Register OCR Register The 32-bit operation conditions register (OCR) stores the voltage profile of the card and the access mode indication. In addition, this register includes a status information bit. Note: 1. OCR = C0FF8080h after the device has completed power-up. Table 7: OCR Parameters OCR Bits OCR Value Description [31] 1b (ready)/0b (busy)1 Device power-on status bit [30:29] 10b Sector mode [28:24] 0 0000b Reserved [23:15] 1 1111 1111b 2.7–3.6V voltage range [14:8] 000 0000b 2.0–2.7V voltage range [7] 1b 1.70–1.95V voltage range [6:0] 000 0000b Reserved industrial_emmc_32_128gb_tlc_5_1_b.ditamap Page 12

CCM005-841846911-10476 Micron Technology, Inc. reserves the right to change products or specifications without notice. industrial_emmc_32_128gb_TLC_5_1_B.pdf - Rev. C 09/2021 EN © 2021 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32GB, 64GB, 128GB: Industrial e.MMC CID Register CID Register The card identification (CID) register is 128 bits wide. It contains the device identification information used during the card identification phase as required by e.MMC protocol. Each device is created with a unique identification number. Table 8: CID Register Field Parameters Name Field Width CID Bits CID Value Manufacturer ID MID 8 [127:120] 13h Reserved – 6 [119:114] – Card/BGA CBX 2 [113:112] 01h OEM/application ID OID 8 [111:104] – Product name PNM 48 [103:56] 32GB: 47314D31354Ch (G1M15L) 64GB: 47314D31354Dh (G1M15M) 128GB:47314D31354Eh (G1M15N) Product revision PRV 8 [55:48] – Product serial number PSN 32 [47:16] – Manufacturing date MDT 8 [15:8] – CRC7 checksum CRC 7 [7:1] – Not used; Always 1 – 1 [0] – industrial_emmc_32_128gb_tlc_5_1_b.ditamap Page 13

CCM005-841846911-10476 Micron Technology, Inc. reserves the right to change products or specifications without notice. industrial_emmc_32_128gb_TLC_5_1_B.pdf - Rev. C 09/2021 EN © 2021 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32GB, 64GB, 128GB: Industrial e.MMC CSD Register CSD Register The card-specific data (CSD) register provides information about accessing the device contents. The CSD register defines the data format, error correction type, maximum data access time, and data transfer speed, as well as whether the DS register can be used. The programmable part of the register (entries marked with W or E in the following table) can be changed by the PROGRAM_CSD (CMD27) command. Table 9: CSD Register Field Parameters Name Field Density Size (Bits) Cell Type1 CSD Bits CSD Value CSD structure CSD_STRUCTURE – 2 R [127:126] 3h System specification version SPEC_VERS – 4 R [125:122] 4h Reserved2 – – 2 R [121:120] – Data read access time 1 TAAC3 – 8 R [119:112] 7Fh Data read access time 2 in CLK cycles (NSAC × 100) NSAC3 – 8 R [111:104] 01h Maximum bus clock frequency TRAN_SPEED – 8 R [103:96] 32h Card command classes CCC – 12 R [95:84] 8F5h Maximum read data block length READ_BL_LEN – 4 R [83:80] 09h Partial blocks for reads supported READ_BL_PARTIAL – 1 R [79] 0h Write block misalignment WRITE_BLK_MISALIGN – 1 R [78] 0h Read block misalignment READ_BLK_MISALIGN – 1 R [77] 0h DSR implemented DSR_IMP – 1 R [76] 0h Reserved – – 2 R [75:74] – Device size C_SIZE – 12 R [73:62] FFFh Maximum read current at VDD,min VDD_R_CURR_MIN – 3 R [61:59] 0h Maximum read current at VDD,max VDD_R_CURR_MAX – 3 R [58:56] 0h Maximum write current at VDD,min VDD_W_CURR_MIN – 3 R [55:53] 0h Maximum write current at VDD,max VDD_W_CURR_MAX – 3 R [52:50] 0h Device size multiplier C_SIZE_MULT – 3 R [49:47] 7h Erase group size ERASE_GRP_SIZE – 5 R [46:42] 1Fh Erase group size multiplier ERASE_GRP_MULT – 5 R [41:37] 1Fh Write protect group size WP_GRP_SIZE – 5 R [36:32] 0Fh Write protect group enable WP_GRP_ENABLE – 1 R [31] 1h Manufacturer default ECC DEFAULT_ECC – 2 R [30:29] 0h Write-speed factor R2W_FACTOR3 – 3 R [28:26] 03h Maximum write data block length WRITE_BL_LEN – 4 R [25:22] 09h industrial_emmc_32_128gb_tlc_5_1_b.ditamap Page 14

CCM005-841846911-10476 Micron Technology, Inc. reserves the right to change products or specifications without notice. industrial_emmc_32_128gb_TLC_5_1_B.pdf - Rev. C 09/2021 EN © 2021 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32GB, 64GB, 128GB: Industrial e.MMC CSD Register Notes: 1. R = Read-only; R/W = One-time programmable and readable; R/W/E = Multiple writable with value kept after a power cycle, assertion of the RST_n signal, and any CMD0 reset, and readable 2. Reserved bits should be read as 0. 3. Host should calculate the write time-out conditions as per JEDEC specification, using CSD register values TAAC, NSAC, and R2W_FACTOR, or higher. Lower time out values may result in application hang, loop forced reset, or re-boot. Additional information is provided in a separate document upon customer request. Partial blocks for writes sup- ported WRITE_BL_PARTIAL – 1 R [21] 0h Reserved – – 4 R [20:17] – Content protection application CONTENT_PROT_APP – 1 R [16] 0h File-format group FILE_FORMAT_GRP – 1 R/W [15] 0h Copy flag (OTP) COPY – 1 R/W [14] 0h Permanent write protection PERM_WRITE_PROTECT – 1 R/W [13] 0h Temporary write protection TMP_WRITE_PROTECT – 1 R/W/E [12] 0h File format FILE_FORMAT – 2 R/W [11:10] 0h ECC ECC – 2 R/W/E [9:8] 0h CRC CRC – 7 R/W/E [7:1] – Not used, always 1 – – 1 – [0] – Table 9: CSD Register Field Parameters (Continued) Name Field Density Size (Bits) Cell Type1 CSD Bits CSD Value industrial_emmc_32_128gb_tlc_5_1_b.ditamap Page 15

CCM005-841846911-10476 Micron Technology, Inc. reserves the right to change products or specifications without notice. industrial_emmc_32_128gb_TLC_5_1_B.pdf - Rev. C 09/2021 EN © 2021 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32GB, 64GB, 128GB: Industrial e.MMC ECSD Register ECSD Register The 512-byte extended card-specific data (ECSD) register defines device properties and selected modes. The most significant 320 bytes are the properties segment. This segment defines device capa- bilities and cannot be modified by the host. The lower 192 bytes are the modes segment. The modes segment defines the configuration in which the device is working. The host can change the properties of modes segments using the SWITCH command. Table 10: ECSD Register Field Parameters Name Field Density Size (Bytes) Cell Type1 ECSD Bytes ECSD Value Properties Segment Reserved2 – – 6 TBD [511:506] – Extended security error sup- port EXT_SECURITY_ERR – 1 R [505] 00h Supported command sets S_CMD_SET – 1 R [504] 01h HPI features HPI_FEATURES – 1 R [503] 01h Background operations sup- port BKOPS_SUPPORT – 1 R [502] 01h Max-packed READ com- mands MAX_PACKED_READS – 1 R [501] 00h Max-packed WRITE com- mands MAX_PACKED_WRITES – 1 R [500] 00h Data tag support DATA_TAG_SUPPORT – 1 R [499] 01h Tag unit size TAG_UNIT_SIZE – 1 R [498] 03h Tag resources size TAG_RES_SIZE – 1 R [497] 00h Context management capa- bilities CONTEXT_CAPABILITIES – 1 R [496] 05h Large unit size LARGE_UNIT_SIZE_M1 – 1 R [495] 03h Extended partitions attri- bute support EXT_SUPPORT – 1 R [494] 03h Supported modes SUPPORTED_MODES – 1 R [493] 01h Field firmware update fea- tures FFU_FEATURES – 1 R [492] 00h Operation code timeout OPERATION_CODE_TIMEOUT – 1 R [491] 00h Field firmware update argu- ments FFU_ARG – 4 R [490:487] 0000FFFFh Barrier support BARRIER_SUPPORT – 1 R [486] 01h Reserved – – 177 TBD [485:309] – CMD queuing support CMDQ_SUPPORT – 1 R [308] 01h CMD queuing depth CMDQ_DEPTH – 1 R [307] 1Fh Reserved – – 1 TBD [306] – Number of firmware sectors correctly programmed NUMBER_OF_FW_SECTORS_COR- RECTLY_PROGRAMMED – 4 R [305:302] 00h industrial_emmc_32_128gb_tlc_5_1_b.ditamap Page 16

CCM005-841846911-10476 Micron Technology, Inc. reserves the right to change products or specifications without notice. industrial_emmc_32_128gb_TLC_5_1_B.pdf - Rev. C 09/2021 EN © 2021 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32GB, 64GB, 128GB: Industrial e.MMC ECSD Register Vendor proprietary health report VENDOR_PROPRI- ETARY_HEALTH_REPORT – 32 R [301:270] 00h Device life time estimate type B DEVICE_LIFE_TIME_EST_TYP_B – 1 R [269] 01h Device life time estimate type A DEVICE_LIFE_TIME_EST_TYP_A – 1 R [268] 01h Pre-end of life information PRE_EOL_INFO – 1 R [267] 01h Optimal read size OPTIMAL_READ_SIZE – 1 R [266] 00h Optimal write size OPTIMAL_WRITE_SIZE – 1 R [265] 40h Optimal trim unit size OPTIMAL_TRIM_UNIT_SIZE – 1 R [264] 00h Device version DEVICE_VERSION – 2 R [263:262] 0000h Firmware version FIRMWARE_VERSION – 8 R [261:254] – Power class for 200 MHz DDR at VCC = 3.6V PWR_CL_DDR_200_360 – 1 R [253] 00h Cache size CACHE_SIZE 32GB 4 R [252:249] 00000800h 64GB 128GB Generic CMD6 timeout GENERIC_CMD6_TIME – 1 R [248] 0Ah Power-off notification (long) timeout POWER_OFF_LONG_TIME – 1 R [247] 32h Background operations sta- tus BKOPS_STATUS – 1 R [246] 00h Number of correctly pro- grammed sectors CORRECTLY_PROG_SECTORS_- NUM – 4 R [245:242] 00000000h First initialization time after partitioning (first CMD1 to device ready) INI_TIMEOUT_AP – 1 R [241] 0Ah Cache flushing policy CACHE_FLUSH_POLICY – 1 R [240] 01h Power class for 52 MHz, DDR at 3.6V PWR_CL_DDR_52_360 – 1 R [239] 00h Power class for 52 MHz, DDR at 1.95V PWR_CL_DDR_52_195 – 1 R [238] 00h Power class for 200 MHz at 1.95V PWR_CL_200_195 – 1 R [237] 00h Power class for 200 MHz, at 1.3V PWR_CL_200_130 – 1 R [236] 00h Minimum write perfor- mance for 8-bit at 52 MHz in DDR mode MIN_PERF_DDR_W_8_52 – 1 R [235] 00h Minimum read performance for 8-bit at 52 MHz in DDR mode MIN_PERF_DDR_R_8_52 – 1 R [234] 00h Table 10: ECSD Register Field Parameters (Continued) Name Field Density Size (Bytes) Cell Type1 ECSD Bytes ECSD Value industrial_emmc_32_128gb_tlc_5_1_b.ditamap Page 17

CCM005-841846911-10476 Micron Technology, Inc. reserves the right to change products or specifications without notice. industrial_emmc_32_128gb_TLC_5_1_B.pdf - Rev. C 09/2021 EN © 2021 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32GB, 64GB, 128GB: Industrial e.MMC ECSD Register Reserved – – 1 TBD [233] – TRIM multiplier TRIM_MULT – 1 R [232] 01h Secure feature support SEC_FEATURE_SUPPORT – 1 R [231] 51h Secure erase multiplier SEC_ERASE_MULT – 1 R [230] 01h Secure trim multiplier SEC_TRIM_MULT – 1 R [229] 01h Boot information BOOT_INFO – 1 R [228] 07h Reserved – – 1 TBD [227] – Boot partition size3 BOOT_SIZE_MULT – 1 R [226] FCh Access size ACC_SIZE – 1 R [225] 00h High-capacity erase unit size HC_ERASE_GRP_SIZE – 1 R [224] 01h High-capacity erase timeout ERASE_TIMEOUT_MULT – 1 R [223] 01h Reliable write-sector count REL_WR_SEC_C – 1 R [222] 01h High-capacity write protect group size HC_WP_GRP_SIZE 32GB 1 R [221] 10h 64GB 20h 128GB 40h Sleep current (VCC) S_C_VCC – 1 R [220] 00h Sleep current (VCCQ) S_C_VCCQ – 1 R [219] 00h Production state awareness timeout PRODUCTION_STATE_AWARE- NESS_TIMEOUT – 1 R [218] 00h Sleep/awake timeout S_A_TIMEOUT – 1 R [217] 14h Sleep notification timeout SLEEP_NOTIFICATION_TIME – 1 R [216] 0Eh Sector count SEC_COUNT 32GB 4 R [215:212] 03B48000h 64GB 07690000h 128GB 0ED20000h Secure write protect infor- mation SECURE_WP_INFO – 1 R [211] 01h Minimum write perfor- mance for 8-bit at 52 MHz MIN_PERF_W_8_52 – 1 R [210] 00h Minimum read performance for 8-bit at 52 MHz MIN_PERF_R_8_52 – 1 R [209] 00h Minimum write perfor- mance for 8-bit at 26 MHz and 4-bit at 52 MHz MIN_PERF_W_8_26_4_52 – 1 R [208] 00h Minimum read performance for 8-bit at 26 MHz and 4-bit at 52 MHz MIN_PERF_R_8_26_4_52 – 1 R [207] 00h Minimum write perfor- mance for 4-bit at 26 MHz MIN_PERF_W_4_26 – 1 R [206] 00h Table 10: ECSD Register Field Parameters (Continued) Name Field Density Size (Bytes) Cell Type1 ECSD Bytes ECSD Value industrial_emmc_32_128gb_tlc_5_1_b.ditamap Page 18

CCM005-841846911-10476 Micron Technology, Inc. reserves the right to change products or specifications without notice. industrial_emmc_32_128gb_TLC_5_1_B.pdf - Rev. C 09/2021 EN © 2021 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32GB, 64GB, 128GB: Industrial e.MMC ECSD Register Minimum read performance for 4-bit at 26 MHz MIN_PERF_R_4_26 – 1 R [205] 00h Reserved – – 1 TBD [204] – Power class for 26 MHz at 3.6V PWR_CL_26_360 – 1 R [203] 00h Power class for 52 MHz at 3.6V PWR_CL_52_360 – 1 R [202] 00h Power class for 26 MHz at 1.95V PWR_CL_26_195 – 1 R [201] 00h Power class for 52 MHz at 1.95V PWR_CL_52_195 – 1 R [200] 00h Partition switching timing PARTITION_SWITCH_TIME – 1 R [199] 01h Out-of-interrupt busy timing OUT_OF_INTERRUPT_TIME – 1 R [198] 0Fh I/O driver strength DRIVER_STRENGTH – 1 R [197] 1Fh Device type DEVICE_TYPE – 1 R [196] 57h Reserved – – 1 TBD [195] – CSD structure version CSD_STRUCTURE – 1 R [194] 02h Reserved – – 1 TBD [193] – Extended CSD revision EXT_CSD_REV – 1 R [192] 08h Modes Segment Command set CMD_SET – 1 R/W/E_P [191] 00h Reserved – – 1 TBD [190] – Command set revision CMD_SET_REV – 1 R [189] 00h Reserved – – 1 TBD [188] – Power class POWER_CLASS – 1 R/W/E_P [187] 00h Reserved – – 1 TBD [186] – High-speed interface timing HS_TIMING – 1 R/W/E_P [185] 00h Strobe support STROBE_SUPPORT – 1 R [184] 01h Bus width mode BUS_WIDTH – 1 W/E_P [183] 00h Reserved – – 1 TBD [182] – Erased memory content ERASED_MEM_CONT – 1 R [181] 00h Reserved – – 1 TBD [180] – Partition configuration PARTITION_CONFIG – 1 R/W/E, R/W/E_P [179] 00h Boot configuration protec- tion BOOT_CONFIG_PROT – 1 R/W, R/W/C_P [178] 00h Boot bus conditions BOOT_BUS_CONDITIONS – 1 R/W/E [177] 00h Reserved – – 1 TBD [176] – Table 10: ECSD Register Field Parameters (Continued) Name Field Density Size (Bytes) Cell Type1 ECSD Bytes ECSD Value industrial_emmc_32_128gb_tlc_5_1_b.ditamap Page 19

CCM005-841846911-10476 Micron Technology, Inc. reserves the right to change products or specifications without notice. industrial_emmc_32_128gb_TLC_5_1_B.pdf - Rev. C 09/2021 EN © 2021 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32GB, 64GB, 128GB: Industrial e.MMC ECSD Register High-density erase group definition ERASE_GROUP_DEF – 1 R/W/E_P [175] 00h Boot write protection status registers BOOT_WP_STATUS – 1 R [174] 00h Boot area write protection register BOOT_WP – 1 R/W, R/W/C_P [173] 00h Reserved – – 1 TBD [172] – User write protection regis- ter USER_WP – 1 R/W, R/W/C_P, R/W/E_P [171] 00h Reserved – – 1 TBD [170] – Firmware configuration FW_CONFIG – 1 R/W [169] 00h RPMB size RPMB_SIZE_MULT – 1 R [168] 20h Write reliability setting regis- ter4 Write reliability parameter register WR_REL_SET – 1 R/W [167] 1Fh WR_REL_PARAM – 1 R [166] 15h SANITIZE START operation SANITIZE_START – 1 W/E_P [165] 00h Manually start background operations BKOPS_START – 1 W/E_P [164] 00h Enable background opera- tions handshake BKOPS_EN – 1 R/W, R/W/E [163] 02h Hardware reset function RST_n_FUNCTION – 1 R/W [162] 00h HPI management HPI_MGMT – 1 R/W/E_P [161] 00h Partitioning support PARTITIONING_SUPPORT – 1 R [160] 07h Maximum enhanced area size MAX_ENH_SIZE_MULT 32GB 3 R [159:157] 0004F0h 64GB 0004F0h 128GB 0004F0h Partitions attribute PARTITIONS_ATTRIBUTE – 1 R/W [156] 00h Partitioning setting PARTITION_SETTING_COMPLETED – 1 R/W [155] 00h General-purpose partition size GP_SIZE_MULT – 12 R/W [154:143] 00h Enhanced user data area size ENH_SIZE_MULT – 3 R/W [142:140] 000000h Enhanced user data start address ENH_START_ADDR – 4 R/W [139:136] 00000000h Reserved – – 1 TBD [135] – Bad block management mode SEC_BAD_BLK_MGMNT – 1 R/W [134] 00h Production state awareness PRODUCTION_STATE_AWARENESS – 1 R/W/E [133] 00h Package case temperature is controlled TCASE_SUPPORT – 1 W/E_P [132] 00h Table 10: ECSD Register Field Parameters (Continued) Name Field Density Size (Bytes) Cell Type1 ECSD Bytes ECSD Value industrial_emmc_32_128gb_tlc_5_1_b.ditamap Page 20

CCM005-841846911-10476 Micron Technology, Inc. reserves the right to change products or specifications without notice. industrial_emmc_32_128gb_TLC_5_1_B.pdf - Rev. C 09/2021 EN © 2021 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32GB, 64GB, 128GB: Industrial e.MMC ECSD Register Periodic wake-up PERIODIC_WAKEUP – 1 R/W/E [131] 00h Program CID/CSD in DDR mode support PROGRAM_CID_CSD_DDR_SUP- PORT – 1 R [130] 01h Reserved – – 2 TBD [129:128] – Vendor specific fields VENDOR_SPECIFIC_FIELD – 64 <vendor specific> [127:64] – Native sector size NATIVE_SECTOR_SIZE – 1 R [63] 00h Sector size emulation USE_NATIVE_SECTOR – 1 R/W [62] 00h Sector size DATA_SECTOR_SIZE – 1 R [61] 00h 1st initialization after dis- abling sector size emulation INI_TIMEOUT_EMU – 1 R [60] 00h Class 6 commands control CLASS_6_CTRL – 1 R/W/E_P [59] 00h Number of addressed group to be released DYNCAP_NEEDED – 1 R [58] 00h Exception events control EXCEPTION_EVENTS_CTRL – 2 R/W/E_P [57:56] 0000h Exception events status EXCEPTION_EVENTS_STATUS – 2 R [55:54] 0000h Extended partitions attribute EXT_PARTITIONS_ATTRIBUTE – 2 R/W [53:52] 0000h Context configuration CONTEXT_CONF – 15 R/W/E_P [51:37] 00h Packed command status PACKED_COMMAND_STATUS – 1 R [36] 00h Packed command failure index PACKED_FAILURE_INDEX – 1 R [35] 00h Power-off notification POWER_OFF_NOTIFICATION – 1 R/W/E_P [34] 00h Control to turn the cache on/off CACHE_CTRL – 1 R/W/E_P [33] 00h Flushing of the cache FLUSH_CACHE – 1 W/E_P [32] 00h Control to turn the barrier on/off BARRIER_CTRL – 1 R/W [31] 00h Mode configuration MODE_CONFIG – 1 R/W/E_P [30] 00h Mode operation codes MODE_OPERATION_CODES – 1 W/E_P [29] 00h Reserved – – 2 TBD [28:27] – Field firmware update status FFU_STATUS – 1 R [26] 00h Pre-loading data size PRE LOADING DATA SIZE – 4 R/W/E_P [25:22] 00h Maximum pre-loading data size MAX_PRE_LOADING_DATA_SIZE 32GB 4 R [21:18] 035B9400h 64GB 06B72800h 128GB 0D6E5000h Product state awareness enablement PRODUCT_STATE_AWARE- NESS_ENABLEMENT – 1 R/W/E&R [17] 03h Secure removal type SECURE_REMOVAL_TYPE – 1 R/W&R [16] 01h Table 10: ECSD Register Field Parameters (Continued) Name Field Density Size (Bytes) Cell Type1 ECSD Bytes ECSD Value industrial_emmc_32_128gb_tlc_5_1_b.ditamap Page 21

CCM005-841846911-10476 Micron Technology, Inc. reserves the right to change products or specifications without notice. industrial_emmc_32_128gb_TLC_5_1_B.pdf - Rev. C 09/2021 EN © 2021 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32GB, 64GB, 128GB: Industrial e.MMC ECSD Register Notes: 1. R = Read-only; R/W = One-time programmable and readable; R/W/E = Multiple writable with the value kept after a power cycle, assertion of the RST_n signal, and any CMD0 reset, and readable; R/W/C_P = Writable after the value is cleared by a power cycle and assertion of the RST_n signal (the value not cleared by CMD0 reset) and readable; R/W/E_P = Multiple writable with the value reset after a power cycle, assertion of the RST_n signal, and any CMD0 reset, and readable; W/E_P = Multiple writable with the value reset after power cycle, assertion of the RST_n signal, and any CMD0 reset, and not readable 2. Reserved bits should be read as 0. 3. Boot partition size is configurable by host. Refer to local Micron support for information. 4. Micron has tested power failure under best-application knowledge conditions with positive results. Customers may request a dedicated test for their specific application condition. Micron set this register during factory test and used the one-time programming option. Command queue mode enable CMDQ_MODE_EN – 1 R/W/E_P [15] 00h Reserved – – 15 TBD [14:0] – Table 10: ECSD Register Field Parameters (Continued) Name Field Density Size (Bytes) Cell Type1 ECSD Bytes ECSD Value industrial_emmc_32_128gb_tlc_5_1_b.ditamap Page 22

CCM005-841846911-10476 Micron Technology, Inc. reserves the right to change products or specifications without notice. industrial_emmc_32_128gb_TLC_5_1_B.pdf - Rev. C 09/2021 EN © 2021 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32GB, 64GB, 128GB: Industrial e.MMC The device current consumption for various device configurations is defined in the power class fields of the ECSD register. VCC is used for the NAND Flash device ; VCCQ is used for the controller and for the e.MMC and NAND interface voltage. Figure 6: Device Power Diagram Note: 1. Voltage on any pin relative to VSS. Table 11: Absolute Maximum Ratings Parameters Symbol Min Max Unit Voltage input VIN –0.2 2.4 V VCC supply VCC –0.6 4.6 V VCCQ supply VCCQ –0.2 2.4 V NAND control signals MMC controller Core regulator Core logic block CLK VDDIM NAND data bus C5 C6 DAT[7:0] VCCQ CLK CMD RST_n DS VCCQ VCC C1 C2 VCCQ C3 C4 NAND I/O block MMC I/O block VCCQ NAND I/O NAND Flash industrial_emmc_32_128gb_tlc_5_1_b.ditamap Page 23

CCM005-841846911-10476 Micron Technology, Inc. reserves the right to change products or specifications without notice. industrial_emmc_32_128gb_TLC_5_1_B.pdf - Rev. C 09/2021 EN © 2021 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32GB, 64GB, 128GB: Industrial e.MMC Product Features Notes: 1. Used to prevent bus floating. 2. If host does not use H/W RESET (RST_n), pull-up resistance is not needed on RST_n line (Extended_CSD[162] = 00h). 3. Impedance match. 4. Recommended in order to compensate eventual impedance mismatch on the PCB. 5. The coupling capacitor should be connected with VCCQ and VSSQ as closely as possible. 6. The coupling capacitor should be connected with VCC and VSS as closely as possible. 7. The coupling capacitor should be connected with VDDIM and VSS as closely as possible. Product Features The list below shows the JEDEC features not supported. See the full JEDEC/MMC Standard No. 84-B51 available at www.jedec.org/sites/default/files/docs/JESD84-B51.pdf

• Packed CMDs
• Context ID/Data tag (this feature is implemented at the protocol level)
• Dynamic device capacity
• Thermal spec
• Large sector size - 4KB (<256GB)
• Extended security protocol
• Secure erase/secure trim*
• Forced erase* * The feature implements as logical erase mode: It moves the mapped host address range to the unmapped host address range. When the operation is complete, the data still exists, but the mapped device address range behaves as if overwritten with all 0s. Table 12: Capacitor and Resistance Specifications Parameter Symbol Min Max Typ Units Notes Pull-up resistance: CMD R_CMD 4.7 50 10 kΩ 1 Pull-up resistance: DAT[7:0] R_DAT 10 50 50 kΩ 1 Pull-up resistance: RST_n R_RST_n 4.7 50 50 kΩ 2 CLK/CMD/DS/DAT[7:0] impedance 45 55 50 Ω 3 Serial resistance on CLK SR_CLK 0 47 22 Ω Serial resistance on DS SR_DS 0 47 22 Ω 4 Pull-down resistance: DS R_DS 10 100 – kΩ VCCQ capacitor C1 2.2 4.7 2.2 µF 5 C2 0.1 0.22 0.1 VCC capacitor C3 2.2 4.7 2.2 µF 6 C4 0.1 0.22 0.1 VDDIM capacitor (Creg) C5 1 4.7 1 µF 7 C6 0.1 0.1 0.1 industrial_emmc_32_128gb_tlc_5_1_b.ditamap Page 24

CCM005-841846911-10476 Micron Technology, Inc. reserves the right to change products or specifications without notice. industrial_emmc_32_128gb_TLC_5_1_B.pdf - Rev. C 09/2021 EN © 2021 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32GB, 64GB, 128GB: Industrial e.MMC

Revision History

Rev. C – 09/2021

• Updated legal status to Production
• Updated temperature ranges
• Remove ES from WT MPNs
• Updated VSF pins description
• Updated CSD register: Updated write-speed factor value; Added note 3 Rev. B – 05/2021
• Updated Features section
• Added Note 3 to Package Dimensions section
• Updated Ordering Information Table: Removed ES from IT MPNs
• Updated ECSD Register Field Parameters table Rev. A – 01/2021
• Initial release 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006 208-368-4000, micron.com/support Micron and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. industrial_emmc_32_128gb_tlc_5_1_b.ditamap Page 25