MTEE2N20FP CYSTEKEC | Alldatasheet

Document overview

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  • PDF pages: 10

Technical content

Features

  • Low On Resistance
  • Simple Drive Requirement
  • Low Gate Charge
  • Fast Switching Characteristic
  • Insulating package, front/back side insulating voltage=2500V(AC)
  • RoHS compliant package Symbol Outline MTEE2N20FP TO-220FP G：Gate D：Drain S：Source G D S

CYStech Electronics Corp. Spec. No. : C881FP Issued Date : 2012.11.20 Revised Date : 2013.05.24 Page No. : 2/ 10 MTEE2N20FP CYStek Product Specification Absolute Maximum Ratings (TC=25°C) Parameter Symbol Limits Unit Drain-Source V oltage (Note 1) VDS 200 Gate-Source V oltage VGS ±30 V Continuous Drain Current @TC=25°C, VGS=10V (Note 1) 4* Continuous Drain Current @TC=100°C, VGS=10V (Note 1) ID 2.8* Continuous Drain Current @TA=25°C, VGS=10V (Note 2) 1.2 Continuous Drain Current @TA=70°C, VGS=10V (Note 2) IDSM 0.9 Pulsed Drain Current @ VGS=10V (Note 3) IDM 9* Avalanche Current (Note 3) IAR 2 A Single Pulse Avalanche Energy @ L=10mH, ID=2Amps, VDD=50V (Note 2) EAS 20 Repetitive Avalanche Energy (Note 3) EAR 2.5 mJ TC=25°C (Note 1) 25 TC=100°C (Note 1) PD 12 TA=25°C (Note 2) 2 Power Dissipation TA=70°C (Note 2) PDSM 1.3 W Maximum Temperature for Soldering @ Lead at 0.063 in(1.6mm) from case for 10 seconds TL 300 Maximum Temperature for Soldering @ Package Body for 10 seconds TPKG 260 Operating Junction and Storage Temperature Tj, Tstg -55~+175 *Drain current limited by maximum junction temperature Thermal Data Parameter Symbol Value Unit Thermal Resistance, Junction-to-case, max RθJC 6 °C/W Thermal Resistance, Junction-to-ambient, max (Note 2) RθJA 62.5 °C/W Note : 1.The power dissipation PD is based on TJ(MAX)=175°C, using junction-to-case thermal resistance, and is more useful in setting the upper dissipation limit for cases where additional heatsinking is used. 2. The value of RθJA is measured with the device mounted on 1 in²FR-4 board with 2 oz. copper, in a still air environment with TA=25°C. The power dissipation PDSM is based on RθJA and the maximum allowed junction temperature of 150°C. The value in any given application depends on the user’s specific board design, and the maximum temperature of 175°C may be used if the PCB allows it. 3. Repetitive rating, pulse width limited by junction temperature TJ(MAX)=175°C. Ratings are based on low frequency and low duty cycles to keep initial TJ=25°C.

CYStech Electronics Corp. Spec. No. : C881FP Issued Date : 2012.11.20 Revised Date : 2013.05.24 Page No. : 3/ 10 MTEE2N20FP CYStek Product Specification Characteristics (Tj=25°C, unless otherwise specified) Symbol Min. Typ. Max. Unit Test Conditions Static BVDSS 200 - - V VGS=0V , ID=250μA ∆BVDSS/∆Tj - 0.2 - V/°C Reference to 25°C, ID=250μA VGS(th) 2.5 3.5 4.5 V VDS = VGS, ID=250μA *GFS - 1 - S VDS =40V , ID=1A IGSS - - ±100 nA VGS=±30V IDSS - - 10 VDS =200V , VGS =0V IDSS - - 100 μA VDS =160V , VGS =0V , Tj=125°C - 650 800 VGS =10V , ID=2.9A *RDS(ON) - 590 730 mΩ VGS =7V , ID=1A Dynamic *Qg - 6.5 - *Qgs - 1.3 - *Qgd - 3.3 - nC VDD=160V , ID=4A,VGS=10V *td(ON) - 9 - *tr - 16 - *td(OFF) - 15 - *tf - 13 - ns VDD=100V , ID=4A, VGS=10V , RG=25Ω Ciss - 232 - Coss - 25 - Crss - 9.1 - pF VGS=0V , VDS=25V , f=1MHz Source-Drain Diode *IS - - 2 *ISM - - 8 A *VSD - 0.77 1.2 V IS=1A, VGS=0V *trr - 120 - ns *Qrr - 500 - nC VGS=0, IF=2A, dI/dt=100A/μs *Pulse Test : Pulse Width ≤300μs, Duty Cycle≤2%

Ordering Information

MTEE2N20FP-0-UB-S TO-220FP (RoHS compliant) 50 pcs/tube, 20 tubes/box, 4 boxes / carton

CYStech Electronics Corp. Spec. No. : C881FP Issued Date : 2012.11.20 Revised Date : 2013.05.24 Page No. : 4/ 10 MTEE2N20FP CYStek Product Specification Typical Characteristics Typical Output Characteristics 048 1 2 1 6 2 Brekdown Voltage vs Ambient Temperature 0.4 0.6 0.8 1.2 1.4 -75 -50 -25 0 25 50 75 100 125 150 175 Tj, Junction Temperature(°C) BVDSS, Normalized Drain-Source Breakdown Voltage ID=250μA, VGS=0V 10V,9V,8V,7V,6.5V,6V VDS, Drain-Source Voltage(V) ID, Drain Current (A) 5.5V V =5VGS Static Drain-Source On-State resistance vs Drain Current 100 1000 10000 0.01 0.1 1 10 ID, Drain Current(A) RDS(on), Static Drain-Source On-State Resistance(mΩ) VGS=10V Reverse Drain Current vs Source-Drain Voltage 0.2 0.4 0.6 0.8 1.2 012345678 I DR, Reverse Drain Current(A) VSD, Source-Drain Voltage(V) Tj=25°C Tj=150°C VGS=0V Static Drain-Source On-State Resistance vs Gate-Source Voltage 500 600 700 800 900 1000 02468 1 Drain-Source On-State Resistance vs Junction Tempearture 0.4 0.8 1.2 1.6 2.4 2.8 -60 -20 20 60 100 140 180 Tj, Junction Temperature(°C) RDS(on), Normalized Static Drain- Source On-State Resistance VGS=10V, ID=2.9A RDS(ON)@Tj=25°C : 650mΩ VGS, Gate-Source Voltage(V) RDS(on), Static Drain-Source On- State Resistance(mΩ) ID=2.9A

CYStech Electronics Corp. Spec. No. : C881FP Issued Date : 2012.11.20 Revised Date : 2013.05.24 Page No. : 5/ 10 MTEE2N20FP CYStek Product Specification Typical Characteristics(Cont.) Capacitance vs Drain-to-Source Voltage 100 1000 0.1 1 10 100 VDS, Drain-Source Voltage(V) Capacitance---(pF) Coss Ciss Crss Threshold Voltage vs Junction Tempearture 0.2 0.4 0.6 0.8 1.2 1.4 -60 -20 20 60 100 140 180 Tj, Junction Temperature(°C) VGS(th), Normalized Threshold Voltage ID=250μA Forward Transfer Admittance vs Drain Current 0.01 0.1 0.001 0.01 0.1 1 ID, Drain Current(A) GFS, Forward Transfer Admittance(S) Ta=25°C Pulsed VDS=40V Gate Charge Characteristics 02468 Qg, Total Gate Charge(nC) VGS, Gate-Source Voltage(V) VDS=160V ID=4A Maximum Safe Operating Area 0.01 0.1 0.1 1 10 100 1000 VDS, Drain-Source Voltage(V) ID, Drain Current(A) TC=25°C, Tj=175°C VGS=10V, θJC=6°C/W Single Pulse DC 100ms RDSON Limited 100μs 1ms 10ms Maximum Drain Current vs Case Temperature 0.5 1.5 2.5 3.5 4.5 25 50 75 100 125 150 175 200 TC, Case Temperature(°C) ID, Maximum Drain Current(A)VGS=10V, RθJC=6°C/W

CYStech Electronics Corp. Spec. No. : C881FP Issued Date : 2012.11.20 Revised Date : 2013.05.24 Page No. : 6/ 10 MTEE2N20FP CYStek Product Specification Typical Characteristics(Cont.) Typical Transfer Characteristics 02468 1 0 1 2 V GS, Gate-Source Voltage(V) ID, Drain Current(A) VDS=10V Power Derating Curve 0 25 50 75 100 125 150 175 200 T C, Case Temperature(℃) PD, Power Dissipation(W) Transient Thermal Response Curves 0.01 0.1 t1, Square Wave Pulse Duration(s) r(t), Normalized Effective Transient Thermal Resistance Single Pulse 0.01 0.02 0.05 0.1 0.2 D=0.5 1.RθJC(t)=r(t)*RθJC 2.Duty Factor, D=t1/t2 3.TJM-TC=PDM*RθJC(t) 4.RθJC=6°C/W

CYStech Electronics Corp. Spec. No. : C881FP Issued Date : 2012.11.20 Revised Date : 2013.05.24 Page No. : 7/ 10 MTEE2N20FP CYStek Product Specification Test Circuit and Waveforms

CYStech Electronics Corp. Spec. No. : C881FP Issued Date : 2012.11.20 Revised Date : 2013.05.24 Page No. : 8/ 10 MTEE2N20FP CYStek Product Specification Test Circuit and Waveforms(Cont.)

CYStech Electronics Corp. Spec. No. : C881FP Issued Date : 2012.11.20 Revised Date : 2013.05.24 Page No. : 9/ 10 MTEE2N20FP CYStek Product Specification Recommended wave soldering condition Product Peak Temperature Soldering Time Pb-free devices 260 +0/-5 °C 5 +1/-1 seconds Recommended temperature profile for IR reflow Profile feature Sn-Pb eutectic Assembly Pb-free Assembly Average ramp-up rate (Tsmax to Tp) 3°C/second max. 3°C/second max. Preheat −Temperature Min(TS min) −Temperature Max(TS max) −Time(ts min to ts max) 100°C 150°C 60-120 seconds 150°C 200°C 60-180 seconds Time maintained above: −Temperature (TL) − Time (tL) 183°C 217°C 60-150 seconds 60-150 seconds Peak Temperature(TP) 240 +0/-5 °C 260 +0/-5 °C Time within 5°C of actual peak temperature(tp) 10-30 seconds 20-40 seconds Ramp down rate 6°C/second max. 6°C/second max. Time 25 °C to peak temperature 6 minutes max. 8 minutes max. Note : All temperatures refer to topside of the package, measured on the package body surface.

CYStech Electronics Corp. Spec. No. : C881FP Issued Date : 2012.11.20 Revised Date : 2013.05.24 Page No. : 10/ 10 MTEE2N20FP CYStek Product Specification TO-220FP Dimension *Typical Inches Millimeters Marking: A1 0.051 REF 1.300 REF H 0.138 REF 3.50 REF e 0.100 * 2.54* N 0.012 REF 0.30 REF F 0.106 REF 2.70 REF Notes: 1.Controlling dimension: millimeters. 2.Maximum lead thickness includes lead finish thickness, and minimum lead thickness is the minimum thickness of base material. 3.If there is any question with packing specification or packing method, please contact your local CYStek sales office. Material:

  • Lead: Pure tin plated.
  • Mold Compound: Epoxy resin family, flammability solid burning class: UL94V-0. Important Notice:
  • All rights are reserved. Reproduction in whole or in part is prohibited without the prior written approval of CYStek.
  • CYStek reserves the right to make changes to its products without notice.
  • CYStek semiconductor products are not warranted to be suitable for use in Life-Support Applications, or systems.
  • CYStek assumes no liability for any consequence of customer product design, infringement of patents, or application assistance. Style: Pin 1.Gate 2.Drain 3.Source 3-Lead TO-220FP Plastic Package CYStek Package Code: FP Date Code Device Name EE2 N20