MT9V403

MT9V403 MICRON | Alldatasheet

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Features

• Array Format: Active: 659H x 494V  Pixel Size and Type: 9.9µm x 9.9µm TrueSNAP™ (shuttered-node active pixel)  Optical Format: 1/2-inch  Frame Rate: 0-200 fram es/sec progressive scan  Data Rate: 66 MB/s (master clock 66 MHz)  Responsivity: 2.0 V/lux-sec with source Illumination at 550nm  SNR: 45dB  ADC: On-chip, 10-bit  Power: 130mW at 200 fps  Supply Voltage: +3.3V  Internal Intra-Scene Dynamic Range: 60dB  Operating Temperature: -5°C to +70°C  Output: 10-bit digital through a single port  Shutter: TrueSNAP freeze-frame electronic shutter  Interface Mode: Master/Snapshot/Slave (with simultaneous or sequential exposure/readout)  Shutter Efficiency: 98.5% S h u t t e r E x p o s u r e T i m e :  Master Mode or Snapshot Mode: 2 rows to 256 frames (20µs to 1.3 sec with 66 MHz clock)  Slave Mode: user controlled  Gain: 1x–18x (step size = 1) or 0.5x–9x (step size = 0.5)  Control Interface: Two- wire serial interface  Package: 48-pin CLCC  Timing and Control: On-chip:  ADC controls, output multiplexing, ADC calibra- tion via two-wire serial interface, exposure time, read/write ADC calibration coefficients, window size and location, gain, biases, master vs. snap- shot vs. slave, simultaneous vs. continuous expo- sure/readout, progressive vs. interlace, ADC reference, vertical and horizontal blanking. Off-chip:  Exposure trigger (snapshot mode), exposure and readout timing (slave mode)  Color Specifications: monochrome or color (Bayer pattern)

Description

The Micron ® Imaging MT9V403 VGA-based CMOS active-pixel sensor has a 1/2-inch optical format and delivers superb resolution at a turbocharged 200 fps, making it the perfect solution for machine vision assembly lines, airbag deployment, golf swing analysis, and special effects in movies. The freeze-frame shutter allows the signal charges of all pixels to be integrated in parallel—all pixels star t integrating simultaneously and stop integrating simult aneously. The charges are then sampled into pixel analog memories (one mem- ory per pixel) and consequently, row by row, are digi- tized and read out-of-chip. The sensor works in master, snapshot, or slave mode. In master mode it generates the readout timing on-chip. In snapshot mode it accepts an external trigger and then generates the readout timing. In slave mode the sensor accepts external readout timing. Th e integration time is pro- grammed through the two-wire serial interface (mas- ter or snapshot mode) or controlled via externally- generated control signals (slave mode). The scanning mode can be progressive or inter- laced. There is also an option to scan just a window of interest by choosing star t row and column and stop row and column. The user can control the frame rate and row rate through the use of vertical and horizontal blanking as well as the master clock frequency. The readout of the data out of the chip can be done simultaneously with integration and ADC operation due to the two-cell SRAM which allows data from the previously converted row to be shifted into the output memory for readout. The sensor’ s ADCs contain special self-calibrating circuitry that allow the sensor to reduce its own col- umn-wise fixed pattern noise. The calibration coeffi- cients can be read from, and written to, the sensor.

1/2-INCH VGA (WITH FREEZE-FRAME) CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR 09005aef80c07280 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9V403_DS.fm - Rev. B 1/04 EN 2 ©2004 Micron Technology. Inc. Figure 1: Block Diagram Reset Expose Frame Row Sensor Interface Block Control Logic Row Decoder Pixel Array Column PGA Column ADCs and calibration memory 667H x 10 SRAM (x2) ADC and Output Registers Gain Control Calibration Data Readout Control Two-Wire Serial Interface Output (9:0) System Clock System Clock System Data Table 1: Pin Description PIN NUMBERS SIGNAL NAME TYPE DESCRIPTIONS 37 SYSCLK Input Clock input for entire chip. Maximum design frequency is 66 MHz (50 percent, ±5 percent duty cycle). 33 LRST_N Input Global logic RESET function (asynchronous). Active low pulse with minimum duration 200ns. 30 ROW_STRT Input Slave mode input signal. Starts row processing sequence of the pixel row (i.e., pixel readout, ADC conversion, and writing of data to ADC registers). The rising edge of ROW_STRT should be synchronous with the falling edge of SYSCLK. A one-clock cycle wide active high pulse. The two-wire serial interface register setting switches this pin between input and output. 31 LD_SHFT_N Input Slave mode input signal. An active LOW signal that enables the column counter and initiates the readout process. Causes the 10-bit output port to be updated with data on the rising edge of the system clock. The two-wire serial interface register setting switches this pin between input and output. 29 EXPOSE Input Trigger for snapshot mode. The two-wire serial interface register setting switches this pin between input and output. No connection should be made in slave mode. 26 PG_N Input Slave mode input signal. Active low pulse that resets all photodetectors, starting a new integration cycle. No connection should be made in master mode or snapshot mode. 25 TX_N Input Slave mode input signal. Active low pulse that controls transfer of charge from photodetector to memory inside each pixel for the entire pixel array. No connection should be made in master mode or snapshot mode. 24 RESMEM Input Slave mode input signal. Active low pulse to reset all pixel memories. No connection should be made in master mode or snapshot mode. 38 SCLK Input Serial port clock. Maximum frequency is 1 MHz. 18 VLNS Input Bias setting voltage for VLN_AMP or VLN_OUT. VLN_AMP and VLN_OUT can be individually disconnected from their internal biases via the two-wire serial interface and driven by this input. 17 VLN1 Input Bias setting voltage for pixel source following operating current. 19 VLP Input Bias setting voltage for the column source follower operating current. 13 VOFF Input Dark offset cancellation. Polarity of offset is set via the two-wire serial interface. 16 V REF Input Op amp bias.

1/2-INCH VGA (WITH FREEZE-FRAME) CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR 09005aef80c07280 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9V403_DS.fm - Rev. B 1/04 EN 3 ©2004 Micron Technology. Inc. 9V REF1 Input ADC reference voltage that sets the maximum input signal level, setting the size of the least significant bit (LSB) in the analog to digital conversion process. 8V REF1DRV Input ADC bias. 7V REF2 Input ADC reference used for the calibration operation. 32 FRAME_SYNC_N Input Slave mode input signal. Active low pulse to reset row and column counters, providing frame synchronization. Low duration should be at least two-clock cycles wide. An input that is held LOW also sets the sensor in LOW, per standby mode, until it is released. Signal is pulled up on-chip. 14 VTEST Input The user should ground this pin. 23 VRSTLOW Input Offset that may be needed for very short exposure conditions. 21 VLN2 Input Bias setting voltage for the ADC operating current.

39 SDATA Input/

Serial port data. 30 FRAME_VALID Output Master mode and snapshot mode output signal. Active HIGH during readout. The two-wire serial interface register setting switches this pin between input and output. 31 ROW_VALID Output Master mode and snapshot mode output signal. Active HIGH when image data are on data output bus. The two-wire serial interface register setting switches this pin between input and output. 29 EXPOSE Output Master mode output signal. Active HIGH during exposure. The two-wire serial interface register setting switches this pin between input and output. 41 DATA9 Output Pixel output data bit 9 (MSB). 40 DATA8 Output Pixel output data bit 8. 45 DATA7 Output Pixel output data bit 7. 42 DATA6 Output Pixel output data bit 6. 46 DATA5 Output Pixel output data bit 5. 47 DATA4 Output Pixel output data bit 4. 48 DATA3 Output Pixel output data bit 3. 1D A T A 2 O u t p u t Pixel output data bit 2. 2D A T A 1 O u t p u t Pixel output data bit 1. 3D A T A 0 O u t p u t Pixel output data bit 0 (LSB). 12, 22 V AA Power 3.3V power supply for analog signal processing circuitry. 20 VRST_PIX Power Power supply for pixel array. Set for 2.5V. 10, 11, 15 A GND Power Ground for analog signal processing circuitry. 6, 27, 36, VDD Power 3.3V digital power supply. 4, 5, 28, 34, 35, 44 DGND Power Ground for digital circuitry. Table 1: Pin Description (continued) PIN NUMBERS SIGNAL NAME TYPE DESCRIPTIONS

1/2-INCH VGA (WITH FREEZE-FRAME) CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR 09005aef80c07280 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9V403_DS.fm - Rev. B 1/04 EN 5 ©2004 Micron Technology. Inc. Figure 5: Master Mode Row Timing Diagram NOTE: Horizontal blanking is nominally 35 rows, and may be increased using register 5. In master mode the frame rate is controlled by inserting vertical and/or horizontal blanking periods during readout, or by changing the input master clock (SYSCLK) frequency (i.e., slowing the sensor down), or by changing the number of rows being readout (i.e., window size). Table 2 shows some examples of how the frame rate changes with window resolution and clock speed. Table 2: Frame Rate vs. Resolution and Clock Speed No blanking, exposure < readout When horizontal blanking is utilized, the ROW_VALID stays LOW for an additional user-pro- grammable number of clock cycles after each row readout. As a result the row time becomes: RT = (1 + 66 6+ 4 + HB) x (1/fsysclk) where HB is the horizontal blanking in SYSCLK cycles (255 clock maximum) specified in register 5. When vertical blanking is utilized, the FRAME_ VALID signal stays LOW for an additional user pro- grammable number of rows after the frame is readout (if exposure time < readout time) or exposed (if expo- sure time > readout time). Table 3 on page 6 shows the various scenarios for calculating the frame time, where VB is the vertical blanking in rows (255 rows maxi- mum) specified in register 6. The default vertical b l a n k i n g i s o n e S Y S C L K c y c l e , s o t h e t r u e v e r t i c a l blanking time is the numb er of blanking rows pro- grammed plus one clock cycle. Horizontal Blanking SYSCLK (input) ROW _VALID (output) DATA [9:0] (output) XXX XXX 12 653 671 671 169 1 12 9 10 648 649 91 0 652 RESOLUTION (# ROWS) CLOCK SPEED (SYSCLK) FRAME RATE (FRAMES/SECOND) 502 (full resolution) 66 MHz 196 251 66 MHz 392 125 66 MHz 784 63 66 MHz 1568 502 (full resolution) 24 MHz 70 251 24MHz 140 125 24 MHz 280 63 24 MHz 560 502 (full resolution) 10 MHz 30

1/2-INCH VGA (WITH FREEZE-FRAME) CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR 09005aef80c07280 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9V403_DS.fm - Rev. B 1/04 EN 6 ©2004 Micron Technology. Inc. Table 3: Determination of Frame Timing NOTE: N = number of rows in image RT = row time VB = vertical blanking rows (255 rows maximum); set in register 6 HB = horizontal blanking in SYSCLK cycles (255 maximum); set forth in register 6 Simultaneous Master Mode There are two possible operation methods for mas- ter mode: simultaneous master mode and sequential master mode. One of these operation modes must be selected via the two-wire se rial interface. In simulta- neous master mode the exposure period occurs during readout. The frame synchronization waveforms are shown in Figure 6 and Figure 7. This is the fastest mode of operation since the exposure and readout are happening in parallel rather than sequentially. Please note that with this speed optimized timing the first row readout is the last row of the previous frame that is still in the row memory. Figure 6: Simultaneous Master Mode Frame Synchronization Waveforms readout time > exposure time NOTE: Vertical blanking is nominally 1 SYSCLK and 0 row times, and may be increased by using register 6. Figure 7: Simultaneous Master Mode Frame Synchronization Waveforms exposure time > readout time NOTE: Vertical blanking is nominally 1 SYSCLK and 0 row times, and may be increased by using register 6. EXPOSURE TIME > READOUT TIME READOUT TIME > EXPOSURE TIME No Blanking Frame Time = Exposure Time Frame Time = N x RT With Vertical Blanking Frame Time = Exposure Time + VB Frame Time = (N + VB) x RT Vertical Blanking EXPOSE (output) FRAME_VALID (output) ROW_VALID (output) DATA [9:0] (output) Exposure Time XXX XXXRow Row Row N Row N-1 Row 479 Row 478 Row 481 Row Row

2 XXXXXXXXX Row

N Row N-1 Row 479 Row 478XXX Row 480( Vertical Blanking EXPOSE (output) FRAME_VALID (output) ROW_VALID (output) DATA [9:0] (output) Exposure Time XXX XXXRow Row Row 479 Row 478 Row Row Row 480 Row 479 Row 478 Row 480( Row 481

1/2-INCH VGA (WITH FREEZE-FRAME) CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR 09005aef80c07280 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9V403_DS.fm - Rev. B 1/04 EN 9 ©2004 Micron Technology. Inc. Figure 12: Slave Mode Block Diagram Simultaneous Slave Mode There are two possible operation methods for slave mode: simultaneous slave and sequential slave mode. The method of operation selected is determined by the means in which the user supplies the control signals. In simultaneous slave mode the exposure period occurs during readout. The row and frame synchroni- zation waveforms are shown in Figures 13 and 14, respectively. This is the fastest mode of operation since the exposure and readout are happening in parallel rather than sequentially. The PG_N, TX_N, and RES- MEM pulses should have a minimum duration of 338 clock cycles and be applied between the 100th and 600th clocks of a given row. Row Counter (1 to 502 MAX) Row Sequencer (1 to 671) Column Counter (1 to 667 MAX) Two-Wire Serial Interface TX_N RESMEMPG_N FRAME_SYNC_N ROW_STRT CLEAR CLEAR CLEAR Reg14 LD_SHFT_N SYSCLK Output(9:0)667 x a10 Output SRAM (x2) Row Driver Pixel Array Column Processing Circuitry (PGA, ADC)

1/2-INCH VGA (WITH FREEZE-FRAME) CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR 09005aef80c07280 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9V403_DS.fm - Rev. B 1/04 EN 11 ©2004 Micron Technology. Inc. Sequential Slave Mode In sequential slave mode the exposure period is fol- lowed by readout. The row and frame synchronization waveforms are shown in Figures 15 and 16, respec- tively. Figure 15: Sequential Slave Mode Row Timing Diagram Example Figure 16: Sequential Slave Mode Frame Synchronization Waveforms Example SYSCLK (input) RESMEM (input) TX_N (input) FRAME_SYNC_N (input) ROW_STRT (input) LD_SHFT_N (input) DATA [9:0] (output) Minimum 338 SYSCLK >10 SYSCLK 671 XXX XXX >10 SYSCLK 1 2 3666 4 667 1 2 PG_N (input) RESMEM (input) TX_N (input) FRAME_SYNC_N (input) ROW_STRT (input) LD_SHFT_N (input) DATA [9:0] (output) Exposure Time Exposure Time Minimum Duration

338 SYSCLK

1/2-INCH VGA (WITH FREEZE-FRAME) CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR 09005aef80c07280 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9V403_DS.fm - Rev. B 1/04 EN 13 ©2004 Micron Technology. Inc. Serial Bus Description Registers are written to and read from the MT9V403 through the two-wire serial interface bus. The MT9V403 is a two-wire se rial interface slave with device ID "1011100x" and is controlled by the two-wire serial interface clock (SCLK), which is driven by the two-wire serial interface master. Data is transferred into and out through the two-wire serial interface data (SDATA) line. The SDATA line is pulled up to 3.3V off- chip by a 1.5K Ω resistor. Either the slave or master device can pull the SDATA line down—the two-wire serial interface protocol determines which device is allowed to pull the SDATA line down at any given time. Protocol The two-wire serial host interface bus defines sev- eral different transmission codes, as follows: a s t a r t b i t  the slave device eight-bit address  a(n) (no) acknowledge bit a n e i g h t - b i t m e s s a g e a s t o p b i t Sequence A typical read or write sequence begins by the mas- ter sending a start bit. After the start bit, the master sends the slave device's eight-bit address. The last bit of the address determines if the request will be a read or a write, where a “0” indicates a write (i.e., address B8h) and a “1” indicates a read (i.e., address B9h). The slave device acknowledges its address by sending an acknowledge bit back to the master. If the request was a write, the master then transfers the eight-bit register address to which a write should take place. The slave sends an acknowledge bit to indi- cate that the register address has been received. The master then transfers the data eight bits at a time, with the slave sending an acknowledge bit after each eight- bits. The MT9V403 uses a 16-bit data for its internal registers, thus requiring two eight-bit transfers to write to one register. To write/read this 16-bit data, first per- form a write/read the eight MSBs, then perform another write/read for eight LSBs. After 16 bits are transferred, the register address should be incre- mented, so that the next 16 bits are written to the next register address. The master stops writing by sending a start or stop bit. A typical read sequence is executed as follows. First the master sends the write-mode slave address and eight-bit register address, just as in the write request. The master then sends a start bit and the read-mode slave address. The master then clocks out the register data eight bits at a time. The master sends an acknowl- edge bit after each eight-bit transfer. The register address should be incremented after every 16 bits is transferred. The data transfer is stopped when the master sends a no-acknowledge bit. Bus Idle State The bus is idle when both the data and clock lines are HIGH. Control of the bus is initiated with a start bit, and the bus is released with a stop bit. Only the master can generate the start and stop bits. Start Bit The start bit is defined as a HIGH-to-LOW transition of the data line while the clock line is HIGH. Stop Bit The stop bit is defined as a LOW-to-HIGH transition of the data line while the clock line is HIGH. Slave Address The eight-bit address of a two-wire serial interface device consists of seven bits of address and one bit of direction. A “0” in the LSB of the address indicates write mode, and a “1” indicates read mode. Data Bit Transfer One data bit is transferred during each clock pulse. The two-wire serial interface clock pulse is provided by the master. The data must be stable during the HIGH period of the two-wire serial interface clock—it can only change when the two-wire serial interface clock is LOW . Data is transferred eight bits at a time, followed by an acknowledge bit. Acknowledge Bit The master generates the acknowledge clock pulse. The transmitter (which is the master when writing, or the slave when reading) releases the data line, and the receiver indicates an acknowledge bit by pulling the data line LOW during the acknowledge clock pulse. No-Acknowledge Bit The no-acknowledge bit is generated when the data line is not pulled down by the receiver during the acknowledge clock pulse. A no-acknowledge bit is used to terminate a read sequence.

1/2-INCH VGA (WITH FREEZE-FRAME) CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR 09005aef80c07280 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9V403_DS.fm - Rev. B 1/04 EN 15 ©2004 Micron Technology. Inc. Registers Table 4: Complete Register Description READ/ WRITE CONTROL REGISTER NAME FUNCTION DEFAULT CONTENTS REGISTER ADDRESS Read only Reg0 Chip Version. 0000001100000001 00000000 W/R Reg1 Row start address. *****000000001 00000001 W/R Reg2 Column start address. **0000001001 00000010 W/R Reg3 Stop row address. ***111100000 00000011 W/R Reg4 Stop column address. **1010001000 00000100 W/R Reg5 Number of blank columns (horizontal blanking). ****10101001 00000101 W/R Reg6 Number of blank rows (vertical blanking). ****00100011 00000110 W/R Reg7 Control mode. Bit 0 = 1 simultaneous mode. Bit 0 = 0 sequential mode. Bit 1 = 1 snapshot mode. Bit 2 = 1 master mode. Bits 3–7 not used; set to 0. Possible combinations are”00000101,” “00000100,” The last combination means slave mode. W/R Reg8 Number of frame times in integration time. ****00000000 00001000 W/R Reg9 Number of rows times in integration time. Maximum = 502. Minimum = 2. W/R Reg10 Interlaced mode control. Bit 0 = 1 interlaced mode 1. Readout of both fields even and odd. Bit 1 = 1 interlaced mode 1 = 2. Readout of only one field – even or odd. Depends on start row. Bits 2–7 not used; set to 0 W/R Reg12 Calibration control. Bit 0 = 1 calibration at the beginning of every frame. W/R Reg13 Dark offset enable and pixel memory reset pulse duration control. Bit 0 = 1 long reset pulse. Bit 1 = 1 dark offset of ADC input signal using VOFF is enabled. Bits 2–7 not used; set to 0. W/R Reg14 Clear signal control. Bit 0 = 1 reset row and column counters in digital block. Sensor is in idle mode. The two-wire serial interface works and it is still possible to WRITE/READ in registers. Changes of registers content follows without delay. Normally, change of register content occurs only at the beginning of next frame in cases where the two-wire serial interface data is not busy. Write only Reg15 ADC calibration data input register. *******0000000 00001111 W/R Reg16 VLN_AMP bias control. Bit 7 = 1 disable internal bias. Bit 0 = 1 high bias. Bit 1 = 1 low bias. Bits 3–6, 8–15 not used, set to 0. 0000000000000000 00010000

1/2-INCH VGA (WITH FREEZE-FRAME) CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR 09005aef80c07280 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9V403_DS.fm - Rev. B 1/04 EN 16 ©2004 Micron Technology. Inc. W/R Reg17 VLN2 bias control. Bit 7 = 1 disable internal bias. Bit 0 = 1 high bias. Bit 1 = 1 low bias. Bits 3–15 not used, set to 0. 0000000000000000 00010001 W/R Reg18 VLN_OUT bias control. Bit 7 = 1disable internal bias. Bit 0 = 1 high bias. Bit 1 = 1 low bias. Bits 3–6, 8–15 not used, set to 0. 0000000000000000 00010010 W/R Reg19 VLN1 bias control. Bit 7 = disable internal bias. Bit 0 = 1 high bias. Bit 1 = 1 low bias. Bits 3–6, 8–15 not used, set to 0. 0000000000000000 00010011 W/R Reg20 VLP bias control. Bit 7 = 1 disable internal control. Bit 0 = 1 high bias. Bit 1 = 1 low bias. Bits 3–6, 8–15 not used, set to 0. 0000000000000000 00010100 W/R Reg21 V REF bias control. Bit 0-3 = bias value. Bit 7 = 1 disable internal bias. Bits 4–6, 8–15 not used, set to 0. 0000000000001010 00010101 W/R Reg22 VREF2 bias control. Bit 0-3 bias value. Bit 7= 1 disable internal bias. Bits 4–6, 8–15 not used, set to 0. 0000000000001010 00010110 W/R Reg23 VOFF bias control. Bit 0-3 bias value. Bit 6 = 1 sign of offset is negative. Bit 7 = 1 disable internal bias. Bits 4–5, 8–15 not used, set to 0. 0000000000000000 00010111 W/R Reg29 VLN2 bias booster. Bit 3 = 1 high bias. 0000000000000000 00011101 W/R Reg43 Blue gain settings. Default gain is 2. Gain settings range is from 1 (00000001) to 18 (00010010). W/R Reg44 Green 1 gain settings. Default gain is 2. Gain settings range is from 1 (00000001) to 18 (00010010). W/R Reg45 Green 2 gain settings. Default gain is 2. Gain settings range is from 1 (00000001) to 18 (00010010). W/R Reg46 Red gain settings. Default gain is 2. Gain settings range is from 1 (00000001) to 18 (00010010). W/R Reg53 Global gain control. Bit 0 = 1 gain is multiplied by factor of 0.5 Table 4: Complete Regist er Description (continued) READ/ WRITE CONTROL REGISTER NAME FUNCTION DEFAULT CONTENTS REGISTER ADDRESS

1/2-INCH VGA (WITH FREEZE-FRAME) CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR 09005aef80c07280 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9V403_DS.fm - Rev. B 1/04 EN 19 ©2004 Micron Technology. Inc. In slave mode the user has more control of the sen- sor but the same basic rules apply; the row time is still always 671 clock cycles. Figure 25 provides a slave mode row timing example for windowing from column 100 to column 200. The row processing is initiated by raising ROW_STRT and requires 671 clock cycles to complete. The user can readout the desired window of columns by lowering LD_SHFT_N and the specified columns will appear on the output with a 3.5 SYSCLK delay. Even though the windowed columns can be readout at the beginning of a row, the user must still wait the required 671 clock cycles for the row process- ing to complete before initiating the processing of the next row with ROW_STRT. Figure 26 provides a slave mode frame timing example for windowing from row 300 to row 400 which—similar to the master mode— shows how changing the number of rows in a window will increase the frame rate. Figure 25: Row Timing for Slave Mode with Windowing Figure 26: Frame Timing for Slave Mode with Windowing SYSCLK (input) ROW_STRT (input) LD_SHFT_N (input) DATA [9:0] (output) 1 1

3.5 SYSCLK DELAY

FRAME_SYNC_N (input) ROW_STRT (input) LD_SHFT_N (input) DATA [9:0] (output) Start Row Stop Row Row 301 Row 395 Row 396 Row 397 Row 399 Row 398 Row 400 Row 300 Row 301 Row 302 Row 303 Row 395 Row 400 Row 300 Row 302 Row 303 Row 396 Row 397 Row 398 Row 399

1/2-INCH VGA (WITH FREEZE-FRAME) CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR 09005aef80c07280 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9V403_DS.fm - Rev. B 1/04 EN 20 ©2004 Micron Technology. Inc. Electronic Shutter Exposure Control For the master and snapshot mode the electronic shutter's exposure duration (integration time) is pro- grammed via the two-wire serial interface. The MT9V403 shutter can be operated to generate continu- ous video output (simultaneous master mode or sequential master mode) or capture single images (snapshot mode). The minimum integration time in master or snap- shot mode is 2 row times. With a 66 MHz SYSCLK the minimum integration time is 20µs (10µs row time ±2 rows). The maximum integratio n time is either is 256 frame times (1.3 sec @ 200 fps) or the inverse of the frame rate. When in simultaneous master mode, the maximum integration time is limited by the inverse of the frame rate because one cannot integrate longer than a frame time. With a 66 MHz clock and full resolution (502 rows) the maximum integration time is 5ms (= 1/200 fps). In sequential master mode or snapshot mode the maximum integratio n time is limited to 256 frame times. T able 5 shows some examples of how the maximum integration time changes with resolution and clock speed. Table 5: Maximum Integration Time vs. Resolution and Clock Speed Sequential mode or snapshot mode Readout Scanning The MT9V403 can operate in either progressive scan or interlaced scan modes. Progressive scan is the default mode. In the interlace scan mode there are two readout options. The frame synchronization wave- forms for interlaced scanning are shown in Figure 27, which shows alternating readout of the even-num- bered and odd-numbered rows in consecutive frames. There is also an option that allows sequential readout of only the odd or even rows of a frame (effectively a X2 vertical subsampling of the image). Figure 27: Frame Synchronization Waveforms for Interlaced Scanning RESOLUTION (# OF ROWS) CLOCK SPEED (SYSCLK) FRAME TIME {= N x 671 x 1/FSYSCLK} MAXIMUM INTEGRATION TIME 502 (full resolution) 66 MHz 5.1ms 1.3 sec 251 66 MHz 2.6ms 0.7 sec 125 66 MHz 1.3ms 0.3 sec 63 66 MHz 0.6ms 0.2 sec 502 (full resolution) 24 MHz 14ms 3.6 sec 251 24 MHz 7ms 1.8 sec 125 24 MHz 5.1ms 0.9 sec 63 24 MHz 1.8ms 0.4 sec 502 (full resolution) 10 MHz 33ms 8 sec Row 2 Row 4 Row 494 Row 493 Row 1 FRAME_VALID ROW_VALID Odd Field Marker

1/2-INCH VGA (WITH FREEZE-FRAME) CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR 09005aef80c07280 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9V403_DS.fm - Rev. B 1/04 EN 21 ©2004 Micron Technology. Inc. Gain Settings There are four independent gain controls which are programmed via the two-wire serial interface. The four gains correspond to four cells of the Bayer pattern color filter array: red, green1, blue, and green2. The gain step size can be set to 1 or 0.5. When the step size is 1 the gain can programmed in 18 steps from X1 to X18. When the step size is 0.5, the gain can be pro- grammed 18 steps from X1 to X9. Global gain control is achieved by changing the four gains equally and simultaneously. To obtain the desired analog signal chain gain, set the following registers as shown in Table 6. Analog Biases VLN1, VLP , VOFF , V REF, V REF1, VLN2 V REF2, VLN_AMP , and VLN_OUT are generated on-chip and can be adjusted via a two-wi re serial interface. Also, the user may disable internal bias via a two-wire serial interface and apply external voltages to the sensor. V REF1DRV is generated on-chip but its internal bias cannot be disabled. VRST_PIX and VRSTLOW are not generated internally and external voltages must be applied. Considerations when Setting Analog Voltages The starting point for setting the analog voltages should be the values suggested in the typical values columns of the Tables 7 and 8. Additionally, Figure 21 on page 17, the “Signal Path Diagram,” indicates how the analog voltages affect the image. Other consider- ations follow: VRSTLOW: Functions as a pixel anti-blooming con- trol. For high illumination conditions (typically used in conjunction with a short integration time) black/white spots may appear. To eliminate these artifacts, this voltage should be set to ~ 0.4V . Once set, this value should not have to be ch anged for different imaging conditions. VLN2: Internal default value should be used as the starting point. VLN2 controls the current in the ADC comparators and there is a safe range where this volt- age has no effect; settings below this range will cause the comparators to fail. For high-speed operation, V L N 2 m a y n e e d t o b e i n c r e a s e d t o r e m o v e r a n d o m white spots. VLN2 may be further increased with regis- ter 17 by setting bit 0 to “1.” If this does not completely solve the problem, set bit 7 in register 18 to disable VLN_OUT . VRST_PIX: Should be set to 2.5V . V REF2: Internal default value is recommended. VLN1: Internal default value is recommended. VOFF: Internal default value is recommended. V REF1: Internal default value is recommended. VLP: Internal default value is recommended. VLN_OUT: Internal default value is recommended. VLN_AMP: Internal default value is recommended. V REF: Internal default value is recommended. ADC Calibration The MT9V403 contains a special self-calibrating cir- cuitry that enables it to reduce its own column-wise fixed-pattern noise. This calibration process consists of connecting a calibration signal to each of the 167 ADC inputs and estimating and storing these 167 off- sets (as 7 bits) to subtract from subsequent samples. Self-calibration automatically occurs after global logic reset (LRST_N) or the two-wire serial interface (register 12), and programs new offset values for each ADC into calibration memory. These values may be different from those calculated in the previous calibration if there has been a change in environment (e.g., temper- ature). The accuracy of ca libration is approximately 1mV rms.

1/2-INCH VGA (WITH FREEZE-FRAME) CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR 09005aef80c07280 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9V403_DS.fm - Rev. B 1/04 EN 22 ©2004 Micron Technology. Inc. Table 6: Pixel Gain Matrix ADC calibration takes 146 SYSCLK cycles. Nomi- nally, calibration should be initiated through the appli- cation of LRST_N, in which case the calibration takes place upon release of the LRST_N. Some applications may require initiating calibration by asynchronously writing a one- to two-wire serial interface to register 12, in which case the calibration is delayed until the beginning of the next frame. Calibration will continue to occur every frame until a zero is written to register 12. A timing diagram for the two-wire serial interface initiated calibration is shown in Figure 28. In master mode and snapshot mode, during two- wire serial interface initiated calibration, ROW_VALID goes HIGH for 146 SYSCLK immediately after FRAME_VALID goes HIGH to indicate that the calibra- tion process is occurring. The output of the sensor is interrupted during the calibration process to prevent output noise from corrupting the calibration. After the calibration process is complete, ROW_VALID goes REGISTERS 43-46 REGISTER 53 TOTAL GAIN 0000 0001 01 . 0 0000 0010 02 . 0 0000 0011 03 . 0 0000 0100 04 . 0 0000 0101 05 . 0 0000 0110 06 . 0 0000 0111 07 . 0000 1000 08 . 0 0000 1001 09 . 0 0000 1010 0 10.0 0000 1011 0 11.0 0000 1100 0 12.0 0000 1101 0 13.0 0000 1110 0 14.0 0000 1111 0 15.0 0001 0000 0 16.0 0001 0001 0 17.0 0001 0010 0 18.0 0000 0001 10 . 5 0000 0010 11 . 0 0000 0011 11 . 5 0000 0100 12 . 0 0000 0101 12 . 5 0000 0110 13 . 0 0000 0111 13 . 5 0000 1000 14 . 0 0000 1001 14 . 5 0000 1010 15 . 0 0000 1011 15 . 5 0000 1100 16 . 0 0000 1101 16 . 5 0000 1110 17 . 0 0000 1111 17 . 5 0001 0000 18 . 0 0001 0001 18 . 5 0001 0010 19 . 0

1/2-INCH VGA (WITH FREEZE-FRAME) CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR 09005aef80c07280 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9V403_DS.fm - Rev. B 1/04 EN 23 ©2004 Micron Technology. Inc. LOW and the normal data readout process com- mences when it returns HIGH. For two-wire serial interface initiated calibration in slave mode, the first ROW_STRT pulse of the calibration frame initiates the 146 SYSCLK calibration process. It is suggested that the user hold LD_SHFT_N HIGH during this calibration process to minimize calibration noise. When the cali- bration is complete, LD_SHFT_N may be lowered to commence the normal frame readout process. Figure 28: Two-Wire Serial Interface Initiated Calibration The calibration coefficients can be read from the MT9V403 and written to it, making it possible to fur- ther reduce column-wise fixed pattern noise by exter- nally calculating and writing the proper offset values to the MT9V403. For example, the user may choose to calculate the more precise offset values by averaging several frames and uploading the coefficients to the MT9V403. The user may also calculate coefficients for several temperature values and upload the appropri- ate values based on the environment. A special write-only two-wire serial interface regis- ter (register 15) is dedicated to the calibration data input. Calibration data can be continuously written to this register with an eight-bit write. To write to the cali- bration register, the typical two-wire serial interface write sequence is adhered to, including address (regis- ter 15), followed by 167 eight-bit transfers (note that each coefficient utilizes the 7 LSBs of the eight-bit two- wire serial interface word). This writing process must be continuous (ADC 1 to ADC 167) and coefficients cannot be selectively written. In a similar manner, a special read-only two-wire serial interface register (register 143) is dedicated to calibration data output. Calibration data can be con- tinuously read from this register with an 8-bit read. To read from the calibration register, the typical two-wire serial interface write sequence is adhered to, including address (register 143), followed by 167 8-bit transfers (note that each coefficient utilizes the 7 LSBs of the eight-bits two-wire serial interface word). This reading process must be continuous (ADC 1 to ADC 167) and coefficients cannot be selectively read. Anti-Eclipse Circuit The MT9V403 includes a pixel memory reset pulse duration control. This control enables a mode where the reset of the pixel is held for a longer period of time. This can be implemented by setting bit 0 to 7 in regis- ter 13. In some extremely br ight lighting conditions, this extended reset may prevent the eclipse-like phe- nomena (black spots on a bright background) to which some CMOS sensors are prone.

146 SYSCLKGLOBAL LOGIC RESET

FRAME_VALID ROW_VALID DATA [9:0] XXX First Valid Row

1/2-INCH VGA (WITH FREEZE-FRAME) CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR 09005aef80c07280 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9V403_DS.fm - Rev. B 1/04 EN 24 ©2004 Micron Technology. Inc. Figure 29: Board Connections NOTE: 1. VLN1, VLP, VOFF , VREF, VREF1, VLN2, and VREF2 are generated on-chip, but user may disable internal bias (via two- wire serial interface) and apply external voltages to sensor. VREF1DRV is generated on chip but its internal bias can- not be disabled. VRST_PIX and VRSTLOW are not generated internally and external voltages must be applied. 2. All bias pins should be decoupled with 0.1µF ceramic and 10µF electrolytic capacitors. (Please see board connections.) Capacitors should be placed as physically close as possible to the MT9V403 package. 3. Digital outputs can drive standard CMOS circuits with 30pF load, but less load capacitance results in less substrate noise on-chip. This is recommended to minimize load capacitance for better noise performance. VAA VAA V DD VDD VDD VDD DATA0 3 DATA1 2 DATA2 1 DATA3 48 DATA4 47 DATA5 46 DATA6 42 DATA7 45 DATA8 40 DATA9 41 Pixel Data Output

8 VREF1DRV

17 VLN1

19 VLP

9 VREF1

7 VREF2

14 VTEST1

Analog +3.3V Digital +3.3V 1.5kΩ 1kΩ 0.1µF 10µF 0.1µF 10µF Analog +3.3V 0.1µF 10µF Analog +3.3V 1kΩ 1kΩ 0.1µF 10µF Analog +3.3V 1kΩ 0.1µF 10µF Analog +3.3V 1kΩ 0.1µF 10µF Analog +3.3V 1kΩ 0.1µF 10µF Analog +3.3V 1kΩ 0.1µF 10µF Analog +3.3V 1kΩ 0.1µF 10µF Analog +3.3V 1kΩ 0.1µF 10µF Analog +3.3V 1kΩ 0.1µF 10µF

4 DGND

5 DGND

28 DGND

34 DGND

35 DGND

44 DGND

10 AGND

11 AGND

15 AGND

Analog GroundDigital Ground Controller Interface

39 SDATA

32 FRAME_SYNC_N

37 SYSCLK

29 EXPOSE

31 ROW_VALID/LD_SHFT_N

38 SCLK

30 FRAME_VALID/ROW_STRT

33 LRST_N

26 PG_N

24 RESMEM

VRST_PIX 20 VREF 16 VOFF 13 Analog +3.3V Digital +3.3V Digital Ground Analog Ground

1/2-INCH VGA (WITH FREEZE-FRAME) CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR 09005aef80c07280 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9V403_DS.fm - Rev. B 1/04 EN 25 ©2004 Micron Technology. Inc. Figure 30: Propagation Delays for Data Output, Frame Valid, and Row Valid Signals SYSCLK DOUT(9:0) TplhD, TphlD tr SYSCLK FRAME_VALID TplhF tr SYSCLK ROW_VALID TplhL tr SYSCLK FRAME_VALID TphlF tr SYSCLK ROW_VALID TphlL tr

1/2-INCH VGA (WITH FREEZE-FRAME) CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR 09005aef80c07280 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9V403_DS.fm - Rev. B 1/04 EN 26 ©2004 Micron Technology. Inc. Electrical Specifications Table 7: AC Electrical Characteristics VPWR = 3.3 ±0.3V; TA = 25°C Table 8: DC Electrical Characteristics VPWR = 3.3 ±0.3V; TA = 25°C NOTE: 1. Where indicated, internally generated biases are typically utilized. The parenthetical number indicates typical value if external voltage is applied. 2. This device contains circuitry to protect the inputs against damage from high static voltages or electric fields, but the user is advised to take precautions to avoid the application of any voltage higher than the maximum rated. SYMBOL DEFINITION CONDITION MIN TYP MAX UNIT tPLHD Data output propagation delay for LOW-to-HIGH transition CLOAD = 10pF 2 ns tPHLD Data output propagation delay for HIGH-to-LOW transition CLOAD = 10pF 2 ns tPLHL ROW_VALID propagation delay for LOW-to-HIGH transition CLOAD = 10pF 2 ns tPHLL ROW_VALID propagation delay for HIGH-to-LOW transition CLOAD = 10pF 2 ns tPLHLF FRAME_VALID propagation delay for LOW-to-HIGH transition CLOAD = 10pF 2 ns tPHLF FRAME_VALID propagation delay for HIGH-to-LOW transition CLOAD = 10pF 2 ns SYMBOL DEFINITION CONDITION MIN TYP1 MAX UNIT VLN_AMP Internal/External 0.5 Internal (0.7) 1.5 V VLN2 Internal/External 0.5 Internal (1.1) 1.5 V VLN_OUT Internal/External 0.5 Internal (0.8) 1.5 V VLN1 Internal/External 0.5 Internal (0.7) 1.5 V VLP Internal/External 1.5 Internal (1.9) 2.5 V VREF Internal/External 1 Internal (1.6) 2 V VREF2 Internal/External 0 Internal (1) 2 V VREF1 Internal/External 0 Internal (1) 2 V VOFF Internal/External 0 Internal (0) 3 V VRST_PIX External Only 1 2.5 3.3 V VRSTLOW External Only 0 0 - 0.4 1 V VTEST External Only - 0 - VREF1DRV Internal Only - open - V VIH Input High Voltage 2.5 V PWR + 0.3 V VIL Input Low Voltage -0.3 0.8 V IIN Input Leakage Current No Pull-up Resistor; VIN - VPWR or VGND -300 +300 uA VOH Output High Voltage V PWR - 0.2 V VIH Output Low Voltage 100 220 mV IOH Output High Current 0.2 mA IPWR Supply Current CLK_IN = 42 MHz; default setting 20 mA

1/2-INCH VGA (WITH FREEZE-FRAME) CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR 09005aef80c07280 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9V403_DS.fm - Rev. B 1/04 EN 29 ©2004 Micron Technology. Inc. Electrical Specifications Table 9: Image Sensor Characteristics TA = 25°C Table 10: Pixel Array SYMBOL PARAMETER TYP UNIT RI Responsivity (ADC VREF1 = 1V) 1,800 LSB/lux-sec. DSNU Dark signal non-uniformity 0.5 %rms VDRK Output referred dark signal 100 mV/sec Dyn_I Internal dynamic range 60 dB PRNU Photo response non-uniformity 1 %rms NSAT Pixel saturation level 110,000 electrons NE Input referred noise: Overlapped conversion and digital readout (200 fps) 98 electrons KDRK Dark current temperature coefficient 100 %/8°C SYMBOL PARAMETER TYP UNIT Resolution Number of pi xels in active image 659 x 494 pixels Pixel Size X-Y dimensions 9.9 µm Pixel Pitch Center-to-c enter pixel spacing 9.9 µm Pixel Fill Factor Area of drawn active area 50 % Shutter Efficiency Equals: 1-(l eakage into in pixel memory) 98.5 %

1/2-INCH VGA (WITH FREEZE-FRAME) CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR 09005aef80c07280 Micron Technology, Inc., reserves the right to change products or specifications without notice.. MT9V403_DS.fm - Rev. B 1/04 EN 32 ©2004 Micron Technology, Inc 8000 S. Federal Way, P .O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992 Micron, the M logo, the Micron logo, and TrueSNAP are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. Figure 41: Package View – Bottom View Figure 42: Package Drawing - Side View NOTE: 1. Dimensions in millimeters. 2. Borosilicate: glass with refractive index: 1.52nm at 546nm. Data Sheet Designation No Marking: This data sheet contains minimum and maximum limits specified over the complete power supply and temperature range for production devices. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. 1.75 2.25

1.02 TYP

11.18 TYP

0.51 TYP

Pin No.1 index

1.52 TYP

0.746 1.178 0.246 0.578 0.710 0.740 0.50 0.60 1.01 1.27 0.38 0.56 1.91 2.46 1.11 1.34 Die MAX

1/2-INCH VGA (WITH FREEZE-FRAME) CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR 09005aef80c07280 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9V403_DS.fm - Rev. B 1/04 EN 33 ©2004 Micron Technology. Inc.

Revision History

 Removed Preliminary Status  Updated Figure 13 U p d a t e d IIN Input Leakage current specifications in the DC Characteristics Table  Added high-static note to DC Characteristics Table  Initial Release of document