MT9V135C12STC

MT9V135C12STC MICRON | Alldatasheet

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Technical content

Features

Preliminary‡ 09005aef82c99cd/Source:09005aef824c99db Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9V135_LDS_1.fm - Rev. B 3/07 EN 1 ©2006 Micron Technology, Inc. All rights reserved. 1/4-Inch System-On-A-Chip (SOC) VGA NTSC/PAL CMOS Digital Image Sensor MT9V135C12STC (Pb-Free CLCC)

• M i c r o n® DigitalClarity® CMOS imaging technology  System-On-a-Chip (SOC)—Completely integrated camera system  NTSC/PAL (true two field) analog composite video output  ITU-R BT.656 parallel output (8-bit, interlaced)  Simultaneous composite and digital video outputs (simplifies focus and setup of network cameras  Serial LVDS data output  Low power, interlaced scan CMOS image sensor  Supports use of external devices for addition of custom overlay graphics  Superior low-light performance  On-chip image flow processor (IFP) performs sophisticated processing  Color recovery and correction, sharpening, gamma, lens shading correction, and on-the-fly defect correction  Automatic features: – Auto exposure – Auto white balance (AWB) – Auto black reference (ABR) – Auto flicker avoidance – Auto color saturation – Auto defect identification and correction S i m p l e t w o - w i r e s e r i a l programming interface

Applications

 Security cameras  900 MHz and 2.4 GHz wireless cameras  Composite video and digital video cameras C C T V s e c u r i t y c a m e r a s S m a r t c a m e r a s  Evidence quality cameras  Cameras using active or passive overlay Note: 1. Customers requiring a similar part with greater temperature range should consider using the Micron MT9V125. Table 1: Key Performance Parameters Parameter Typical Value Optical format 1/4-inch (4:3) Active imager size 3.63mm(H) x 2.78mm(V) 4.57mm diagonal Active pixels 640H x 480V NTSC output 720H x 486V PAL output 720H x 576V Pixel size 5.6µm x 5.6µm Color filter array RGB Paired Bayer pattern Shutter type Electronic rolling shutter (ERS) Maximum data rate master clock

13.5 Mp/s

27 MHz

Frame rate (VGA 640H x 480V) 30 fps at 27 MHz (NTSC) 25 fps at 27 MHz (PAL) Integration time (composite video output) 16µs–33ms (NTSC) 16µs–40ms (PAL) ADC resolution 10-bit, on-chip Responsivity 5 V/lux-sec (550nm) Pixel dynamic range 70dB SNR MAX 39dB Supply voltage I/O digital 2.5–3.1V (2.8V nominal) Core digital 2.5–3.1V (2.8V nominal) Analog 2.5–3.1V (2.8V nominal) Power consumption 320 mW @ 2.8V, 25°C Operating temperature 1 –30°C to +70°C Packaging 48-pin CLCC Table 2: Ordering Information Part Number Description MT9V135C12STC ES 48-pin CLCC ES, Pb-Free MT9V135C12STCD Demo kit MT9V135C12STCH Demo kit headboard

PDF: 09005aef82c99cd/Source:09005aef824c99db Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9V135_LDS_2.fm - Rev. B 3/07 EN 2 ©2006 Micron Technology, Inc. All rights reserved. MT9V135: SOC VGA Digital Image Sensor General Description Preliminary General Description The MT9V135 is a VGA CMOS image sensor featuring Micron’ s breakthrough Digital- Clarity technology—a low-noise CMOS imaging technology that achieves CCD image quality (based on signal-to-noise ratio and low-light sensitivity) while maintaining the inherent size, cost, low power, and integration advantages of CMOS. The MT9V135 performs sophisticated processing functions including color recovery, color correction, sharpening, programmable gamma correction, auto black reference clamping, auto exposure, automatic 50Hz/60Hz flicker avoidance, lens shading correc- tion, auto white balance (AWB), and on-the-fly defect identification and correction. The MT9V135 outputs interlaced-scan images at 30 or 25 fps, supporting both NTSC and PAL video formats. The MT9V135 includes digital video output that can be switched to the NTSC/PAL encoder. This can be used in conjunction with an external DSP to provide an overlay (such as a logo or a menu screen) on top of the live video. The image data can be output on any one of three output ports:  Composite analog video (support for both single-ended and differential)  Low-voltage differential signalling (LVDS)  CCIR 656 interlaced digital video in parallel 8-bit format Figure 1: MT9V135 Quantum Efficiency vs. Wavelength Table 3: MT9V135 Detailed Performance Parameters Parameter Value Output Gain 28 e-/LSB Read Noise 5.3 e-RMS at 16X Dark Current 1600 e-/pix/s at 70°C 350 450 550 650 750 850 950 1050 Quantum Efficiency [%] Wavelength [nm]

PDF: 09005aef82c99cd/Source:09005aef824c99db Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9V135_LDS_2.fm - Rev. B 3/07 EN 6 ©2006 Micron Technology, Inc. All rights reserved. MT9V135: SOC VGA Digital Image Sensor Typical Connections Preliminary Figure 5: 48-pin CLCC Assignment Table 4: Pin Descriptions Pin Assignment Name Type Description 17 EXTCLK Input Master clock in sensor. 19 RESET_BAR Input Active LOW: asynchronous reset. 22 SADDR Input Two-wire serial interface device ID selection 1:0xBA, 0:0x90. 23 RSVD Input Must be attached to DGND. 21 SCLK Input Two-wire serial interface clock.

18 STANDBY Input Multifunctional signal to control device addressing, power-down,

and state functions (covering output enable function). 24 HORIZ_FLIP Input If “0” at reset: Default horizontal setting. If “1” at reset: Flips the image readout format in the horizontal direction. 25 NTSC_PAL_SELECT Input If “0” at reset: Default NTSC mode. If “1” at reset: Default PAL mode. 1 2 3 4 56 44 43 19 20 21 22 23 24 25 26 27 28 29 30 DIN[6] DIN[5] DIN[4] DIN[3] DIN[2] DIN[1] DIN[0] DIN_CLK DGND VDD CLK_IN STANDBY FV LV V DDPLL LVDS_POS LVDS_NEG DGND VDD DAC_POS VDDDAC DAC_NEG DGND DAC_REF RESET_BAR SDATA SCLK SADDR RSVD HORIZ_FLIP NTSC_PAL_SELECT LVDS_ENABLE PEDESTAL VAA AGND VAAPIX DIN[7] DOUT[7] DOUT[6] DOUT[5] DOUT[4] DOUT[3] DOUT[2] DOUT[1] DOUT[0] DOUT_LSB1 DOUT_LSB0 PIXCLK 48 47 46 45

PDF: 09005aef82c99cd/Source:09005aef824c99db Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9V135_LDS_2.fm - Rev. B 3/07 EN 7 ©2006 Micron Technology, Inc. All rights reserved. MT9V135: SOC VGA Digital Image Sensor Typical Connections Preliminary Notes: 1. ALL power pins (V DD/VDDDAC/VDDPLL/VAA/VAAPIX) must be connected to 2.8V (nominal). Power pins cannot be floated. 2. ALL ground pins (A GND/DGND) must be connected to ground. Ground pins cannot be floated. 3. Inputs are not tolerant to signal voltages above 3.1V. 4. All unused inputs must be tied to GND or V DD. 5. V AA and VAAPIX must be tied to the same potential for proper operation. 27 PEDESTAL Input If “0” at reset: Does not add pedestal to composite video output. If “1” at reset: Adds pedestal to composite video output. Valid for NTSC only, pull low for PAL operation. 26 LVDS_ENABLE Input Active HIGH: Enables the LVDS output port. Must be HIGH if LVDS is to be used. 6, 7, 8, 9, 10, 11, 12, 13 DIN[7:0] Input External data input port selectable at video encoder input. 14 DIN_CLK Input DIN capture clock. (This clock must be synchronous to CLK_IN.) 20 SDATA Output Two-wire serial interface data I/O. 5, 4, 3, 2, 1, 48, 47, 46 DOUT[7:0] Output Pixel data output DOUT7 (most significant bit (MSB)), DOUT0 (least significant bit (LSB)). Data output [9:2] in sensor stand-alone mode.

44 D OUT_LSB0 Output Sensor stand-alone mode output 0— typically left unconnected for

normal SOC operation.

45 DOUT_LSB1 Output Sensor stand-alone mode output 1— typically left unconnected for

normal SOC operation. 42 FRAME_VALID Output Active HIGH: FRAME_VALID; indicates active frame. 41 LINE_VALID Output Active HIGH: LINE_VALID, DATA_VALID; indicates active pixel. 43 PIXCLK Output Pixel clock output. 35 DAC_POS Output Positive video DAC output in differential mode. Video DAC output in single-ended mode. 33 DAC_NEG Output Negative video DAC output in differential mode. 31 DAC_REF Output External reference resistor for video DAC. 39 LVDS_POS Output LVDS positive output. 38 LVDS_NEG Output LVDS negative output. 29 AGND Supply Analog ground. 15, 32, 37 DGND Supply Digital ground. 28 VAA Supply Analog power: 2.5V–3.1V (2.8V nominal). 30 VAAPIX Supply Pixel array analog power supply: 2.5V–3.1V (2.8V nominal). 16, 36 VDD Supply Digital power: 2.5V-3.1V (2.8V nominal). 34 VDDDAC Supply DAC power: 2.5V-3.1V (2.8V nominal). 40 VDDPLL Supply LVDS PLL power: 2.5V-3.1V (2.8V nominal). Table 4: Pin Descriptions (continued) Pin Assignment Name Type Description

MT9V135: SOC VGA Digital Image Sensor Detailed Architecture Overview PDF: 09005aef82c99cd/Source:09005aef824c99db Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9V135_LDS_2.fm - Rev. B 3/07 EN 9 ©2006 Micron Technology, Inc. All rights reserved. Preliminary Figure 7: Image Capture Example The sensor core uses a paired RGB Bayer color pattern, as shown in Figure 9 on page 11. Row pairs consist of the following: rows 0, 1, rows 2, 3, rows 4, 5, and so on. The even- numbered row pairs (0/1, 4/5, and so on) in the active array contain green and red pixels. The odd-numbered row pairs (2/3, 6/7, and so on) contain blue and green pixels. The odd-numbered columns contain green and blue pixels; even-numbered columns contain red and green pixels. SCENE (Front view) OPTICS IMAGE CAPTURE IMAGE RENDERING Start Readout Row by Row IMAGE SENSOR (Rear view) Start Rasterization Process of I ma ge Gatherin g and Image Displa y DISPLAY (Front view)

PDF: 09005aef82c99cd/Source:09005aef824c99db Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9V135_LDS_2.fm - Rev. B 3/07 EN 11 ©2006 Micron Technology, Inc. All rights reserved. MT9V135: SOC VGA Digital Image Sensor Detailed Architecture Overview Preliminary Figure 9: Spatial Illustration of Image Readout VALID IMAGE ODD FIELD HORIZONTAL BLANKING VERTICAL EVEN BLANKING VERTICAL/HORIZONTAL BLANKING VALID IMAGE EVEN FIELD HORIZONTAL BLANKING VERTICAL ODD BLANKING VERTICAL/HORIZONTAL BLANKING

PDF: 09005aef82c99cd/Source:09005aef824c99db Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9V135_LDS_2.fm - Rev. B 3/07 EN 12 ©2006 Micron Technology, Inc. All rights reserved. MT9V135: SOC VGA Digital Image Sensor Detailed Architecture Overview Preliminary Image Flow Processor The MT9V135 IFP consists of a color processing pipeline, and a measurement and control logic block (the camera controller). The stream of raw data from the sensor enters the pipeline and undergoes several transformations. Image stream processing starts with conditioning the black level and applying a digital gain. The lens shading block compensates for signal loss caused by the lens. Next, the data is interpolated to recover missing color components for each pixel. The resulting interpolated RGB data passes through the current color correction matrix (CCM), gamma, and saturation corrections, and is formatted for final output. The measurement and control logic continuously accumulate image brightness and color statistics. Based on these measurements, the IFP calculates updated values for exposure time and sensor analog gains that are sent to the sensor core through the control bus. Black Level Conditioning The sensor core black level calibration works to maintain black pixel values at a constant level, independent of analog gain, reference current, voltage settings, and temperature conditions. If this black level is above zero, it must be reduced before color processing can begin. The black level subtraction block in the IFP re-maps the black level of the sensor to zero prior to lens shading correction. Following lens shading correction, the black level addition block provides capability for another black level adjustment. However, for good contrast, this level should be set to zero. Digital Gain Controlled by auto exposure logic, the input digital gain stage amplifies the raw image in low-light conditions. (Range: x1–x8). Test Pattern A built-in test pattern generator produces a test image stream that can be multiplexed with the gain stage. The test pattern can be selected through register settings. Lens Shading Correction Inexpensive lenses tend to attenuate image intensity near the edges of pixel arrays. Other factors also cause signal and coloration differences across the image. The net result of all these factors is known as lens shading. Lens shading correction (LC) compensates for these differences. Typically, the profile of lens shading induced anomalies across the frame is different for each color component. Lens shading correction is independently calibrated for the color channels. Interpolation and Aperture Correction A demosaic engine converts the single color per pixel Bayer data from the sensor into RGB (10-bit per color channel). The demosaic algorithm analyzes neighboring pixels to generate a best guess for the missing color components. Edge sharpness is preserved as much as possible. Aperture correction sharpens the image by an adjustable amount. Sharpening can be programmed to phase out as light levels drop to avoid amplifying noise.

PDF: 09005aef82c99cd/Source:09005aef824c99db Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9V135_LDS_2.fm - Rev. B 3/07 EN 13 ©2006 Micron Technology, Inc. All rights reserved. MT9V135: SOC VGA Digital Image Sensor Detailed Architecture Overview Preliminary Defect Correction This device supports 2D defect correction. In 2D defect detection/correction, pixels with values different from their neighbors by greater than a defined threshold are considered defects unless near the image boundary. The approach is termed 2D, as pixels on neigh- boring lines as well as neighboring pixels on the same line are considered in both detec- tion and correction. Color Correction To obtain good color rendition and saturation, it is necessary to compensate for the differences between the spectral characteristics of the imager color filter array and the spectral response of the human eye. This compensation, also known as color separation, is achieved through linear transformation of the image with a 3 x 3 element color correc- tion matrix. The optimal values for the color correction coefficients depend on the spectra of the incident illumination and can be programmed by the user. Color Saturation Control Both color saturation and sharpness enhancement can be set by the user, or adjusted automatically by tracking the magnitude of the gains used by the auto exposure algo- rithm. Automatic White Balance The MT9V135 has a built-in AWB algorithm designed to compensate for the effects of changing scene illumination on the quality of the color rendition. This sophisticated algorithm consists of two major submodules:  A measurement engine (ME) performing statistical analysis of the image.  A module selecting the optimal color corr ection matrix and analog color channel gains in the sensor core. While the default algorithm settings are adequate in most situations, the user can repro- gram base color correction matrices and limit color channel gains. The AWB does not attempt to locate the brightest or grayest elements in the image; it performs in-depth image analysis to differentiate between changes in predominant spectra of illumination and changes in predominant scene colors. Factory defaults are suitable for most appli- cations; however, a wide range of algorithm parameters can be overwritten by the user through the serial interface. Auto Exposure The auto exposure algorithm performs automatic adjustments to image brightness by controlling exposure time and analog gains in the sensor core, as well as digital gain applied to the image. The algorithm relies on the auto exposure measurement engine that tracks speed and amplitude changes in the overall luminance of selected windows in the image. Back light compensation is achieved by weighting the luminance in the center of the image higher than the luminance on the periphery. Other algorithm features include fast-fluctuating illumination rejection (time averaging), response-speed control, and controlled sensitivity to small changes. While the default settings are adequate in most situations, the user can program target brightness, measurement window, and other parameters as described above. The auto exposure algorithm enables compensation for a broad range of illumination intensities.

PDF: 09005aef82c99cd/Source:09005aef824c99db Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9V135_LDS_3.fm - Rev. B 3/07 EN 14 ©2006 Micron Technology, Inc. All rights reserved. MT9V135: SOC VGA Digital Image Sensor Electrical Specifications Preliminary Electrical Specifications Notes: 1. V DD, VAA, and VAAPIX must all be at the same potential to avoid excessive current draw. Care must be taken to avoid excessive noise injection in the analog supplies if all three sup- plies are tied together. 2. Customers requiring a similar part with great er temperature range should consider using the Micron MT9V125. Table 5: Electrical Characteristics and Operating Conditions TA = 25°C Parameter1 Condition Min Typ Max Unit I/O and core digital voltage (VDD) N/A 2.5 2.8 3.1 V LVDS PLL voltage N/A 2.5 2.8 3.1 V Video DAC voltage N/A 2.5 2.8 3.1 V Analog voltage (VAA) N/A 2.5 2.8 3.1 V Pixel supply voltage (VAAPIX) N/A 2.5 2.8 3.1 V Leakage current STANDBY, no clocks 10 µA Imager operating temperature2 N/A –30 +70 °C Storage temperature N/A –30 +125 °C Table 6: Video DAC Electrical Characteristics TA = 25°C; All table values are estimates until the block is tested and characterized Parameter Condition Min Typ Max Unit Resolution 10 bits DNL Single-ended mode 0.8 1.1 bits INL Single-ended mode 5.7 8.1 bits Output local oad Single-ended mode, output pad (DAC_POS) 75 Ohm Single-ended mode, unused output (DAC_NEG) 0 Ohm Output voltage Single-ended mode, code 000h 0.02 V Single-ended mode, code 3FFh 1.42 V Output current Single-ended mode, code 000h 0.6 mA Single-ended mode, code 3FFh 37.9 mA DNL Differential mode 0.7 1 bits INL Differential mode 1.4 3 bits Output local load Differential mode per pad (DAC_POS and DAC_NEG)

37.5 Ohm

Output voltage Differential mode, code 000h, pad dacp 0.37 V Differential mode, code 000h, pad dacn 1.07 V Differential mode, code 3FFh, pad dacp 1.07 V Differential mode, code 3FFH, pad dacn 0.37 V Output voltage Differential mode, code 000h, pad dacp 0.6 mA Differential mode, code 000h, pad dacn 37.9 mA Differential mode, code 3FFh, pad dacp 37.9 mA Differential mode, code 3FFH, pad dacn 0.6 mA Differential output mid level Differential mode 0.72 V Supply current Estimate 55 mA

PDF: 09005aef82c99cd/Source:09005aef824c99db Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9V135_LDS_3.fm - Rev. B 3/07 EN 15 ©2006 Micron Technology, Inc. All rights reserved. MT9V135: SOC VGA Digital Image Sensor Electrical Specifications Preliminary Power Consumption Notes: 1. 10pF nominal. 2. (NTSC or PAL) and LVDS should not be operated at the same time. Table 7: Digital I/O Parameters Signal Parameter Definition Condition Min Typ Max Unit All Outputs Load capacitance 1 30 pF Output signal slew 2. 8V, 30pF load 0.72 V/ns 2.8V, 5pF load 1.25 V/ns VOH Output high voltage 2.5 2.8 3.1 V VOL Output low voltage –0.3 0.3 V IOH Output high current V DD = 2.8V, VOH = 2.4V 16 26.5 mA IOL Output low current V DD = 2.8V, VOL = 0.4V 15.9 21.3 mA All Inputs VIH Input high voltage VDD = 2.8V 1.48 V VIL Input low voltage VDD = 2.8V 1.43 V IIN Input leakage current –2 2 µA Signal CAP Input signal capacitance 3.5 pF EXTCLK freq Master clock frequency Absolute minimum 2 MHz VGA at 30 fps 27 MHz Table 8: Power Consumption TA = Ambient = 25°C; All supplies at 2.8V Mode Sensor (mW) Image-Flow Proc (mW) I/Os (mW)1 DAC (mW) LVDS (mW) Total (mW) Active mode 2 60 100 10 150 80 400 Standby 0.56

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 prodmktg@micron.com www.micron.com Customer Comment Line: 800-932-4992 Micron, the M logo, the Micron logo, and DigitalClarity are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. Preliminary: This data sheet contains initial characterization limits that are subject to change upon full characterization of production devices. MT9V135: SOC VGA Digital Image Sensor Package Diagram PDF: 09005aef82c99cd/Source:09005aef824c99db Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9V135_LDS_3.fm - Rev. B 3/07 EN 16 ©2006 Micron Technology, Inc. All rights reserved. Preliminary Package Diagram Figure 10: 48-Pin CLCC Package Outline Drawing Notes: 1. Optical center = package center. 2. All dimensions are in millimeters. Seating plane 4.4 11.43 5.215 5.715 Lid material: borosilicate glass 0.55 thickness Wall material: alumina ceramic Substrate material: alumina ceramic 0.7 thickness 8.8 4.4 5.715 4.84 5.215 0.8 TYP 1.75

0.8 TYP

8.8 48 1 10.9 ±0.1 CTR 47X 1.0 ±0.2 48X R 0.15 48X 0.40 ±0.05 11.43 10.9 ±0.1 CTR Lead finish: Au plating, 0.50 microns minimum thickness over Ni plating, 1.27 microns minimum thickness 2.3 ±0.2 1.7 First clear pixel Optical center

1 C A

B Optical area Optical area: Maximum rotation of optical area relative to package edges: 1º Maximum tilt of optical area relative to seating plane A : 50 microns Maximum tilt of optical area relative to top of cover glass D : 100 microns A D 0.90 for reference only 1.400 ±0.125 0.35 for reference only V CTR Ø0.20 A B C H CTR Ø0.20 A B C Image sensor die: 0.675 thickness 0.10 A 0.05 0.2 4X

PDF: 09005aef82c99cd/Source:09005aef824c99db Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9V135_LDS_3.fm - Rev. B 3/07 EN 17 ©2006 Micron Technology, Inc. All rights reserved. MT9V135: SOC VGA Digital Image Sensor

Revision History

 Updated package drawing.