MT9V112

MT9V112 MICRON | Alldatasheet

Document overview

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Technical content

Features

• DigitalClarity ™ CMOS Imaging Technology  System-On-a-Chip (SOC)—Completely integrated camera system  Ultra-low power, low cost, progressive scan CMOS image sensor  Superior low-light performance  On-chip image flow processor (IFP) performs sophisticated processing: Color recovery and correction, sharpening, gamma, lens shading correction, and on-the-fly defect cor- rection  Filtered image downscaling to arbitrary size with smooth, continuous zoom and pan  Automatic Features: Auto exposure, auto white balance (AWB), auto black reference (ABR), auto flicker avoidance, auto color saturation, and auto defect identification and correction  Fully automatic Xenon and LED-type flash support, fast exposure adaptation  Multiple parameter contexts, easy/fast mode switching  Camera control sequencer automates: Snapshots, snapshots with flash, and video clips S i m p l e t w o - w i r e s e r i a l programming interface  ITU-R BT .656 (YCbCr), 565RGB, 555RGB, or 444RGB formats (progressive scan)  Raw and processed Bayer formats

Applications

 Cellular phones P D A s T o y s  Other battery-powered products Table 1: Key Performance Parameters PARAMETER TYPICAL VALUE Optical Format 1/6-inch (4:3) Active Imager Size 2.30mm(H) x 1.73mm(V) 2.88mm Diagonal Active Pixels 640H x 480V Pixel Size 3.6µm x 3.6µm Color Filter Array RGB Bayer Pattern Shutter Type Electronic Rolling Shutter (ERS) Maximum Data Rate/ Master Clock 12 MPS–13.5 MPS/

24 MHz–27 MHz

Frame Rate (VGA 640H x 480V) 30 fps at 27 MHz ADC Resolution 10-bit, on-chip Responsivity 1.0 V/lux-sec (550nm) Dynamic Range 71dB SNR MAX 44dB Supply Voltage I/O Digital 1.7V–3.6V Core Digital 1.7V–1.9V or 2.5V–3.1V (1.8V or 2.8V nominal) Analog 2.5V–3.1V (2.8V nominal) Power Consumption 76mW at 1.8V, 15fps Operating Temperature -30°C to +70°C Packaging 36-Ball ICSP, wafer or die

SOC VGA DIGITAL IMAGE SENSOR PRELIMINARY 09005aef8154a39d/09005aef8175e6cc Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9V112TOC.fm- Rev. A 1/05 EN 2 ©2004 Micron Technology, Inc. All rights reserved. Table of Contents

SOC VGA DIGITAL IMAGE SENSOR PRELIMINARY 09005aef8154a39d/09005aef8175e6cc Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9V112TOC.fm- Rev. A 1/05 EN 3 ©2004 Micron Technology, Inc. All rights reserved.

SOC VGA DIGITAL IMAGE SENSOR PRELIMINARY 09005aef8154a39d/09005aef8175e6cc Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9V112LOT.fm - Rev. A 1/05 EN 5 ©2004 Micron Technology, Inc. All rights reserved. List of Tables

SOC VGA DIGITAL IMAGE SENSOR PRELIMINARY 09005aef8154a39d/09005aef8175e6cc Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9V112_2.fm- Rev. A 1/05 EN 6 ©2004 Micron Technology, Inc. All rights reserved. General Description The Micron  Imaging MT9V112 is a VGA-format, single-chip camera CMOS ac tive-pixel digital image sensor. This device combines the MT9V012 image sen- sor core with fourth-generation digital image flow pro- cessor technology from Micron Imaging. It captures high-quality color images at VGA resolution. The VGA CMOS image sensor features DigitalClar- ity—Micron’ s breakthrough low-noise CMOS imaging technology that achieves CCD image quality (based on signal-to-noise ratio and lo w-light sensitivity) while maintaining the inherent size, cost, and integration advantages of CMOS. The sensor is a complete camera-on-a-chip solu- tion designed specifically to meet the low-power, low- cost demands of battery-powered products such as cellular phones, PDAs, and toys. It incorporates sophisticated camera functions on-chip and is pro- grammable through a simple two-wire serial interface. The MT9V112 performs sophisticated processing functions including color recovery, color correction, sharpening, programmable gamma correction, auto black reference clamping, auto exposure, automatic 50Hz/60Hz flicker avoidance, lens shading correction, auto white balance (AWB), and on-the-fly defect iden- tification and correction. Ad ditional features include day/night mode configurations; special camera effects such as sepia tone and solarization; and interpolation to arbitrary image size with continuous filtered zoom and pan. The device supports both Xenon and LED- type flash light sources in several snapshot modes. The MT9V112 can be programmed to output pro- gressive-scan images up to 30 frames per second (fps). The image data can be output in any one of six 8-bit formats:  ITU-R BT.656 (formerly CCIR656, progressive scan only) YCbCr  565RGB  555RGB  444RGB  Raw Bayer P r o c e s s e d B a y e r The FRAME_VALID and LINE_VALID signals are output on dedicated balls, along with a pixel clock that is synchronous with valid data. Functional Overview The MT9V112 is a fully-automatic, single-chip cam- era, requiring only a power supply, lens, and clock source for basic operation. O u t p u t v i d e o i s s t r e a m e d via a parallel 8-bit D OUT port, shown in Figure 1 on page 7. The output pixel clock is used to latch data, while FRAME_VALID and LINE_VALID signals indicate the active video. The MT9V 112 internal registers are configured using a two-wire serial interface. The device can be put in a low-power sleep mode by asserting STANDBY and shutting down the clock. Out- put signals can be tri-stated. Both tri-stating output signals and entry in standby mode also can be achieved via two-wire serial interface register writes. The MT9V112 accepts input clocks up to 27 MHz, delivering up to 30 fps for VGA resolution images. Internal Architecture Internally, the MT9V112 consists of a sensor core and an image flow processor (IFP). The IFP is divided in two sections: the colorpipe (CP), and the camera controller (CC). The sensor core captures raw Bayer- encoded images that are then input in the IFP . The CP section of the IFP processes the incoming stream to create interpolated, color-corrected output, and the CC section controls the sensor core to maintain the desired exposure and color balance, and to support snapshot modes. The sensor core, CP , and CC registers are grouped in three separate address spaces, shown in Figure 2. When accessing internal registers via the two-wire serial interface, select the desired address space by programming the R240 register. The MT9V112 accelerates mode-switching with hardware-assisted context switching, and supports taking snapshots, flash snapshots, and video clips using a configurable sequencer. The MT9V112 supports a range of color formats derived from four primary color representations: YCbCr, RGB, raw Bayer (unprocessed, directly from the sensor), and processed Bayer (Bayer format data regenerated from processed RGB). The device also supports a variety of output signaling/timing options:  Standard FRAME_VALID/LINE_VALID video interface with gated pixel clocks  ITU-R BT .656 marker-embedded video interface with either gated or uniform pixel clocking

SOC VGA DIGITAL IMAGE SENSOR PRELIMINARY 09005aef8154a39d/09005aef8175e6cc Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9V112_2.fm- Rev. A 1/05 EN 9 ©2004 Micron Technology, Inc. All rights reserved. Figure 4: 36-Ball ICSP Assignment A B C D E F Top View (Ball Down) DOUT3 DGND DOUT2 DOUT VDDQ PIXCLK DOUT5 DOUT4 DGND DGND STROBE SCLK VDD DOUT0 DOUT1 DOUT SADDR VDD DOUT7 DOUT6 DGND DGND STAND BY VDD LINE VDD VAA AGND VAAPIX CLKIN VDDQ FRAME TEST DGND SDATA _LSB0 _LSB1 RESET# _VALID _VALID _ENABLE Table 2: Ball Description BALL ASSIGNMENT NAME TYPE DESCRIPTION A5 CLKIN Input Master clock in sensor. E4 RESET# Input Active LOW: asynchronous reset. E1 S ADDR Input Two-Wire Serial Interface Device ID selection 1:0xBA, 0:0x90. D5 TEST_ENABLE Input Tie to DGND for normal operation. (Manufacturing use only.) F3 SCLK Input Two-Wire Serial Interface Clock. F4 STANDBY Input Multifunctional signal to control device addressing, power-down, and state functions (covering output enable function). F5 S DATA Output Two-Wire Serial Interface Data I/O. B1, C1, C2, A2, B3, A3, B4, A4 DOUT(7:0) Output Pixel Data Output bit 0, DOUT(7) (most significant bit (MSB)), DOUT(0) (least significant bit (LSB)). D1 D OUT_LSB0 Output Sensor bypass mode output 0—typically left unconnected for normal SOC operation. D2 D OUT_LSB1 Output Sensor bypass mode output 1—typically left unconnected for normal SOC operation. C5 FRAME_VALID Output Active HIGH: FRAME_VALID; indicates active frame. B6 LINE_VALID Output Active HIGH: LINE_VALID, DATA_VALID; indicates active pixel. F2 PIXCLK Output Pixel clock output. E3 STROBE Output Active HIGH: strobe (Xenon) or turn on (LED) flash. E6 A GND Supply Analog ground. B2, C3, C4, D3, D4, E5 DGND Supply Core digital ground.

SOC VGA DIGITAL IMAGE SENSOR PRELIMINARY 09005aef8154a39d/09005aef8175e6cc Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9V112_2.fm- Rev. A 1/05 EN 10 ©2004 Micron Technology, Inc. All rights reserved. NOTE: All inputs and outputs are implemented with bidirectional buffers. Care must be taken that all inputs are driven and all outputs are driven if tri-stated. D6 V AA Supply Analog power: 2.5V–3.1V (2.8V nominal). F6 VAAPIX Supply Pixel array analog power supply: 2.5V–3.1V (2.8V nominal). B5, E2 V DDQ Supply I/O digital power: 1.7V–3.6V. Table 2: Ball Description (continued) BALL ASSIGNMENT NAME TYPE DESCRIPTION

SOC VGA DIGITAL IMAGE SENSOR PRELIMINARY 09005aef8154a39d/09005aef8175e6cc Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9V112_2.fm- Rev. A 1/05 EN 11 ©2004 Micron Technology, Inc. All rights reserved. Architecture Overview The MT9V112 consists of a sensor core, the color processing pipeline, and a measurement and control logic block (the camera controller). Below is a brief overview of the architecture. Sensor Core The sensor core is taken from the MT9V012 stand- alone sensor and includes a number of features specif- ically targeting the mobile market. Of primary interest is support for preview/viewfinding with hardware- accelerated switching to full resolution for snapshots. This switch can be achieved without adversely affect- ing exposure or color balance. This enables taking sin- gle frame and Xenon flash snapshots while minimizing snapshot lag. LED snapshots are discussed below; they also benefit significantly from this feature. Lens Shading Correction and Black Level Conditioning The stream of raw data from the sensor enters the pipeline and undergoes several transformations. Image stream processing star ts with conditioning the black level and applying a digital gain. The lens shading block compensates for spatially varying signal loss caused by the lens. The block is pro- grammable and implements separate correction func- tions for R,G, and B independently. Defect Correction Following lens correction, the data stream is ana- lyzed for the presence of defects. A two-dimensional digital filter calculates suitable replacement values. Edge sensitivity minimizes false detections, helping to preserve image sharpness. Interpolation, Aperture, and Color Correction The Bayer pixel pattern data is interpolated to recover missing color components for each pixel fol- lowing defect correction. Configurable aperture cor- rection sharpens the image and to avoid amplifying noise, can be programmed to be less aggressive in low light conditions. The resulting interpolated RGB data passes through the current color correction matrix (CCM), gamma, and color saturation corrections. The CCM can be manually loaded or dynamically configured by the auto white balance (AWB) unit. The gamma correction unit is fully user-programmable, and color saturation adjustments can be made both by the user and the auto exposure unit (for dynamic satu- ration reduction in high or low lighting situations). Resize The IFP can resize to virtually any output resolution through digitally filtered sub-sampling. Output resolu- tions include, but are not limited to, VGA, QVGA, CIF , and QCIF . When the output resolution is smaller than the sensor-generated im age, smooth, continuous zoom and pan become available. The user simply defines the zoom window, pan offset, and output reso- lution, and the resizer calculates all other parameters for the resize function. Camera Control The camera controller continuously accumulates image brightness and color statistics. Two units use these measurements to adjust the sensor and color- pipe settings. The auto exposure unit adjusts gain and shutter-width to maintain a user-defined luma target. The image measurement region can be modified to permit, for example, back light compensation. The user can also control the speed and sensitivity of the algorithm from highly responsive (for LED flash and viewfinding) to somewhat dampened (for video). Finally, the unit can detect 50Hz or 60Hz rolling flicker bars (due to ambient illumination) and adjusts expo- sure appropriately to elimin ate this adverse effect on image quality. The AWB module adjusts gains and the CCM to compensate for the effects of changing scene illumina- tion on the quality of the color rendition. The user has control over the region of the scene to be analyzed as well as the responsivity of the algorithm to illuminant changes. Camera Interface and Test Patterns The MT9V112 outputs process video as a standard ITU-R BT .656 stream, an RGB stream, or as processed or unprocessed Bayer data. The ITU-R BT .656 stream contains YCbCr 4:2:2 data with optional embedded synchronization codes. This output is typically suit- able for subsequent display by standard (progressive scan) video equipment, or JPEG/MPEG compression. RGB functionality provides support for LCD devices. The MT9V112 can be configured to output 16-bit RGB (RGB565), 15-bit RGB (RGB555), and two types of 12-bit RGB (RGB444). The user can configure internal registers to swap odd and even bytes, chrominance channels, and luminance and chrominance compo- nents to ease interfacing to application processors.

SOC VGA DIGITAL IMAGE SENSOR PRELIMINARY 09005aef8154a39d/09005aef8175e6cc Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9V112_2.fm- Rev. A 1/05 EN 12 ©2004 Micron Technology, Inc. All rights reserved. To assist in integration an d system debug, a variety of test patterns are provided, from simple ramps to colorbars. Contexts, Snapshots, and Flash For a number of parameters, registers are provided for storing two “contexts”: context A and context B. These contexts enable the user to setup the camera for a number of different modes, then switch between modes with a single register WRITE to the global con- text control register (GCCR). A typical example is to use context A for viewfinder/preview settings and context B for snapshots. Functions supporting context switch- ing include:  The resizer (output resolutions for preview and snapshot)  Camera interface (e.g., RGB565 for LCD preview and YCbCr for snapshots) To facilitate taking snapshots and flash snapshots, the IFP includes a camera control sequencer that auto- mates the process of stepping through a number of p r e s e t c o n f i g u r a b l e p r o g r a m s . I n a d d i t i o n t o b a s i c snapshots, there are programs for both Xenon and LED assisted snapshots. A flash-triggering controller provides an appropriate timing strobe for synchroniz- ing the onset of flash illu mination with the rolling shutter.

SOC VGA DIGITAL IMAGE SENSOR PRELIMINARY 09005aef8154a39d/09005aef8175e6cc Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9V112_2.fm- Rev. A 1/05 EN 13 ©2004 Micron Technology, Inc. All rights reserved. Output Data Ordering Table 3: Data Ordering in YCbCr Mode MODE BYTE Default Cbi Yi Cri Yi+1 Swap CrCb Cri Yi Cbi Yi+1 SwapYC Yi Cbi Yi+1 Cri Swap CrCb, SwapYC Yi Cri Yi+1 Cbi Table 4: Output Data Ordering in Processed Bayer Mode MODE LINE BYTE Default First Gi Ri+1 Gi+2 Ri+3 Second Bi Gi+1 Bi+2 Gi+3 Flip Bayer Col First Ri Gi+1 Ri+2 Gi+3 Second Gi Bi+1 Gi+2 Bi+3 Flip Bayer Row First Bi Gi+1 Bi+2 Gi+3 Second Gi Ri+1 Gi+2 Ri+3 Flip Bayer Col, Flip Bayer Row First Gi Bi+1 Gi+2 Bi+3 Second Ri Gi+1 Ri+2 Gi+3 Table 5: Output Data Ordering in RGB Mode MODE (SWAP DISABLED) BYTE D7 D6 D5 D4 D3 D2 D1 D0 RGB565 First R7 R6 R5 R4 R3 G7 G6 G5 Second G4 G3 G2 B7 B6 B5 B4 B3 R G B 5 5 5 F i r s t 0R 7R 6R 5R 4R 3G 7G 6 Second G5 G4 G3 B7 B6 B5 B4 B3 RGB444x First R7 R6 R5 R4 G7 G6 G5 G4 Second B7 B6 B5 B4 0 0 0 0 RGBx444 First 0 0 0 0 R7 R6 R5 R4 Second G7 G6 G5 G4 B7 B6 B5 B4 Table 6: Output Data Ordering in (8 + 2) Bypass Mode MODE BYTE D7 D6 D5 D4 D3 D2 D1 D0 8 + 2 b y p a s s F i r s t B 9B 8B 7B 6B 5B 4B 3B 2 S e c o n d 000000 B 1 B 0

SOC VGA DIGITAL IMAGE SENSOR PRELIMINARY 09005aef8154a39d/09005aef8175e6cc Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9V112_2.fm- Rev. A 1/05 EN 14 ©2004 Micron Technology, Inc. All rights reserved. Image Flow Processor Registers Table 7: Colorpipe Registers – Address Page 1 REGISTER #DEC (HEX) REGISTER NAME DATA FORMAT DEFAULT VALUE DEC (HEX) MODULE 5 (05) Aperture Correction 0000 0000 0000 dddd 3 (0003) Interp 6 (06) Operating Mode Control dddd dddd 0ddd dddd 28686 (700E) Cfg 8 (08) Output Format Control 00 00 0ddd dddd dddd 128 (0080) Cfg 37 (25) Color Saturation Control 0000 0000 00dd dddd 5 (0005) rgb2yuv 52 (34) Luma Offset dddd dddd dddd dddd 16 (0010) Camlnt 53 (35) Luma Clip dddd dddd dddd dddd 61456 (F010) Camlnt 58 (3A) Output Format Control 2A 0ddd dddd dddd dddd 512 (0200) CamInt 59 (3B) Lens Correction Parameter 1 — 1066 (042A) LensCorr 60 (3C) Lens Correction Parameter 2 — 1024 (0400) LensCorr 71 (47) Reserved — 24 (0018) — 72 (48) Test Pattern Generator Control 0000 0000 d000 0ddd 0 (0000) FifoInt 83 (53) Gamma Correction Parameter 1 — 7700 (1E14) GmaCorr 84 (54) Gamma Correction Parameter 2 — 17966 (462E) GmaCorr 85 (55) Gamma Correction Parameter 3 — 34666 (876A) GmaCorr 86 (56) Gamma Correction Parameter 4 — 47008 (B7A0) GmaCorr 87 (57) Gamma Correction Parameter 5 — 57548 (E0CC) GmaCorr 88 (58) Gamma Correction Parameter 6 — 0 (0000) GmaCorr 104 (68) Reserved — 17 (0011) — 128 (80) Lens Correction Parameter 3 — 3 (0003) LensCorr 129 (81) Lens Correction Parameter 4 — 0 (0000) LensCorr 130 (82) Lens Correction Parameter 5 — 0 (0000) LensCorr 131 (83) Lens Correction Parameter 6 — 0 (0000) LensCorr 132 (84) Lens Correction Parameter 7 — 0 (0000) LensCorr 133 (85) Lens Correction Parameter 8 — 0 (0000) LensCorr 134 (86) Lens Correction Parameter 9 — 0 (0000) LensCorr 135 (87) Lens Correction Parameter 10 — 0 (0000) LensCorr 136 (88) Lens Correction Parameter 11 — 0 (0000) LensCorr 137 (89) Lens Correction Parameter 12 — 0 (0000) LensCorr 138 (8A) Lens Correction Parameter 13 — 0 (0000) LensCorr 139 (8B) Lens Correction Parameter 14 — 0 (0000) LensCorr 140 (8C) Lens Correction Parameter 15 — 0 (0000) LensCorr 141 (8D) Lens Correction Parameter 16 — 0 (0000) LensCorr

SOC VGA DIGITAL IMAGE SENSOR PRELIMINARY 09005aef8154a39d/09005aef8175e6cc Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9V112_2.fm- Rev. A 1/05 EN 15 ©2004 Micron Technology, Inc. All rights reserved. 142 (8E) Lens Correction Parameter 17 — 0 (0000) LensCorr 143 (8F) Lens Correction Parameter 18 — 0 (0000) LensCorr 144 (90) Lens Correction Parameter 19 — 0 (0000) LensCorr 145 (91) Lens Correction Parameter 20 — 0 (0000) LensCorr 146 (92) Lens Correction Parameter 21 — 0 (0000) LensCorr 147 (93) Lens Correction Parameter 22 — 0 (0000) LensCorr 148 (94) Lens Correction Parameter 23 — 0 (0000) LensCorr 149 (95) Lens Correction Parameter 24 — 0 (0000) LensCorr 155 (9B) Output Format Control 2—Context B 0 ddd dddd dddd dddd 512 (0200) CamInt 157 (9D) Reserved — 9390 (24AE) — 159 (9F) Reserved—obsolete — 0 (0000) – 160 (A0) Reserved—obsolete — 640 (0280) – 161 (A1) Reducer Horizontal Si ze Resize—Context B 0000 0ddd dddd dddd 480 (01E0) Interp 162 (A2) Reserved—obsolete — 0 (0000) – 163 (A3) Reserved—obsolete — 480 (01E0) – 164 (A4) Reducer Vertical Size Resize—Conte xt B 0000 0ddd dddd dddd 480 (01E0) Interp 165 (A5) Reducer Horizontal Pan Resize 0d 00 0ddd dddd dddd 0 (0000) Interp 166 (A6) Reducer Horizontal Zoom Resize 0000 0ddd dddd dddd 640 (0280) Interp 167 (A7) Reducer Horizontal Si ze Resize—Context A 0000 0ddd dddd dddd 320 (0140) Interp 168 (A8) Reducer Vertical Pan Resize 0d00 0ddd dddd dddd 0 (0000) Interp 169 (A9) Reducer Vertical Zoom Resize 0000 0ddd dddd dddd 480 (01E0) Interp 170 (AA) Reducer Vertical Size Resize—Context A 0000 0ddd dddd dddd 240 (00F0) Interp 171 (AB) Reducer Current Zoom Horizontal 0000 0??? ???? ???? 640 (0280) Interp 172 (AC) Reducer Current Zoom Vertical 0000 0??? ???? ???? 480 (01E0) Interp 174 (AE) Reducer Zoom Step Size dddd dddd dddd dddd 3081 (0C09) Interp 175 (AF) Reducer Zoom Control 0000 00dd 0ddd dddd 0 (0000) Interp 180 (B4) Reserved — 32 (0020) — 182 (B6) Lens Correction Parameter 25 — 0 (0000) LensCorr 183 (B7) Lens Correction Parameter 26 — 0 (0000) LensCorr 184 (B8) Lens Correction Parameter 27 — 0 (0000) LensCorr 185 (B9) Lens Correction Parameter 28 — 0 (0000) LensCorr 186 (BA) Lens Correction Parameter 29 — 0 (0000) LensCorr 187 (BB) Lens Correction Parameter 30 — 0 (0000) LensCorr 188 (BC) Lens Correction Parameter 31 — 0 (0000) LensCorr 189 (BD) Lens Correction Parameter 32 — 0 (0000) LensCorr 190 (BE) Lens Correction Parameter 33 — 0 (0000) LensCorr Table 7: Colorpipe Registers – Address Page 1 (continued) REGISTER #DEC (HEX) REGISTER NAME DATA FORMAT DEFAULT VALUE DEC (HEX) MODULE

SOC VGA DIGITAL IMAGE SENSOR PRELIMINARY 09005aef8154a39d/09005aef8175e6cc Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9V112_2.fm- Rev. A 1/05 EN 16 ©2004 Micron Technology, Inc. All rights reserved. 191 (BF) Lens Correction Parameter 34 — 0 (0000) LensCorr 192 (C0) Lens Correction Parameter 35 — 0 (0000) LensCorr 193 (C1) Lens Correction Parameter 36 — 0 (0000) LensCorr 194 (C2) Lens Correction Parameter 37 — 0 (0000) LensCorr 195 (C3) Lens Correction Parameter 38 — 0 (0000) LensCorr 196 (C4) Lens Correction Parameter 39 — 0 (0000) LensCorr 200 (C8) Global Context Co ntrol dddd dddd dddd dd dd 0 (0000) CntxCtl 201 (C9) Reserved dddd dddd dddd dddd 0 (0000) MBist/ samobs 202 (CA) Reserved — N/A MBist/ samobs 203 (CB) Reserved — N/A MBist/ samobs 204 (CC) Reserved — N/A MBist/ samobs 205 (CD) Reserved — N/A MBist/ samobs 206 (CE) Reserved — N/A MBist/ samobs 207 (C) Reserved — N/A MBist/ samobs 208 (D0) Reserved — N/A MBist/ samobs 220 (DC) Gamma Correction Parameter 7 — 7700 (1E14) GmaCorr 221 (DD) Gamma Correction Parameter 8 — 17966 (462E) GmaCorr 222 (DE) Gamma Correction Parameter 9 — 34666 (876A) GmaCorr 223 (DF) Gamma Correction Parameter 10 — 47008 (B7A0) GmaCorr 224 (E0) Gamma Correction Parameter 11 — 57548 (E0CC) GmaCorr 225 (E1) Gamma Correction Parameter 12 — 0 (0000) GmaCorr 226 (E2) Effects Mode dddd dddd 0000 0ddd 28672 (7000) GmaCorr 227 (E3) Effects Sepia dddd dddd dddd dddd 45091 (B023) GmaCorr Table 7: Colorpipe Registers – Address Page 1 (continued) REGISTER #DEC (HEX) REGISTER NAME DATA FORMAT DEFAULT VALUE DEC (HEX) MODULE

SOC VGA DIGITAL IMAGE SENSOR PRELIMINARY 09005aef8154a39d/09005aef8175e6cc Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9V112_2.fm- Rev. A 1/05 EN 17 ©2004 Micron Technology, Inc. All rights reserved. Table 8: Camera Control Registers – Address Page 2 REGISTER # DEC (HEX) REGISTER NAME DATA FORMAT DEFAULT VALUE DEC (HEX) MODULE 2 (02) Color Correction Paramet er 1 — 174 (00AE) ColorCorr 3 (03) Color Correction Parameter 2 — 10531 (2923) ColorCorr 4 (04) Color Correction Paramet er 3 — 1188 (04A4) ColorCorr 9 (09) Color Correction Paramet er 4 — 182 (00B6) ColorCorr 10 (0A) Color Correction Parameter 5 — 208 (00D0) ColorCorr 11 (0B) Color Correction Parameter 6 — 144 (0090) ColorCorr 12 (0C) Color Correction Paramet er 7 — 217 (00D9) ColorCorr 13 (0D) Color Correction Parameter 8 — 150 (0096) ColorCorr 14 (0E) Color Correction Parameter 9 — 54 (0036) ColorCorr 15 (0F) Color Correction Parameter 10 — 77 (0073) ColorCorr 16 (10) Color Correction Parameter 11 — 93 (005D) ColorCorr 17 (11) Color Correction Parameter 12 — 201 (00C9) ColorCorr 18 (12) Color Correction Parameter 13 — N/A ColorCorr 19 (13) Color Correction Parameter 14 — N/A ColorCorr 20 (14) Color Correction Parameter 15 — N/A ColorCorr 21 (15) Color Correction Parameter 16 — 73 (0049) ColorCorr 22 (16) Color Correction Parameter 17 — 23 (0017) ColorCorr 23 (17) Color Correction Parameter 18 — 1 (0011) ColorCorr 24 (18) Color Correction Parameter 19 — 46 (002E) ColorCorr 25 (19) Color Correction Parameter 20 — 52 (0034) ColorCorr 26 (1A) Color Correction Parameter 21 — 3 (0003) ColorCorr 27 (1B) Color Correction Parameter 22 — 62 (003E) ColorCorr 28 (1C) Color Correction Parameter 23 — 77 (004D) ColorCorr 29 (1D) Color Correction Parameter 24 — 90 (005A) ColorCorr 30 (1E) AWB Parameter 1 — 108 (006C) AWB 31 (1F) AWB Parameter 2 — 160 (00A0) AWB 32 (20) AWB Parameter 3 — 51220 (C814) AWB 33 (21) AWB Parameter 4 — 32896 (8080) AWB 34 (22) AWB Parameter 5 — 55648 (D960) AWB 35 (23) AWB Parameter 6 — 55648 (D960) AWB 36 (24) AWB Parameter 7 — 32512 (7F00) AWB 38 (26) Auto Exposure Horizontal Window Boundaries dddd dddd dddd dddd 32768 (8000) AE 39 (27) Auto Exposure Vertical Window Boundaries dddd dddd dddd dddd 32776 (8008) AE 40 (28) AWB Parameter 8 — 61218 (EF22) AWB 41 (29) AWB Parameter 9 — 36211 (8D73) AWB 42 (2A) AWB Parameter 10 — 208 (00D0) AWB 43 (2B) Auto Exposure Horizontal Center Wind ow Boundaries dddd dddd dddd dddd 24608 (6020) AE 44 (2C) Auto Exposure Vertical Center Window Boundaries dddd dddd dddd dddd 24608 (6020) AE 45 (2D) AWB Window Boundaries dddd dddd dddd dddd 61600 (F0A0) AWB 46 (2E) Auto Exposure Target and Precisio n Control dddd dddd dddd dddd 3146 (0C4A) AE 47 (2F) Auto Exposure Speed and Sensitivity Co ntrol—Context A dddd dddd dddd dddd 57120 (DF20) AE 48 (30) AWB Parameter 11 — N/A AWB

SOC VGA DIGITAL IMAGE SENSOR PRELIMINARY 09005aef8154a39d/09005aef8175e6cc Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9V112_2.fm- Rev. A 1/05 EN 18 ©2004 Micron Technology, Inc. All rights reserved. 49 (31) AWB Parameter 12 — N/A AWB 50 (32) AWB Parameter 13 — N/A AWB 51 (33) Auto Exposure Parameter 1 — 5230 (146E) AE 54 (36) Auto Exposure Parameter 2 — 30736 (7810) AE 55 (37) Auto Exposure Parameter 3 — 768 (0300) AE 56 (38) Auto Exposure Parameter 4 — 1088 (0440) AE 57 (39) Auto Exposure Parameter 5 — 1702 (06A6) AE 58 (3A) Auto Exposure Parameter 6 — 1702 (06A6) AE 59 (3B) Auto Exposure Parameter 7 — 1371 (055B) AE 60 (3C) Auto Exposure Parameter 8 — 1371 (055B) AE 61 (3D) Auto Exposure Parameter 9 — 6105 (17D9) AE 62 (3E) AWB Parameter 14 — 7423 (1CFF) AWB 63 (3F) Auto Exposure Parameter 10 — N/A AE 70 (46) Auto Exposure Parameter 11 — 55552(D900) AE 75 (4B) Reserved — 0 (0000) — 76 (4C) Auto Exposure Parameter 12 — N/A AE 77 4D) Auto Exposure Parameter 13 — N/A AE 79 (4F) Reserved — 0 (0000) — 87 (57) Auto Exposure Parameter 14 — 470 (01D6) AE 88 (58) Auto Exposure Parameter 15 — 564 (0234) AE 89 (59) Auto Exposure Parameter 16 — 1970 (01D6) AE 90 (5A) Auto Exposure Parameter 17 — 564 (0234) AE 91 (5B) Flicker Control 0 ?000 0000 0000 0ddd 2 (0002) FD 92 (5C) Reserved — 4108 (100C) — 93 (5D) Reserved — 5392 (1510) — 94 (5E) Color Correction Parameter 2 — 26952 (6948) ColorCorr 95 (5F) Color Correction Parameter 26 — 14632 (3928) ColorCorr 96 (60) Color Correction Parameter 27 — 2 (0002) ColorCorr 97 (61) Reserved — 32896 (8080) — 99 (63) Reserved — N/A — 100 (64) Reserved — 23036(59FC) — 101 (65) Auto Exposure Parameter 18 — 0 (000) AE 103 (67) Auto Exposure Digital Gain Li mits dddd dddd dddd dddd 16400 (4010) AE 104 (68) Reserved — 17 (0011) — 106 (6A) Reserved — N/A — 107 (6B) Reserved — N/A — 108 (6C) Reserved — N/A — 109 (6D) Reserved — N/A — 110 (6E) Reserved — N/A — 111 (6F) Reserved — N/A — 112 (70) Reserved — N/A — 113 (71) Reserved — N/A — 114 (72) Reserved — N/A — Table 8: Camera Control Regist ers – Address Page 2 (continued) REGISTER # DEC (HEX) REGISTER NAME DATA FORMAT DEFAULT VALUE DEC (HEX) MODULE

SOC VGA DIGITAL IMAGE SENSOR PRELIMINARY 09005aef8154a39d/09005aef8175e6cc Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9V112_2.fm- Rev. A 1/05 EN 19 ©2004 Micron Technology, Inc. All rights reserved. 115 (73) Reserved — N/A — 116 (74) Reserved — N/A — 117 (75) Reserved — N/A — 118 (76) Reserved — N/A — 119 (77) Reserved — N/A — 120 (78) Reserved — N/A — 121 (79) Reserved — N/A — 122 (7A) Reserved — N/A — 123 (7B) Reserved — N/A — 124 (7C) Reserved — N/A — 125 (7D) Reserved — N/A — 130 (82) Auto Exposure Parameter 19 — 1020 (03FC) AE 131 (83) Auto Exposure Parameter 20 — 769 (0301) AE 132 (84) Auto Exposure Parameter 21 — 193 (00C1) AE 133 (85) Auto Exposure Parameter 22 — 929 (03A1) AE 134 (86) Auto Exposure Parameter 23 — 980 (03D4) AE 135 (87) Auto Exposure Parameter 24 — 983 (03D7) AE 136 (88) Auto Exposure Parameter 25 — 921 (0399) AE 137 (89) Auto Exposure Parameter 26 — 1016 (03F8) AE 138 (8A) Auto Exposure Parameter 27 — 28 (001C) AE 139 (8B) Auto Exposure Parameter 28 — 957 (03BD) AE 140 (8C) Auto Exposure Parameter 29 — 987 (03DB) AE 141 (8D) Auto Exposure Parameter 30 — 957 (03BD) AE 142 (8E) Auto Exposure Parameter 31 — 1020 (03FC) AE 143 (8F) Auto Exposure Parameter 32 — 990 (03DE) AE 144 (90) Auto Exposure Parameter 33 — 990 (03DE) AE 145 (91) Auto Exposure Parameter 34 — 990 (03DE) AE 146 (92) Auto Exposure Parameter 35 — 990 (03DE) AE 147 (93) Auto Exposure Parameter 36 — 31 (001F) AE 148 (94) Auto Exposure Parameter 37 — 65 (0041) AE 149 (95) Auto Exposure Parameter 38 — 867 (0363) AE 150 (96) Reserved — 0 (0000) — 151 (97) Reserved — N/A — 152 (98) Reserved — 255 (00FF) — 153 (99) Reserved — 1 (0001) — 156 (9C) Auto Exposure Speed and Sensitivity— Context B dddd dddd dddd dddd 57120 (DF20) AE 180 (B4) Reserved — 32 (0020) — 181 (B5) Reserved — N/A — 198 (C6) Reserved — 0 (0000) — 199 (C7) Reserved — N/A — 200 (C8) Global Context Control dddd dddd dddd dddd 0 (0000) CntxCtl 201 (C9) Context Control Parameter 2 — N/A CntxCtl 202 (CA) Camera Control Sequencer Parameter — N/A CntxCtl 203 (CB) Camera Control Sequencer Parameter 2 — 0 (0000) CntxCtl Table 8: Camera Control Regist ers – Address Page 2 (continued) REGISTER # DEC (HEX) REGISTER NAME DATA FORMAT DEFAULT VALUE DEC (HEX) MODULE

SOC VGA DIGITAL IMAGE SENSOR PRELIMINARY 09005aef8154a39d/09005aef8175e6cc Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9V112_2.fm- Rev. A 1/05 EN 20 ©2004 Micron Technology, Inc. All rights reserved. NOTE: Data Format Key: 0 = “Don't Care” bit. The exceptions: R0:0 and R255:0, which are hardwired R/O binary values. d = R/W bit ? = R/O bit. 204 (CC) Camera Control Sequencer Parameter 3 — 0 (0000) CntxCtl 205 (CD) Camera Control Sequencer Parameter 4 — 2190 (21A0) CntxCtl 206 (CE) Camera Control Sequence r Parameter 5 — 7835 (1E9B) CntxCtl 207 (CF) Camera Control Sequencer Parameter 6 — 19018(4A4A) CntxCtl 208 (D0) Camera Control Sequencer Parameter 7 — 5773 (168D) CntxCtl 209 (D1) Camera Control Sequencer Parameter 8 — 77 (004D) CntxCtl 210 (D2) Camera Control Sequencer Parameter 9 — 0 (0000) CntxCtl 211 (D3) Camera Control Sequencer Parameter 10 — 0 (0000) CntxCtl 212 (D4) Camera Control Sequencer Parameter 11 — 520 (0208) CntxCtl 213 (D5) Camera Control Sequencer Parameter 12 — 0 (0000) CntxCtl 239 (EF) AWB Parameter 15 — 8 (0008) AWB 242 (F2) AWB Parameter 16 — 0 (0000) AWB 243 (F3) Reserved — 0 (0000) — 245 (F5) Color Correction Parameter 29 — 135 (0040) ColorCorr 246 (F6) Color Correction Paramete r 30 — 127 (007F) ColorCorr 255 (FF) Color Correction Parameter 39 — 43136(A880) ColorCorr Table 8: Camera Control Regist ers – Address Page 2 (continued) REGISTER # DEC (HEX) REGISTER NAME DATA FORMAT DEFAULT VALUE DEC (HEX) MODULE

SOC VGA DIGITAL IMAGE SENSOR PRELIMINARY 09005aef8154a39d/09005aef8175e6cc Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9V112_2.fm- Rev. A 1/05 EN 21 ©2004 Micron Technology, Inc. All rights reserved. Image Flow Processor Register Description Configuration The vast majority of IFP registers associate to one of the IFP modules. These modules are identified in Table 7 on page 14 and in Table 8 on page 17. Detailed r e g i s t e r d e s c r i p t i o n s f o l l o w i n T a b l e 9 a n d i n T a b l e 1 0 on page 28. A few registers create effects across a num- ber of module functions. These include R240 page map register (R/W); R6:1 0x106 operating mode con- trol register (R/W); R8:1 0x108 output format control register (R/W); the R62:2 0x23E gain types and CCM threshold register—the gain threshold for CCM adjust- ment (R/W). Table 9: Colorpipe Register Description REGISTER# (HEX) DESCRIPTION R5:1—0x105 – Aperture Correction Default 0x0003 Description Aperture correction scal e factor used for sharpening. Bit 3 Enables automatic sharpness re duction control (see R51:2 0x233). Bits 2:0 Sharpening factor: “000” — No sharpening. “001”— 25% sharpening. “010”— 50% sharpening. “011”— 75% sharpening. “100”— 100% sharpening. “101”— 125% sharpening. “110”— 150% sharpening. “111”— 200% sharpening. R6:1—0x106 – Operatin g Mode Control (R/W) Default 0x700E Description This register specifies the operating mode of the IFP. Bit 15 Enables manual white balance. User can set the ba se matrix and color channel gains. This bit must be asserted and de-asserted with a frame in between to force new color correction settings to take effect. Bit 14 Enables auto exposure. Bit 13 Enables on-the-fly defect correction. Bit 12 Reserved—obsolete. The user should write “0” to this bit. Bit 11 Not used. Bit 10 Enables lens shading correction. 1: Enables lens shading correction. Bits 9:8 Reserved. Bit 7 Enables flicker detection. 1: Enables automatic flicker detection. Bit 6 Reserved for future expansion. Bit 5 Reserved. Bit 4 Bypasses color correction matrix. 1: Outputs “raw” color bypassing color correction. 0: Normal color processing. Bits 3:2 Auto exposure back light compensation control. “00”—Auto exposure sampling wind ow is specified by R38:2 and R39:2 (“large window”). “01” — Auto exposure sampling window is specified by R43:2 and R44:2 (“small window”). “1X”— Auto exposure sampling window is specified by the weighted sum of the large window and the small window, with the small window weighted four times more heavily.

SOC VGA DIGITAL IMAGE SENSOR PRELIMINARY 09005aef8154a39d/09005aef8175e6cc Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9V112_2.fm- Rev. A 1/05 EN 22 ©2004 Micron Technology, Inc. All rights reserved. Bit 1 Enables auto white balance. 1: Enables auto white balance. 0: Freezes white balance at current values. Bit 0 Reserved for future expansion. R8:1—0X108 – Output Format Control (R/W) Default 0x0080 Description This register specifies the ou tput timing and format in conjunction with R58:1 or R155:1 (depending on the context). Bits 15:11 Reserved fo r future expansion. Bit 10 Gate PIXCLK. 0: PIXCLK not gated. 1: PIXCLK gated with LINE_VALID. Bit 9 Flip Bayer columns in pr ocessed Bayer output mode. 0: Column order is green, red and blue, green. 1: Column order is red, green and green, blue. Bit 8 Flip Bayer row in processed Bayer output mode. 0: First row contains green and red; the second row contains blue and green. 1: First row contains blue and green; the second row contains green and red. Bit 7 Controls the values used for the protection bits in Rec. ITU-R BT.656 codes. 0: Use zeros for the protection bits. 1: Use the correct values. Bit 5 Multiplexes Y (in YCbCr mode) or green (in RGB mode) channel on all channels (monochrome). 1: Forces Y/G onto all channels. Bit 4 Disables Cb color output channe l (Cb = 128) in YCbCr mode and disables the blue color output channel (B = 0) in RGB mode. 1: Forces Cab to 128 or B to 0. Bit 3 Disables Y color output channel (Y = 128) in YCbCr and disables the green color output channel (G = 0) in RGB mode. 1: Forces Y to 128 or G to 0. Bit 2 Disables Cr color output channel (Cr = 128) in YCbCr mode and disables the red color output channel (R = 0) in RGB mode. 1: Forces Cr to 128 or R to 0. Bit 1 Toggles the assumptions ab out Bayer vertical CFA shift. 0: Row containing red comes first. 1: Row containing blue comes first. Bit 0 Toggles the assu mptions about Bayer horizontal CFA shift. 0: Green comes first. 1: Red or blue comes first. R37:1—0x125 – Color Saturation Control (R/W) Default 0x0005 Description This register specifies th e color saturation control settings. Bit 5:3 Specify overall attenuat ion of the color saturation. “000” — Full color saturation “001”— 75% of full saturation “010”— 50% of full saturation “011”— 37.5% of full saturation “100”— 25% of full saturation “101”— 150% of full saturation “110”— Black and white Table 9: Colorpipe Regist er Description (continued)

SOC VGA DIGITAL IMAGE SENSOR PRELIMINARY 09005aef8154a39d/09005aef8175e6cc Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9V112_2.fm- Rev. A 1/05 EN 23 ©2004 Micron Technology, Inc. All rights reserved. Bit 2:0 Specify color saturation attenu ation at high luminance (linearly increasing attenuation from no attenuation to monochrome at luminance of 224). “000”— No attenuation. “001”— Attenuation starts at luminance of 216. “010”— Attenuation starts at luminance of 208. “011”— Attenuation starts at luminance of 192. “100”— Attenuation starts at luminance of 160. “101”— Attenuation starts at luminance of 96. R52:1—0x134 – Luma Offset (can be used to control brightness) (R/W) Default 0x0010 Description Offset added to th e luminance prior to output. Bits 15:8 Y Offset in YCbCr mode. Bits 7:0 Offset in RGB mode. R53:1—0x135 – Luma Clip (R/W) Default 0xF010 Description Clipping limi ts for output luminance. Bits 15:8 Highest value of output luminance. Bits 7:0 Lowest value of output luminance. R58:1—0x13A – Output Format Control 2—Context A (R/W) Default 0x0200 Description Output forma t control 2—context A. Bit 14 Output processed Bayer data. Bit 13 Debug flicker luma. Bit 12 Reserved. Bit 11 Enables embedding Rec. ITU-R BT.656 synchronization codes in the output data. See R155:1. Bit 10 Entire image processing is bypa ssed and raw bayer is output directly. In YCbCr or RGB mode: 0: Normal operation, sensor core data flows through IFP. 1: Bypass IFP and output Imager data directly (full 10 bits). The image data still passes through the camera interface FIFO and the 10 bits are formatted to two output bytes through the camera interface; i.e., 8 + 2. Data rate is effectively the same as default 16-bit /per pixel modes. Auto exposure/AWB, etc., still function and control the sensor, though they are assuming some gain/correction through the colorpipe. See R155:1. Bit 9 Inverts output pixel clock. By default, this bit it a sserted and data is launched off the falling edge of PIXCLK for capture by the receiver on the rising edge. See R155:1. Bit 8 Enables RGB output. 0: Output YCbCr data. 1: Output RGB format data as defined by R58:1[7:6]. Bits 7:6 RGB output format: “00” — 16-bit RGB565. “01”— 15-bit RGB555. “10”— 12-bit RGB444x. “11”— 12-bit RGBx444. Bits 5:4 Test Ramp output: “00”— Off. “01”— By column. “10”— By row. “11”— By frame. Bit 3 Outputs RGB or YCbCr values are shifted 3 bits up. Use with R58:1[5:4] to test LCDs with low color depth. Bit 2 Averages two nearby chrominance bytes. See R155:1. Table 9: Colorpipe Regist er Description (continued)

SOC VGA DIGITAL IMAGE SENSOR PRELIMINARY 09005aef8154a39d/09005aef8175e6cc Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9V112_2.fm- Rev. A 1/05 EN 24 ©2004 Micron Technology, Inc. All rights reserved. Bit 1 In YCbCr mode swap C and Y bytes. In RGB mode, swap odd and even bytes. See R155:1. Bit 0 In YCbCr mode, swaps Cb and Cr channels. In RGB mode, swaps R and B channels. See R155:1. R72:1—0x148 - Test Pattern Generator control (R/W) Default 0x0000 Description This register enables test pattern generation at the input of the image processor. Values greater than “0” turn on the test pattern generator. The brightness of the flat-color areas depends on the value programmed (from 6–1) in this register. The value 7 produces the color bar pattern. Value 0 selects the sensor image. Bit 7 Test pattern selection. Bits 2:0 1: Forces WB digital gains to 1.0. 0: Normal operation. R153:1—0x199 – Line Counter (R/O) Default N/A Description Use line counter to determine th e number of the line currently being output. Bits 15:0 Line count. R154:1—0x19A – Frame Counter (R/O) Default N/A Description Use frame counter to determine th e index of the frame currently being output. Bits 15:0 Frame count. R155:1—0x19B – Output Format Control 2—Context B (R/W) Default 0x0200 Description Output forma t control 2—context B. Bit 14 Output processed Bayer data. Bit 13 Reserved. Bit 12 Reserved Bit 11 Enables embedding Rec. ITU-R BT.656 synchronization codes to the output data. See R58:1. Bit 10 Entire image processing is bypa ssed and raw bayer is output directly. In YCbCr or RGB mode: 0: Normal operation, sensor core data flows through IFP. 1: Bypass IFP and output Imager data directly (full 10 bits). The image data still passes through the camera interface FIFO and the 10 bits are formatted to two output bytes through the camera interface; i.e., 8 + 2. Data rate is effectively the same as default 16-bit /per pixel modes. auto exposure/AWB, etc. still function and control the sensor, though they are assuming some gain/correction through the colorpipe. See R58:1. Bit 9 Inverts output pixel clock. By default, this bit it a sserted and data is launched off the falling edge of PIXCLK for capture by the receiver on the rising edge. See R58:1. Bit 8 Enables RGB output. 0: Output YCbCr data. 1: Output RGB format data as defined by R155:1[7:6]. See R58:1. Bits 7:6 RGB output format: “00” — 16-bit RGB565. “01”— 15-bit RGB555. “10”— 12-bit RGB444x. “11”— 12-bit RGBx444. Bits 5:4 Test Ramp output: “00”— Off. “01”— By column. “10”— By row. “11”— By frame. Bit 3 Output RGB or YCbCr values are shifted 3 bits up. Use with R58:1[5:4] to test LCDs with low color depth. Bit 2 Averages two nearby chrominance bytes. See R58:1 Table 9: Colorpipe Regist er Description (continued)

SOC VGA DIGITAL IMAGE SENSOR PRELIMINARY 09005aef8154a39d/09005aef8175e6cc Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9V112_2.fm- Rev. A 1/05 EN 25 ©2004 Micron Technology, Inc. All rights reserved. Bit 1 In YCbCr mode swap C and Y bytes. In RGB mode, swap odd and even bytes. See R58:1. Bit 0 In YCbCr mode, swaps Cb and Cr channels. In RGB mode, swaps R and B channels. See R58:1. R161:1—0x1A1 – Reducer Horizontal Ou tput Size Resize—Context B (R/W) R164:1—0x1A4 – Reducer Vertical Output Size Resize—Context B (R/W) Default 0x0IE0 Description Controls reducer vertic al output size in context B. (Sensor Window Height 179 ≥ = YZoom Window Height ≥ = Output YSize) Bits 10:0 Y Size. R165:1—0x1A5 – Reducer Horizontal Pan Resize (R/W) Default 0x0000 Description Controls reducer horizontal pan. Pan and Zoom se ttings are NOT context switchable. The same field of view will be active for both context A and context B. Bit 14 0: MT9V112-compatible offset from X = 0. 1: Centered origin at 320 for more convenient zoom and resize. Bits 10:0 X Pan: Unsigned offset from X = 0 (Bit 14 = 0), or two’s complement from X = 320 (Bit 14 = 1). R166:1—0x1a6 – Reducer Horizontal Zoom Resize (R/W) Default 0x0280 Description Controls reducer ho rizontal zoom. Pan and Zoom settings are NOT context switchable. The same field of view will be active for both context A and context B. Bits 10:0 X Zoom. R167:1—0x1a7 – Reducer Horizontal Ou tput Size Resize—Context A (R/W) Default 0x0140 Description Controls reducer horizont al output size in context A. Bits 10:0 X Size. R168:1—0x1A8 – Reducer Vertical Pan Resize (R/W) Default 0x0000 Description Controls reducer vertical pan. Pan and Zoom se ttings are NOT context switchable. The same field of view will be active for both context A and context B. Bit 14 0: MT9V112-compat ible origin at Y = 0. 1: Centered origin at Y = 240 for more convenient zoom and resize. Bits 10:0 Y Pan: unsigned offset from y = 0 (Bit 14 = 0), or two’s complement from Y = 240 (Bit 14 = 1). R169:1—0x1A9 – Reducer Vertical Zoom Resize (R/W) Default 0x0IE0 Description Controls reducer vert ical zoom. Pan and Zoom settings are NOT context switchable. The same field of view will be active for both context A and context B. Bits 10:0 Y Zoom. R170:1—0x1AA – Reducer Vertical Ou tput Size Resize—Context A (R/W) Default 0x00F0 Description Controls reducer vertic al output size in context A. Bits 10:0 Y Size. R171:1—0x1AB – Reducer Current Horizontal Zoom (R/O) Default 0x0280 Description Current horizontal zoom. Bits 13:12 IR X shift. 0: No IR 1: 2x 2: 4x 3: 8x Table 9: Colorpipe Regist er Description (continued)

SOC VGA DIGITAL IMAGE SENSOR PRELIMINARY 09005aef8154a39d/09005aef8175e6cc Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9V112_2.fm- Rev. A 1/05 EN 26 ©2004 Micron Technology, Inc. All rights reserved. Bits 11:0 Current zoom window width. After automatic zoom (R175:1), copy R171:1 to the snapshot X Zoom register R166:1 (context A) or R160:1 (context B) so the snapshot has the same field of view as preview. Also copy to snapshot X Size register R167:1 (context A) or R161 (context B) for largest snapshot. R172:1—0x1AC – Reducer Current Vertical Zoom (R/O) Default 0x0IE0 Description Current vertical zoom. Bits 13:12 IR Y Shift. 0: No IR 1: 2x 2: 4x 3: 8x Bits 11:0 Current zoom window height. After automatic zoom (R175:1), copy R172:1 to the snapshot Y Zoom register R169:1 (context A) or R163:1 (context B) so the snapshot has the same field of view as preview. Also copy to snapshot X Size register R170:1 (context A) or R164 (context B) for largest snapshot. R174:1—0x1AE – Reducer Zoom Step Size (R/W) Default 0x0C09 Description Zoom step sizes. Should be a multiple of the aspect ratio 5:4 for VGA or 4:3 VGA or 11:9 for CIF. Bits 15:8 Zoom step size in X. Bits 7:0 Zoom step size in Y. R175:1—0x1AF – Reduce r Zoom Control (R/W) Default 0x0000 Description Resize Interpolation and zoom control. Bit 15:10 Reserved. Bit 9 Starts automatic “zoom out” in step sizes defined in R174:1. Bit 8 Starts automatic “zoom in” in step sizes defined in R174:1. Bit 7:0 Reserved. R200:1—0x1C8 – Global Context Control (R/W) Default 0x0000 Description Defines sensor and colorpipe context for current frame. Registers R200:0, R200:1, and R200:2 are shadows of each other. See description in R200:2. It is recommended that all updates to R200:n are handled by means of a WRITE to R200:2. Bit 15:0 See R200:2[15:0]. R226:1—0x1E2 – Effects Mode (R/W) Default 0x7000 Description This register specifies which of several special effects to apply to each pixel passing through the pixel pipe. Bits 15:8 Solarization threshold. Bits 2:0 Specification of the effects mode. “000” — No effect (pixels pass through unchanged). “001”— Monochrome (chromas set to 0). “010”— Sepia (chromas set to the value in the effects sepia register). “011”— Negative (all color channels inverted). “100”— Solarize (luma conditionally inverted). “101”— Solarize2 (luma conditionally inverted, chromas inverted when luma inverted). R227:1—0x1E3 – Effects Sepia (R/W) Default 0xB023 Description This register specifie s the chroma values for the sepia effect. In sepia mode, the chroma values of each pixel are set to this value. By default, this register contains a brownish color, but it can be set to an arbitrary color. Bit 15 Sign of Cb. Bits 14:8 Magnitude of Cb in 0.7 fixed point. Table 9: Colorpipe Regist er Description (continued)

SOC VGA DIGITAL IMAGE SENSOR PRELIMINARY 09005aef8154a39d/09005aef8175e6cc Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9V112_2.fm- Rev. A 1/05 EN 27 ©2004 Micron Technology, Inc. All rights reserved. Bit 7 Sign of Cr. Bits 6:0 Magnitude of Cr in 0.7 fixed point. Table 9: Colorpipe Regist er Description (continued)

SOC VGA DIGITAL IMAGE SENSOR PRELIMINARY 09005aef8154a39d/09005aef8175e6cc Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9V112_2.fm- Rev. A 1/05 EN 28 ©2004 Micron Technology, Inc. All rights reserved. Table 10: Camera Contro l Register Description R38:2—0x226 – Auto Exposure Horizontal Window Boundaries (R/W) Default 0x8000 Description This register specif ies the left and right boundaries of the window used by the auto exposure measurement engine. The values programmed in the registers are the fractional percentage, where 128 (decimal) is the right-most edge of the frame, 64 (decimal) is the middle of the frame, and 0 is the left-most edge of the frame. Bits 15:8 Right window boundary. Bits 7:0 Left window boundary. R39:2—0x227 – Auto Exposure Vertical Window Boundaries (R/W) Default 0x8008 Description This register specifies the top and bottom boundaries of the window used by the auto exposure measurement engine. The values programmed in the registers are the fractional percentage, where 128 (decimal) is the bottom edge of the frame, 64 (decimal) is the middle of the frame, and 0 is the top edge of the frame. Bits 15:8 Bottom window boundary. Bits 7:0 Top window boundary. R43:2—0x22B – Auto Exposure Horizont al Center Window Boundaries (R/W) Default 0x6020 Description This register specif ies the left and right boundaries of the window used by the auto exposure measurement engine in back light compensation mode. The values programmed in the registers are the fractional percentage, where 128 (decimal) is the right-most edge of the frame, 64 (decimal) is the middle of the frame, and 0 is the left-most edge of the frame. Bits 15:8 Right window boundary. Bits 7:0 Left window boundary. R44:2—0x22C – Auto Exposure Vertical Center Window Boundaries (R/W) Default 0x6020 Description This register specifies the top and bottom boundaries of the window used by the auto exposure measurement engine in back light compensation mode. The values programmed in the registers are the fractional percentage, where 128 (decimal) is the bottom edge of the frame, 64 (decimal) is the middle of the frame, and “0” is the top edge of the frame. Bits 15:8 Bottom window boundary. Bits 7:0 Top window boundary. R45:2—0x22D – AWB Window Boundaries (R/W) Default 0xF0A0 Description This register specifies the boun daries of the window used by the AWB measurement engine. Essentially, it describes the AWB measurement window in terms relative to the size of the image— horizontally, in units of 1/10ths of the width of the image; vertically, in units of 1/16 of the height of the image. So although the positioning is highly quantized, the window remains roughly in place as the resolution changes. Bits 15:12 Bottom window boundary (in units of blocks). Bits 11:8 Top window boundary (in units of blocks). Bits 7:4 Right window boundary (in units of 2 blocks). Bits 3:0 Left window boundary (in units of 2 blocks). R46:2—0x22E – Auto Exposure Target and Precision Control (R/W) Default 0x0C4A Description This register specifies the luma target of the au to exposure algorithm and the size of the window/range around the target in which no auto exposure adjustment is made. This window is centered on target, but the value programmed in the register is 1/2 of the window size. Bits 15:8 Half-size of the auto exposure stability window/range.

SOC VGA DIGITAL IMAGE SENSOR PRELIMINARY 09005aef8154a39d/09005aef8175e6cc Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9V112_2.fm- Rev. A 1/05 EN 29 ©2004 Micron Technology, Inc. All rights reserved. Bits 7:0 Luma value of the auto exposure target. R47:2—0x22F – Auto Exposure Speed and Sensitivity Control—Context A (R/W) Default 0xDF20 Description This register specifies the speed and sensit ivity to changes of auto exposure in context A. Bit 15 Reserved. Bit 14 Reserved. Bits 13:12 Reserved. Bit 11 Reserved. Bit 10 Reserved. Bit 9 Reserved. Bits 8:6 Factor of reduction of the difference between current luma and target luma. In one adjustment auto exposure advances from current luma to target as follows: “000” — 1/4 way going down, 1/8 going up. “001”— 1/4 way in both directions. “010”— 1/2 way in both directions. “011”— 1/2 way going down, 1/4 going up. “100”— All the way in both directions (fast adaptation!). “101”— 3/4 way in both directions. “110”— 7/8 way in both directions. “111”— Reserved. Currently the same as “100” Bit 5 Reserved Bits 4:3 Auto exposure luma is updated every N frames, where N is given by this field. Bits 2:0 Hysteresis control via time-ave raged smoothing of luma data. Luma measurements for auto exposure are time-averaged as follows: “000”— Auto exposure luma = current luma. “001”— Auto exposure luma = 1/2 current luma + 1/2 buffered value. “010”— Auto exposure luma = 1/4 current luma + 3/4 buffered value. “011”— Auto exposure luma = 1/8 current luma + 7/8 buffered value. “100”— Auto exposure luma = 1/16 current luma + 15/16 buffered value. “101”— Auto exposure luma = 1/32 current luma + 31/32 buffered value. “110”— Auto exposure luma = 1/64 current luma + 63/64 buffered value. “111”— Auto exposure luma = 1/128 current luma + 127/128 buffered value. R91:2—0x25B - Flicker Control (R/W) Default 0x0002 Description Primary Flicker Control Register. Bit 15 (READ only) 50Hz/60Hz detected. 0: 50Hz detected. 1: 60Hz detected. Bit 2 Reserved. Bit 1 When in “manual” flicker mode (R91:2[0] = 1), defines which flicker frequency to avoid. 0: Forces 50Hz detection. 1: Forces 60Hz detection. Bit 0 0: Auto flicker detection. 1: Manual Mode. R98:2—0x262 – Auto Exposure Digital Gains Monitor (R/W*) Default Description These digital gains are applied within th e IFP; they are independent of the imager gains. Bits 15:8 Post-lens correction digital gain (writable if auto exposure is disabled). Bits 7:0 Pre-lens correction digital gain (w ritable if auto exposure is disabled). Table 10: Camera Control Re gister Description (continued)

SOC VGA DIGITAL IMAGE SENSOR PRELIMINARY 09005aef8154a39d/09005aef8175e6cc Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9V112_2.fm- Rev. A 1/05 EN 30 ©2004 Micron Technology, Inc. All rights reserved. R103:2—0x267 – Auto Exposure Digital Gain Limits (R/W) Default 0x4010 Description This register specifies the uppe r limits of the digital gains used by the auto exposure algorithm. The values programmed to this register are 16 times the absolute gain values. The value of 16 represents the gain 1.0. Bits 15:8 Maximum limit on post -lens correction digital gain. Bits 7:0 Maximum limit on pre- lens correction digital gain. R156:2—0x29C – Auto Exposure Speed an d Sensitivity Control—Context B (R/W) Default 0xDF20 Description This register specifies the speed and sens itivity to auto exposure changes in context B. Bit 15 Reserved. Bit 14 Reserved. Bits 13:12 Reserved. Bit 11 Reserved. Bit 10 Reserved. Bit 9 Reserved. Bits 8:6 Factor of reduction of the difference between current luma and target luma. In one adjustment, auto exposure advances from current luma to target as follows: “000” — 1/4 way going down, 1/8 going up. “001”— 1/4 way in both directions. “010”— 1/2 way in both directions. “011”— 1/2 way going down, 1/4 going up. “100”— All the way in both directions (fast adaptation!). “101”— 3/4 way in both directions. “110”— 7/8 way in both directions. “111”— Reserved. Currently the same as “100.” Bit 5 Reserved. Bits 4:3 Auto exposure luma is updated every N frames, where N is given by this field. Bits 2:0 Hysteresis control via time-ave raged smoothing of luma data. Luma measurements for auto exposure are time-averaged as follows: “000”— Auto exposure luma = current luma. “001”— Auto exposure luma = 1/2 current luma + 1/2 buffered value. “010”— Auto exposure luma = 1/4 current luma + 3/4 buffered value. “011”— Auto exposure luma = 1/8 current luma + 7/8 buffered value. “100”— Auto exposure luma = 1/16 current luma + 15/16 buffered value. “101”— Auto exposure luma = 1/32 current luma + 31/32 buffered value. “110”— Auto exposure luma = 1/64 current luma + 63/64 buffered value. “111”— Auto exposure luma = 1/128 current luma + 127/128 buffered value. R180:2 – Reserved R200:2—0x2C8 – Global Context Control (R/W) Default 0x0000 Description Defines sensor and colorpipe context for current frame. Context A is typically used to define preview or viewfinder mode, while context B is typically used for snapshots. The bits of this register directly control the respective functions, so care must be taken when writing to this register if a bad frame is to be avoided during the context switch. Bit 15 Controls assertion of sensor restart on update of glob al context control register. This helps ensure that the very next frame is generated with the new context (a problem with regard to exposure due to the rolling shutter). This bit is automatically cleared once the restart has occurred. 0: Do not restart sensor. 1: Restart sensor. Table 10: Camera Control Re gister Description (continued)

SOC VGA DIGITAL IMAGE SENSOR PRELIMINARY 09005aef8154a39d/09005aef8175e6cc Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9V112_2.fm- Rev. A 1/05 EN 31 ©2004 Micron Technology, Inc. All rights reserved. Bit 14 Reserved. Bit 13 Reserved. Bit 12 Reserved. Bit 11 Reserved. Bit 10 Resize/zoom context. Sw itch resize/zoom contexts: 0: Context A 1: Context B Bit 9 Output format control 2 Co ntext. See R58:1 and R155:1. 0: Context A 1: Context B Bit 8 Gamma table context. 0: Context A 1: Context B Bit 7 Arm Xenon Flash. Bit 6 Blanking control. This is primarily for use by the internal sequencer when taking automated (e.g., flash) snapshots. Setting this bit stops frames from being sent over the BT656 external pixel interface. This is useful for ensuring that the desired frame during a snapshot sequence is the only frame captured by the host. 0: No blanking 1: Blank frames to host Bit 5 Reserved. Bit 4 Reserved. Bit 3 Sensor Read Mode context (s kip mode, power mode (second ADC on/off), see R33:0 and R32:0. 0: Context A 1: Context B Bit 2 LED Flash ON: 0: Turn off LED Flash 1: Turn on LED Flash Bit 1 Vertical blanking context: 0: Context A 1: Context B Bit 0 Horizontal blanking context: 0: Context A 1: Context B Table 10: Camera Control Re gister Description (continued)

SOC VGA DIGITAL IMAGE SENSOR PRELIMINARY 09005aef8154a39d/09005aef8175e6cc Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9V112_2.fm- Rev. A 1/05 EN 32 ©2004 Micron Technology, Inc. All rights reserved. Sensor Core Overview The sensor consists of a pixel array of 695 x 504 total, an analog readout chain, 10-bit ADC with programma- ble gain and black offset, and timing and control. Figure 5: Sensor Core Block Diagram Pixel Data Format Pixel Array Structure The sensor core pixel array is configured as 695 col- umns by 504 rows, shown in Figure 6. The first 34 col- umns and the first 14 rows of pixels are optically black, and can be used to monitor the black level. The last 12 columns and the last row of pixels also are optically black. The black row data is used internally for the auto- matic black level adjustment. However, these black rows can also be read out by setting the sensor to raw data output mode. There are 649 columns by 489 rows of optically- active pixels that provide a four-pixel boundary around the VGA (640 x 480) image to avoid boundary effects during color interpolation and correction. The additional active colu mn and additional active row are used to enable horizontally and vertically mir- rored readout to start on the same color pixel. Figure 6: Pixel Array Description The sensor core uses an RGB Bayer color pattern, shown in Figure 7. The even-numbered rows contain green and red color pixels, and odd-numbered rows contain blue and green color pixels. The even-num- bered columns contain green and blue color pixels; odd-numbered columns contain red and green color pixels. Figure 7: Pixel Color Pattern Detail (top right corner) Communication Bus to IFP 10-Bit Data to IFP Sync Signals Clock Control Register Analog Processing Active Pixel Sensor (APS) Array Timing and Control ADC

34 Black Columns

1 Black Row

14 Black Rows

(0, 0)

12 Black Columns

(694,503) VGA (640 x 480) + 4-pixel boundary for color correction + additional active column + additional active row = 649 x 489 active pixels Black Pixels Column Readout Direction ... Row Readout Direction G B G B G B R G R G R G G B G B G B R G R G R G G B G B G B R G R G R G G B G B G B First Clear Pixel (34, 14)

SOC VGA DIGITAL IMAGE SENSOR PRELIMINARY 09005aef8154a39d/09005aef8175e6cc Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9V112_2.fm- Rev. A 1/05 EN 33 ©2004 Micron Technology, Inc. All rights reserved. Output Data Format The sensor core image data is read out in a progres- sive scan. Valid image data is surrounded by horizontal blanking and vertical blanking, shown in Figure 8. LINE_VALID is HIGH during the shaded region of the figure. FRAME_VALID timing is described in “ Appen- dix A ” on page 52. Figure 8: Spatial Illustration of Image Readout VALID IMAGE HORIZONTAL BLANKING VERTICAL BLANKING VERTICAL/HORIZONTAL BLANKING

SOC VGA DIGITAL IMAGE SENSOR PRELIMINARY 09005aef8154a39d/09005aef8175e6cc Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9V112_2.fm- Rev. A 1/05 EN 34 ©2004 Micron Technology, Inc. All rights reserved. Sensor Core Registers Table 11: Sensor Registers – Address Page 0 REGISTER# DEC (HEX) REGISTER NAME DATA FORMAT DEFAULT VALUE DEC (HEX) 0 (0x00) Chip Version 0001 0010 0010 1001 (LSB) 4649 (0x1229) 1 (0x01) Row Start 0000 0d dd dddd dddd 18 (0x12) 2 (0x02) Column Start 0000 0ddd dddd dddd 38 (0x0026) 3 (0x03) Row Width 0000 0ddd dddd dddd 480 (0x01E0) 4 (0x04) Column Width 0000 0ddd dddd dddd 640 (0x280) 5 (0x05) Horizontal Blanking—Conte xt B 00dd dddd dd dd dddd 203 (0xCB) 6 (0x06) Vertical Blanking—Context B 0ddd dddd dddd dddd 11 (0x0B) 7 (0x07) Horizontal Blanking—Conte xt A 00dd dddd dd dd dddd 203 (0xCB) 8 (0x08) Vertical Blanking—Context A 0ddd dddd dddd dddd 11 (0x0B) 9 (0x09) Shutter Width dddd dddd dddd dddd 470 (0x1D6) 10 (0x0A) Row Speed ddd0 000d dddd dddd 17 (0x0011) 11 (0x0B) Extra Delay 00dd dddd dddd dddd 0 (0x0000) 12 (0x0C) Shutter Delay 00dd dddd dddd dddd 0 (0x0000) 13 (0x0D) Reset d000 00dd 00dd dddd 8 (0x0008) 32 (0x20) Read Mode—Context B d d00 0ddd dddd dddd 1792 (0x0700) 33 (0x21) Read Mode—Context A 0000 0d00 0000 dd00 1024 (0x0400) 34 (0x22) Reserved — 299 (0x012B) 35 (0x23) Flash Control ??dd dddd dddd dddd 1544 (0x0608) 36 (0x24) Reserved — 16384 (0x4000) 43 (0x2B) Green1 Gain 0000 0ddd dddd dddd 32 (0x0020) 44 (0x2C) Blue Gain 0000 0ddd dddd dddd 32 (0x0020) 45 (0x2D) Red Gain 0000 0ddd dddd dddd 32 (0x0020) 46 (0x2E) Green2 Gain 0000 0ddd dddd dddd 32 (0x0020) 47 (0x2F) Global Gain 0000 0ddd dddd dddd 32 (0x0020) 48 (0x30) Reserved — 1066 (0x042A) 49 (0x31) Reserved — 7168 (0x1C00) 50 (0x32) Reserved — 42 (0x002A) 51 (0x33) Reserved — 833 (0x0341) 52 (0x34) Reserved — 49160 (0xC009) 53 (0x35) Clip Control — 8226 (0x2022) 54 (0x36) Reserved — 61680 (0xF0F0) 55 (0x37) Reserved — 0 (0x0000) 59 (0x3B) Reserved — 33 (0x0021) 60 (0x3C) Reserved — 6688 (0x1A20) 61 (0x3D) Reserved — 8222 (0x201E) 62 (0x3E) Reserved — 8224 (0x2020) 63 (0x3F) Reserved — 4128 (0x1020) 64 (0x40) Reserved — 8192 (0x2000) 65 (0x41) Reserved — 215 (0x00D7) 66 (0x42) Reserved — 1911 (0x0777) 88 (0x58) New Black Level Algorithm — 0 (0x000) 89 (0x59) Reserved — 12 (0x000C) 90 (0x5A) Reserved — 57354 (0xE00A)

SOC VGA DIGITAL IMAGE SENSOR PRELIMINARY 09005aef8154a39d/09005aef8175e6cc Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9V112_2.fm- Rev. A 1/05 EN 35 ©2004 Micron Technology, Inc. All rights reserved. 91 (0x5B) Reserved — N/A 92 (0x5C) Reserved — N/A 93 (0x5D) Reserved — N/A 94 (0x5E) Reserved — N/A 95 (0x5F) Reserved — 8989 (0x231D) 96 (0x60) Reserved — 128 (0x0080) 97 (0x61) Reserved — 0 (0x0000) 98 (0x62) Reserved — 0 (0x0000) 99 (0x63) Reserved — 0 (0x0000) 100 (0x64) Reserved — 0 (0x0000) 112 (0x70) Reserved — 31498 (0x7B0A) 113 (0x71) Reserved — 31498 (0x7B0A) 114 (0x72) Reserved — 6414 (0x190E) 115 (0x73) Reserved — 29967 (0x750F) 116 (0x74) Reserved — 22322 (0x5732) 117 (0x75) Reserved — 22068 (0x5634) 118 (0x76) Reserved — 29493 (0x7335) 119 (0x77) Reserved — 12306 (0x3012) 120 (0x78) Reserved — 30978 (0x7902) 121 (0x79) Reserved — 29958 (0x7506) 122 (0x7A) Reserved — 30474 (0x770A) 123 (0x7B) Reserved — 30729 (0x7809) 124 (0x7C) Reserved — 32006 (0x7D06) 125 (0x7D) Reserved — 12560 (0x3110) 126 (0x7E) Reserved — 126 (0x007E) 127 (0x7F) Reserved — 31745 (0x7C01) 128 (0x80) Reserved — 22788 (0x5904) 129 (0x81) Reserved — 22788 (0x5904) 130 (0x82) Reserved — 22282 (0x570A) 131 (0x83) Reserved — 22539 (0x580B) 132 (0x84) Reserved — 18188 (0x470C) 133 (0x85) Reserved — 18446 (0x480E) 134 (0x86) Reserved — 23298 (0x5B02) 135 (0x87) Reserved — 92 (0x005C) 200 (0xC8) Context Control d00 0 0000 d000 dddd 11 (0x000B) 240 (0xF0) Page Map 0000 0000 0000 0ddd 0 (0x0000) 241 (0xF1) Bytewise Address Reserved Reserved 245 (0xF5) Reserved — 1023 (0x03FF) 246 (0xF6) Reserved — 511 (0x01FF) 247 (0xF7) Reserved — 0 (0x0000) 248 (0xF8) Reserved — 0 (0x0000) 249 (0xF9) Reserved — 0 (0x0000) 250 (0xFA) Reserved — 0 (0x0000) 251 (0xFB) Reserved — 0 (0x0000) 252 (0xFC) Reserved — 0 (0x0000) Table 11: Sensor Registers – Address Page 0 (continued) REGISTER# DEC (HEX) REGISTER NAME DATA FORMAT DEFAULT VALUE DEC (HEX)

SOC VGA DIGITAL IMAGE SENSOR PRELIMINARY 09005aef8154a39d/09005aef8175e6cc Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9V112_2.fm- Rev. A 1/05 EN 36 ©2004 Micron Technology, Inc. All rights reserved. NOTE: Data Format Key: 0 = “Don't Care” bit d = R/W bit ? = R/O bit. The exceptions: R0:0 and R255:0, which are hardwired R/O binary values. 253 (0xFD) Reserved — 0 (0x0000) 255 (0x00) Chip Version 0001 0010 0010 1001 (LSB) 4649 (0x1229) Table 11: Sensor Registers – Address Page 0 (continued) REGISTER# DEC (HEX) REGISTER NAME DATA FORMAT DEFAULT VALUE DEC (HEX)

SOC VGA DIGITAL IMAGE SENSOR PRELIMINARY 09005aef8154a39d/09005aef8175e6cc Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9V112_2.fm- Rev. A 1/05 EN 37 ©2004 Micron Technology, Inc. All rights reserved. Table 12: Sensor Core Register Descriptions BIT FIELD DESCRIPTION DEFAULT (HEX) SYNC’D TO FRAME START BAD FRAME READ/ WRITE R0:0—0x000 – Chip Version (R/O) Bits 15:0 Hardwired READ only. 0x1229 R R1:0—0x001 – Row Start Bits 10:0 Row Start The first row to be read out (not counting dark rows that may be read). To window the image down, set this register to the starting Y value. Setting a value less than 8 is not recommended since the dark rows should be read using Reg0x022. 0x12 Y YM W R2:0—0x002 – Column Start Bits 10:0 Col Start The first column to be read out (not counting dark columns that may be read). To window the image down, set this register to the starting X value. Setting a value below 0x18 is not recommended since readout of dark columns should be controlled by Reg0x022. 0x26 Y YM W R3:0—0x003 – Row Width Bits 10:0 Row Width Number of rows in the image to be read out (not counting dark rows or border rows that may be read). 0x1E0 Y YM W R4:0—0x004 – Column Width Bits 10:0 Col Width Number of columns in image to be read out (not counting dark columns or border columns that may be read). 0x284 Y YM W R5:0—0x005 – Horizontal Blanking—Context B Bits 10:0 Horizontal Blanking B Number of blank columns in a row when context B is chosen (bit 0, Reg0x0C8 = 1). The extra columns are added at the beginning of a row. The minimum supported value is 132. 0xCB Y YM W R6:0—0x006 – Vertical Blanking—Context B Bits 14:0 Vertical Blanking B Number of blank rows in a frame when context B is chosen (bit 1, Reg0x0C8 = 1). This number must be equal to or larger than the number of dark rows read out in a frame specified by Reg0x022. 0x0B Y N W R7:0—0x007 – Horizontal Blanking—Context A Bits 10:0 Horizontal Blanking A Number of blank columns in a row when context A is chosen (bit 0, Reg0x0C8 = 0). The extra columns are added at the beginning of a row. The minimum supported value is 132. 0xCB Y YM W R8:0—0x008 – Vertical Blanking—Context A Bits 14:0 Vertical Blanking A Number of blank rows in a frame when context A is chosen (bit 1, Reg0x0C8 = 1). This number must be equal to or larger than the number of dark rows read out in a frame specified by Reg0x022. 0xB Y N W R9:0—0x009 – Shutter Width Bits 15:0 Shutter Width Integration time in number of rows. In addition to this register, the shutter delay register (Reg0x0C) and the overhead time influences the integration time for a given row time. 0x1D6 Y N W R10:0—0x00A – Row Speed Bit 13 Invert to cb clock. —— — — Bit 8 Invert Pixel Clock Invert pixel clock. When set, LINE_VALID, FRAME_VALID, and DATA_OUT is set to the falling edge of PIXCLK. When clear, they are set to the rising edge if there is no pixel clock delay. 0x0 N 0 W

SOC VGA DIGITAL IMAGE SENSOR PRELIMINARY 09005aef8154a39d/09005aef8175e6cc Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9V112_2.fm- Rev. A 1/05 EN 38 ©2004 Micron Technology, Inc. All rights reserved. Bits 7:4 Delay Pixel Clock Delay PIXCLK in half-master-clock cycles. When set, the pixel clock can be delayed in increments of half-master- clock cycles compared to the synchronization of FRAME_VALID, LINE_VALID, and DATA_OUT. 0x1 N 0 W Bits 3:0 Pixel Clock Speed The pixel clock period is doubled, so the ADC clock period remains the same for one programmed register value. The value “0” is not allowed, and “1” is used instead. 0x1 Y YM W R11:0—0x00B – Extra Delay Bits 13:0 Extra Delay Extra blanking inserted between frames specified in pixel clocks. Can be used to get a more exact frame rate. For integration times less than a frame, however, it might affect the integration times for parts of the image. 0x0 Y 0 W R12:0—0x00C – Shutter Delay Bits 10:0 Shutter Delay The amount of time from the end of the sampling sequence to the beginning of the pixel reset sequence. This variable is automatically halved in low-power mode, so the time in use remains the same. This register has an upper value defined by the fact that the reset needs to finish prior to readout of that row to prevent changes in the row time. 0x0 Y N W R13:0—0x00D – Reset Bit 15 Synchronize Changes 0: Normal operation, updates changes to registers that affect image brightness at the next frame boundary (integration time, integration delay, gain, horizontal blanking and vertical blanking, window size, row/column skip, or row mirror. 1: Do not update any changes to these settings until this bit is returned to “0.” All registers that are frame-synchronized are affected by this bit setting. 0x0 N 0 W Bit 13 Stop_soc Setting this bit turns off all SOC clocks. 0x0 N 0 W Bit 12 Div 2 By setting this bit, the CLK_IN is divided by two before going to master clock control. 0x0 N 0 W Bit 10 Switch Two-wire Interface ID Setting this bit converts SHIP_ID from default to the other (0xBA/0xBB => 0x90/0x91). 0x0 N N W Bit 9 Restart Bad Frames When set, a forced restart occurs when a bad frame is detected. This can shorten the delay when waiting for a good frame because the delay when masking out a bad frame is the integration time rather than the full frame time. 0x0 N 0 W Bit 8 Show Bad Frames 0: Only output good frames (default) A bad frame is defined as the first frame following a change to: window size or position, horizontal blanking, pixel clock speed, zoom, row or column skip, or mirroring. 1: Output all frames (including bad frames) 0x0 N 0 W Bit 7 Inhibit Standby Setting this bit stops STANDBY from affecting entry to or exit from the low-power state. Bit 6 Drive Signals By default, asserting STANDBY causes the ball interface to enter High-Z. Setting this bit stops STANDBY from contributing to output enable control. Table 12: Sensor Core Register Descriptions (continued) BIT FIELD DESCRIPTION DEFAULT (HEX) SYNC’D TO FRAME START BAD FRAME READ/ WRITE

SOC VGA DIGITAL IMAGE SENSOR PRELIMINARY 09005aef8154a39d/09005aef8175e6cc Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9V112_2.fm- Rev. A 1/05 EN 39 ©2004 Micron Technology, Inc. All rights reserved. Bit 5 Reset SOC This reset signal is fed directly to the SOC part of the chip, and has no functionality in a stand alone sensor. 0x0 N 0 W Bit 4 Output Disable When set, the output signals are tri-stated. 0x0 N 0 W Bit 3 Chip Enable 0: Stop sensor readout. When this is returned to “1,” sensor readout restarts and begins resetting the starting row in a new frame. To reduce the digital power, the master clock to the sensor can be disabled or STANDBY can be used. 1: Normal operation. 0x1 N YM W Bit 2 Standby 0: Normal operation (default) 1: Disable analog circuitry and internal clocks. Whenever this bit is set to “1” the chip enable bit (bit 3) should be set to “0.” 0x0 N YM W Bit 1 Restart Setting this bit causes the sensor to abandon the current frame and start resetting the first row. The delay before the first valid frame is read out equals the integration time. This bit always reads “0.” 0x0 N YM W Bit 0 Reset Setting this bit puts the sensor in reset mode; this sets the sensor to its default power-up state. Clearing this bit resumes normal operation. 0x0 N YM W R32:0—0x020 – Read Mode—Context B Bit 15 XOR Line Valid 0: LINE_VALID determined by bit 9. Ineffective if Continuous LINE_VALID is set. 1: LINE_VALID = “Continuous” Line Valid XOR Frame Valid, 0x0 N 0 W Bit 14 Continuous Line Valid 0: Normal LINE_VALID (default, no line valid during vertical blanking). 1: “Continuous” LINE_VALID (continue producing line valid during vertical blanking). 0x0 N 0 W Bit 10 Low-Power Mode— Context B When READ mode context B is selected (bit 3, Reg0x0C8 = 1): 0: Full power, maximum readout speed. 1: Low power. Maximum readout frequency is now half of the master clock, and the pixel clock is automatically adjusted as described for the pixel clock speed register. 0x1 Y YM W Bit 9 Show Border This bit indicates whether to show the border enabled by bit 8. When bit 8 is 0, this bit has no meaning. When bit 8 is 1, this bit decides whether the border pixels should be treated as extra active pixels (1) or extra blanking pixels (0). 0x1 N 0 W Bit 8 Over Sized When this bit is set, a 4-pixel border is output around the active image array independent of readout mode (skip, zoom, mirror, etc.). Setting this bit therefore adds eight to the numbers of rows and columns in the frame. 0x1 Y YM W Bits 7:6 Reserved. 0x0 Y YM W Bit 5 Column Skip 4x 0: Normal readout. 1: READ out two columns, and then skip six columns (as with rows). 0x0 Y YM W Bit 4 Row Skip 4x 0: Normal readout. 1: READ out two rows, and then skip six rows (i.e., row 8, row 9, row 16, row 17…). 0x0 Y YM W Table 12: Sensor Core Register Descriptions (continued) BIT FIELD DESCRIPTION DEFAULT (HEX) SYNC’D TO FRAME START BAD FRAME READ/ WRITE

SOC VGA DIGITAL IMAGE SENSOR PRELIMINARY 09005aef8154a39d/09005aef8175e6cc Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9V112_2.fm- Rev. A 1/05 EN 40 ©2004 Micron Technology, Inc. All rights reserved. Bit 3 Column Skip 2x — Context B When READ mode context B is selected (bit 3, Reg0x0C8 = 1): 0: Normal readout. 1: READ out two columns, and then skip two columns (as with rows). 0x0 Y YM W Bit 2 Row Skip 2x— Context B When READ mode context B is selected (bit 3, Reg0x0C8 = 1): 0: Normal readout. 1: READ out two rows, then skip two rows (i.e., row 8, row 9, row 12, row 13…). 0x0 Y YM W Bit 1 Mirror Columns Read out columns from right to left (mirrored). When set, column readout starts from column (Col Start + Col Size) and continues down to (Col Start + 1). When clear, readout starts at Col Start and continues to (Col Start + Col Size - 1). This ensures that the starting color is maintained. 0x0 Y YM W Bit 0 Mirror Rows Read out rows from bottom to top (upside down). When set, row readout starts from row (Row Start + Row Size) and continues down to (Row Start + 1). When clear, readout starts at Row Start and continues to (Row Start + Row Size - 1). This ensures that the starting color is maintained. 0x0 Y YM W R33:0—0x021 – Read Mode—Context A Bit 10 Low-Power Mode— Context A When READ mode, context A is selected (bit 3, Reg0x0C8 = 0): 0: Full power, maximum readout speed. 1: Low power. Maximum readout frequency is now half of the master clock, and the pixel clock is automatically adjusted as described for the pixel clock speed register. 0x1 Y YM W Bit 3 Column Skip 2x — Context A When READ mode context A is selected (bit 3, Reg0x0C8 = 0): 0: Normal readout. 1: READ out two columns, and then skip two columns (as with rows). 0x0 Y YM W Bit 2 Row Skip 2x— Context A When READ mode context A is selected (bit 3, Reg0x0C8 = 0): 0: Normal readout. 1: READ out two rows, and then skip two rows (i.e., row 8, row 9, row 12, row 13…). 0x0 Y YM W R35:0—0x023 – Flash Control Bit 15 Flash Strobe READ only bit that indicates whether FLASH_STROBE is enabled. 0x0 0 0 R Bit 14 Reserved. —— — — Bit 13 Xenon Flash Enable Xenon flash. When set, the FLASH_STROBE output signal is pulsed HIGH for the programmed period during vertical blanking. This is achieved by keeping the integration time equal to one frame and the pulse width less than the vertical blanking time. 0x0 Y N W Bits 12:11 Frame Delay Delay of the flash pulse measured in frames. 0x0 N N W Bit 10 End of Reset 0: In Xenon mode, the flash should be enabled after the readout of a frame. 1: In Xenon mode, the flash should be triggered after the resetting of a frame. 0x1 N N W Table 12: Sensor Core Register Descriptions (continued) BIT FIELD DESCRIPTION DEFAULT (HEX) SYNC’D TO FRAME START BAD FRAME READ/ WRITE

SOC VGA DIGITAL IMAGE SENSOR PRELIMINARY 09005aef8154a39d/09005aef8175e6cc Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9V112_2.fm- Rev. A 1/05 EN 41 ©2004 Micron Technology, Inc. All rights reserved. Bit 9 Every Frame 0: Flash should be enabled for one frame only. 1: Flash should be enabled every frame. 0x1 N N W Bit 8 LED Flash Enables LED flash. When set, the FLASH_STROBE goes on prior to the start of a frame reset. When disabled, the FLASH_STROBE remains HIGH until readout of the current frame completes. 0x0 Y Y W Bits 7:0 Xenon Count Length of FLASH_STROBE pulse when Xenon flash is enabled. The value specifies the length in 1,024 master clock cycle increments. 0x08 N N W R43:0—0x02B – Green1 Gain Bits 11:9 Digital Gain Total gain = (Bit 9 + 1) x (Bit 10 + 1) (Bit 11 + 1) x analog gain (each bit gives 2x gain). 0x0 Y N W Bits 8:7 Analog Gain Analog gain = (Bit 8 + 1) x (Bit 7 + 1) x initial gain (each bit gives 2x gain). 0x0 Y N W Bits 6:0 Initial Gain Initial gain = bits (6:0) x 0.03125. 0x20 Y N W R44:0—0x02C – Blue Gain Bits 11:9 Digital Gain Total gain = (Bit 9 + 1) x (Bit 10 + 1) (Bit 11 + 1) x analog gain (each bit gives 2x gain). 0x0 Y N W Bits 8:7 Analog Gain Analog gain = (Bit 8 + 1) x (Bit 7 + 1) x initial gain (each bit gives 2x gain). 0x0 Y N W Bits 6:0 Initial Gain Initial gain = bits (6:0) x 0.03125. 0x20 Y N W R45:0—0x02D – Red Gain Bits 11:9 Digital Gain Total gain = (Bit 9 + 1) x (Bit 10 + 1) x (Bit 11 + 1) x analog gain (each bit gives 2x gain). 0x0 Y N W Bits 8:7 Analog Gain Analog gain = (Bit 8 + 1) x (Bit 7 + 1) x initial gain (each bit gives 2x gain). 0x0 Y N W Bits 6:0 Initial Gain Initial gain = bits (6:0) x 0.03125. 0x20 Y N W R46:0—0x02E – Green2 Gain Bits 11:9 Digital Gain Total gain = (Bit 9 + 1) x (Bit 10 + 1) x (Bit 11 + 1) x analog gain (each bit gives 2x gain). 0x0 Y N W Bits 8:7 Analog Gain Analog gain = (Bit 8 + 1) x (Bit 7 + 1) x initial gain (each bit gives 2x gain). 0x0 Y N W Bits 6:0 Initial Gain Initial gain = bits (6:0) x 0.03125. 0x20 Y N W R47:0—0x02F – Global Gain Bits 11:0 Global Gain This register can be used to set all four gains at once. When read, it returns the value stored in Reg0x2B. 0x20 Y N W R200:0—0x0C8 – Context Control Bit 15 Restart Setting this bit causes the sensor to abandon the current frame and start resetting the first row. Same physical register as Reg0x00D, bit 1. 0x0 N YM W Table 12: Sensor Core Register Descriptions (continued) BIT FIELD DESCRIPTION DEFAULT (HEX) SYNC’D TO FRAME START BAD FRAME READ/ WRITE

SOC VGA DIGITAL IMAGE SENSOR PRELIMINARY 09005aef8154a39d/09005aef8175e6cc Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9V112_2.fm- Rev. A 1/05 EN 42 ©2004 Micron Technology, Inc. All rights reserved. Bit 7 Xenon Flash Enable Enable Xenon flash. Same physical register as Reg0x023, bit 13. 0x0 Y N W Bit 3 Read Mode Select 0: Use READ mode, context A, Reg0x021. 1: Use READ mode, context B, Reg0x020. Note that bits found only in the READ mode context B register is always taken from that register. 0x1 Y YM W Bit 2 LED Flash Enable Enable LED flash. Same physical register as Reg0x023, bit 8. 0x0 Y Y W Bit 1 Vertical Blanking Select 0: Use vertical blanking, context A, Reg0x008. 1: Use vertical blanking, context B, Reg0x006. 0x1 Y YM W Bit 0 Horizontal Blanking Select 0: Use horizontal blanking, context A, Reg0x007. 1: Use horizontal blanking, context B, Reg0x005. 0x1 Y YM W R240:0—0x0F0 – Page Map Bits 2:0 Page Map Page mapping register. Must be kept at 0 to be able to WRITE to/READ from sensor. Used in the SOC to access other pages with registers. 0x0 N 0 W R241:0—0x0F1 – Byte-Wise Address Bit 0 Byte-Wise Address Special address to perform 8-bit (instead of 16-bit) READs and WRITEs to the sensor. For additional information, see “Two- Wire Serial Interface Sample” on page 54 and “Appendix A” on page 52. N/A 0 0 0 R255:0—0x000 – Chip Version (R/O) Bits 15:0 Hardwired READ only. 0x1229 R Table 12: Sensor Core Register Descriptions (continued) BIT FIELD DESCRIPTION DEFAULT (HEX) SYNC’D TO FRAME START BAD FRAME READ/ WRITE

SOC VGA DIGITAL IMAGE SENSOR PRELIMINARY 09005aef8154a39d/09005aef8175e6cc Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9V112_2.fm- Rev. A 1/05 EN 43 ©2004 Micron Technology, Inc. All rights reserved. NOTE: Notation used in the above table: Sync’d to frame start 0 = Not applicable, e.g., read-only register. N = The register value is updated and used immediately. Y = The register value is updated at next frame start as long as the synchronize-changes bit is 0. Note also that frame start is defined as when the first dark row is read out. By default, this is eight rows before FRAME_VALID goes HIGH. Bad frame A bad frame is a frame where all rows do not have the same integration time, or offsets to the pixel values changed during the frame. 0 = Not applicable, e.g., read-only register. N = Changing the register value does not produce a bad frame. Y = Changing the register value might produce a bad frame. YM = Yes, but the bad frame is masked out unless the show-bad-frames feature is enabled. Read / Write R = read-only register/bit. W = read / write register/bit.

SOC VGA DIGITAL IMAGE SENSOR PRELIMINARY 09005aef8154a39d/09005aef8175e6cc Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9V112_2.fm- Rev. A 1/05 EN 44 ©2004 Micron Technology, Inc. All rights reserved. Modes and Timing This section provides an overview of typical usage modes for the MT9V112. Contexts The MT9V112 supports hardware-accelerated con- text switching. A number of parameters have two cop- ies of their setup registers; this allows two “contexts” to be loaded at any given time. These are referred to as context A and context B. Context selection for any sin- gle parameter is determined by the global context con- trol register (GCCR, see R200:2). There are copies of this register in each address page. A WRITE to any one of them has the identical effect. However, a READ from address page 0 only returns the subset bits of R200 that are specific to the sensor core. Contexts are generically named because they can be utilized for a variety of purposes. One typical usage model is to define context A as viewfinder or preview mode and context B as snapshot mode. The device defaults are configured with this in mind. This mecha- nism enables the user to have settings for viewfinder and snapshot modes loaded at the same time, and then switch between them with a single WRITE to a register (e.g., R200:2). Viewfinder/Preview and Full- Resolution/Snapshot Modes No context switching is necessary in the sensor core because this is a single ADC device. Context switching occurs in the colorpipe stage. Preview Mode QVGA (320 x 240) images are generated at up to 30 fps. The reduced-size images are generated by a scaling down operation. The sensor always outputs a VGA size image to the colorpipe in both context A and context B. Snapshot Mode VGA (640 x 480) images are generated at up to 30 fps. T h i s i s t y p i c a l l y s e l e c t e d b y s e t t i n g R 2 0 0 : n [ 1 0 ] = 1 selecting resize/zoom context B. Switching Modes Typically, switching to snapshot mode is achieved by writing R200:2 = 0x9F0B. This restarts the sensor and sets most contexts to context B. Following this WRITE, a READ from R200:1 or R200:2 results in 0x1F0B being read. Note that the MSB is cleared auto- matically by the sensor. A READ from R200:0 results in 0x000B, as only the lower 4 bits and the restart MSB are implemented in the sensor core. Clocks The sensor core is a master in the system. The sen- sor core frame rate defines the overall image flow pipe- line frame rate. Horizontal blanking and vertical blanking are influenced by the sensor configuration, and are also a function of certain image flow pipeline functions—particularly resize. The relationship of the primary clocks are depicted in Figure 9. The image flow pipeline typically generates up to 16-bits per pixel—for exam ple, YCbCr or RGB565—but has only an 8-bit port through which to communicate this pixel data. There is no phase-locked loop (PLL), so the primary input clock (CLKIN) must be twice the fundamental pixel rate (def ined by the sensor pixel clock). T o g e n e r a t e V G A i m a g e s a t 3 0 f p s , t h e s e n s o r c o r e r e q u i r e s a c l o c k i n t h e 2 4 M H z – 2 7 M H z r a n g e . T h e device defaults assume a 24 MHz clock, and minimum clock frequency is 2 MHz. Figure 9: Primary Sensor Core Clock Relationships 10 bits/pixel 1 pixel/clock 16 bits/pixel 1 pixel/clock 16 bits/pixel (typical) 0.5 pixel/clock Sensor Core Colorpipe Output Interface Sensor Pixel Clock Sensor Master ClockCLKIN

SOC VGA DIGITAL IMAGE SENSOR PRELIMINARY 09005aef8154a39d/09005aef8175e6cc Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9V112_2.fm- Rev. A 1/05 EN 45 ©2004 Micron Technology, Inc. All rights reserved. Turning Frame Rates Actual frame rates can be tuned by adjusting various sensor parameters. The sensor registers are in address page 0, some of which are shown in Table 13. Default Blanking Calculations The MT9V112 default blan king calculations are shown in Table 14. In the MT9V112, the sensor core adds four border pixels all the way around th e image, taking the active image size to 648 x 488 in full power mode. This is achieved through the default settings:  oversize and show border bits are set by default  oversize and show border bits are not context switchable, and therefore, their location is only in read mode context B. User Blanking Calculations When calculating blanking for different clock rates, minimum values for horizontal blanking and vertical blanking must be taken into account. Table 15 shows minimum values for each register. Table 13: Register Address Functions REGISTER FUNCTION R0x04:0 Column width, typically 640 in the MT9V112 R0x03:0 Row width, typically 480 in the MT9V112 R0x07:0, R0x05:0 Horizontal blanking, default is 203 (units of sensor pixel clocks) R0x08:0, R0x06:0 Vertical blanking, default is 11 (rows including black rows) Table 14: Blanking Pa rameter Calculations PARAMETER CALCULATION PC_PERIOD Sensor Pixel Clock Period (2/24)µs = 0.083µs A: Active Data Time (per line): R0 x 04:0 + 8 (border) * PC_PERIOD 648 x (2/24) = 53.784µs Q: Horizontal Blanking: [R0 x 05:0 | R0 x 07:0] * PC_PERIOD 154 x (2/24) = 12.782µs Row Time = Q + A 66.566µs P: Frame Start / End Blanking: 6 * PC_PERIOD 6 x (2/24) = 0.5µs V: Vertical Blanking: [R0 x 06:0 | R0 x 08:0] * (Q + A) + (Q - 2 * P) ( 11 x 66.566) + (12.782 - 1.0) = 744µs F: Total Frame Time: (R0 x 03:0 + [R0 x 06:0 | R00 x 08:0]) * (Q + A) (488 + 11) x 66.566µs = 33216.434µs ≥30 fps Table 15: User Blanking Minimum Values PARAMETER MINIMUM Horizontal Blanking 132 (sensor pixel clocks) Vertical Blanking 6 + Reg0x22:0[2:0] rows

SOC VGA DIGITAL IMAGE SENSOR PRELIMINARY 09005aef8154a39d/09005aef8175e6cc Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9V112_2.fm- Rev. A 1/05 EN 46 ©2004 Micron Technology, Inc. All rights reserved. Output Timing Figure 10: Vertical Timing Figure 11: Horizontal Timing Typical Resolutions, Modes, and Timing The parameters listed in Table 16 are illustrated in a waveform diagram, Figure 10. Table 21 on page 50 provides values for these parameters in some common resolutions and operating modes. Line 0 Line 1 LineN-3 LineN-2 LineN-1 Line 0 FRAME_VALID LINE_VALID D[7:0] EF DBCA NO DATA

10 FF 00 00 80 CB0 Y0 CR1 Y1 CB3 Y3 CRn

-1 Yn FF 00 00 90 PIXCLK LINE_VALID D[7:0] 10 Table 16: Blanking Definitions DESIGNATION DEFINITION (A) FRAME_VALID (rising edge) to LINE_VALID (rising edge) delay (B) LINE_VALID (falling edge) to FRAME_VALID (falling edge) delay (C) LINE_VALID (HIGH/valid) time (D) LINE_VALID (LOW/horizontal blanking) time (E) FRAME_VALID (HIGH/valid) time (F) FRAME_VALID (LOW/vertical blanking) time

SOC VGA DIGITAL IMAGE SENSOR PRELIMINARY 09005aef8154a39d/09005aef8175e6cc Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9V112_2.fm- Rev. A 1/05 EN 47 ©2004 Micron Technology, Inc. All rights reserved. Reset, Clocks, and Standby Reset Power-up reset is asserted/de-asserted on RESET#. It is active LOW . In this reset state, all control registers have the default values. Soft reset is asserted/de- asserted by the two-wire serial interface program. In soft-reset mode, the two- wire serial interface and register ring bus are still run- ning. All control registers are reset using default values. See R13:0. Clocks The MT9V112 has two pr imary clocks; a master clock coming from the CLKIN signal, and a pixel clock via a clock-gated operation running at half frequency of the master clock. All device clocks are turned off in power-down mode. When the MT9V112 operates in sensor stand-alone mode, the image flow pipeline clocks can be shut off to conserve power. See R13:0 on page 38. When the MT9V112 is operated with the MT9M111 in a dual-camera application, the MT9V112 employs a divide-by-two clock option, allowing a 54 MHz input to the master clock. For more information about this fea- ture, see the R13:0 register description on page 38 in Table 12. Standby STANDBY is a multifunctional signal that controls power-down, device addressing, and tri-state func- tions. Table 17 shows how STANDBY affects the out- put signal state. Hard standby is asserted/de-asserted on STANDBY. It is active HIGH. In this hard standby state, all internal clocks are turned off and the analog block is in standby mode to save power consumption. The signal state is High-Z when R13[4] = 0 and R13[6] = 0. Two-wire interface ID addressing is based on the result of S ADDR XOR R13:0[10]. (The R13:0[10] default is “0” .) The R13:0[10] bit is not writable when STANDBY is asserted “1.” Soft standby is asserted/d e-asserted by a two-wire serial interface to R13:0[2]. In soft standby, all internal clocks are turned off, the analog block is in standby mode, but the signal state is not affected. Following the assertion of either hard or soft standby, the analog cir- cuitry completes reading the current row and then enters the standby state. It is necessary to keep clock- ing the sensor for an entire row time to ensure proper entry into the standby state. Table 17: STANDBY Effect on the Output State DRIVE SIGNAL R13:0[6] OUTPUT DISABLE R13:0[4] STANDBY OUTPUT STATE 0 0 0 Driven 00 1 H i g h - Z 1 0 x Driven x1 x H i g h - Z

SOC VGA DIGITAL IMAGE SENSOR PRELIMINARY 09005aef8154a39d/09005aef8175e6cc Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9V112_2.fm- Rev. A 1/05 EN 48 ©2004 Micron Technology, Inc. All rights reserved. Electrical Specifications NOTE: VDD, VAA, and VAAPIX must all be at the same potential to avoid excessive current draw. Care must be taken to avoid excessive noise injection in the analog supplies if all three supplies are tied together. Table 18: Electrical Characte ristics and Operating Conditions TA = Ambient = 25°C PARAMETER CONDITION MIN TYP MAX UNIT I/O Digital Voltage (VDDQ) N/A 1.7 3.6 V Analog Voltage (VAA) N/A 2.5 2.8 3.1 V Pixel Supply Voltage (VAAPIX) 2.5 2.8 3.1 V Leakage Current STANDBY, no clocks 10 µA Operating Temperature Measured at junction -30 +70 °C

SOC VGA DIGITAL IMAGE SENSOR PRELIMINARY 09005aef8154a39d/09005aef8175e6cc Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9V112_2.fm- Rev. A 1/05 EN 49 ©2004 Micron Technology, Inc. All rights reserved. Power Consumption Table 19: I/O Parameters SIGNAL PARAMETER DEFINITIONS CONDITION MIN TYP MAX UNIT All Outputs Load capacitance TBD TBD pF Output signal slew 2.8V, 30pF load TBD 0.72 TBD V/ns 2.8V, 5pF load TBD 1.25 TBD V/ns 1.8V, 30pF load TBD 0.34 TBD V/ns 1.8V, 5pF load TBD 0.51 TBD V/ns VOH Output high voltage TBD TBD V VOL Output low voltage TBD TBD V IOH Output high current V DDQ = 2.8V, VOH = 2.4V TBD TBD mA VDDQ = 1.8V, VOH = 1.4V TBD TBD mA IOL Output low current V DDQ = 2.8V, VOL = 0.4V TBD TBD mA VDDQ = 1.8V, VOL = 0.4V TBD TBD mA IOZ Tri-state output leakage current TBD TBD All Inputs VIH Input high voltage V DDQ = 2.8V TBD TBD V VDDQ = 1.8V TBD TBD V VIL Input low voltage V DDQ = 2.8V TBD TBD V VDDQ = 1.8V TBD TBD V IIN Input leakage current TBD TBD Signal CAP Input signal capacitance TBD TBD pF CLKIN freq Master clock frequency Absolute minimum 2 MHz VGA at 30 fps 24 27 MHz Table 20: Power Consumption MODE SENSOR/mW IMAGE-FLOW PROC/mW I/OS (10pF)/mW TOTAL M/mW VGA at 15 fps 54 18 4 76

SOC VGA DIGITAL IMAGE SENSOR PRELIMINARY 09005aef8154a39d/09005aef8175e6cc Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9V112_2.fm- Rev. A 1/05 EN 50 ©2004 Micron Technology, Inc. All rights reserved. I/O Timing By default, the MT9V112 launches pixel data, FRAME_VALID, and LINE_VALID synchronously with the falling edge of PIXCLK. The expectation is that the user captures data, FRAME_VALID, and LINE_VALID using the rising edge of PIXCLK. The timing diagram is shown in Figure 12. As an option, the polarity of the P I X C L K c a n b e i n v e r t e d f r o m t h e d e f a u l t . T h i s i s achieved by programming R58:1[9] or R155:1[9] to “0.” Figure 12: I/O Timing Table 21: I/O Timing SIGNAL PARAMETER CONDITIONS SLOW FAST UNITMIN MAX MIN MAX CLKIN Tclkin_min_high TBD TBD TBD TBD ns Tclkin_min_low TBD TBD TBD TBD ns Tclkin_min_period TBD TBD TBD TBD ns PIXCLK Tclkinr_pixclkf TBD TBD TBD TBD ns Tclkinf_pixclkfr TBD TBD TBD TBD ns Tpixclk_min_low 50:50, 27 MHz CLKIN TBD TBD TBD TBD ns Tpixclk_min_high 50:50, 27 MHz CLKIN TBD TBD TBD TBD ns DATA[7:0] Tclkinr_dout TBD TBD TBD TBD ns Tdout_su 50:50, 27 MHz CLKIN TBD TBD TBD TBD ns Tdout_ho 50:50, 27 MHz CLKIN TBD TBD TBD TBD ns FRAME_VALID/ LINE_VALID Tclkinr_fvlv TBD TBD TBD TBD ns Tfvlv_su 50:50, 27 MHz CLKIN TBD TBD TBD TBD ns Tfvlv_ho 50:50, 27 MHz CLKIN TBD TBD TBD TBD ns Tclkinf_pixclkr Tdout_su Tdout_ho CLKIN PIXCLK DATA[7:0] FRAME_VALID LINE_VALID Tpixclk_min_lowTpixclk_min_high Tclkin_min_high Tfvlv_su Tfvlv_ho Tclkinr_pixclkf Tclkinr_dout Tclkinr_fvlv Tclkin_min_low Tclkin_min_period UNDEFINED

SOC VGA DIGITAL IMAGE SENSOR PRELIMINARY 09005aef8154a39d/09005aef8175e6cc Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9V112_2.fm- Rev. A 1/05 EN 52 ©2004 Micron Technology, Inc. All rights reserved. Appendix A Serial Bus Description Registers are written to and read from the MT9V112 through the two-wire serial interface bus. The sensor is a serial interface slave cont rolled by the serial clock (SCLK), which is driven by the serial interface master. Data is transferred in and out of the MT9V112 through the serial data (S DATA) line. The SDATA line is pulled up to VDDQ off-chip by a 1.5KΩ resistor. Either the slave or the master device can pull the S DATA line down—the serial interface protocol determines which device is allowed to pull the S DATA line down at any given time. Protocol The two-wire serial interf ace defines several differ- ent transmission codes, as follows: a s t a r t b i t  a(an) (no) acknowledge bit  an 8-bit message a s t o p b i t  the slave device 8-bit address S ADDR and R13:0[10] are used to select between two different addresses in case of conflict with another device. If S ADDR XOR R13:0[10] is LOW, the slave address is 0x90; if S ADDR XOR R13:0[10] is HIGH, the slave address is 0xBA. See Table 22. Sequence A typical read or write sequence begins with the master sending a start bit. After the start bit, the mas- ter sends the 8-bit slave device address. The last bit of the address determines if the request is a READ or a WRITE, where a “0” indicates a WRITE and a “1” indi- cates a READ. The slave device acknowledges its address by sending an acknowledge bit back to the master. If the request was a write, the master transfers the 8- bit register address for where a write should take place. The slave sends an acknowledge bit to indicate that the register address has been received. The master then transfers the data, 8 bits at a time, with the slave send- ing an acknowledge bit after each eight bits. The MT9V112 uses 16-bit da ta for its internal regis- ters, thus requiring two 8-bit transfers to write to one register. After 16 bits are transferred, the register address is automatically incremented, so that the next 16 bits are written to the next register address. The master stops writing by sending a start or stop bit. A typical read sequence is executed as follows. The master sends the write mode slave address and 8-bit register address, just as in the write request. The mas- ter then sends a start bit and the read mode slave address. The master clocks out the register data, eight bits at a time, and sends an acknowledge bit after each 8-bit transfer. The register address is auto-incre- mented after every 16 bits is transferred. The data transfer is stopped when the master sends a no- acknowledge bit. Bus Idle State The bus is idle when both the data and clock lines are HIGH. Control of the bus is initiated with a start bit, and the bus is released with a stop bit. Only the master can generate the start and stop bits. Start Bit The start bit is defined as a HIGH-to-LOW transition of the data line while the clock line is HIGH. Stop Bit The stop bit is defined as a LOW-to-HIGH transition of the data line while the clock line is HIGH. Slave Address The 8-bit address of a two-wire serial interface device consists of 7 bits of address and 1 bit of direction. A “0” in the LSB of the address indicates write mode, and a “1” indicates read mode. The write address of the sen- sor is 0xBA; the read address is 0xBB. This applies only when the S ADDR is set HIGH. Data Bit Transfer One data bit is transferred during each clock pulse. The serial interface clock pulse is provided by the mas- ter. The data must be stable during the HIGH period of the two-wire serial interface clock—it can only change when the serial clock is LOW . Data is transferred 8 bits at a time, followed by an acknowledge bit. Table 22: Two-Wire Interface ID Address Switching SADDR R13:0[10] TWO-WIRE INTERFACE ADDRESS ID 0 0 0x90 01 0 x B A 10 0 x B A 1 1 0x90

SOC VGA DIGITAL IMAGE SENSOR PRELIMINARY 09005aef8154a39d/09005aef8175e6cc Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9V112_2.fm- Rev. A 1/05 EN 53 ©2004 Micron Technology, Inc. All rights reserved. Acknowledge Bit The master generates the acknowledge clock pulse. The transmitter (which is the master when writing, or the slave when reading) releases the data line, and the receiver signals an acknowledge bit by pulling the data line LOW during the acknowledge clock pulse. No-Acknowledge Bit The no-acknowledge bit is generated when the data line is not pulled down by the receiver during the acknowledge clock pulse. A no-acknowledge bit is used to terminate a read sequence.

SOC VGA DIGITAL IMAGE SENSOR PRELIMINARY 09005aef8154a39d/09005aef8175e6cc Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9V112_2.fm - Rev. A 1/05 EN 57 ©2004 Micron Technology, Inc. All rights reserved. 8000 S. Federal Way, P .O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992 Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. Figure 25: 36-Ball ICSP Package NOTE: All dimensions in millimeters. Data Sheet Designation Preliminary This data sheet contains initial characterization li mits that are subject to change upon full charac- terization of production devices. SEATING PLANE 5.80 ±0.075 2.90 ±0.051.875 2.90 ±0.05 ENCAPSULANT: EPOXY IMAGE SENSOR DIE LID MATERIAL: BOROSILICATE GLASS 0.40 THICKNESS OPTICAL AREA OPTICAL CENTER PACKAGE CENTER 1.17 ±0.10 0.22 (FOR REFERENCE ONLY) 0.95 (FOR REFERENCE ONLY) 4.00 CTR

2.304 CTR

3.75 4.00 CTR 1.728 CTR 1.875

0.75 TYP

5.80 ±0.075 0.375 ±0.075 0.575 ±0.050 0.175 (FOR REFERENCE ONLY) C L C L 3.75 SUBSTRATE MATERIAL: PLASTIC LAMINATE SOLDER BALL MATERIAL: 62% Sn, 36% Pb, 2% Ag OR 96.5% Sn, 3% Ag, 0.5% Cu BALL PADS Ø 0.27 SOLDER MASK DEFINED 0.10 A B BALL A1 BALL A1 ID BALL A6 36X Ø0.35 DIMENSIONS APPLY TO SOLDER BALLS POST REFLOW. THE PRE-REFLOW DIAMETER IS Ø0.33 BALL A1 CORNER 2.714 ±0.075 0.186 (FOR REFERENCE ONLY) MAXIMUM ROTATION OF OPTICAL AREA RELATIVE TO PACKAGE EDGES: 1º MAXIMUM TILT OF OPTICAL AREA RELATIVE TO 0.3º. MAXIMUM TILT OF OPTICAL AREA RELATIVE TO TOP OF COVER GLASS: 0.3º. B PIXEL (0,0) 2.900 ±0.075

SOC VGA DIGITAL IMAGE SENSOR PRELIMINARY 09005aef8154a39d/09005aef8175e6cc Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9V112_2.fm- Rev. A 1/05 EN 58 ©2004 Micron Technology, Inc. All rights reserved.

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