MT9V011

MT9V011 MICRON | Alldatasheet

Document overview

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Technical content

Features

• DigitalClarity™ CMOS Imaging Technology  Ultra low-power, low cost CMOS image sensor  Superior low-light performance  Simple two-wire serial interface  Auto black level calibration  Window Size: VGA, programmable to any smaller format (QVGA, CIF)  Programmable Controls: Gain, frame rate, left-right and up-down image reversal, window size and panning

Applications

 Cellular phones P D A s P C C a m e r a s  T oys and other battery-powered products

Description

The Micron® Imaging MT9V011 is a VGA-format with a 1/4-inch CMOS active-pixel digital image sen- sor. The active imaging pixel array is 649H x 489V . It incorporates sophisticated camera functions on-chip such as windowing, column and row mirroring. It is programmable through a simple two-wire serial bus interface and has very low power consumption. The MT9V011 features DigitalClarity, our break- through, low-noise CMOS imaging technology that achieves CCD image quality (based on signal-to-noise ratio and low-light sensitivity) while maintaining the inherent size, cost and integration advantages of CMOS. Table 1: Key Performance Parameters The sensor can be operated in its default mode or programmed by the user for frame size, exposure, gain setting, and other parameters. The default mode out- puts a VGA-size image at 30 frames per second (fps). An on-chip analog-to-digital converter (ADC) provides 10 bits per pixel. FRAME_VALID and LINE_VALID sig- nals are output on dedicated pins, along with a pixel clock which is synchronous with valid data. PARAMETER TYPICAL VALUE Optical Format 1/4-inch (4:3) Active Imager Size 3.58mm(H) x 2.688mm (V), 8.4mm Diagonal Active Pixels 640H x 480V Pixel Size 5.6um x 5.6um Color Filter Array RGB Bayer Pattern Shutter Type Electronic Rolling Shutter (ERS) Max. Data Rate/Master Clock 13.5 MPS/27 MHz Frame Rate VGA (640x480) 30 fps at 27 MHz CIF (352x288) Programmable up to 60 fps QVGA (320x240) Programmable up to 90 fps ADC Resolution 10-bit, on-chip Responsivity 1.9 V/lux-sec (550nm) Dynamic Range 60dB SNRMAX 45dB Supply Voltage 2.8V ±0.25V Power Consumption 70mW at 2.8V, 20pF load,

27 MHz, 30 fps

Operating Temperature -20°C to +60°C Packaging 28-Pin PLCC

1/4-INCH VGA CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR Preliminary 09005aef80c6407f Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9V011TOC.fm - Rev. A 8/04 EN 2 ©2004 Micron Technology, Inc. Table of Contents

1/4-INCH VGA CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR Preliminary 09005aef80c6407f Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9V011LOT.fm - Rev. A 8/04 EN 4 ©2004 Micron Technology, Inc. List of Tables

1/4-INCH VGA CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR Preliminary 09005aef80c6407f Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9V011_external_DS_2.fm - Rev. A 8/04 EN 6 ©2004 Micron Technology, Inc. Figure 3: Pin Out Diagram - 28-Pin PLCC CLK_IN DOUT0 DOUT1 VDD DGND DOUT2 DOUT3 VAA AGND VAAPIX SCAN_EN RESET_BAR STANDBY NC 11 10 9 8 7 6 5 PIXCLK FRAME_VALID LINE_VALID SCLK SDATA NC AGND 19 20 21 22 23 24 25 DOUT4 DOUT5 DOUT6 DOUT7 DOUT8 DOUT9 OE_BAR Table 2: Pin Descriptions PIN NUMBER NAME TYPE DESCRIPTION 12 V AA Power Analog Power (2.8V). 14 VAAPIX Power Pixel Power (2.8V). 1V DD Power Digital Power Supply (2.8V). 28 D GND Ground Digital Ground. 11,13 A GND Ground Analog Ground. 4 CLK_IN Input Master Clock into sensor (27 MHz maximum). 19 OE_BAR Input Output_Enable_Bar pin. When HIGH: disables the pixel data output drivers. 16 RESET_BAR Input Asynchronous reset of sensor when LOW. All registers assume factory defaults. 15 SCAN_EN Input Tie to Digital Ground. 8 SCLK Input Serial Clock. 17 STANDBY Input When HIGH: disables the imager. 9 SDATA Bi-directional Serial Data I/O. 3D OUT0 Output Pixel Data Output Bit 0, D0 (LSB). 2D OUT1 Output Pixel Data Output Bit 1, D1. 27 D OUT2 Output Pixel Data Output Bit 2, D2. 26 D OUT3 Output Pixel Data Output Bit 3, D3. 25 D OUT4 Output Pixel Data Output Bit 4, D4. 24 D OUT5 Output Pixel Data Output Bit 5, D5. 23 D OUT6 Output Pixel Data Output Bit 6, D6.

1/4-INCH VGA CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR Preliminary 09005aef80c6407f Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9V011_external_DS_2.fm - Rev. A 8/04 EN 7 ©2004 Micron Technology, Inc. 22 D OUT7 Output Pixel Data Output Bit 7, D7. 21 D OUT8 Output Pixel Data Output Bit 8, D8. 20 D OUT9 Output Pixel Data Output Bit 9, D9 (MSB). 6 FRAME_VALID Output Active HIGH during frame of valid pixel data.

7 LINE_VALID Output Active HIGH during line of selectable valid pixel data (see Reg0x20 for

options). 5 PIXCLK Output Pixel Clock Output. Pixel data outputs are valid during rising edge of this clock. Frequency = 1/2 (master clock). 10 NC - No connect. 18 NC - No connect. Table 2: Pin Descriptions (continued) PIN NUMBER NAME TYPE DESCRIPTION

1/4-INCH VGA CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR Preliminary 09005aef80c6407f Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9V011_external_DS_2.fm - Rev. A 8/04 EN 10 ©2004 Micron Technology, Inc. Frame Timing Formulas The constant 113 in the formulas in Table 3 is the constant value in default mode, when 8 dark columns are read out through Reg0x30. The constant follows the dark columns read out as shown in Table 4. Sensor timing is shown above in terms of pixel clock and master clock cycles (please refer to Figure 7). The recommended master clock frequency is 27 MHz. Table 4: Constant Value The vertical blanking and total frame time equa- tions assume that the number of integration rows (bits 11 through 0 of Reg0x09) is less than the number of active plus blanking rows (Reg0x03 + 1 + Reg0x06 + 1). If this is not the case, the number of integration rows must be used instead to determine the frame time, as shown in Table 5. Table 3: Frame Time PARAMETER NAME EQUATION DEFAULT TIMING AT 27 MHZ A Active Data Time (Reg0x04 + 1) x (Reg0x0A + 2) 640 pixel clocks = 1280 master = 47.4µs P Frame Start/End Blanking 6 x (Reg0x0A + 2) 6 pixel clocks = 12 master = 0.44µs Q Horizontal Blanking (113 + Reg0x05) x (Reg0x0A + 2) (minimum Reg0x05 value = 9) 244 pixel clocks = 488 master = 18.07µs A+Q Row Time (Reg0x04 + 1 + 113 + Reg0x05) x (Reg0x0A + 2) 884 pixel clocks = 1,768 master = 65.48µs V Vertical Blanking (Reg0x06 + 1) x (A + Q) + (Q - 2 x P) 25,868 pixel clocks = 51,736 master = 1.92ms N rows x (A + Q) Frame Valid Time (Reg0x03 + 1) x (A + Q) - (Q - 2 x P) 424,088 pixel clocks = 848,176 master = 31.41ms F Total Frame Time (Reg0x03 + 1 + Reg0x06 + 1) x (A + Q) 449,956 pixel clocks = 899,912 master = 33.33ms REG 0X30, BIT 1:0 CONSTANT 1x 121 For 16 columns 01 113 For 8 columns 00 107 For no dark columns read, no row-wise noise correction applied Table 5: Frame Time - Master Clock PARAMETER NAME EQUATION (MASTER CLOCK) DEFAULT TIMING V’ Vertical Blanking (long integration time) (Reg0x09 - Reg0x03) x (A + Q) + (Q - 2 x P) 25,868 pixel clocks = 51,736 master = 1.92 ms F’ Total Frame Time (long integration time) (Reg0x09 + 1) x (A + Q) 449,956 pixel clocks = 899,912 master = 33.33ms

1/4-INCH VGA CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR Preliminary 09005aef80c6407f Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9V011_external_DS_2.fm - Rev. A 8/04 EN 11 ©2004 Micron Technology, Inc. Serial Bus Description Registers are written to and read from the MT9V011 through the two-wire serial interface bus. The sensor is a serial interface slave and is controlled by the serial clock (SCLK), which is driven by the serial interface master. Data is transferred into and out through the MT9V011 serial data (SDATA) line. The SDATA line is pulled up to V DD off-chip by a 1.5K Ω resistor. Either the slave or master device can pull the SDATA line down—the serial interface protocol determines which device is allowed to pull the SDATA line down at any given time. The registers are 16 bits wide, and can be accessed through 16- or eight-bit two-wire serial bus sequences. Protocol The two-wire serial interface defines several differ- ent transmission codes, as follows: a s t a r t b i t  the slave device eight-bit address  a(n) (no) acknowledge bit a n e i g h t - b i t m e s s a g e a s t o p b i t Sequence A typical read or write sequence begins by the mas- ter sending a start bit. After the start bit, the master sends the slave device’ s eight-bit address. The last bit of the address determines if the request will be a read or a write, where a “0” indicates a write and a “1” indi- cates a read. The slave device acknowledges its address by sending an acknowledge bit back to the master. If the request was a write, the master then transfers the eight-bit register address to which a write should take place. The slave sends an acknowledge bit to indi- cate that the register address has been received. The master then transfers the data eight bits at a time, with the slave sending an acknowledge bit after each eight bits. The MT9V011 uses 16-bit data for its internal reg- isters, thus requiring two eight-bit transfers to write to one register. After 16 bits are transferred, the register address is automatically incremented, so that the next 16 bits are written to the next register address. The master stops writing by sending a start or stop bit. A typical read sequence is executed as follows. First the master sends the write-mode slave address and eight-bit register address, just as in the write request. The master then sends a start bit and the read-mode slave address. The master then clocks out the register data eight bits at a time. The master sends an acknowl- edge bit after each eight-bit transfer. The register address is auto-incremented after every 16 bits is transferred. The data transfer is stopped when the master sends a no-acknowledge bit. The MT9V011 allows for eight-bit data transfers through the two-wire serial interface by writing (or reading) the most signifi- cant eight bits to the register and then writing (or read- ing) the least significant eight bits to Reg0x80 (128). Bus Idle State The bus is idle when both the data and clock lines are HIGH. Control of the bus is initiated with a start bit, and the bus is released with a stop bit. Only the master can generate the start and stop bits. Start Bit The start bit is defined as a HIGH-to-LOW transition of the data line while the clock line is HIGH. Stop Bit The stop bit is defined as a LOW-to-HIGH transition of the data line while the clock line is HIGH. Slave Address The eight-bit address of a two-wire serial interface device consists of seven bits of address and 1 bit of direction. A “0” in the LSB of the address indicates write mode, and a “1” indicates read mode. The write address of the sensor is 0xBA, while the read address is 0xBB. Data Bit Transfer One data bit is transferred during each clock pulse. The two-wire serial interface clock pulse is provided by the master. The data must be stable during the HIGH period of the serial clock—it can only change when the two-wire serial interface clock is LOW. Data is trans- ferred eight bits at a time, followed by an acknowledge bit. Acknowledge Bit The master generates the acknowledge clock pulse. The transmitter (which is the master when writing, or the slave when reading) releases the data line, and the receiver indicates an acknowledge bit by pulling the data line low during the acknowledge clock pulse.

1/4-INCH VGA CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR Preliminary 09005aef80c6407f Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9V011_external_DS_2.fm - Rev. A 8/04 EN 12 ©2004 Micron Technology, Inc. No-Acknowledge Bit The no-acknowledge bit is generated when the data line is not pulled down by the receiver during the acknowledge clock pulse. A no-acknowledge bit is used to terminate a read sequence.

1/4-INCH VGA CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR Preliminary 09005aef80c6407f Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9V011_external_DS_2.fm - Rev. A 8/04 EN 15 ©2004 Micron Technology, Inc. Registers Register Map Table 6: Register Map REGISTER # (HEX) DESCRIPTION DATA FORMAT (BINARY) DEFAULT VALUE (HEX) 0x00/0xFF Chip Version 1000 0010 0011 0010 0x8232 0x01 Row Start 0000 000d dddd dddd 0x000A 0x02 Column Start 0000 00dd dddd dddd 0x0016 0x03 Window Height 0000 000d dddd dddd 0x01DF 0x04 Window Width 0000 00dd dddd dddd 0x027F 0x05 Horizontal Blanking 0000 00dd dddd dddd 0x0083 0x06 Vertical Blanking 0000 dddd dddd dddd 0x001C 0x07 Output Control dddd dddd dddd dddd 0x3002 0x09 Shutter Width 0000 dddd dddd dddd 0x01FC 0x0A Pixel Clock Speed 0000 0000 000d dddd 0x0000 0x0B Restart 0000 0000 0000 000d 0x0000 0x0C Shutter Delay 0000 00dd dddd dddd 0x0000 0x0D Reset 0000 0000 0000 000d 0x0000 0x1E Digital Zoom 0000 0ddd 0000 00dd 0x0000 0x20 Read Mode dddd dddd dddd dddd 0x1000 0x21 Reserved - 0x0000 0x22 Reserved - 0x0000 0x27 Reserved - 0x0024 0x2B Green1 Gain 0000 0ddd dddd dddd 0x0020 0x2C Blue Gain 0000 0ddd dddd dddd 0x0020 0x2D Red Gain 0000 0ddd dddd dddd 0x0020 0x2E Green2 Gain 0000 0ddd dddd dddd 0x0020 0x2F Reserved -0 x F 7 B 0 0x30 Reserved - 0x0005 0x31 Reserved - 0x002A 0x32 Reserved - 0x0000 0x33 Reserved - 0x300F 0x34 Reserved - 0x0100 0x35 Global Gain 0000 0ddd dddd dddd 0x0020 0x3B Reserved N/A 0x3C Reserved - 0x0820 0x3D Reserved - 0x068F 0x3E Reserved N/A 0x3F Reserved - 0x06A0 0x40 Reserved - 0x01E0 0x41 Reserved - 0x00D1 0x42 Reserved - 0x0882 0x58 Reserved - 0x0078 0x59 Reserved - 0x0703 0x5A Reserved - 0x0427 0x5B Reserved R/O

1/4-INCH VGA CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR Preliminary 09005aef80c6407f Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9V011_external_DS_2.fm - Rev. A 8/04 EN 16 ©2004 Micron Technology, Inc. NOTE: 1 = always 1 0 = always 0 d = programmable ? = read only Do not change reserved register defaults; doing so may put device into an unknown state. 0x5C Reserved R/O 0x5D Reserved R/O 0x5E Reserved R/O 0x5F Reserved - 0xA31D 0x60 Reserved - 0x0000 0x61 Reserved - 0x0000 0x62 Reserved - 0x0418 0x63 Reserved - 0x0000 0x64 Reserved - 0x0000 0x65 Reserved - 0x0000 0xF1 Chip Enable 0000 0000 0000 00dd 0x0001 0xF7 Reserved R/O 0xF8 Reserved R/O 0xF9 Reserved - 0x002C 0xFA Reserved R/O 0xFB Reserved R/O 0xFC Reserved R/O 0xFD Reserved R/O Table 6: Register Map (continued) REGISTER # (HEX) DESCRIPTION DATA FORMAT (BINARY) DEFAULT VALUE (HEX)

1/4-INCH VGA CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR Preliminary 09005aef80c6407f Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9V011_external_DS_2.fm - Rev. A 8/04 EN 17 ©2004 Micron Technology, Inc. Register Descriptions Table 7: Register Description REGISTER BIT DESCRIPTION Chip Version 0x00 / 0xFF 0-15 This register is read-only and gives the chip identification number: 0x8232. Window Control These registers control the size of the window. 0x01 0-8 First row to be read out— default = 0x000A (10). Minimum recommended value = 0x0006. 0x02 0-9 First column to be read out— default = 0x0016 (22). Minimum recommended value = 0x0012 (18). 0x03 0-8 Window height (number of rows - 1)— default = 0x01DF (479). 0x04 0-9 Window width (number of columns - 1)— default = 0x027F (639). Minimum recommended value = 0x0009. Blanking Control These registers control the blanking time in a row and between frames. 0x05 0-9 Horizontal Blanking (number of columns)— default = 0x0083 (131 pixel clocks). Minimum value for 0x05 = 0x0009. Minimum recommended value for 0x05 = 0x007B (123 pixel clocks). 0x06 0-11 Vertical Blanking (number of rows -1)— default = 0x001C (28 rows). Minimum recommended value = 0x0003. Output Control This register controls various features of the output format for the sensor. 0x07 0 Synchronize changes (copied to Reg0xF1, bit1). 0 = normal operation, update changes to registers that affect image brightness (integration time, integration delay, gain, horizontal and vertical blanking, window size, row/column skip, or row mirror) at the next frame boundary. 1 = do not update any changes to these settings until this bit is returned to “0.” 1 Chip Enable (copied to Reg0xF1, bit0). 1 = normal operation. 0 = stop sensor readout. When this is returned to “1,” sensor readout restarts at the starting row in a new frame. The digital power consumption can then also be reduced to less than 5uA by turning off the master clock. 4 By setting this bit to “1,” the sampling and reset timing of the pixels will be halved. This bit should therefore only be used if the master clock frequency is 13.5 MHz or less. When this bit is set the minimum recommended horizontal blanking value is 17, compared to 123 when this bit is not set. Shutter Delay will be master clocks divided by 2 when this bit is set, compared to master clocks divided by 4 when this bit is 0. Note: Use this register for 15 fps with 12 MHz master clock. 5 Allow Shutter Width to be exactly one full frame. 0 = normal operation = Maximum Shutter Width equals the total number of rows - 1. If Shutter Width exceeds the number of rows -1, the total number of rows in the image will be increased to Shutter Width + 1. 1 = Maximum Shutter Width equals the total number of rows. When the Shutter Width exceeds the number of rows, the total number of rows in the image will be increased to match the Shutter Width. 6 Reserved. 8 -11 Shift pixel clock: (11,10,9,8) = (1, x, x, x): shift pixel clock 1 clock earlier (0, 1, x, x): shift pixel clock ½ clock earlier (0, 0, 1, x): delay pixel clock by ½ clock(0, 0, 0, 1): delay pixel clock by 1 clock (0, 0, 0, 0): no delay pixel clock (default mode).

15 Invert pixel clock:

0 = normal operation. 1 = invert pixel clock.

1/4-INCH VGA CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR Preliminary 09005aef80c6407f Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9V011_external_DS_2.fm - Rev. A 8/04 EN 18 ©2004 Micron Technology, Inc. Pixel Integration Control These registers (along with the Window Size and Blanking registers) control the integration time for the pixels. 0x09 0-11 Number of rows of integration, default = 0x01FC (508). 0x0C 0-9 Reset delay, default = 0x0000 (0). This is the number of master clocks x 4 that the timing and control logic waits before asserting the reset for a given row. Pixel Clock Speed 0x0A 4-0 This register determines the pixel data rate, default = 0x0000 (0). Pixel clock period = 2 master clocks + [Reg0x0A, bits (4-0)]. The pixel clock out can be shifted relative to the data out by setting bit 8-11 of Reg0x07 appropriately. Maximum value for 0x0A = 0x0015. Frame Restart 0x0B 0 Setting bit 0 to “1” of Reg0x0B will cause the sensor to abandon the readout of the current frame and restart from the first row. This register automatically resets itself to 0x0000 after the frame restart. The first frame after this event is considered to be a "bad frame" (see description for Reg0x20, bit 0). Reset (Soft) 0x0D 0 This register is used to reset the sensor to its default, power-up state. To reset the MT9V011, first write a “1” into bit 0 of this register to put the MT9V011 in reset mode, then write a “0” into bit 0 to resume operation. Zoom Mode / True Decimation Mode 0x1E 0 Zoom by 2. 1 Zoom by 4 (if bit 0 is 0). 8 True decimation by 2. Decimate 2x will skip every other column and row, without considering the colors of the pixels. 9 True decimation by 4. Decimate 4x will skip 3 rows/columns for every row/column read out, without considering the colors of the pixels. 10 True decimation by 8. Decimate 8x will skip 7 rows/columns for every row/column read out, without considering the colors of the pixels. Table 7: Register Description (continued) REGISTER BIT DESCRIPTION

1/4-INCH VGA CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR Preliminary 09005aef80c6407f Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9V011_external_DS_2.fm - Rev. A 8/04 EN 19 ©2004 Micron Technology, Inc. Read Mode This register is used to control many aspects of the readout of the sensor. 0x20 0 Show bad frames: 1 = output all frames (including bad frames). 0 = only output good frames. A bad frame is defined as the first frame following a change to: window size or position, horizontal blanking, pixel clock speed, zoom, row or column skip, or mirroring.

3 Column skip:

1= read out two columns, and then skip two columns (as with rows). 0 = normal readout.

4 Row skip:

1 = read out two rows, and then skip two rows (i.e. row 8, row 9, row 12, row 13…). 0 = normal readout. 9 "Continuous" Line Valid (continue producing line valid during vertical blanking). 0 = Normal Line Valid (default, no line valid during vertical blanking). 10 Line valid = "Continuous" Line Valid XOR Frame Valid. 0 = Normal Line Valid. Ineffective if Continuous Line Valid is set. 11 The four dark rows 0 to 3 are read out in addition to the valid data. 0 = normal readout. To preserve a right-reading image and the correct color order, all four of these bits should be set to “1” to invert the image. 5 1 = readout starting 1 column later. 0 = normal readout. 7 1 = readout starting 1 row later. 0 = normal readout. 14 1 = read out from right to left (mirrored). 0 = normal readout. 15 1 = read out from bottom to top (upside down). 0 = normal readout. Gain Settings The gain can be individually controlled for each color in the Bayer pattern. 0x2B Green1 Gain— default = 0x0020 (32) = 1x gain. 0-6 Initial Gain = bits (6:0) x 0.03125. 7, 8 Analog Gain = (Bit 8 + 1) x (Bit 7 + 1) x Initial Gain (each bit gives 2x gain). 9,10 9, 10: Total Gain = (Bit 9 + 1) x (Bit 10 + 1) x Analog Gain (each bit gives 2x gain). 0x2C Blue Gain— default = 0x0020 (32) = 1x gain. 0-6 Initial Gain = bits (6-0) x 0.03125. 7, 8 Analog gain = (Bit 8 + 1) x (Bit 7 + 1) x Initial Gain (each bit gives 2x gain). 9,10 9, 10: Total Gain = (Bit 9 + 1) x (Bit 10 + 1) x Analog Gain (each bit gives 2x gain). 0x2D Red gain— default = 0x0020 (32) = 1x gain. 0-6 Initial Gain = bits (6-0) x 0.03125. 7, 8 Analog Gain = (Bit 8 + 1) x (Bit 7 + 1) x Initial Gain (each bit gives 2x gain). 9,10 9, 10: Total Gain = (Bit 9 + 1) x (Bit 10 + 1) x Analog Gain (each bit gives 2x gain). 0x2E Green2 gain— default = 0x0020 (32) = 1x gain. 0-6 Initial Gain = bits (6-0) x 0.03125. 7, 8 Analog Gain = (Bit 8 + 1) x (Bit 7 + 1) x Initial Gain (each bit gives 2x gain). 9,10 9, 10: Total gain = (Bit 9 + 1) x (Bit 10 + 1) x Analog Gain (each bit gives 2x gain). Table 7: Register Description (continued) REGISTER BIT DESCRIPTION

1/4-INCH VGA CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR Preliminary 09005aef80c6407f Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9V011_external_DS_2.fm - Rev. A 8/04 EN 20 ©2004 Micron Technology, Inc. 0x35 GlobalGain— default = 0x0020 (32) = 1x gain. This register can be used to set all four gains at once. When read, it will return the value stored in Reg0x2B. 0-6 Initial Gain = bits (6-0) x 0.03125. 7, 8 Analog Gain = (Bit 8 + 1) x (Bit 7 + 1) x Initial Gain (each bit gives 2x gain). 9,10 9, 10: Total Gain = (Bit 9 + 1) x (Bit 10 + 1) x Analog Gain (each bit gives 2x gain). Table 7: Register Description (continued) REGISTER BIT DESCRIPTION

1/4-INCH VGA CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR Preliminary 09005aef80c6407f Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9V011_external_DS_2.fm - Rev. A 8/04 EN 21 ©2004 Micron Technology, Inc. Feature Description Window Control Reg0x01 Row Start, Reg0x02 Column Start, Reg0x03 Window Height (row size), and Reg0x04 Window Width (column size) These registers control the size and starting coordi- nates of the window. By changing these registers, any image format smaller than or equal to VGA can be specified. Blanking Control Reg0x05 Horizontal Blanking, and Reg0x06 Verti- cal Blanking Blanking Control: These registers control the blanking time in a row (called column fill-in or horizontal blanking) and between frames (vertical blanking).  Horizontal blanking is specified in terms of pixel clocks.  Vertical blanking is specified in terms of row readout times. (The programmed value is one less than the actual value.) The actual imager timing can be calculated using T able 3 on page 10 which describes "Row Timing and FRAME_VALID/LINE_VALID Signals.” The number of dark rows read out depends on the vertical blanking set as shown in the T able 8. Pixel Integration Control Reg0x09 Shutter Width, and Reg0x0C Shutter Delay These registers (along with the Window Size and horizontal blanking registers) control the integration time for the pixels. Reg0x09: number of rows of integration, default = 0x01FC (508) Reg0x0C: reset delay, default = 0x0000 (0). This is the number of master clocks that the timing and control logic waits before asserting the reset for a given row. The actual total integration time, tINT , is: tINT = Reg0x09 x Row Time - Overhead time - Reset delay, where: Row Time = (Reg0x04 + 1 + 113 + Reg0x05) x (Reg0x0A + 2) master clock periods Overhead time = K x 57 master clock periods Reset delay = K x Reg0x0C master clock periods If the value in Reg0x0C exceeds (row time - 444)/K master clock cycles, the row time will be extended by (K x Reg0x0C - (row time - 444)) clock cycles. Where : K = 4 when Reg0x07[4] = 0, and K = 2 when Reg0x07[4] = 1 In this expression the row time term corresponds to the number of rows integrated. The overhead time is the time between the READ cycle and the RESET cycle, and the final term is the effect of the reset delay. Typically, the value of Reg0x09 (Shutter Width) is limited to the number of rows per frame (which includes vertical blanking rows), such that the frame rate is not affected by the integration time. If Reg0x09 is increased beyond the total number of rows per frame, the MT9V011 will add additional blanking rows as needed. A second constraint is that tINT must be adjusted to avoid banding in the image from light flicker. Under 60 Hz flicker, this means tINT must be a multiple of 1/120 of a second. Under 50 Hz flicker, tINT must be a multiple of 1/100 of a second. Pixel Clock Speed Reg0x0A Pixel Clock Speed The pixel clock speed is set by Reg0x0A. The pixel clock period will be the number set plus two master clock cycles. The default value is 0, which is equal to 2 master clock cycles. With a master clock frequency of 27 MHz the PIXCLK frequency will be 13.5 MHz. The pixel clock out can be shifted relative to the data out by setting bit 8-11 of Reg0x07 appropriately. Reset Reg0x0D Reset This register is used to reset the sensor to its default, power-up state. To reset the MT9V011, first write a “1” into bit 0 of this register, then write a “0” into bit 0 to resume operation. Table 8: Vertical Blanking REG0X06 # DARK ROWS 1-2 2 3+ 4

1/4-INCH VGA CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR Preliminary 09005aef80c6407f Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9V011_external_DS_2.fm - Rev. A 8/04 EN 24 ©2004 Micron Technology, Inc. Recommdended Gain Settings The gains for green1, blue, red, and green2 pixels are set by registers Reg0x2B, Reg0x2C, Reg0x2D, and Reg0x2D, respectively. Gain can also be set globally by Reg0x35. The analog gain is set by bits[8:0] of the cor- responding register as following: Gain = (Bit[8] + 1) x (Bit[7] + 1) x (Bit[6:0]/32) Digital gain is set by bits 9 and 10 of the same regis- ters. The analog gain circuitry (pre-ADC) is designed to offer signal gains from 1 to 15.875. The minimum gain of 1 (register set to 0x0020) cor- responds to the lowest setting where the pixel signal is guaranteed to saturate the ADC under all specified operating conditions. Any reduction of the gain below this value may cause the sensor to saturate at ADC out- put values less than the maximum, under certain con- ditions. It is recommended that this guideline be followed at all times. Since bits 7 and 8 of the gain registers are multipli- cative factors for the gain settings, there are alternative w a y s o f a c h i e v i n g c e r t a i n g a i n s . S o m e s e t t i n g s o f f e r superior noise performance to others, while the same overall gain. Table 9 lists the recommended gain set- tings. Table 9: Recommended Gain Settings DESIRED GAIN RECOMMENDED SETTINGS (GAIN REGISTERS) CONVERSION FORMULA (ARITHMETIC) 1.000 to 1.969 0x0020 to 0x003F (Register value)/32 2.000 to 7.938 0x00A0 to 0x00FF (Register value - 128)/16 8.000 to 15.875 0x01C0 to 0x01FF (Register value - 384)/8

1/4-INCH VGA CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR Preliminary 09005aef80c6407f Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9V011_external_DS_2.fm - Rev. A 8/04 EN 25 ©2004 Micron Technology, Inc. Electrical Specifications NOTE: 1. To place the chip in standby mode, first raise STANDBY to VDD, then wait two master clock cycles before turning off the master clock. Two master clock cycles are required to place the analog circuitry into standby, low-power mode. Table 10: DC Electrical Characteristics (VPWR = 2.8 ±0.25V; TA = Ambient = 25°C; 30 fps at 27 MHz) SYMBOL DEFINITION CONDITION MIN TYP MAX UNIT NOTES VIH Input High Voltage VPWR-0.25 V PWR+0.25 V VIL Input Low Voltage -0.3 0.8 V IIN Input Leakage Current No Pull-up Resistor; VIN = VPWR or VGND -5 5 µA VOH Output High Voltage VPWR-0.2 V VOL Output Low Voltage 0.2 V IOH Output High Current 5.0 µA IOL Output Low Current 5.0 µA IOZ Tri-state Output Leakage Current 5.0 µA IAA Analog Operating Current CLK = 27 MHz; default setting, CLOAD = 10pF 14.0 20.0 28.0 mA IDD Digital Operating Current CLK = 27 MHz; default setting, CLOAD = 10pF 3.0 5.0 8.0 mA IAA Standby Analog Standby Supply Current STDBY = VDD 0.0 0.0 5.0 µA1 IDD Standby Digital Standby Supply Current STDBY = VDD 0.0 1.0 5.0 µA1

1/4-INCH VGA CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR Preliminary 09005aef80c6407f Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9V011_external_DS_2.fm - Rev. A 8/04 EN 26 ©2004 Micron Technology, Inc. NOTE: 1. For 30 fps operation with a 27 MHz clock, it is very important to have a precise duty cycle equal to 50%. With a slower frame rate and a slower clock the clock duty cycle can be relaxed. Table 11: AC Electrical Characteristics (VDD = 2.8 ±0.25V; TA = Ambient = 25°C) SYMBOL DEFINITION CONDITION MIN TYP MAX UNIT NOTES fCLK_IN Input Clock Frequency 27 27 MHz Clock Duty Cycle 45 50 55 % 1 tR Input Clock Rise Time 2.5 ns tF Input Clock Fall Time 2.0 ns tPLHP, tPHLP CLK_IN to PIXCLK propagation delay: LOW-TO-HIGH HIGH-TO-LOW CLOAD = 10pF 12.0 10.0 ns tDVSETUP tDVHOLD PIXCLK to DOUT<9:0> Setup Time Hold Time CLOAD = 10pF, 15.0 14.0 ns tOH Data Hold Time from CLK_IN 9.0 ns tPLHFL tPHLFL CLK_IN to FRAME_VALID and LINE_VALID propagation delay: LOW-TO-HIGH, HIGH-TO-LOW CLOAD = 10pF 12.0 11.0 ns tPLH tPHL Output propagation delay: LOW-TO-HIGH, HIGH-TO-LOW CLOAD = 10pF 7.5 7.0 ns tOUTR Output Rise Time CLOAD = 10pF 7.0 ns tOUTF Output Fall Time CLOAD = 10pF 9.0 ns

1/4-INCH VGA CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR Preliminary 09005aef80c6407f Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9V011_external_DS_2.fm - Rev. A 8/04 EN 28 ©2004 Micron Technology, Inc. Figure 21: Data Output Timing Diagram PIXCLK = max. 27 MHz tFVSETUP = / setup time for FRAME_VALID before rising edge of PIXCLK / = 18 ns tFVHOLD = / hold time for FRAME_VALID after falling edge of PIXCLK / = 18 ns tLVSETUP = / setup time for LINE_VALID before rising edge of PIXCLK / = 18 ns tLVHOLD = / hold time for LINE_VALID after falling edge of PIXCLK / = 18 ns tDSETUP = / setup time for DOUT before rising edge of PIXCLK / = 15 ns tDHOLD = / hold time for DOUT after falling edge of PIXCLK / = 14 ns tFTOL= / FRAME_VALID to LINE_VALID time / = 440 ns PIXCLK FRAME_VALID LINE_VALID DOUT(9:0) DSETUPt LVSETUP t t FVSETUP tFTOL DHOLDt LVHOLDt tFVHOLD toutR toutF

1/4-INCH VGA CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR Preliminary 09005aef80c6407f Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9V011_external_DS_2.fm - Rev. A 8/04 EN 30 ©2004 Micron Technology, Inc. Figure 28: Spectral Response 0.0 0.2 0.4 0.6 0.8 1.0 1.2 350 450 550 650 750 850 950 1050 Wavelength (nm) Relative Response Blue Green (B) Green (R) Red Relative Spectral Response

1/4-INCH VGA CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR Preliminary 09005aef80c6407f Micron Technology, Inc., reserves the right to change products or specifications without notice.. MT9V011_external_DS_2.fm - Rev. A 8/04 EN 32 ©2004 Micron Technology, Inc 8000 S. Federal Way, P .O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992 Micron, the M logo, and the Micron logo are trademarks and/or service marks of Micron Technology, Inc. All other trademarks are the property of their respective owners. Figure 31: 28-Pin PLCC Package Outline Drawing Data Sheet Designation Preliminary: This data sheet contains initial characterization limits that are subject to change upon full characterization of production devices. 2.35 ±0.15 SEATING PLANE SECTION A–A 0.08 0.70 ±0.05 128

1.27 TYP

A 7.62 LID MATERIAL: BOROSILICATE GLASS LEAD FINISH: GOLD PLATING,

20 MICRO INCHES MINIMUM

SUBSTRATE MATERIAL: FR4 RESIN 7.62 A 1.70 ±0.10 11.43 ±0.10

0.64 TYP

29X R0.225 27X 1.27 2.16 0.350 ±0.050 1.450 ±0.075 0.55 ±0.05 8X 1.905 ±0.100 11.43 ±0.10 0.08

1/4-INCH VGA CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR Preliminary 09005aef80c6407f Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9V011_external_DS_2.fm - Rev. A 8/04 EN 33 ©2004 Micron Technology, Inc.

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