MT9M011 MICRON | Alldatasheet
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Preliminary‡ PDF: 09005aef81051c04/Source: 09005aef8102abe8 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9M011_1.fm - Rev. D 1/05 EN 1 ©2004 Micron Technology, Inc. All rights reserved. ‡Products and specifications discussed herein are for evaluation and reference purposes only and are subject to change by Micron without notice. Products are only warranted by Micron to meet Micron’s production data sheet specifications. 1/3-Inch Megapixel CMOS Active-Pixel Digital Image Sensor MT9M011 For the latest data sheet revision, please refer to Micron’s Web site: www.micron.com/imaging
- DigitalClarity ™ CMOS Imaging Technology H i g h f r a m e r a t e Superior low-light performance L o w d a r k c u r r e n t Simple two-wire serial interface Auto black level calibration O p e r a t i n g M o d e s : Snapshot and flash control, high frame rate preview, electronic panning Programmable Controls: Gain, frame size/rate, exposure, left-right and top- bottom image reversal, window size, and panning
Applications
Cellular phones P D A s T o y s Other battery-powered products General Description The Micron® Imaging MT9M011 is an SXGA-format, 1/3-inch CMOS active-pixel digital image sensor with an active imaging pixel array of 1,280H x 1,024V . It incorporates sophisticated camera functions on-chip such as windowing, column and row skip mode, and snapshot mode. It is programmable through a simple two-wire serial interface and has low power consump- tion. The megapixel CMOS image sensor features Digital- Clarity—Micron’ s breakthrough low-noise CMOS imaging technology that achieves CCD image quality (based on signal-to-noise ratio and low-light sensitiv- ity) while maintaining the inherent size, cost, and inte- gration advantages of CMOS. The sensor can be operated in its default mode or pro- grammed by the user for frame size, exposure, gain set- ting, and other parameters. The default mode outputs an SXGA image at 13.9 frames per second (fps). An on-chip analog-to-digital converter (ADC) provides 10 bits per pixel. FRAME_VALID and LINE_VALID sig- nals are output on dedicated pins, along with a pixel clock that is synchronous with valid data. A flash out- put signal is also available to synchronize external light sources with sensor exposure time. Table 1: Key Performance Parameters Parameter Typical Value Optical Format 1/3-inch (5:4) Active Imager Size 4.6mm(H) x 3.7mm(V), 5.9mm (diagonal) Active Pixels 1,280H x 1,024V Pixel Size 3.6µm x 3.6µm Color Filter Array RGB Bayer Pattern Shutter Type Electronic Rolling Shutter (ERS) Maximum Data Rate/ Master Clock
25 MPS/25 MHz
SXGA (1280 x 1024) Programmable up to 15 fps VGA (640 x 480) Programmable up to 60 fps CIF (352 x 288) Programmable up to 150 fps ADC Resolution 10-bit, on-chip Responsivity 1.0 V/lux-sec (550nm) Dynamic Range >71dB SNR MAX 44dB Supply Voltage I/O Digital 1.7V −3.6V Core Digital 2.5V −3.1V (2.8V nominal) Analog 2.5V −3.1V (2.8V nominal) Power Consumption 129mW (full resolution mode) 70mW (preview mode) Operating Temperature -30°C to +70°C
PDF: 09005aef81051c04/Source: 09005aef8102abe8 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9M011TOC.fm - Rev. D 1/05 EN 2 ©2004 Micron Technology, Inc. All rights reserved. MT9M011 - 1/3-Inch Megapixel Image Sensor Table of Contents Preliminary‡ Table of Contents
PDF: 09005aef81051c04/Source: 09005aef8102abe8 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9M011LOT.fm - Rev. D 1/05 EN 4 ©2004 Micron Technology, Inc. All rights reserved. MT9M011 - 1/3-Inch Megapixel Image Sensor List of Tables Preliminary‡ List of Tables
PDF: 09005aef81051c04/Source: 09005aef8102abe8 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9M011_2.fm - Rev. D 1/05 EN 6 ©2004 Micron Technology, Inc. All rights reserved. MT9M011 - 1/3-Inch Megapixel Image Sensor Preliminary‡ Table 2: Signal Description Name Type Description RESET# Input Asynchronous reset of sensor when LOW. All registers reset to factory defaults. STANDBY Input Enables low power standby mode when = 1. OE# Input Enables output drivers when = 0. SCLK Input Serial Clock. CLKIN Input Master Clock into sensor (25 MHz maximum). SDATA I/O Serial Data. LINE_VALID Output Line Valid: Active HIGH during line of selectable valid pixel data (see Reg0x20 for options). FRAME_VALID Output Frame Valid: Active HIGH during frame of valid pixel data. FLASH Output Synchronization pulse for external light source. PIXCLK Output Pixel Clock Output. Pixel data outputs are valid during rising edge of this clock. DOUT0O u t p u t Pixel Data Output Bit 0 (LSB). DOUT1O u t p u t Pixel Data Output Bit 1. DOUT2O u t p u t Pixel Data Output Bit 2. DOUT3O u t p u t Pixel Data Output Bit 3. DOUT4O u t p u t Pixel Data Output Bit 4. DOUT5O u t p u t Pixel Data Output Bit 5. DOUT6O u t p u t Pixel Data Output Bit 6. DOUT7O u t p u t Pixel Data Output Bit 7. DOUT8O u t p u t Pixel Data Output Bit 8. DOUT9O u t p u t Pixel Data Output Bit 9 (MSB). VDDQP o w e r Digital I/O Power. VAA Power Analog Power. VAAPIX Power Pixel Array Power. VDD Power Digital Core Power. AGND Ground Analog Ground. DGND Ground Digital Core Ground. DGNDQG r o u n d Digital I/O Ground. NC – No Connect.
PDF: 09005aef81051c04/Source: 09005aef8102abe8 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9M011_2.fm - Rev. D 1/05 EN 8 ©2004 Micron Technology, Inc. All rights reserved. MT9M011 - 1/3-Inch Megapixel Image Sensor Pixel Data Format Preliminary‡ Output Data Format The MT9M011 image data is read out in a progressive scan. Valid image data is sur- rounded by horizontal blanking and vertical blanking, as shown in Figure 5. The amount of horizontal blanking is programmable through Reg0x05 and Reg0x07; while vertical blanking is programmable through Reg0x06 and Reg0x08, respectively. LINE_VALID is HIGH during the shaded region of the figure. FRAME_VALID timing is described in “Out- put Data Timing” on page 9. Figure 5: Spatial Illust ration of Image Readout VALID IMAGE HORIZONTAL BLANKING VERTICAL BLANKING VERTICAL/HORIZONTAL BLANKING
PDF: 09005aef81051c04/Source: 09005aef8102abe8 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9M011_2.fm - Rev. D 1/05 EN 10 ©2004 Micron Technology, Inc. All rights reserved. MT9M011 - 1/3-Inch Megapixel Image Sensor Pixel Data Format Preliminary‡ 1ADC_MODE: Reg0xC8, bit 3 = 1: Reg0x20, bit 10 Reg0xC8, bit 3 = 0: Reg0x21, bit 10 (0 = 2 ADC mode, 1 = 1 ADC mode) Default = 0 HBLANK_REG: Reg0xC8, bit 0 = 1: Reg0x05 Reg0xC8, bit 0 = 0: Reg0x07 1ADC_MODE = 0: Minimum value is 202, 1ADC_MODE = 1: Minimum value is 114 Default = 396 (13.9 fps) Note: For frame rate of 15 fps, set Reg0x05 to 272 VBLANK_REG: Reg0xC8, bit 1 = 1: Reg0x06 Reg0xC8, bit 1 = 0: Reg0x08 Minimum value: sum of dark and extra rows enabled in Reg0x22 and Reg0x24 Default = 50 PIXCLK_PERIOD: 1ADC_MODE = 0: Reg0x0A, bit 3 - 0 1ADC_MODE = 1: (Reg0x0A, bit 3 - 0) x 2 A value of 0 in the register is not allowed. Default = 1 Table 3: Frame Time Parameter Name Equation (master clocks units) Default Timing at 25 MHZ A Active Data Time Reg0x04 x PIXCLK_PERIOD (For skip 2x mode: divide Reg0x04 by 2, For skip 4x mode: divide Reg0x04 by 4) 1,280 pixel clocks = 1,280 master = 51.2µs P Frame Start/End Blanking 6 x PIXCLK_PERIOD 6 pixel clocks = 6 master = 0.24µs Q Horizontal Blanking HBLANK_REG x PIXCLK_PERIOD 396 pixel clocks = 396 master = 15.84µs A+Q RowTime (Reg0x04 + HBLANK_REG) x PIXCLK_PERIOD 1,676 pixel clocks = 1,676 master = 67.04µs V Vertical Blanking VBLANK_REG x (A + Q) + (Q - 2 x P) 84,184 pixel clocks = 84,184 master = 3.37ms Nrows x (A + Q) Frame Valid Time Reg0x03 x (A + Q) - (Q - 2 x P) (For skip 2x mode: divide Reg0x03 by 2, For skip 4x mode: divide Reg0x03 by 4) 1,715,840 pixel clocks = 1,715,840 master = 68.63ms F Total Frame Time (Reg0x03 + VBLANK_REG) x (A + Q) 1,800,024 pixel clocks = 1,800,024 master = 72.0ms
PDF: 09005aef81051c04/Source: 09005aef8102abe8 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9M011_2.fm - Rev. D 1/05 EN 11 ©2004 Micron Technology, Inc. All rights reserved. MT9M011 - 1/3-Inch Megapixel Image Sensor Pixel Data Format Preliminary‡ The sensor timing is shown in terms of pixel clock and master clock cycles (please refer to Figure 6 on page 9). The recommended master clock frequency is 25 MHz. The verti- cal blank and total frame time equations assume that the number of integration rows (Reg0x09) is less than or equal to the number of active rows plus blanking rows (Reg0x03 + VBLANK_REG). If this is not the case, the number of integration rows must be used instead to determine the frame time, as shown in Table 4. Table 4: Frame Time — Long Integration Time Parameter Name Equation (master clock) Default Timing V’ Vertical Blanking (long integration time) (Reg0x09 – Reg0x03) x (A + Q) + (Q - 2 x P) 84,184 pixel clocks = 3.37ms F’ Total Frame Time (long integration time) (Reg0x09) x (A + Q) 1,800,024 pixel clocks = 72.0ms
PDF: 09005aef81051c04/Source: 09005aef8102abe8 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9M011_2.fm - Rev. D 1/05 EN 12 ©2004 Micron Technology, Inc. All rights reserved. MT9M011 - 1/3-Inch Megapixel Image Sensor Serial Bus Description Preliminary‡ Serial Bus Description Registers are written to and read from the MT9M011 through the two-wire serial inter- face bus. The sensor is a serial interface slave and is controlled by the serial clock (SCLK), which is driven by the serial interface master. Data is transferred into and out of the MT9M011 through the serial data (S DATA) line. The SDATA line is pulled up to 2.8V off- chip by a 1.5KΩ resistor. Either the slave or master device can pull the SDATA line down— the serial interface protocol determines which device is allowed to pull the SDATA line down at any given time. Protocol The two-wire serial interface defines several different transmission codes, as follows: a s t a r t b i t the slave device 8-bit address a(an) (no) acknowledge bit an 8-bit message a s t o p b i t Sequence A typical read or write sequence begins by the master sending a start bit. After the start bit, the master sends the slave device's 8-bit address. The last bit of the address deter- mines if the request will be a read or a write, where a “0” indicates a write and a “1” indi- cates a read. The slave device acknowledges its address by sending an acknowledge bit back to the master. If the request was a write, the master then transfers the 8-bit register address to which a write should take place. The slave sends an acknowledge bit to indicate that the register address has been received. The master then transfers the data 8 bits at a time, with the slave sending an acknowledge bit after each 8 bits. The MT9M011 uses 16-bit data for its internal registers, thus requiring two 8-bit transfers to write to one register. After 16 bits are transferred, the register address is automatically incremented, so that the next 16 bits are written to the next register address. The master stops writing by sending a start or stop bit. A typical read sequence is executed as follows. First the master sends the write-mode slave address and 8-bit register address, just as in the write request. The master then sends a start bit and the read-mode slave address. The master then clocks out the regis- ter data 8 bits at a time. The master sends an acknowledge bit after each 8-bit transfer. The register address is auto-incremented after every 16 bits is transferred. The data transfer is stopped when the master sends a no-acknowledge bit. Bus Idle State The bus is idle when both the data and clock lines are HIGH. Control of the bus is initi- ated with a start bit, and the bus is released with a stop bit. Only the master can generate the start and stop bits. Start Bit The start bit is defined as a HIGH-to-LOW transition of the data line while the clock line is HIGH. Stop Bit The stop bit is defined as a LOW-to-HIGH transition of the data line while the clock line is HIGH.
PDF: 09005aef81051c04/Source: 09005aef8102abe8 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9M011_2.fm - Rev. D 1/05 EN 13 ©2004 Micron Technology, Inc. All rights reserved. MT9M011 - 1/3-Inch Megapixel Image Sensor Serial Bus Description Preliminary‡ Slave Address The 8-bit address of a two-wire serial interface device consists of 7 bits of address and 1 bit of direction. A “0” (0xBA) in the LSB (least significant bit) of the address indicates write mode, and a “1” (0xBB) indicates read mode. Data Bit Transfer One data bit is transferred during each clock pulse. The serial interface clock pulse is provided by the master. The data must be stable during the HIGH period of the two-wire serial interface clock—it can only change wh en the serial clock is LOW . Data is trans- ferred 8 bits at a time, followed by an acknowledge bit. Acknowledge Bit The master generates the acknowledge clock pulse. The transmitter (which is the master when writing, or the slave when reading) releases the data line, and the receiver indi- cates an acknowledge bit by pulling the data line LOW during the acknowledge clock pulse. No-Acknowledge Bit The no-acknowledge bit is generated when the data line is not pulled down by the receiver during the acknowledge clock pulse. A no-acknowledge bit is used to terminate a read sequence.
PDF: 09005aef81051c04/Source: 09005aef8102abe8 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9M011_2.fm - Rev. D 1/05 EN 16 ©2004 Micron Technology, Inc. All rights reserved. MT9M011 - 1/3-Inch Megapixel Image Sensor Registers Preliminary‡ Registers Note: 1 = always 1 0 = always 0 d = programmable ? = read only Table 5: Register List and Default Value Register Number (Hex) Description Data Format (Binary) Default Value (Hex) 0x00/0xFF Chip Version 0001 0100 0010 0010 (LSB) 0x1433 0x01 Row Start 0000 0ddd dddd dddd 0x000C 0x02 Column Start 0000 0ddd dddd dddd 0x001E 0x03 Row Width 0000 0ddd dddd dddd 0x0400 0x04 Column Width 0000 0ddd dddd dddd 0x0500 0x05 Horizontal Blanking B 00dd dddd dddd dddd 0x018C 0x06 Vertical Blanking B 0ddd dddd dddd dddd 0x0032 0x07 Horizontal Blanking A 00dd dddd dddd dddd 0x00C6 0x08 Vertical Blanking A 0ddd dddd dddd dddd 0x0019 0x09 Shutter Width dddd dddd dddd dddd 0x0432 0x0A Row Speed ddd0 000d dddd dddd 0x0011 0x0B Extra Delay 00dd dd dd dddd dddd 0x0000 0x0C Shutter Delay 00dd dddd dddd dddd 0x0000 0x0D Reset d000 00dd 00dd dddd 0x0008 0x1F Frame Valid Control dddd dddd dddd dddd 0x0000 0x20 Read Mode B dd00 0ddd dddd dddd 0x0200 0x21 Read Mode A 0000 0d00 0000 dd00 0x040C 0x22 Dark Col/Rows 0000 00dd dddd dddd 0x0129 0x23 Flash ??dd dddd dddd dddd 0x0608 0x2B Green1 Gain 0000 0ddd dddd dddd 0x0020 0x2C Blue Gain 0000 0d dd dddd dddd 0x0020 0x2D Red Gain 0000 0ddd dddd dddd 0x0020 0x2E Green2 Gain 0000 0ddd dddd dddd 0x0020 0x2F Global Gain 0000 0ddd dddd dddd 0x0020 0xC8 Context Control d000 0000 d000 dddd 0x000B
PDF: 09005aef81051c04/Source: 09005aef8102abe8 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9M011_2.fm - Rev. D 1/05 EN 17 ©2004 Micron Technology, Inc. All rights reserved. MT9M011 - 1/3-Inch Megapixel Image Sensor Registers Preliminary‡ Table 6: Reserved Register List and Default Value Register Number (Hex) Description Default Value (Hex) 0x24 Reserved 0x806F 0x30 Reserved 0x042A 0x31 Reserved 0x1C00 0x32 Reserved 0x0000 0x33 Reserved 0x0349 0x34 Reserved 0xC019 0x36 Reserved 0xF0F0 0x37 Reserved 0x0000 0x3B Reserved 0x0021 0x3C Reserved 0x1A20 0x3D Reserved 0x201E 0x3E Reserved 0x2020 0x3F Reserved 0x2020 0x40 Reserved 0x201C 0x41 Reserved 0x00D7 0x42 Reserved 0x0777 0x59 Reserved 0x000C 0x5A Reserved 0xC00F 0x5B Reserved RO 0x5C Reserved RO 0x5D Reserved RO 0x5E Reserved RO 0x5F Reserved 0x231D 0x60 Reserved 0x0080 0x61 Reserved 0x0000 0x62 Reserved 0x0000 0x63 Reserved 0x0000 0x64 Reserved 0x0000 0x65 Reserved 0x0000 0x70 Reserved 0x7B0A 0x71 Reserved 0x7B0A 0x72 Reserved 0x190E 0x73 Reserved 0x180F 0x74 Reserved 0x5732 0x75 Reserved 0x5634 0x76 Reserved 0x7335 0x77 Reserved 0x3012 0x78 Reserved 0x7902 0x79 Reserved 0x7506 0x7A Reserved 0x770A 0x7B Reserved 0x7809 0x7C Reserved 0x7D06 0x7D Reserved 0x3110 0x7E Reserved 0x007E 0x80 Reserved 0x007F
PDF: 09005aef81051c04/Source: 09005aef8102abe8 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9M011_2.fm - Rev. D 1/05 EN 18 ©2004 Micron Technology, Inc. All rights reserved. MT9M011 - 1/3-Inch Megapixel Image Sensor Registers Preliminary‡ Note: Writing to these regi sters may cause the part to go into an unknown state. 0x81 Reserved 0x007F 0x82 Reserved 0x570A 0x83 Reserved 0x580B 0x84 Reserved 0x470B 0x85 Reserved 0x480E 0x86 Reserved 0x5B02 0x87 Reserved 0x005C 0xF0 Reserved 0x0000 0xF5 Reserved 0x07FF 0xF6 Reserved 0x07FF 0xF7 Reserved 0x0000 0xF8 Reserved 0x0000 0xF9 Reserved 0x007C 0xFA Reserved 0x0000 0xFB Reserved 0x0000 0xFC Reserved 0x0000 0xFD Reserved 0x0000 Table 6: Reserved Register List and Default Value Register Number (Hex) Description Default Value (Hex)
PDF: 09005aef81051c04/Source: 09005aef8102abe8 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9M011_2.fm - Rev. D 1/05 EN 19 ©2004 Micron Technology, Inc. All rights reserved. MT9M011 - 1/3-Inch Megapixel Image Sensor Registers Preliminary‡ Table 7: Register Description Bit Bit Description Default (Hex) Sync’d to Frame Start Bad Frame Read/ write 0x00/0xFF (0/255) Chip Version 15:0 Chip Version Chip version - read-only. 1433 R 0x01 (1) Row Start 10:0 Row Start The first row to be read out (not counting any dark rows that may be read). To window the image down, set this register to the starting Y value. Setting a value less than 8 is not recommended since the dark rows should be read using Reg0x22. 0C Y YM W 0x02 (2) Column Start 10:0 Column Start The first column to be read out (not counting dark columns that may be read). To window the image down, set this register to the starting X value. Setting a value below 24 decimals (0x18) is not recommended since readout of dark columns should be controlled by Reg0x22. 1E Y YM W 0x03 (3) Row Width 10:0 Row Width Number of rows in th e image to be read out (not counting any dark rows or border rows that may be read).
400 Y YM W
0x04 (4) Column Width 10:0 Column Width Number of columns in image to be read out (not counting any dark columns or border columns that may be read).
500 Y YM W
0x05 (5) Horizontal Blanking B 10:0 Horizontal Blanking B Number of blank columns in a row when context B is chosen (Reg0xC8, bit 0 = 1). If set smaller than the minimum value the minimum value will be used. With default settings the minimum horizontal blanking will be 202 columns when using two ADCs and 114 columns when using one ADC. Default of 0x18C = 13.9 fps @ 25 MHz Setting of 0x110 = 15 fps @ 25 MHz 18C Y YM W 0x06 (6) Vertical Blanking B 14:0 Vertical Blanking B Number of blank rows in a frame when context B is chosen (Reg0xC8, bit 1 = 1). This number must be equal to or larger than the number of dark rows read out in a frame specified by Reg0x22.
32 Y N W
0x07 (7) Horizontal Blanking A 10:0 Horizontal Blanking A Number of blank columns in a row when context A is chosen (Reg0xC8, bit 0 = 0). The extra columns will be added at the beginning of a row. If set smaller than the minimum value the minimum value will be used. With default settings the minimum horizontal blanking will be 202 columns when using two ADCs and 114 columns when using one ADC. Default of 0xC6 = 27.8 fps @ 25 MHz Setting of 0x88 = 30 fps @ 25 MHz C6 Y YM W
PDF: 09005aef81051c04/Source: 09005aef8102abe8 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9M011_2.fm - Rev. D 1/05 EN 20 ©2004 Micron Technology, Inc. All rights reserved. MT9M011 - 1/3-Inch Megapixel Image Sensor Registers Preliminary‡ 0x08 (8) Vertical Blanking A 14:0 Vertical Blanking A Number of blank rows in a frame when context A is chosen (Reg0xC8, bit 1 = 1). This number must be equal to or larger than the number of dark rows read out in a frame specified by Reg0x22.
19 Y N W
0x09 (9) Shutter Width 15:0 Shutter Width Integration time in numb er of rows. In addition to this register the shutter delay register (Reg0x0C) and the overhead time will influence the integration time for a given row time.
432 Y N W
0x0A (10) Row Speed 3:0 Pixel Clock Period Pixel clock period in master clocks when two ADCs are used (Reg0x20/0x21, bit 10 = 0). The ADC clock will always be half the programmed frequency. When only one ADC is used the pixel clock frequency will be halved as well, so in this case will be equal to the ADC clock frequency. The value “0” is not allowed, “1” will be used instead. 1Y Y M W 7:4 Delay Pixel Clock Delay PIXCLK in half master clock cycles. When set the pixel clock can be delayed in increments of half master clock cycles compared to the synchronization of FRAME_VALID, LINE_VALID and DATA_OUT. 1N W
8 Invert Pixel
Invert pixel clock. When set, LINE_VALID, FRAME _VALID, and DATA_OUT will be set up to the falling edge of PIXCLK. When clear, they are set up to the rising edge if there are no delay of the pixel clock. 0N W 15:14 Reserved –0 – – – 0x0B (11) Extra Delay 13:0 Extra Delay Extra blanking insert ed between frames specified in pixel clocks. Can be used to get a more exact frame rate. It might affect the integration times of parts of the image when the integration time is less than one frame. 0Y W 0x0C (12) Shutter Delay 10:0 Shutter Delay The amount of time from the end of the sampling sequence to the beginning of the pixel reset sequence. This variable will automatically be halved when one ADC is used so the time in us will remain the same. This register has an upper value defined by the fact that the reset needs to finish before the readout of that row to prevent changes in the row time. 0Y N W Table 7: Register Description (Continued) Bit Bit Description Default (Hex) Sync’d to Frame Start Bad Frame Read/ write
PDF: 09005aef81051c04/Source: 09005aef8102abe8 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9M011_2.fm - Rev. D 1/05 EN 21 ©2004 Micron Technology, Inc. All rights reserved. MT9M011 - 1/3-Inch Megapixel Image Sensor Registers Preliminary‡ 0x0D (13) Reset
0 Reset Setting this bit will pu t the sensor into reset mode,
which will set the sensor to its default power-up state. Clearing this bit will resume normal operation. 0N Y M W
1 Restart Setting this bit will ca use the sensor to abandon the
current frame and start resetting the first row. The delay before the first valid frame is read out equals the integration time. This bit always reads “0.” 0N Y M W 2 Analog standby 0 = norma l operation (default). 1 = disable analog circuitry. 0N Y M W 3 Chip Enable 1 = normal operation. 0 = stop sensor readout. When this is returned to “1,” sensor readout restarts and starts resetting the starting row in a new frame. To reduce the digital power further the master clock to the sensor can be disabled or the standby pin can be used. 1N Y M W
4 Reserved –0 – – –
5 Reserved –0 – – –
8 Show bad
1 = output all frames (including bad frames). 0 = only output good frames (default). A bad frame is defined as the first frame following a change to: window size or position, horizontal blanking, pixel clock speed, zoom, row or column skip, or mirroring. 0N W
9 Restart bad
When set a restart will be forced to take place when a bad frame is detected. This can shorten the delay when waiting for a good frame, since the delay when masking out a bad frame will be the integration time rather than the full frame time. 0N W
15 Synchronize
0 = normal operation, update changes to registers that affect image brightness (integration time, integration delay, gain, horizontal and vertical blanking, window size, row/column skip, or row mirror) at the next frame boundary. 1 = do not update any changes to these settings until this bit is returned to “0.” All registers that are frame synchronized will be affected by the setting of this bit. 0N W 0x1F (31) FRAME_VALID Control 6:0 Early FRAME_VALID rise When enabled, the FRAME_VALID rising edge will happen for the programmed number of rows before the first LINE_VALID: (bits 6:0) x row time + horiz blank + constant (constant = 3 in default mode). 0N W
7 Enable early
FRAME_VALID rise 1 = Enables the early rise of FRAME_VALID as set in bits 6:0. 0 = default. FRAME_VALID will go HIGH six pixel clocks before first LINE_VALID. 0N W Table 7: Register Description (Continued) Bit Bit Description Default (Hex) Sync’d to Frame Start Bad Frame Read/ write
PDF: 09005aef81051c04/Source: 09005aef8102abe8 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9M011_2.fm - Rev. D 1/05 EN 22 ©2004 Micron Technology, Inc. All rights reserved. MT9M011 - 1/3-Inch Megapixel Image Sensor Registers Preliminary‡ 14:8 Early FRAME_VALID fall When enabled the FRAME_VALID falling edge will happen the programmed number of rows before the end of the last LINE_VALID: (1 + bits 14:8) x row time + constant (constant = 3 in default mode). 0N W
15 Enable early
FRAME_VALID fall 1 = Enables the early disabling of FRAME_VALID as set in bits 14:8. Note that LINE_VALID will still be generated for all active rows. 0 = default. FRAME_VALID will go LOW six pixel clocks after last LINE_VALID. 0N W 0x20 (32) Read Mode - Context B 0 Mirror rows Read out rows from bottom to top (upside down). When set, row readout starts from row (Row Start + Row Size) and continues down to (Row Start + 1). When clear, readout starts at Row Start and continues to (Row Start + Row Size - 1). This ensures that the starting color is maintained. 0Y Y M W 1 Mirror columns Read out co lumns from right to left (mirrored). When set, column readout starts from column (Col Start + Col Size) and continues down to (Col Start + 1). When clear, readout starts at Col Start and continues to (Col Start + Col Size - 1). This ensures that the starting color is maintained. 0Y Y M W
2 Row skip 2x -
When Read Mode context B is selected (Reg0xC8, bit 3 = 1): 1 = read out two rows, and then skip two rows (i.e. row 8, row 9, row 12, row 13…). 0 = normal readout. 0Y Y M W
3 Column skip 2x
- context B When Read Mode context B is selected (Reg0xC8, bit 3 = 1): 1 = read out two columns, and then skip two columns (as with rows). 0 = normal readout. 0Y Y M W 4 Row skip 4x 1 = read ou t two rows, and then skip six rows (i.e. row 8, row 9, row 16, row 17…). 0 = normal readout. 0Y Y M W
5 Column skip 4x 1 = read out two colu mns, and then skip six columns (as
with rows). 0 = normal readout. 0Y Y M W Table 7: Register Description (Continued) Bit Bit Description Default (Hex) Sync’d to Frame Start Bad Frame Read/ write
PDF: 09005aef81051c04/Source: 09005aef8102abe8 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9M011_2.fm - Rev. D 1/05 EN 23 ©2004 Micron Technology, Inc. All rights reserved. MT9M011 - 1/3-Inch Megapixel Image Sensor Registers Preliminary‡ 7:6 Zoom In zoom mode, the pixel data rate is slowed down by a factor of either 2 or 4, and either 1 or 3 additional blank rows are added between each output row. This is designed to give the controller logic time to repeat data to fill in a window that is either 2 or 4 times larger with repeated data. The pixel clock speed is not affected by this operation, and the output data for each pixel is valid for either 2 or 4 pixel clocks. In 2X zoom mode, every row is followed by a blank row (with its own LINE_VALID, but all data bits = 0) of equal time. In 4X zoom mode, every row is followed by three blank rows. The combination of this register and an appropriate change to the window start registers allows the user to zoom to a region of interest without affecting the frame rate. 00 = no zoom (default) X1 = zoom 2X 10 = zoom 4X 0Y Y M W
8 Over Sized When this bit is set a 4-pixel border will be output
around the active image array independent of readout mode (skip, zoom, mirror, etc.). Setting this bit will therefore add eight to the number of rows and columns in the frame. 0Y Y M W
9 Show Border This bit in dicates whether to show the border enabled
by bit 8. When bit 8 is 0 this bit has no meaning. When bit 8 is 1, this bit decides whether the border pixels should be treated as extra active pixels (1) or extra blanking pixels (0). 1N W
10 Use 1 ADC -
0 = Use both ADCs to achieve maximum speed. 1 = Use one ADC to reduce power. Maximum readout frequency is now half of the master clock, and the pixel clock is automatically adjusted as described for the pixel clock speed register. 0Y Y M W
14 Continuous
1 = "Continuous" Line_Valid (continue producing line valid during vertical blanking). 0 = Normal Line_Valid (default) no line valid during vertical blanking. 0N W
15 Xor Line Valid 1 = Line valid = "C ontinuous" Line_Valid XOR Frame
Valid. 0 = Normal Line Valid. Ineffective if Continuous Line_Valid is set. 0N W Table 7: Register Description (Continued) Bit Bit Description Default (Hex) Sync’d to Frame Start Bad Frame Read/ write
PDF: 09005aef81051c04/Source: 09005aef8102abe8 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9M011_2.fm - Rev. D 1/05 EN 24 ©2004 Micron Technology, Inc. All rights reserved. MT9M011 - 1/3-Inch Megapixel Image Sensor Registers Preliminary‡ 0x21 (33) Read Mode - Context A When Read Mode context A is selected (Reg0xC8, bit 3 = 0): 1 = read out two rows, and then skip two rows (i.e. row 8, row 9, row 12, row 13…). 0 = normal readout. 1Y Y M W
- Context A When Read Mode context A is selected (Reg0xC8, bit 3 = 0): 1 = read out two columns, and then skip two columns (as with rows). 0 = normal readout. 1Y Y M W 10 1 ADC mode - Context A When Read Mode context A is selected (Reg0xC8, bit 3 = 0): 0 = Use both ADCs to achieve maximum speed. 1 = Use one ADC to reduce power. Maximum readout frequency is now half of the master clock, and the pixel clock is automatically adjusted as described for the pixel clock speed register. 1Y Y M W 0x22 (34) Show Control 2:0 Number of dark rows Specifies the number of dark rows to read out at the beginning of each frame when the dark row readout is enabled (bit 3). The programmed number is 1 less than the number of rows. 1N Y W
3 Enable dark
Enables the readout of the dark rows specified in bits 2:0. 1N Y W 6:4 Dark start address The start address for the dark rows. Must be set so all dark rows read out falls in the address space 0-7. 2N N W
7 Show dark rows When set, the progra mmed dark rows will be output
before the active window. Frame valid will thus be asserted earlier than normal. This has no effect on integration time or frame rate. Whether the dark rows are shown in the image or not the definition frame start is before the dark rows are read out. All frame synced registers will be updated at this point. 0N N W
8 Read dark
When disabled, an arbitrary number of dark columns can be read out by including them in the active image. Enabling the dark columns do not have an effect on the row time, but it will increase the minimum horizontal blanking value allowed. 1N Y W
9 Show dark
When set, the programmed dark columns will be output before the active pixels in a line. 0N N W 0x23 (35) Flash Control 7:0 Xenon count Length of FLASH_STROBE pulse when Xenon flash is enabled. The value specifies the length in 1,024 master clock cycle increments. 8N N W 8 LED flash Enable LED flash. When set, the FLASH_STROBE will go on prior to the start of the resetting of a frame. When disabled the FLASH_STROBE will remain high until the finish of the readout of the current frame. 0Y Y W Table 7: Register Description (Continued) Bit Bit Description Default (Hex) Sync’d to Frame Start Bad Frame Read/ write
PDF: 09005aef81051c04/Source: 09005aef8102abe8 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9M011_2.fm - Rev. D 1/05 EN 25 ©2004 Micron Technology, Inc. All rights reserved. MT9M011 - 1/3-Inch Megapixel Image Sensor Registers Preliminary‡ 9 Every frame 1 = Flash should be enabled every frame. 0 = Flash should be enabled for 1 frame only. 1N N W
10 End of reset 1 = In Xenon mode th e flash should be triggered after
the resetting of a frame. 0 = In Xenon mode the flash should be enabled after the readout of a frame. 1N N W 12:11 Frame delay Delay of the flash pulse measured in frames. 0N N W 13 Xenon flash Enable Xenon flash. When set, the output pin FLASH_STROBE will be pulsed high for the programmed period during vertical blanking. This is achieved by keeping the integration time equal to one frame, and the pulse width less than the vertical blanking time. 0Y N W
14 Reserved –0 – – –
15 FLASH_STROBE Read-only bit th at indicated whether the
FLASH_STROBE pin is enabled. 0x2B (43) Green1 Gain 6:0 Initial gain Init ial Gain = bits (6:0) x 0.03125. 20 Y N W 8:7 Analog gain Analog Gain = (Bit 8 + 1) x (Bit 7 + 1) x initial gain (each bit gives 2x Gain). 0Y N W 10:9 Digital gain Total Gain = (Bit 9 + 1) x (Bit 10 + 1) x analog gain (each bit gives 2x gain). 0Y N W 0x2C (44) Blue Gain 6:0 Initial gain Init ial Gain = bits (6:0) x 0.03125. 20 Y N W 8:7 Analog gain Analog Gain = (Bit 8 + 1) x (Bit 7 + 1) x initial gain (each bit gives 2x gain). 0Y N W 10:9 Digital gain Total Gain = (Bit 9 + 1) x (Bit 10 + 1) x analog gain (each bit gives 2x gain). 0Y N W 0x2D (45) Red Gain 6:0 Initial gain Init ial Gain = bits (6:0) x 0.03125. 20 Y N W 8:7 Analog gain Analog Gain = (Bit 8 + 1) x (Bit 7 + 1) x initial gain (each bit gives 2x gain). 0Y N W 10:9 Digital gain Total Gain = (Bit 9 + 1) x (Bit 10 + 1) x analog gain (each bit gives 2x gain). 0Y N W 0x2E (46) Green2 Gain 6:0 Initial gain Init ial Gain = bits (6:0) x 0.03125. 20 Y N W 8:7 Analog gain Analog Gain = (Bit 8 + 1) x (Bit 7 + 1) x initial gain (each bit gives 2x gain). 0Y N W 10:9 Digital gain Total Gain = (Bit 9 + 1) x (Bit 10 + 1) x analog gain (each bit gives 2x gain). 0Y N W 0x2F (47) Global Gain 10:0 Global Gain This register can be us ed to set all four gains at once. When read, it will return the value stored in Reg0x2B.
20 Y N W
Table 7: Register Description (Continued) Bit Bit Description Default (Hex) Sync’d to Frame Start Bad Frame Read/ write
PDF: 09005aef81051c04/Source: 09005aef8102abe8 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9M011_2.fm - Rev. D 1/05 EN 26 ©2004 Micron Technology, Inc. All rights reserved. MT9M011 - 1/3-Inch Megapixel Image Sensor Registers Preliminary‡ The following notation is used in Table 7: Sync’d to frame start N = No. The register value will be updated and used immediately. Y = Yes. The register value will be updated at next frame start as long as the synchronize changes bit is 0. Note also that frame start is defined as when the first dark row is read out. By default this is eight rows before FRAME_VALID goes HIGH Bad frame A bad frame is a frame where all rows do not have the same integration time, or offsets to the pixel values changed during the frame. N = No. Changing the register value will not produce a bad frame. Y = Yes. Changing the register value might produce a bad frame. YM = Yes, but the bad frame will be masked out unless the show bad frames feature is enabled. Read/Write R = Read-only register/bit. W = Read/Write register/bit. 0xC8 (200) Context Control
0 Horizontal
1 = Use Horizontal Blanking context B, Reg0x05. 0 = Use Horizontal Blanking context A, Reg0x07. 1Y Y M W
1 Vertical
1 = Use Vertical Blanking context B, Reg0x06. 0 = Use Vertical Blanking context A, Reg0x08. 1Y Y M W
2 LED flash
Enable LED flash. Same physical register as Reg0x23, bit 0Y Y W
3 Read mode
1 = Use Read Mode context B, Reg0x20. 0 = Use Read Mode context A, Reg0x21. Note that bits only found in Read Mode context B register will always be taken from this register. 1Y Y M W
7 Xenon flash
Enable Xenon flash. Same physical register as Reg0x23, bit 13. 0Y N W
15 Restart Setting this bit will ca use the sensor to abandon the
current frame and start resetting the first row. Same physical register as Reg0x0D, bit 1. 0N Y M W Table 7: Register Description (Continued) Bit Bit Description Default (Hex) Sync’d to Frame Start Bad Frame Read/ write
PDF: 09005aef81051c04/Source: 09005aef8102abe8 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9M011_2.fm - Rev. D 1/05 EN 29 ©2004 Micron Technology, Inc. All rights reserved. MT9M011 - 1/3-Inch Megapixel Image Sensor Feature Description Preliminary‡ Figure 16: Readout of 8 Pixels in Normal and Zoom 2X Output Mode Frame Rate Control When a window size is set, the blanking registers (Reg0x05-Reg0x08) along with the Row Speed Register (Reg0x0A) will let you program a desired frame rate. The frame timing equations at the beginning of this document shows you how to calculate the different timings. If these equations are turned around they can help you set the horizontal or ver- tical blanking values to achieve a desired frame rate: HBLANK_REG = master clock freq / (f rame rate x (Reg0x03 + VBLANK_REG) x PIXCLK_PERIOD) - Reg0x04 VBLANK_REG = master clock freq / (frame rate x (Reg0x04 + HBLANK_REG) x PIXCLK_PERIOD) - Reg0x03 Readout Speeds and Power Savings The MT9M011 sensor has two ADCs to convert the pixel values to digital. Since the ADCs run at half the master clock frequency, this makes it possible to achieve a data rate equal to the master clock frequency. On the other hand, it also makes it an option for slower readout to turn one of the ADCs off in order to reduce the power consumption of the sensor. Reg0x20 (Reg0x21), bit 10, chooses between the two modes: 0 = Use both ADCs and read out at the set pixel clock frequency (Reg0x0A, bits 3:0) 1 = Use 1 ADC and read out at half the set pixel clock frequency (Reg0x0A, bits 3:0) This can be used, for example, when the camera is in preview mode. To make the transi- tions between two sensor settings easier, some simple context switching is available in the MT9M011, as described below. Context Switching Reg0xC8 is designed to help switching between sensor modes easily. Some key registers and bits in the sensor have two physical register locations, called contexts. Bits 0, 1, and 3 of Reg0xC8 will decide which context of the register that is currently in use. A 1 in a bit will choose context B, while a 0 will select context A for that parameter. The select bits can be used in any combination, but by default it is set up to make switching between a preview mode to a full resolution mode easy: Full resolution mode: (default) Context B: Reg0xC8 = 0x000B (Context B) Reg0x05 = 0x018C (Horizontal Blanking) Reg0x06 = 0x0032 (Vertical Blanking) Reg0x20, bit 10 = 0, bit 3 = 0, bit 2 = 0 (2 ADCs, no column or row skip) A full resolution SXGA picture will be output at the master clock frequency at 13.9 fps. DOUT9–DOUT0 LINE_VALID Normal readout G0 (9:0) (9:0) (9:0) (9:0) (9:0) (9:0) (9:0) DOUT9–DOUT0 LINE_VALID Zoom 2X readout (9:0) (9:0) (9:0) (9:0) (9:0) PIXCLK PIXCLK
PDF: 09005aef81051c04/Source: 09005aef8102abe8 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9M011_2.fm - Rev. D 1/05 EN 30 ©2004 Micron Technology, Inc. All rights reserved. MT9M011 - 1/3-Inch Megapixel Image Sensor Feature Description Preliminary‡ Context A: Reg0xC8 = 0x0000 (Context A) Reg0x07 = 0x00C6 (Horizontal Blanking) Reg0x08 = 0x0019 (Vertical Blanking) Reg0x21, bit 10 = 1, bit 3 = 1, bit 2 = 1 (1 ADC, column and row skip enabled) A preview image (half SXGA size) will be output at half of the master clock frequency at 27.8 fps. Note that the horizontal and vertical blanking values are set so the row time will be pre- served in the two modes. This way, a switch between the modes will not affect the inte- gration time. This is also the reason that the shutter delay register (Reg0x0C) is automatically halved in 1 ADC mode. A few more control bits are also available through the context register (Reg0xC8) so flash and restarting of the sensor can be done at the same time as changing the contexts. See Table 7, Register Description, on page 19 for more information. Minimum Horizontal Blanking The minimum horizontal blanking value is constrained by the time used for sampling a row of pixels and the overhead in the readout of a row. This can be expressed in an equa- tion as: min hblank = sampling time + dark col time + overhead
2 ADC Mode:
min hblank = 20 x (Reg0x22, bit 8) + 182 = 202 (default)
1 ADC Mode:
min hblank = 20 x (Reg0x22, bit 8) + 94 = 114 (default)
PDF: 09005aef81051c04/Source: 09005aef8102abe8 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9M011_2.fm - Rev. D 1/05 EN 32 ©2004 Micron Technology, Inc. All rights reserved. MT9M011 - 1/3-Inch Megapixel Image Sensor Feature Description Preliminary‡ Integration Time The following registers along with the row time control the integration time: Register 0x09: number of rows of integration, default = 0x0432 (1074) Register 0x0C: shutter delay, default = 0x0000 (0). This is the number of pixel clocks that the timing and control logic waits before asserting the reset for a given row The actual total integration time, tINT , is: tINT = Reg0x09 x Row Time - Overhead Time - Shutter Delay where: Row Time = (Reg0x04 + HBLANK_REG) x PIXCLK_PERIOD master clock periods Overhead Time = 64 master clock periods Shutter Delay = Reg0x0C x PIXCLK_PERIOD master clock periods In this expression, the row time term, Reg0x09 x row time, corresponds to the number of rows integrated. The overhead time (64 master clocks) is the overhead time between the READ cycle and the RESET cycle, and the final term is the effect of the shutter delay. Typically, the value of Reg0x09 is limited to the number of rows per frame (which includes vertical blanking rows), such that the frame rate is not affected by the integra- tion time. If Reg0x09 is increased beyond the total number of rows per frame, MT9M011 will add additional blanking rows as needed. A second constraint is that tINT must be adjusted to avoid banding in the image from light flicker. Under 60Hz flicker, this means tINT must be a multiple of 1/120 of a second. Under 50Hz flicker, tINT must be a multi- ple of 1/100 of a second. Maximum Shutter Delay The maximum shutter delay is set by the reset cycle time and the overall row time avail- able. It will differ for 1 and 2 ADC mode, as shown in the equations below: max_shutter_delay = row time - 385 = row time - (365 + 20 x (Reg0x22, bit 8)) = row time - (sampling time + resetting time + dark cols + overhead) max_shutter_delay = row time - 614 = row time - (574 + 2 x 20 (Reg0x22, bit 8)) Flash Description Reg0x23 The MT9M011 supports both Xenon and LED flash through the FLASH_STROBE output pin. The timing of the FLASH_STROBE pin with the default settings are shown in Figure 19, Figure 20, and Figure 21. Additionally, the flash can be programmed to only be fired once, be delayed by a few frames when asserted, or programmed for other timing, as described in T able 7 on page 19. Since enabling the LED flash will cause one bad frame, where several of the rows only had the flash on for part of their integration time, it is recommended to do a restart (Reg0x0D, bit 1) of the sensor when enabling the flash. The first bad frame will then be masked out as shown in Figure 21.
PDF: 09005aef81051c04/Source: 09005aef8102abe8 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9M011_2.fm - Rev. D 1/05 EN 34 ©2004 Micron Technology, Inc. All rights reserved. MT9M011 - 1/3-Inch Megapixel Image Sensor Feature Description Preliminary‡ Recommended Gain Settings The gains for green1, blue, red, and green2 pixels are set by registers Reg0x2B, Reg0x2C, Reg0x2D, and Reg0x2D, respectively. Gain can also be set globally by Reg0x2F . The analog gain is set by bits[8:0] of the corresponding register as following: Gain = (Bit[8] + 1) x (Bit[7] + 1) x (Bit[6:0]/32) Digital gain is set by bits 9 and 10 of the same registers. The analog gain circuitry (pre-ADC) is designed to offer signal gains from 1 to 15.875. The minimum gain of 1 (register set to 0x0020) corresponds to the lowest setting where the pixel signal is guaranteed to saturate the ADC under all specified operating condi- tions. Any reduction of the gain below this value may cause the sensor to saturate at ADC output values less than the maximum, under certain conditions. It is recommended that this guideline be followed at all times. Since bits 7 and 8 of the gain registers are multiplicative factors for the gain settings, there are alternative ways of achieving certain gains. Some settings offer superior noise performance to others, while the same overall gain. Table 8 lists the recommended gain settings. Table 8: Recommended Gain Settings Desired Gain Recommended Settings (gain registers) Conversion Formula (arithmetic) 1.000 to 1.969 0x020 to 0x03F (Register value)/32 2.000 to 7.938 0x0A0 to 0x0FF (Register value - 128)/16 8.000 to 15.875 0x1C0 to 0x 1FF (Register value - 384)/8
PDF: 09005aef81051c04/Source: 09005aef8102abe8 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9M011_2.fm - Rev. D 1/05 EN 35 ©2004 Micron Technology, Inc. All rights reserved. MT9M011 - 1/3-Inch Megapixel Image Sensor Electrical Specifications Preliminary‡ Electrical Specifications Notes: 1. To place the chip in stand by mode, first raise STANDBY to HIGH then wait ten master clock cycles before turning off the master clock. Ten master clock cycles are required to place the analog circuitry into standby, low-power mode. 2. Summation of currents for all power supplies. Table 9: DC Electrical Characteristics (VDD = VAA = VDDQ = 2.8V; TA = 25°C; 13.9 fps at 25 MHz) Symbol Definition Conditions MIN TYP MAX Units VIH Input High Voltage VDD - 0.3 V DD + 0.3 V VIL Input Low Voltage -0.3 0.8 V IIN Input Leakage Current No Pull-up Resistor; VIN = VDD or DGND -15 15 µA VOH Output High Voltage VDDQV VOL Output Low Voltage 00 . 2 V IOZ Tri-state Output Leakage Current 15 µA IPWR Total Quiescent Supply Current2 CLKIN = 25 MHz; default settings; C LOAD = 68.5pF 46 68 mA IPWR Standby Total Standby Supply Current2 STANDBY = VDDQ1, CLKIN = 0 MHz 11 0 µ A
PDF: 09005aef81051c04/Source: 09005aef8102abe8 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9M011_2.fm - Rev. D 1/05 EN 36 ©2004 Micron Technology, Inc. All rights reserved. MT9M011 - 1/3-Inch Megapixel Image Sensor Electrical Specifications Preliminary‡ Table 10: AC Electrical Characteristics TA = Ambient = 25°C; Load capacitance = 68.5pF; Master clock frequency = 25 MHz) Symbol Definition MIN TYP MAX Units FCLK_IN Input Clock Frequency Clock 12 5 2 5 M H z tDUTY_CYCLE Input Duty Cycle 50 % tCLK_JITTER Input Clock Jitter % tR Input Clock Rise Time ns tF Input Clock Fall Time ns tPLHP tPHLP CLKIN to PIXCLK propagation delay LOW-to-HIGH HIGH-to-LOW ns ns tPLHD tPHLD CLKIN to DOUT<:9:0> propagation delay LOW-to-HIGH HIGH-to-LOW ns ns tFVSETUP Setup time for FRAME_VALID before rising edge of PIXCLK 7n s tFVHOLD Hold time for FRAME_VALID after falling edge of PIXCLK 20 ns tLVSETUP Setup time for LINE_VALID before rising edge of PIXCLK 8n s tLVHOLD Hold time for LINE_VALID after falling edge of PIXCLK 25 ns tDSETUP Setup Time for DOUT before rising edge of PIXCLK 6n s tDHOLD Hold Time for DOUT after falling edge of PIXCLK ns tFTOL Time between rising edge of FRAME_VALID and LINE_VALID 240 ns tOUTR DOUT Rise Time 12 ns tOUTF DOUT Fall Time 11 ns tPLHF CLKIN to FRAME_VALID propagation delay, LOW-to-HIGH 7n s tPLHL CLKIN to LINE_VALID propagation delay, LOW-to-HIGH 7n s tPHLF CLKIN to FRAME_VALID propagation delay, HIGH-to-LOW 4n s tPHLL CLKIN to LINE_VALID propagation delay, HIGH-to-LOW 5n s
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 prodmktg@micron.com www.micron.com Customer Comment Line: 800-932-4992 Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. Preliminary: This data sheet contains initial characterization limits that are subject to change upon full characterization of production devices. MT9M011 - 1/3-Inch Megapixel Image Sensor Electrical Specifications Preliminary‡ PDF: 09005aef81051c04/Source: 09005aef8102abe8 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9M011_2.fm - Rev. D 1/05 EN 40 ©2004 Micron Technology, Inc. All rights reserved. Spectral Response Figure 31: Spectral Response 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 350 450 550 650 750 850 950 1050 Wavelength (nm) Relative Response Relative Spectral Response B R G
PDF: 09005aef81051c04/Source: 09005aef8102abe8 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9M011_2.fm - Rev. D 1/05 EN 41 ©2004 Micron Technology, Inc. All rights reserved. MT9M011 - 1/3-Inch Megapixel Image Sensor
Revision History
Preliminary‡ Changed master clock frequency to 25 MHz in Table 1, and updated related timings in Table 3 Added settings for maximum frame ra te and updated description to Table 7, Register Description, on page 19—Reg0x05 and Reg0x07 Changed current values and conditions in Tabl e 9, DC Electrical Characteristics, on page 35 Updated Table 10, AC Electrical Characteristics, on page 36 Removed ICSP package information and ball description Updated Table 5, Register List and Default Value, on page 16 Updated Table 7, Register Description, on page 19 Updated Table 1, Key Performance Parameters, on page 1 Updated Figure 2 on page 5 Replaced Ballout drawing Updated Table 5, Register List and Default Value, on page 16 Updated “Electrical Specifications” on page 35 Original release