MT9M001

MT9M001 MICRON | Alldatasheet

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80a3e031 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9M001_DS_1.fm - Rev. C 7/05 EN 1 ©2004 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice. 1/2-Inch Megapixel CMOS Digital Image Sensor MT9M001C12STM (Monochrome) For the latest data sheet, refer to Micron’s Web site: www.micron.com\\imaging

• DigitalClarity ™ CMOS Imaging Technology  Array Format (5:4): 1,280H x 1,024V (1,310,720 active pixels). Total (incl. dark pixels): 1,312H x 1,048V (1,374,976 pixels)  Frame Rate: 30 fps progressive scan; programmable  Shutter: Electronic Rolling Shutter (ERS)  Window Size: SXGA; programmable to any smaller format (VGA, QVGA, CIF , QCIF , etc.)  Programmable Controls: Gain, frame rate, frame size

Applications

 Digital still cameras  Digital video cameras P C c a m e r a s General Description The Micron ® Imaging MT9M001 is an SXGA-format with a 1/2-inch CMOS active-pixel digital image sen- sor. The active imaging pixel array of 1,280H x 1,024V . It incorporates sophisticated camera functions on-chip such as windowing, column and row skip mode, and snapshot mode. It is programmable through a simple two-wire serial interface. This megapixel CMOS image sensor features Digital- Clarity—Micron’ s breakthrough low-noise CMOS imaging technology that achieves CCD image quality (based on signal-to-noise ratio and low-light sensitiv- ity) while maintaining the inherent size, cost, and inte- gration advantages of CMOS. Table 1: Key Performance Parameters The sensor can be operated in its default mode or pro- grammed by the user for frame size, exposure, gain set- ting, and other parameters. The default mode outputs an SXGA-size image at 30 fr ames per second (fps). An on-chip analog-to-digital converter (ADC) provides 10 bits per pixel. FRAME_VALI D and LINE_VALID signals are output on dedicated pins, along with a pixel clock that is synchronous with valid data.

Ordering Information

Optical format 1/2-inch (5:4) Active imager size 6.66mm(H) x 5.32mm(V) Active pixels 1,280H x 1,024V Pixel size 5.2µm x 5.2µm Shutter type Electronic rolling shutter (ERS) Maximum data rate/ master clock

48 MPS/48 MHz

(1280 x 1024) 30 fps progressive scan; programmable ADC resolution 10-bit, on-chip Responsivity 2. 1 V/lux-sec Dynamic range 68.2dB SNR MAX 45dB Supply voltage 3.0V −3.6V, 3.3V nominal Power consumption 325mW at 3.3V; Standby 275µW Operating temperature 0°C to +70°C Packaging 48-pin CLCC Table 2: Available Part Numbers Part Number Description MT9M001C12STM 46-pin CLCC

80a3e031 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9M001TOC.fm - Rev. C 7/05 EN 2 ©2004 Micron Technology, Inc. All rights reserved. MT9M001 - 1/2-Inch Megapixel Digital Image Sensor Table of Contents Table of Contents

80a3e031 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9M001LOT.fm - Rev. C 7/05 EN 3 ©2004 Micron Technology, Inc. All rights reserved. MT9M001 - 1/2-Inch Megapixel Digital Image Sensor List of Tables List of Tables

80a3e031 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9M001_DS_2.fm - Rev.C 7/05 EN 6 ©2004 Micron Technology, Inc. All rights reserved. MT9M001 - 1/2-Inch Megapixel Digital Image Sensor General Description Table 2: Pin Descriptions Pin Numbers Symbol Type Description 29 CLKIN Input Clock in. Master clock into sensor (48 MHz maximum). 13 OE# Input Output enable. OE# when HIGH places outputs DOUT<0:9>, FRAME_VALID, LINE_VALID, PIXCLK, and STROBE into a tri-state configuration. 10 RESET# Input Reset. Activates (LOW) asynchronous reset of sensor. All registers assume factory defaults. 46 SCLK Input Serial clock. Clock for serial interface. 7 STANDBY Input Standby. Activates (HIGH) standby mode, disables analog bias circuitry for power saving mode. 8 TRIGGER Input Trigger. Activates (HIGH) snapshot sequence. 45 S DATA Input/Output Serial data. Serial data bus, requires 1.5KΩ resistor to 3.3V for pull-up. 24–28, 32–36 D OUT<0–9> Output Data out. Pixel data output bits 0:9, DOUT<9> (MSB), DOUT<0> (LSB). 41 FRAME_VALID Output Frame valid. Output is pulsed HIGH during frame of valid pixel data. 40 LINE_VALID Output Line valid. Output is pulsed HIGH during line of selectable valid pixel data (see Reg0x20 for options). 31 PIXCLK Output Pixel clock. Pixel data outputs are valid during falling edge of this clock. Frequency = (master clock). 39 STROBE Output Strobe. Output is pulsed HIGH to indicate sensor reset operation of pixel array has completed. 15,17,18,21, 47, AGND Supply Analog ground. Provide isolated ground for analog block and pixel array. 5,23,38,43 D GND Supply Digital ground. Provide isolated ground for digital block. 16,20 V AA Supply Analog power. Provide power supply for analog block, 3.3V ±0.3V. 1 VAAPIX Supply Analog pixel power. Provide power supply for pixel array, 3.3V ±0.3V (3.3V). 4,22,37 V DD Supply Digital power. Provide power supply for digital block, 3.3V ±0.3V. 2,3,6,9,11,12, 14,19,30,42,44 NC — No connect. These pins must be left unconnected.

80a3e031 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9M001_DS_2.fm - Rev.C 7/05 EN 9 ©2004 Micron Technology, Inc. All rights reserved. MT9M001 - 1/2-Inch Megapixel Digital Image Sensor Pixel Data Format Frame Timing Formulas Notes: 1. Row skip mode should have no effect on the integration time. Column skip mode changes the effective value of Column Size (Reg0x04) as follows: Column Skip 2 => R4eff = (int(R4 / 4) x 2) + 1 Column Skip 4 => R4eff = (int(R4 / 8) x 2) + 1 Column Skip 8 => R4eff = (int(R4 / 16) x 2) + 1 where the int() function truncates to the next lowest integer. Now use R4eff in the equa- tion for row time instead of R4 2. Default for Reg0x05 = 9. However, sensor ignores any value for Reg0x05 less than 19. Sensor timing is shown above in terms of pixel clock and master clock cycles (please refer to Figure 6). The recommended master clock frequency is 48 MHz. The vertical blank and total frame time equations assume that the number of integration rows (bits 13 through 0 of Reg0x09) is less than the number of active plus blanking rows (Reg0x03 + 1 + Reg0x06 + 1). If this is not the case, the number of integration rows must be used instead to determine the frame time, as shown in Table 4. Table 3: Frame Timing Parameter Name Equation (MASTER CLOCK) Default Timing Notes A Active Data Time (Reg0x04 + 1) 1,280 pixel clocks = 26.7µs P1 Frame Start Blanking (242) 242 pixel clocks = 5.04µs P2 Frame End Blanking (2 + Reg0x05 - 19) (MIN Reg0x05 value = 19) 2 pixel clocks = 0.042µs Q = P1 + P2 Horizontal Blanking (244 + Reg0x05 - 19) (MIN Reg0x05 value = 19) 244 pixel clocks = 5.08µs A + Q Row Time ((Reg0x04 + 1) + (244 + Reg0x05 - 19)) 1,524 pixel clocks = 31.75µs V Vertical Blanking (Reg0x06 + 1) x (A + Q) (MIN Reg0x06 value = 15) 39,624 pixel clocks = 825.5µs NROWS x (A + Q) Frame Valid Time (Reg0x03 + 1) x (A + Q) 1,560,576 pixel clocks = 32.51ms F Total Frame Time (Reg0x03 + 1 + Reg0x06 + 1) x (A + Q) 1,600,200 pixel clocks = 33.34ms Table 4: Frame Time — Long Integration Time Parameter Name Equation (master clock) Default Timing V’ Vertical Blanking (long integration time) (Reg0 x09 – Reg0x03) x (A + Q) 39,624 pixel clocks = 82.5µs F’ Total Frame Time (long integration time) (Reg0x09 + 1) x (A + Q) 1,600,200 pixel clocks = 33.34ms

80a3e031 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9M001_DS_2.fm - Rev.C 7/05 EN 10 ©2004 Micron Technology, Inc. All rights reserved. MT9M001 - 1/2-Inch Megapixel Digital Image Sensor Serial Bus Description Serial Bus Description Registers are written to and read from the MT9M001 through the two-wire serial inter- face bus. The sensor is a two-wire serial interface slave and is controlled by the serial clock (SCLK), which is driven by the serial interface master. Data is transferred into and out of the MT9M001 through the serial data (S DATA) line. The SDATA line is pulled up to 3.3V off-chip by a 1.5KΩ resistor. Either the slave or master device can pull the SDATA line down—the serial interface protocol determines which device is allowed to pull the S DATA line down at any given time. Protocol The two-wire serial interface defines several different transmission codes, as follows: a s t a r t b i t  the slave device eight-bit address  a(an) (no) acknowledge bit  an 8-bit message a s t o p b i t Sequence A typical read or write sequence begins by the master sending a start bit. After the start bit, the master sends the slave device's eight-bit address. The last bit of the address determines if the request will be a read or a write, where a “0” indicates a write and a “1” indicates a read. The slave device acknowledges its address by sending an acknowledge bit back to the master. If the request was a write, the master then transfers the 8-bit register address to which a write should take place. The slave sends an acknowledge bit to indicate that the register address has been received. The master then transfers the data eight bits at a time, with the slave sending an acknowledge bit after each eight bits. The MT9M001 uses 16-bit data for its internal registers, thus requiring two 8-bit transfers to write to one register. After 16 bits are transferred, the register address is automatically incremented, so that the next 16 bits are written to the next register address. The master stops writing by sending a start or stop bit. A typical read sequence is executed as follows. First the master sends the write-mode slave address and 8-bit register address, just as in the write request. The master then sends a start bit and the read-mode slave address. The master then clocks out the regis- ter data eight bits at a time. The master sends an acknowledge bit after each 8-bit trans- fer. The register address is auto-incremented after every 16 bits is transferred. The data transfer is stopped when the master sends a no-acknowledge bit. Bus Idle State The bus is idle when both the data and clock lines are HIGH. Control of the bus is initi- ated with a start bit, and the bus is released with a stop bit. Only the master can generate the start and stop bits. Start Bit The start bit is defined as a HIGH-to-LOW transition of the data line while the clock line is HIGH. Stop Bit The stop bit is defined as a LOW-to-HIGH transition of the data line while the clock line is HIGH.

80a3e031 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9M001_DS_2.fm - Rev.C 7/05 EN 11 ©2004 Micron Technology, Inc. All rights reserved. MT9M001 - 1/2-Inch Megapixel Digital Image Sensor Serial Bus Description Slave Address The 8-bit address of a two-wire serial interface device consists of seven bits of address and 1 bit of direction. A “0” (0xBA) in the LSB (least significant bit) of the address indi- cates the write mode, and a “1” (0xBB) indicates read mode. Data Bit Transfer One data bit is transferred during each clock pulse. The serial interface clock pulse is provided by the master. The data must be stable during the HIGH period of the two-wire serial interface clock—it can only change wh en the serial clock is LOW . Data is trans- ferred eight bits at a time, followed by an acknowledge bit. Acknowledge Bit The master generates the acknowledge clock pulse. The transmitter (which is the master when writing, or the slave when reading) releases the data line, and the receiver indi- cates an acknowledge bit by pulling the data line LOW during the acknowledge clock pulse. No-Acknowledge Bit The no-acknowledge bit is generated when the data line is not pulled down by the receiver during the acknowledge clock pulse. A no-acknowledge bit is used to terminate a read sequence.

80a3e031 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9M001_DS_2.fm - Rev.C 7/05 EN 13 ©2004 Micron Technology, Inc. All rights reserved. MT9M001 - 1/2-Inch Megapixel Digital Image Sensor Registers Registers Register Map Note: 1 = always 1 0 = always 0 d = programmable Table 5: Register List and Default Values Register # (Hex) Description Data Format (Binary) Default Value (Hex) 0x00 Chip Version 1000 0100 0001 0001 0x8431 0x01 Row Start 0000 0ddd dddd dddd 0x000C 0x02 Column Start 0000 0ddd dddd dddd 0x0014 0x03 Row Size (Window Height ) 0000 0ddd dddd dddd 0x03FF 0x04 Col Size (Window Width) 0000 0ddd dddd dddd 0x04FF 0x05 Horizontal Blanking 0000 0ddd dddd dddd 0x0009 0x06 Vertical Blanking 0000 0ddd dddd dddd 0x0019 0x07 Output Control 0000 0000 0d00 00dd 0x0002 0x09 Shutter Width 00dd dddd dddd dddd 0x0419 0x0B Restart 0000 0000 0000 000d 0x0000 0x0C Shutter Delay 0000 0ddd dddd dddd 0x0000 0x0D Reset 0000 0000 0000 000d 0x0000 0x1E Read Options 1 1000 dddd 00dd dd00 0x8000 0x20 Read Options 2 dd01 0dd1 d00d d10d 0x1104 0x2B Even Row, Even Column 0000 0000 0ddd dddd 0x0008 0x2C Odd Row, Even Column 0000 0000 0ddd dddd 0x0008 0x2D Even Row, Odd Column 0000 0000 0ddd dddd 0x0008 0x2E Odd Row, Odd Column 0000 0000 0ddd dddd 0x0008 0x35 Global Gain 0000 0000 0ddd dddd 0x0008 0x5F Cal Threshold dddd dddd d0dd dddd 0x0904 0x60 Even Row, Even Column 0000 000d dddd dddd 0x0000 0x61 Odd Row, Odd Column 0000 000d dddd dddd 0x0000 0x62 Cal Ctrl d00d d100 1001 1ddd 0x0498 0x63 Even Row, Odd Column 0000 000d dddd dddd 0x0000 0x64 Odd Row, Even Column 0000 000d dddd dddd 0x0000 0xF1 Chip Enable 0000 0000 0000 00dd 0x0001

80a3e031 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9M001_DS_2.fm - Rev.C 7/05 EN 14 ©2004 Micron Technology, Inc. All rights reserved. MT9M001 - 1/2-Inch Megapixel Digital Image Sensor Registers Table 6: Register Description Register Bit Description Chip ID 0x00 15:0 This register is read-only and gives the chip identification number: 0x8431. Window Control These registers control the size of the window. 0x01 10:0 First row to be read out— default = 0x000C (12). 0x02 10:0 First column to be read out— default = 0x0014 (20). Register value must be an even number. 0x03 10:0 Window height (number of rows - 1)— default = 0x03FF (1023). Minimum value for 0x03 = 0x0002. 0x04 10:0 Window width (number of columns - 1)— default = 0x04FF (1279). Register value must be an odd number. Minimum value for 0x04 = 0x0003. Blanking Control These registers control the blanking time in a row (called column fill-in or horizontal blanking) and between frames (vertical blanking). Horizontal blanking is specified in terms of pixel clocks. Vertical blanking is specified in terms of row readout times. The actual imager timing can be calculated using Table 3, Frame Timing, on page 9. 0x05 10:0 Horizontal Blanking — default = 0x0009 (9 pixels). 0x06 10:0 Vertical Blanking— default = 0x0019 (25 rows). Output Control This register controls various features of the output format for the sensor. 0x07 0 Synchronize changes (copied to Reg0xF1, bit1). 0 = normal operation. Update changes to registers that affect image brightness (integration time, integration delay, gain, horizontal blanking and vertical blanking, window size, row/column skip or row mirror) at the next frame boundary. The “frame boundary” is 8 row_times before the rising edge of FRAME_VALID. (If “Show Dark Rows” is set, it will be coincident with the rising edge of FRAME_VALID.) 1 = do not update any changes to these settings until this bit is returned to “0.” 1 Chip Enable (copied to Reg0xF1, bit0). 1 = normal operation. 0 = stop sensor readout. When this is returned to “1,” sensor readout restarts at the starting row in a new frame. The digital power consumption can then also be reduced to less than 5uA by turning off the master clock.

2 Reserved

— default is 0; set to zero at all times. 3 Reserved— default is 0; set to zero at all times. 6 Use Test Data. When set, a test pattern will be output instead of the sampled image from the sensor array. The value sent to the DOUT[9:0] pins will alternate between the Test Data register (Reg0x32) in even columns and the inverse of the Test Data register for odd columns. The output “image” will have the same width, height, and frame rate as it would otherwise have. No digital processing (gain or offset) is applied to the data. When clear (the default), sampled pixel values are output normally.

80a3e031 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9M001_DS_2.fm - Rev.C 7/05 EN 15 ©2004 Micron Technology, Inc. All rights reserved. MT9M001 - 1/2-Inch Megapixel Digital Image Sensor Registers Pixel Integration Control These registers (along with the window sizing and blanking registers) control the integration time for the pixels. The actual total integration time (tINT) is: tINT = Reg0x09 x row time - overhead time - reset delay, where: Row time = ((Reg0x04 + 1) + 244 + Reg0x05 - 19) pixel clock periods Overhead time = 180 pixel clock periods Reset delay = 4 x Reg0x0C pixel clock periods If the value in Reg0x0C exceeds (row time - 548)/4 pixel clock cycles, the row time will be extended by (4 x Reg0x0C - (row time - 548)) pixel clock cycles. In this expression, the row time term, Reg0x09 x ((number of columns) + 244 + horizontal blanking register - 19), corresponds to the number of rows integrated. The overhead time (180 pixel clocks) is the overhead time between the READ cycle and the RESET cycle, and the final term is the effect of the reset delay. Typically, the value of Reg0x09 is limited to the number of rows per frame (which includes vertical blanking rows) such that the frame rate is not affected by the integration time. If Reg0x09 is increased beyond the total number of rows per frame, the MT9M001 will add additional blanking rows as needed. A second constraint is that tINT must be adjusted to avoid banding in the image from light flicker. Under 60Hz flicker, this means tINT must be a multiple of 1/120 of a second. Under 50Hz flicker, tINT must be a multiple of 1/100 of a second. 0x09 13:0 Number of rows of integration— default = 0x0419 (1049). 0x0C 10:0 Shutter delay— default = 0x0000 (0). This is the number of master clocks times four that the timing and control logic waits before asserting the reset for a given row. Frame Restart 0x0B 0 Setting bit 0 to “1” of Reg0x0B will cause the sensor to abandon the readout of the current frame and restart from the first row. This register automatically resets itself to 0x0000 after the frame restart. The first frame after this event is considered to be a "bad frame" (see description for Reg0x20, bit0). Reset 0x0D 0 This register is used to reset the sensor to its default, power-up state. To put the MT9M001 in reset mode first write a “1” into bit 0 of this register, then write a “0” into bit 0 to resume operation. Table 6: Register Description (continued) Register Bit Description

80a3e031 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9M001_DS_2.fm - Rev.C 7/05 EN 16 ©2004 Micron Technology, Inc. All rights reserved. MT9M001 - 1/2-Inch Megapixel Digital Image Sensor Registers Read Mode 1 In read mode 1, this register is used to control many aspects of the readout of the sensor. 0x1E 0 Reserved— default is 0; set to zero at all times. 1 Reserved— default is 0; set to zero at all times. 2 Column Skip 4— default is 0 (disable). 1 = enable. 3 Row Skip 4— default is 0 (disable). 1 = enable. 4 Column Skip 8— default is 0 (disable). 1 = enable. 5 Row Skip 8— default is 0 (disable). 1 = enable. 6 Reserved— default is 0; do not change. 7 Reserved— default is 0; do not change. 8 Snapshot Mode— default is 0 (continuous mode). 1 = enable (wait for TRIGGER; TRIGGER can come from outside signal (TRIGGER pin on the sensor) or from serial interface register restart, i.e. programming a “1” to bit 0 of Reg0x0B. 9 STROBE Enable— default is 0 (no STROBE signal). 1 = enable STROBE (signal output from the sensor during the time all rows are integrating. See STROBE width for more information).

10 STROBE Width— default is 0 (STROBE signal width at minimum length, 1 row of integration time,

prior to line valid going HIGH). 1 = extend STROBE width (STROBE signal width extends to entire time all rows are integrating).

11 Strobe Override

— default is 0 (STROBE signal created by digital logic). 1 = override STROBE signal (STROBE signal is set HIGH when this bit is set, LOW when this bit is set LOW. It is assumed that STROBE enable is set to “0” if STROBE override is being used). 12 Reserved— default is 0; do not change. 13 Reserved— default is 0; do not change. 14 Reserved— default is 0; do not change. 15 Reserved— default is 1; do not change. Gain Settings The gain is individually controllable for each of the four groups of pixels that lie in odd rows and columns, even rows and columns, odd rows and even columns, and even rows and odd columns. This is shown in the register chart. Formula for gain setting: Gain ≤ 8 Gain = (bit[6] + 1) x (bit[5-0] x 0.125) Gain > 8 (bit[6] = 1 and bit[5] = 1) Gain = 8.0 + bit[2-0] Since bit[6] of the gain registers are multiplicative factors for the gain settings, there are alternative ways of achieving certain gains. Some settings offer superior noise performance to others, despite the same overall gain. The following lists the recommended gain settings: Gain Increments Recommended Settings 1.000 to 4.000 0.125 0x08 to 0x20 4.25 to 8.00 0.25 0x51 to 0x60 9.0 to 15.0 1.0 0x61 to 0x67 0x2B 6:0 Even row, even column— default = 0x08 (8) = 1x gain. 0x2C 6:0 Odd row, even column— default = 0x08 (8) = 1x gain. Table 6: Register Description (continued) Register Bit Description

80a3e031 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9M001_DS_2.fm - Rev.C 7/05 EN 17 ©2004 Micron Technology, Inc. All rights reserved. MT9M001 - 1/2-Inch Megapixel Digital Image Sensor Registers 0x2D 6:0 Even row, odd column— default = 0x08 (8) = 1x gain. 0x2E 6:0 Odd row, odd column— default = 0x08 (8) = 1x gain. 0x35 6:0 Global gain— default = 0x08 (8) = 1x gain. This register can be used to set all four gains at once. Test Data 0x32 11:2 Test Data. The value used to produce a test pattern in “Use Test Data” mode (Reg0x07 bit 6). Read Mode 2 This register is used to control many aspects of the readout of the sensor. 0x20 0 No bad frames— 1 = output all frames (including bad frames). 0 (default) = only output good frames. A bad frame is defined as the first frame following a change to: window size or position, horizontal blanking, row or column skip, or mirroring. 1 Reserved— default is 0; do not change. 2 Reserved— default is 1; set to “1” at all times.

3 Column skip— 1= read out two columns, and then skip two columns (for example, col 0, col 1, col 4,

col 5…). 0 = normal readout (default).

4 Row skip— 1 = read out two rows, and then skip two rows (for example, row 0, row 1, row 4, row

5…). 0 = normal readout (default).

5 Reserved

— default is 0; do not change. 6 Reserved— default is 0; set to zero at all times. 7 Flip Row— 1 = readout starting 1 row later (alternate color pair). 0 (default) = normal readout. 8 Reserved— default is 1; set to “1” at all times. 9 1 = "Continuous" LINE_VALID (continue producing LINE_VALID during vertical blanking). 0 = normal LINE_VALID (default, no LINE_VALID during vertical blanking). 10 1 = LINE_VALID = "Continuous" LINE_VALID XOR FRAME_VALID. 0 = LINE_VALID determined by bit 9. 11 Reserved— default is 0; do not change. 12 Reserved— default is 1; do not change. 13 Reserved— default is 0; do not change. 14 Reserved— default is 0; do not change. 15 Mirror Row— 1 = read out from bottom to top (upside down). 0 (default) = normal readout (top to bottom). Test Data 0x32 11:2 Test Data. The value used to produce a test pattern in “Use Test Data” mode (Reg0x07 bit 6). Black Level Calibration These registers are used in the black level calibration. Their functionality is described in detail in the next section. Table 6: Register Description (continued) Register Bit Description

80a3e031 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9M001_DS_2.fm - Rev.C 7/05 EN 18 ©2004 Micron Technology, Inc. All rights reserved. MT9M001 - 1/2-Inch Megapixel Digital Image Sensor Registers 0x5F 5:0 Thres_lo— Lower threshold for black level in ADC LSBs—d efault = 000100. 7 1 = override automatic Thres_hi and Thres_lo adjust (Thres_hi always = bits 14:8; Thres_lo always = bits 5:0). Default = 0 = Automatic Thres_hi and Thres_lo adjustment. 14:8 Thres_hi — Maximum allowed black level in ADC LSBs (default = Thres_lo + 5). Black level maximum is set to this value when bit 7 = 1; black level maximum is reset to this value after every black level average restart if bit 15 = 1 and bit 7 = 0. 15 No gain dependence. 1 = Thres_lo is set by the programmed value of bits 5:0, Thres_hi is reset to the programmed value (bits 14:8) after every black level average restart. 0 = Thres_lo and Thres_hi are set automatically, as described above. 0x60 8:0 Even row, even column— analog offset correction value for even row, even column, bits 0:7 sets magnitude, bit 8 set sign. 0 = positive; 1 = negative. two’s complement, if bit 8 = 1, Offset = bits [0:7] - 256. 0x61 8:0 Odd row, odd column— analog offset correction value for odd row, odd column, bits 0:7 sets magnitude, bit 8 set sign. 0 = positive; 1 = negative. two’s complement, if bit 8 = 1, Offset = bits [0:7] - 256. 0x62 0 Manual override of black level correction. 1 = override automatic black level correction with programmed values. 0 = normal operation (default). 2:1 Force/disable black level calibration. 00 = apply black level calibration during ADC operation only (default). 10 = apply black level calibration continuously. X1= disable black level correction (Offset Correction Voltage = 0.0V). (In this case, no black level correction is possible). 4:3 Reserved— default is 1; do not change. 6:5 Reserved— default is 0; do not change. 7 Reserved— default is 1; do not change. 9:8 Reserved— default is 0; do not change. 10 Reserved— default is 1; do not change. 11 1 = do not reset the upper threshold after a black level recalculation sweep. 0 = reset the upper threshold after a black level recalculation sweep (default). 12 1 = start a new running digitally filtered average for the black level (this is internally reset to “0” immediately), and do a rapid sweep to find the new starting point. 0 = normal operation (default). 14:3 Reserved— default is 0; set to zero at all times. 15 1 = do not perform the rapid black level sweep on new gain settings. 0 = normal operation. 0x63 8:0 Even row, odd column— analog offset correction value for even row, odd column, bits 0:7 sets magnitude, bit 8 set sign. 0 = positive; 1 = negative. two’s complement, if bit 8 = 1, Offset = bits [0:7] - 256. 0x64 8:0 Odd row, even column— analog offset correction value for odd row, even column, bits 0:7 sets magnitude, bit 8 set sign. 0 = positive; 1 = negative. two’s complement, if bit 8 = 1, Offset = bits [0:7] - 256. Table 6: Register Description (continued) Register Bit Description

80a3e031 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9M001_DS_2.fm - Rev.C 7/05 EN 19 ©2004 Micron Technology, Inc. All rights reserved. MT9M001 - 1/2-Inch Megapixel Digital Image Sensor Registers Chip Enable and Two-Wire Serial Interface Write Synchronize. 0xF1 0 Mirrors the functionality of Reg0x07 bit1 (Chip Enable). 1 = normal operation. 0 = stop sensor readout; when this is returned to “1,” sensor readout restarts at the starting row in a new frame. Table 6: Register Description (continued) Register Bit Description

80a3e031 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9M001_DS_2.fm - Rev.C 7/05 EN 20 ©2004 Micron Technology, Inc. All rights reserved. MT9M001 - 1/2-Inch Megapixel Digital Image Sensor Feature Description Feature Description Signal Path The MT9M001 signal path consists of two stages, a programmable gain stage and a pro- grammable analog offset stage. Programmable Gain Stage A total programmable gain of 15 is available and can be calculated using the following formula: Gain 1 to 8: Gain = (bit[6] + 1) x (bit[5:0] x 0.125) For gain higher than eight, the user would need to set bit[6:5] = 11 and use the lower 3 LSB's bit[2:0] to set the higher gain values. The formula for obtaining gain greater than eight is as follows: Total gain = 8 + bit[2:0] For example, for total gain = 12, the value to program is bit[6–0] = 1100100. The maximum total gain = 15, i.e. bit[6:0] = 1100111. The gain circuitry in the MT9M001 is designed to offer signal gains from one to 15. The minimum gain of one corresponds to the lowest setting where the pixel signal is guaran- teed to saturate the ADC under all specified operating conditions. Any reduction of the gain below this value may cause the sensor to saturate at ADC output values less than the maximum, under certain conditions. It is recommended that this guideline be fol- lowed at all times. Since bit[6] of the gain registers are multiplicative factors for the gain settings, there are alternative ways of achieving certain gains. Some settings offer superior noise perfor- mance to others, despite the same overall gain. Recommended gain settings are listed in Table 7. Figure 10: Signal Path Table 7: Recommended Gain Settings at 48 MHz Nominal Gain Increments Recommended Settings 1 to 4.000 0.125 0x08 to 0x20 4.25 to 8.00 0.25 0x51 to 0x60 9 to 15 1.0 0x61 to 0x67 X + Pixel Output (signal minus reset) Offset Correction Voltage (Reg0x60, Reg0x61, Reg0x63, Reg0x64) (signed lower 9 bits) x 2mV 10-bit ADC ADC Data (9:0) Gain Selection (Reg0x2B - 0x2E)

80a3e031 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9M001_DS_2.fm - Rev.C 7/05 EN 23 ©2004 Micron Technology, Inc. All rights reserved. MT9M001 - 1/2-Inch Megapixel Digital Image Sensor Registers Registers Table 8: Black Level Registers Register bit Description Reg0x5F This register controls the operation of the black level calibration thresholds. 15 No gain dependence. 1 = Thres_lo is set by the programmed value of bits 5:0, Thres_hi is reset to the programmed value (bits 14:8) after every black level average restart. 0 = Thres_lo and Thres_hi are set automatically as described below. 14:8 Thres_hi — maximum allowed black level in ADC LSBs (default = Thres_lo + 5). Black level maximum is set to this value when bit 7 = 1, black level maximum is reset to this value after every black level average restart if bit 15 = 1 and bit 7 = 0. 7 1 = override automatic Thres_hi and Thres_lo adjust (Thres_hi always = bits 14:8, Thres_lo always = bits 5:0). 0 = automatic Thres_hi and Thres_lo adjustment. 5:0 Thres_lo— Lower threshold for black level in ADC LSBs. Under default automatic operation (bit 7 = 0, bit 15 = 0), Thres_lo = RegGainmax/4 x (RegGainmax, bit 6 +1) x (RegGainmax, bit 7 +1), where RegGainmax is the maximum of the four independent gain register settings. Whenever a jump in the calibration causes the black level data to change from below Thres_lo to above Thres_hi, Thres_hi is adjusted according to the following: If new black level < 64: Thres_hi = Thres_lo + 2 + (2 x Delta), where Delta = new black level - Thres_lo If new black level > 63 and < 119: Thres_hi = new black level + 4 If new black level > 119: Thres_hi = 123 After any recalculation of the black level and average restart, Thres_hi is reset to either Thres_lo + 5 (automatic, default mode), Thres_hi (bit 7 = 1). Reg0x62, bit 11 will override this. Reg0x62 This register is used to control the automatic black level calibration circuitry. 15 1 = do not perform the rapid black level sweep on new gain settings. 0 = normal operation.

14 Reserved

— default is 0; do not change. 13 Reserved— default is 0; do not change. 12 1 = start a new running digitally filtered average for the black level (this is internally reset to “0” immediately), and do a rapid sweep to find the new starting point. 11 1 = do not reset the upper threshold after a black level recalculation sweep. 0 = reset the upper threshold after a black level recalculation sweep (default). 10:3 Reserved— default is 1; do not change. 2:1 Force/disable black level calibration. 00 = apply black level calibration during ADC operation only (default). 10 = apply black level calibration continuously. X1 = disable black level correction (Offset Correction Voltage = Skew Voltage = 0.0V). (In this case, no black level correction is possible). 0 Manual override of black level correction. 1 = override automatic black level correction with programmed values. 0 = normal operation (default).

80a3e031 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9M001_DS_2.fm - Rev.C 7/05 EN 24 ©2004 Micron Technology, Inc. All rights reserved. MT9M001 - 1/2-Inch Megapixel Digital Image Sensor Registers Reg0x60, Reg0x61, Reg0x63, Reg0x64 These registers contain the 9-bit signed black level calibration values. In normal operation, these values are calculated at the beginning of each frame. However, if Reg0x62, bit 0 is set to “1,” these registers can be written to, overriding the automatic black level calculation. This feature can be used in conjunction with readout of the black rows (Reg0x20, bit 11) if the user would like to use an external black level calibration circuit. The offset correction voltage is generated according to the following formula: Offset Correction Voltage = (9-bit signed calibration value, -256 to 255) x (2mV x Enable bit) two’s complement, if bit 8 = 1, Offset = bits [0:7] - 256 ADC input voltage = Pixel Output Voltage x Analog Gain - Offset Correction Voltage Registers Table 8: Black Level Registers (continued) Register bit Description

80a3e031 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9M001_DS_2.fm - Rev.C 7/05 EN 26 ©2004 Micron Technology, Inc. All rights reserved. MT9M001 - 1/2-Inch Megapixel Digital Image Sensor Electrical Specifications Electrical Specifications Data Output and Propagation Delays By default, the MT9M001 launches pixel data, FRAME_VALID and LINE_VALID with the rising edge of PIXCLK. The expectation is that the user captures DOUT[7:0], FRAME_VALID and LINE_VALID using the rising edge of PIXCLK. Figure 17: Data Output Timing Diagram Table 9: DC Electrical Characteristics (DC Setup Conditions: fCLKIN = 48 MHz, VDD = 3.3V, VAA = 3.3V, VAAPIX = 3.3V, TA = 25°C) Symbol Definition Condition Min Typ Max Units VDD Core digital voltage 33 . 3 3 . 6 V VAA Analog voltage 33 . 3 3 . 6 V VAAPIX Pixel supply voltage 33 . 3 3 . 6 V VIH Input high voltage VPWR - 0.3 V PWR + 0.3 V VIL Input low voltage -0.3 0.8 V IIN Input leakage current No Pull-up Resistor; V IN = VDD or DGND -15 15 µA VOH Output high voltage VPWR - 0.2 — V VOL Output low voltage 0.2 V IOZ Tri-state output leakage current —1 5 µ A IDD Digital operating current —2 0 2 4m A IAA Analog operating current —8 5 1 1 0 m A IAAPIX Pixel supply current —5 1 0 m A CLKIN PIXCLK tR tFtCLKIN Data[0-7] Frame Valid/ Line Valid XXXXXX XXX XXX XXXXXX Note: Frame_Valid leads Line_Valid by 242 PIXCLKs. Note: Frame_Valid trails Line_Valid (1+ Reg0x05-19) PIXCLKS. tCP tPFL tPLL tFVS tPD tOH P0 P1 P2 PN tLVS tOS tPFH tPLH T

80a3e031 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9M001_DS_2.fm - Rev.C 7/05 EN 27 ©2004 Micron Technology, Inc. All rights reserved. MT9M001 - 1/2-Inch Megapixel Digital Image Sensor Electrical Specifications Note: 1Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Expo- sure to absolute maximum rating conditions for extended periods may affect reliability. ISTDBYD Digital standby current STDBY = V DD, CLKIN = 0 MHz —9 2 0 m A ISTDBYD W/CLK Digital standby current STDBY = V DD, CLKIN = 48 MHz —5 5 1 2 5 µ A ISTDBYDA Analog standby current STDBY = V DD —8 0 1 0 0 µ A Table 10: AC Electrical Characteristics (AC Setup Conditions: fCLKIN= 48 MHz, VDD = 3.3V, VAA = 3.3V, VAAPIX = 3.3V, Output Load = 30pF , TA = 25°C)) Symbol Definition Condition Min Typ Max Unit fCLKIIN Input clock frequency 1— 4 8 M H z tCLKIN Input clock period 1000 — 20.83 ns T PIXCLK period 1000 — 20.83 ns tR Input clock rise time 4V / n s tF Input clock fall time —4 V / n s Clock duty cycle 45/55 50/50 55/45 % tCP CLKIN to PIXCLK propagation delay —1 0 — n s tPD PIXCLK to data valid ——1 n s tPFH PIXCLK to FV high ——7 n s tPLH PIXCLK to LV high ——7 n s tPFL PIXCLK to FV low ——3 n s tPLL PIXCLK to LV low ——2 n s tOS Setup time for data befo re falling edge of PIXCLK T/2 -1 T/2 T/2 +1 ns tOH Hold time for data after falling edge of PIXCLK T/2 -1 T/2 T/2 +1 ns tFVS Setup time for FV befo re falling edge of PIXCLK 23 — n s tLVS Setup time for LV befo re falling edge of PIXCLK 23 — n s CLOAD Load capacitance 30 pF Table 11: Absolute Maximum Ratings Symbol Parameter Rating UnitMIN MAX TOP Operating temperature 07 0 ° C TSTG1 Storage temperature –40 125 °C Table 9: DC Electrical Characteristics (continued) (DC Setup Conditions: fCLKIN = 48 MHz, VDD = 3.3V, VAA = 3.3V, VAAPIX = 3.3V, TA = 25°C) Symbol Definition Condition Min Typ Max Units

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 prodmktg@micron.com www.micron.com Customer Comment Line: 800-932-4992 Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. This data sheet contains minimum and maximum limits specified over the complete power supply and temperature range for production devices. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. MT9M001 - 1/2-Inch Megapixel Digital Image Sensor Electrical Specifications 80a3e031 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9M001_DS_2.fm - Rev.C 7/05 EN 31 ©2004 Micron Technology, Inc. All rights reserved. Figure 27: 48-pin CLCC Package Outline Drawing Note: All dimensions in millimeters. SEATING PLANE 1.016 TYP 148 11.176 LID MATERIAL: BOROSILICATE GLASS 0.55 THICKNESS SUBSTRATE MATERIAL: ALUMINA CERAMIC 11.176 5.588 7.11 47X 1.02

1.016 TYP

48X 0.50 7.125 ±0.125 6.398 ±0.125 13.00 CTR 13.00 CTR 2.00 2.21 ±0.27 48X R 0.197.11 14.220 +0.300 -0.125 14.220 +0.300 -0.125 5.588 A D C B OPTICAL AREA OPTICAL CENTER PACKAGE AND DIE CENTER MAXIMUM ROTATION OF OPTICAL AREA RELATIVE TO PACKAGE EDGES B AND C : 1º MAXIMUM TILT OF OPTICAL AREA RELATIVE TO SEATING PLANE A : 50 MICRONS MAXIMUM TILT OF OPTICAL AREA RELATIVE TO TOP OF COVER D : 50 MICRONS

0.015 FOR

0.712 FOR

1.270 ±0.0851

0.44 FOR

0.94 ±0.261 LEAD FINISH: GOLD PLATING,

20 MICRO INCHES

NOTE: 1. THESE DIMENSIONS ARE NON ACCUMULATIVE

80a3e031 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9M001_DS_2.fm - Rev.C 7/05 EN 32 ©2004 Micron Technology, Inc. All rights reserved. MT9M001 - 1/2-Inch Megapixel Digital Image Sensor

Revision History

Rev C, 06/2005  Remove color information  Updated Table 1, Key Performance Parameters, on page 1  Updated Table 5, Register List and Default Values, on page 13  Updated Table 6, Register Description, on page 14  Updated Figure 12, Readout of Six Rows in Normal and Row Mirror Output Mode, on page 21  Deleted Figure 13, Readout of Eight Pixels in Normal and Column Skip Output Mode, on page 22  Updated Table 10, AC Electrical Characteristics, on page 27  Updated Figure 25, Image Center Offset, on page 30  Updated Figure 27, 48-pin CLCC Package Outline Drawing, on page 31 Rev B, 05/2005  Page 1, remove PRELIMINARY disclaimer  Page 1, add Key Performance Parameters table, add APPLICATIONS  Page 2, add Table of Contents  Page 6, update Pin Description table  Page 11, update Serial Bus Description  Page 12, update Timing Diagram Showing a Read from Reg0x09; Returned Value 0x0284 figure  Page 13, update Register List and Default Values table  Page 14, update Register Description Table (add Test Data-Reg0x32[11:2], update Output Control-Reg0x07[6]  Page 28, update AC and DC Elec trical Characteristics table  Page 29, add Figure 17, Data Output Timing Di agram, and Absolute Maximum Ratings, Table 11  Page 30, update Propagation Delay for Frame_Valid and Li ne_Valid Signals (Data Output and Propagation Delays  Page 32, delete Quantum Efficiency figure (Color)  Page 33, update Figure 27, 48-pin CLCC Package Outline Drawing Rev A, Preliminary 11/2003  Initial Release of document