MT9LD272A

MT9LD272A MICRON | Alldatasheet

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Technical content

2, 4 Meg x 72 Nonbuffered DRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice. DM60.p65 – Rev. 6/98  1998, Micron Technology, Inc.1 2, 4 MEG x 72 NONBUFFERED DRAM DIMMs OBSOLETE DRAM MODULE MT9LD272A(X), MT18LD472A(X) For the latest data sheet revisions, please refer to the Micron Web site: www.micron.com/mti/msp/html/datasheet.html

FEATURES

• JEDEC-standard, eight-CAS#, ECC pinout in a 168-pin, dual in-line memory module (DIMM)
• 16MB (2 Meg x 72) and 32MB (4 Meg x 72)
• Nonbuffered
• High-performance CMOS silicon-gate process
• Single +3.3V ±0.3V power supply
• All inputs, outputs and clocks are TTL-compatible
• Refresh modes: RAS#-ONLY, CAS#-BEFORE-RAS# (CBR) and HIDDEN
• 2,048-cycle refresh distributed across 32ms
• FAST-PAGE-MODE (FPM) or Extended Data-Out (EDO) PAGE MODE access cycles
• Serial presence-detect (SPD) OPTIONS MARKING
• Package 168-pin DIMM (gold) G
• Timing 50ns access -5* 60ns access -6
• Access Cycles FAST PAGE MODE None EDO PAGE MODE X *EDO version only PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL 1V SS 43 V SS 85 V SS 127 V SS

2 DQ0 44 OE2# 86 DQ32 128 RFU

3 DQ1 45 RAS2# 87 DQ33 129 NC/RAS3#*

4 DQ2 46 CAS2# 88 DQ34 130 CAS6#

5 DQ3 47 CAS3# 89 DQ35 131 CAS7#

6V DD 48 WE2# 90 V DD 132 RFU

7 DQ4 49 V DD 91 DQ36 133 V DD

8 DQ5 50 NC 92 DQ37 134 NC

9 DQ6 51 NC 93 DQ38 135 NC

10 DQ7 52 CB2 94 DQ39 136 CB6

11 DQ8 53 CB3 95 DQ40 137 CB7

12 V SS 54 V SS 96 V SS 138 V SS

13 DQ9 55 DQ16 97 DQ41 139 DQ48

14 DQ10 56 DQ17 98 DQ42 140 DQ49

15 DQ11 57 DQ18 99 DQ43 141 DQ50

16 DQ12 58 DQ19 100 DQ44 142 DQ51

17 DQ13 59 V DD 101 DQ45 143 V DD

18 V DD 60 DQ20 102 V DD 144 DQ52

19 DQ14 61 NC 103 DQ46 145 NC

20 DQ15 62 RFU 104 DQ47 146 RFU

21 CB0 63 NC 105 CB4 147 NC

22 CB1 64 V SS 106 CB5 148 V SS

23 V SS 65 DQ21 107 V SS 149 DQ53

24 NC 66 DQ22 108 NC 150 DQ54

25 NC 67 DQ23 109 NC 151 DQ55

26 V DD 68 V SS 110 V DD 152 V SS

27 WE0# 69 DQ24 111 RFU 153 DQ56

28 CAS0# 70 DQ25 112 CAS4# 154 DQ57

29 CAS1# 71 DQ26 113 CAS5# 155 DQ58

30 RAS0# 72 DQ27 114 NC 156 DQ59

31 OE0# 73 V DD 115 RFU 157 V DD

32 V SS 74 DQ28 116 V SS 158 DQ60

33 A0 75 DQ29 117 A1 159 DQ61

34 A2 76 DQ30 118 A3 160 DQ62

35 A4 77 DQ31 119 A5 161 DQ63

36 A6 78 V SS 120 A7 162 V SS

37 A8 79 NC 121 A9 163 NC

38 A10 80 NC 122 NC (A11) 164 NC

39 NC (A12) 81 NC 123 NC (A13) 165 SA0

40 V DD 82 SDA 124 V DD 166 SA1

41 V DD 83 SCL 125 RFU 167 SA2

42 RFU 84 V DD 126 RFU 168 V DD

PIN ASSIGNMENT (Front View) 168-Pin DIMM KEY TIMING PARAMETERS EDO Operating Mode SPEED tRC tRAC tPC tAA tCAC tCAS -5 84ns 50ns 20ns 25ns 13ns 8ns -6 104ns 60ns 25ns 30ns 15ns 10ns FPM Operating Mode SPEED tRC tRAC tPC tAA tCAC tRP -6 110ns 60ns 35ns 30ns 15ns 40ns NOTE: Pin symbols in parentheses are not used on these modules but may be used for other modules in this product family. They are for reference only.

2, 4 Meg x 72 Nonbuffered DRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice. DM60.p65 – Rev. 6/98  1998, Micron Technology, Inc.2 2, 4 MEG x 72 NONBUFFERED DRAM DIMMs OBSOLETE PART NUMBERS EDO Operating Mode PART NUMBER CONFIGURATION SPEED MT9LD272AG-5 X 2 Meg x 72 ECC 50ns MT9LD272AG-6 X 2 Meg x 72 ECC 60ns MT18LD472AG-5 X 4 Meg x 72 ECC 50ns MT18LD472AG-6 X 4 Meg x 72 ECC 60ns FPM Operating Mode PART NUMBER CONFIGURATION SPEED MT9LD272AG-6 2 Meg x 72 ECC 60ns MT18LD472AG-6 4 Meg x 72 ECC 60ns EDO PAGE MODE EDO PAGE MODE, designated by the “X” version, is an accelerated FAST-PAGE-MODE cycle. The primary advan- tage of EDO is the availability of data-out even after CAS# goes back HIGH. EDO provides for CAS# precharge time tCP) to occur without the output data going invalid. This elimination of CAS# output control provides for pipelined READs. FAST-PAGE-MODE modules have traditionally turned the output buffers off (High-Z) with the rising edge of CAS#. EDO-PAGE-MODE DRAMs operate like FAST- PAGE-MODE DRAMs, except data will remain valid or become valid after CAS# goes HIGH during READs, pro- vided RAS# and OE# are held LOW. If OE# is pulsed while RAS# and CAS# are LOW, data will toggle from valid data to High-Z and back to the same valid data. If OE# is toggled or pulsed after CAS# goes HIGH while RAS# remains LOW, data will transition to and remain High-Z. During an application, if the DQ outputs are wire OR’d, OE# must be used to disable idle banks of DRAMs. Alterna- tively, pulsing WE# to the idle banks during CAS# HIGH time will also High-Z the outputs. Independent of OE# control, the outputs will disable after tOFF, which is refer- enced from the rising edge of RAS# or CAS#, whichever occurs last. (Refer to the 4 Meg x 4 [MT4LC4M4E8] DRAM data sheet for additional information on EDO functional- ity.) REFRESH Returning RAS# and CAS# HIGH terminates a memory cycle and decreases chip current to a reduced standby level. Also, the chip is preconditioned for the next cycle during the RAS# HIGH time. Correct memory cell data is pre- served by maintaining power and executing any RAS# cycle (READ, WRITE) or RAS# REFRESH cycle (RAS#- ONLY, CBR or HIDDEN) so that all combinations of RAS# addresses (A0-A9/A10) are executed at least every tREF, regardless of sequence. The CBR REFRESH cycle will in- voke the internal refresh counter for automatic RAS# ad- dressing. SERIAL PRESENCE-DETECT OPERATION This module family incorporates serial presence-detect (SPD). The SPD function is implemented using a 2,048-bit EEPROM. This nonvolatile storage device contains 256 bytes. The first 128 bytes can be programmed by Micron to identify the module type and various DRAM organizations and timing parameters. The remaining 128 bytes of storage are available for use by the customer. System READ/ WRITE operations between the master (system logic) and the slave EEPROM device (DIMM) occur via a standard IIC bus using the DIMM’s SCL (clock) and SDA (data) signals, GENERAL DESCRIPTION The MT9LD272A(X) and MT18LD472A(X) are randomly accessed 16MB and 32MB memories organized in a x72 configuration. They are specially processed to operate from 3V to 3.6V for low-voltage memory systems. During READ or WRITE cycles, each bit is uniquely addressed through the 21/22 address bits, which are en- tered 11 bits (A0 -A10) at RAS# time and 10/11 bits (A0- A10) at CAS# time. READ and WRITE cycles are selected with the WE# input. A logic HIGH on WE# dictates read mode, while a logic LOW on WE# dictates write mode. During a WRITE cycle, data-in (D) is latched by the falling edge of WE# or CAS#, whichever occurs last. An EARLY WRITE occurs when WE# is taken LOW prior to CAS# falling. A LATE WRITE or READ-MODIFY-WRITE occurs when WE# falls after CAS# was taken LOW. During EARLY WRITE cycles, the data-outputs (Q) will remain High-Z regardless of the state of OE#. During LATE WRITE or READ-MODIFY- WRITE cycles, OE# must be taken HIGH to disable the data- outputs prior to applying input data. If a LATE WRITE or READ-MODIFY-WRITE is attempted while keeping OE# LOW, no WRITE will occur, and the data-outputs will drive read data from the accessed location. FAST PAGE MODE FAST-PAGE-MODE operations allow faster data opera- tions (READ or WRITE) within a row-address-defined page boundary. The FAST-PAGE-MODE cycle is always initiated with a row address strobed in by RAS#, followed by a column address strobed in by CAS#. Additional col- umns may be accessed by providing valid column addresses, strobing CAS# and holding RAS# LOW , thus executing faster memory cycles. Returning RAS# HIGH terminates the FAST-PAGE-MODE operation.

2, 4 Meg x 72 Nonbuffered DRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice. DM60.p65 – Rev. 6/98  1998, Micron Technology, Inc.4 2, 4 MEG x 72 NONBUFFERED DRAM DIMMs OBSOLETE FUNCTIONAL BLOCK DIAGRAM MT9LD272A(X) (16MB) A0-A10 OE2# WE2# CAS4# RAS2# CAS5# CAS7# CAS6# U1-U9 = MT4LC2M8B1 FAST PAGE MODE U1-U9 = MT4LC2M8E7 EDO PAGE MODE OE0# WE0# CAS0# RAS0# CAS1# CAS3# CAS2# 11 11 11 11 11 11 11 11 DQ0-DQ7 DQ8-DQ15 CB0-CB7 DQ16-DQ23 DQ32-DQ39 DQ40-DQ41 DQ48-DQ55 DQ56-DQ63 DQ24-DQ31 A0–A10 WE# OE# RAS# CAS# DQ0-DQ7 A0–A10 WE# OE# RAS# CAS# DQ0-DQ7 A0–A10 WE# OE# RAS# CAS# DQ0-DQ7 A0–A10 WE# OE# RAS# CAS# DQ0-DQ7 A0–A10 WE# OE# RAS# CAS# DQ0-DQ7 A0–A10 WE# OE# RAS# CAS# DQ0-DQ7 A0–A10 WE# OE# RAS# CAS# DQ0-DQ7 A0–A10 WE# OE# RAS# CAS# DQ0-DQ7 A0–A10 WE# OE# RAS# CAS# SPD SCL SDA SA0 SA1 SA2 A0 A1 A2 VDD VSS U1-U9 U1-U9

2, 4 Meg x 72 Nonbuffered DRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice. DM60.p65 – Rev. 6/98  1998, Micron Technology, Inc.5 2, 4 MEG x 72 NONBUFFERED DRAM DIMMs OBSOLETE FUNCTIONAL BLOCK DIAGRAM MT18LD472A(X) (32MB) U1-U18 = MT4LC4M4B1 FAST PAGE MODE U1-U18 = MT4LC4M4E8 EDO PAGE MODE 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 OE0# CAS1# CAS2# CAS3# WE0# CAS0# OE2# CAS5# CAS6# CAS7# WE2# CAS4# A0-A10 RAS0# RAS2# SPD SCL SDA A0 A1 A2 SA0 SA1 SA2 WE# OE# RAS# CAS# DQ0-DQ3 A0–A10 WE# OE# RAS# CAS# DQ0-DQ3 A0–A10 WE# OE# RAS# CAS# DQ0-DQ3 A0–A10 WE# OE# RAS# CAS# DQ0-DQ3 A0–A10 WE# OE# RAS# CAS# DQ0-DQ3 A0–A10 WE# OE# RAS# CAS# DQ0-DQ3 A0–A10 WE# OE# RAS# CAS# DQ0-DQ3 A0–A10 WE# OE# RAS# CAS# DQ0-DQ3 A0–A10 WE# OE# RAS# CAS# DQ0-DQ3 A0–A10 WE# OE# RAS# CAS# DQ0-DQ3 U10 A0–A10 WE# OE# RAS# CAS# DQ0-DQ3 U11 A0–A10 WE# OE# RAS# CAS# DQ0-DQ3 U12 A0–A10 WE# OE# RAS# CAS# DQ0-DQ3 U13 A0–A10 WE# OE# RAS# CAS# DQ0-DQ3 U14 A0–A10 WE# OE# RAS# CAS# DQ0-DQ3 U15 A0–A10 WE# OE# RAS# CAS# DQ0-DQ3 U16 A0–A10 WE# OE# RAS# CAS# DQ0-DQ3 U17 A0–A10 WE# OE# RAS# CAS# DQ0-DQ3 DQ0-DQ3 DQ4-DQ7 DQ8-DQ11 DQ12-DQ15 DQ16-DQ19 DQ20-DQ23 DQ24-DQ27 DQ28-DQ31 DQ32-DQ35 DQ36-DQ39 DQ40-DQ43 DQ44-DQ47 CB4-CB7 CB4-CB7 DQ48-DQ51 DQ52-DQ55 DQ56-DQ59 DQ06-DQ63 U18 A0–A10 VDD VSS U1-U18 U1-U18

2, 4 Meg x 72 Nonbuffered DRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice. DM60.p65 – Rev. 6/98  1998, Micron Technology, Inc.6 2, 4 MEG x 72 NONBUFFERED DRAM DIMMs OBSOLETE PIN DESCRIPTIONS PIN NUMBERS SYMBOL TYPE DESCRIPTION 30, 45 RAS0#, RAS2# Input Row-Address Strobe: RAS# is used to clock-in the row- address bits. Two RAS# inputs allow for one x72 bank or two x36 banks. 28, 29, 46, 47, 112, CAS0#-CAS7# Input Column-Address Strobe: CAS# is used to clock-in the 113, 130, 131 column-address bits, enable the DRAM output buffers and strobe the data inputs on WRITE cycles. Eight CAS# inputs allow byte access control for any memory bank configuration. 27, 48 WE0#, WE2# Input Write Enable: WE# is the READ/WRITE control for the DQ pins. If WE# is LOW prior to CAS# going LOW, the access is an EARLY WRITE cycle. If WE# is HIGH while CAS# is LOW, the access is a READ cycle, provided OE# is also LOW. If WE# goes LOW after CAS# goes LOW, then the cycle is a LATE WRITE cycle. A LATE WRITE cycle is generally used in conjunction with a READ cycle to form a READ-MODIFY-WRITE cycle. 31, 44 OE0#, OE2# Input Output Enable: OE# is the input/output control for the DQ pins. These signals may be driven, allowing LATE WRITE cycles. 33-38, 117-121 A0-A10 Input Address Inputs: These inputs are multiplexed and clocked by RAS# and CAS#. 2-5, 7-11, 13-17, 19-20, DQ0-DQ63 Input/ Data I/O: For WRITE cycles, DQ0-DQ63 act as inputs to 55-58, 60, 65-67, 69-72, Output the addressed DRAM location. For READ access cycles, 74-77, 86-89,91-95, DQ0-DQ63 act as outputs for the addressed DRAM 97-101, 103-104, location. 139-142, 144, 149-151, 153-156, 158-161 21-22, 52-53, 105-106, CB0-CB7 Input/Output Check Bits. 136-137 42, 62, 111, 115, RFU – Reserved for Future Use: These pins should be left 125-126, 128, 132, 146 unconnected. 6, 18, 26, 40, 41, 49, 59, VDD Supply Power Supply: +3.3V ±0.3V. 73, 84, 90, 102, 110, 124, 133, 143, 157, 168 1, 12, 23, 32, 43, 54, 64, VSS Supply Ground. 68, 78, 85, 96, 107, 116, 127, 138, 148, 152, 162 82 SDA Input/Output Serial Presence-Detect Data. SDA is a bidirectional pin used to transfer addresses and data into and data out of the presence-detect portion of the module. 83 SCL Input Serial Clock for Presence-Detect. SCL is used to synchronize the presence-detect data transfer to and from the module. 165-167 SA0-SA2 Input Presence-Detect Address Inputs. These pins are used to configure the presence-detect device.

2, 4 Meg x 72 Nonbuffered DRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice. DM60.p65 – Rev. 6/98  1998, Micron Technology, Inc.7 2, 4 MEG x 72 NONBUFFERED DRAM DIMMs OBSOLETE SERIAL PRESENCE-DETECT MATRIX BYTE DESCRIPTION ENTRY (VERSION) BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 HEX

0 NUMBER OF BYTES USED BY MICRON 128 10000000 8 0

1 TOTAL NUMBER OF SPD MEMORY BYTES 256 00001000 0 8

2 MEMORY TYPE FAST PAGE MODE 00000001 0 1

EDO PAGE MODE 00000010 0 2

3 NUMBER OF ROW ADDRESSES 11 00001011 0 B

4 NUMBER OF COLUMN ADDRESSES 10 (16MB) 00001010 0 A

11 (32MB) 00001011 0 B

5 NUMBER OF BANKS 1 00000001 0 1

6 DATA WIDTH x72 01001000 4 8

7 DATA WIDTH (continued) NONE 00000000 0 0

8 VOLTAGE INTERFACE LVTTL 00000001 0 1

9 RAS# ACCESS TIME ( tRAC) 50ns (-5) 00110010 3 2

60ns (-6) 00111100 3 C

10 CAS# ACCESS TIME ( tCAC) 13ns (-5) 00001101 0 D

15ns (-6) 00001111 0 F

11 MODULE CONFIGURATION TYPE ECC 00000010 0 2

12 REFRESH RATES 15.625 µs/NORMAL 00000000 0 0

13 DRAM WIDTH (PRIMARY DRAM) x8 (16MB) 00001000 0 8

x4 (32MB) 00000100 0 4

14 ERROR CHECKING DRAM DATA WIDTH x8 (16MB) 00001000 0 8

x4 (32MB) 00000100 0 4 15-61 RESERVED 00000000 0 0 62 SPD REVISION REV. 0 00000000 0 0

63 CHECKSUM FOR BYTES 0-62 16MB -5 (EDO) 00111010 3 A

16MB -6 (EDO) 01000110 4 6 16MB -6 (FPM) 01000101 4 5 32MB -5 (EDO) 00110011 3 3 32MB -6 (EDO) 00111111 3 F 32MB -6 (FPM) 00111110 3 E

64 MANUFACTURER’S JEDEC ID CODE MICRON 00101100 2 C

65-71 MANUFACTURER’S JEDEC CODE (CONT.) 11111111 F F

72 MANUFACTURING LOCATION 00000001 0 1

73-90 MODULE PART NUMBER (ASCII) xxxxxxxx x x

91 PCB IDENTIFICATION CODE 1 00000001 0 1

92 IDENTIFICATION CODE (CONT.) 0 00000000 0 0

93 YEAR OF MANUFACTURE IN BCD xxxxxxxx x x

94 WEEK OF MANUFACTURE IN BCD xxxxxxxx x x

95-98 MODULE SERIAL NUMBER xxxxxxxx x x 99-125 MANUFACTURE SPECIFIC DATA (RSVD) ––––––––– NOTE: 1. “1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW.” 2. x = Variable Data.

2, 4 Meg x 72 Nonbuffered DRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice. DM60.p65 – Rev. 6/98  1998, Micron Technology, Inc.8 2, 4 MEG x 72 NONBUFFERED DRAM DIMMs OBSOLETE ABSOLUTE MAXIMUM RATINGS* Voltage on Inputs or I/O Pins *Stresses greater than those listed under “Absolute Maxi- mum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indi- cated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS (Notes: 1) (VDD = +3.3V ±0.3V) PARAMETER/CONDITION SYMBOL SIZE MIN MAX UNITS NOTES SUPPLY VOLTAGE V DD ALL 3 3.6 V INPUT HIGH VOLTAGE: Logic 1; All inputs V IH ALL 2 V DD + 0.3 V 30 INPUT LOW VOLTAGE: Logic 0; All inputs V IL ALL -0.5 0.8 V 30 INPUT LEAKAGE CURRENT: CAS0#-CAS7# I I1 16MB -4 4 µA Any input 0V ≤ VIN ≤ VDD + 0.3V 32MB -6 6 (All other pins not under test = 0V) A0-A10 I I2 16MB -18 18 µA 32MB -36 36 WE0#, WE2#, I I3 16MB -10 10 µA OE0#, OE2# 32MB -18 18 RAS0#-RAS3# I I4 16MB -10 10 32MB -18 18 µA OUTPUT LEAKAGE CURRENT: DQ0-DQ63, I OZ 16MB -5 5 µA DQ is disabled; 0V ≤ VOUT ≤ VDD + 0.3V CB0-CB7 32MB -5 5 OUTPUT LEVELS: V OH ALL 2.4 – V Output High Voltage (IOUT = -2mA) Output Low Voltage (IOUT = 2mA) V OL ALL – 0.4 V

2, 4 Meg x 72 Nonbuffered DRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice. DM60.p65 – Rev. 6/98  1998, Micron Technology, Inc.9 2, 4 MEG x 72 NONBUFFERED DRAM DIMMs OBSOLETE ICC OPERATING CONDITIONS AND MAXIMUM LIMITS (Notes: 1, 5, 6) (VDD = +3.3V ±0.3V) PARAMETER/CONDITION SYMBOL SIZE -5* -6 UNITS NOTES STANDBY CURRENT: TTL I CC 1 16MB 9 9 mA (RAS# = CAS# = VIH) 32MB 18 18 STANDBY CURRENT: CMOS I CC 2 16MB 9 9 mA (RAS# = CAS# = VDD - 0.2V) 32MB 9 9 OPERATING CURRENT: Random READ/WRITE I CC 3 16MB 990 900 mA 3, 24 Average power supply current 32MB 1,980 1,800 (RAS#, CAS#, address cycling: tRC = tRC [MIN]) OPERATING CURRENT: FAST PAGE MODE I CC 4 16MB – 720 mA 3, 24 Average power supply current 32MB – 1,440 (RAS# = VIL, CAS#, address cycling: tPC = tPC [MIN]) OPERATING CURRENT: EDO PAGE MODE (“X” version only) I CC 5 16MB 990 900 mA 3, 24 Average power supply current (X only) 32MB 1,980 1,800 (RAS# = VIL, CAS#, address cycling: tPC = tPC [MIN]) REFRESH CURRENT: RAS#-ONLY I CC 6 16MB 990 900 mA 3, 24 Average power supply current 32MB 1,980 1,800 (RAS# cycling, CAS# = VIH: tRC = tRC [MIN]) REFRESH CURRENT: CBR I CC 7 16MB 990 900 mA 3, 4 Average power supply current 32MB 1,980 1,800 (RAS#, CAS#, address cycling: tRC = tRC [MIN]) * EDO version only MAX

2, 4 Meg x 72 Nonbuffered DRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice. DM60.p65 – Rev. 6/98  1998, Micron Technology, Inc.10 2, 4 MEG x 72 NONBUFFERED DRAM DIMMs OBSOLETE CAPACITANCE PARAMETER SYMBOL 16MB 32MB UNITS NOTES Input Capacitance: A0-A10 C I1 51 96 pF 2 Input Capacitance: WE0#, WE2#, OE0#, OE2# C I2 39 67 pF 2 Input Capacitance: RAS0#, RAS2# C I3 39 67 pF 2 Input Capacitance: CAS0#-CAS7# C I4 17 24 pF 2 Input Capacitance: SCL, SA0-SA2 C I5 66 p F 2 Input/Output Capacitance: DQ0-DQ63, CB0-CB7, SDA C IO 10 10 pF 2 MAX FAST PAGE MODE AC ELECTRICAL CHARACTERISTICS AC CHARACTERISTICS - FAST PAGE MODE OPTION -6 PARAMETER SYMBOL MIN MAX UNITS NOTES Access time from column address tAA 30 ns Column-address hold time (referenced to RAS#) tAR 45 ns Column-address setup time tASC 0 ns Row-address setup time tASR 0 ns Column address to WE# delay time tAWD 55 ns 23 Access time from CAS# tCAC 15 ns 14 Column-address hold time tCAH 10 ns CAS# pulse width tCAS 15 10,000 ns CAS# hold time (CBR Refresh) tCHR 10 ns 4 CAS# to output in Low-Z tCLZ 3 ns 25 CAS# precharge time tCP 10 ns 15 Access time from CAS# precharge tCPA 35 ns CAS# to RAS# precharge time tCRP 5 ns CAS# hold time tCSH 60 ns CAS# setup time (CBR Refresh) tCSR 5 ns 4 CAS# to WE# delay time tCWD 40 ns 23 WRITE command to CAS# lead time tCWL 15 ns Data-in hold time tDH 10 ns 22 Data-in setup time tDS 0 ns 22 Output disable tOD 3 15 ns Output enable tOE 15 ns OE# hold time from WE# during READ-MODIFY-WRITE cycle tOEH 15 ns 21 Output buffer turn-off delay tOFF 3 15 ns 19, 25, 26 OE# setup prior to RAS# during HIDDEN REFRESH cycle tORD 0 ns FAST-PAGE-MODE READ or WRITE cycle time tPC 35 ns

2, 4 Meg x 72 Nonbuffered DRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice. DM60.p65 – Rev. 6/98  1998, Micron Technology, Inc.11 2, 4 MEG x 72 NONBUFFERED DRAM DIMMs OBSOLETE FAST PAGE MODE AC ELECTRICAL CHARACTERISTICS AC CHARACTERISTICS - FAST PAGE MODE OPTION -6 PARAMETER SYMBOL MIN MAX UNITS NOTES FAST-PAGE-MODE READ-WRITE cycle time tPRWC 85 ns Access time from RAS# tRAC 60 ns 13 RAS# to column-address delay time tRAD 15 ns 17 Row-address hold time tRAH 10 ns RAS# pulse width tRAS 60 10,000 ns RAS# pulse width (FAST PAGE MODE) tRASP 60 125,000 ns Random READ or WRITE cycle time tRC 110 ns RAS# to CAS# delay time tRCD 20 ns 16 READ command hold time (referenced to CAS#) tRCH 0 ns 18 READ command setup time tRCS 0 ns Refresh period (2,048 cycles) tREF 32 ms RAS# precharge time tRP 40 ns RAS# to CAS# precharge time tRPC 0 ns READ command hold time (referenced to RAS#) tRRH 0 ns 18 RAS# hold time tRSH 15 ns READ-WRITE cycle time tRWC 155 ns RAS# to WE# delay time tRWD 85 ns 23 WRITE command to RAS# lead time tRWL 15 ns Transition time (rise or fall) tT25 0 n s WRITE command hold time tWCH 10 ns WRITE command hold time (referenced to RAS#) tWCR 45 ns WE# command setup time tWCS 0 ns 23 WRITE command pulse width tWP 10 ns WE# hold time (CBR Refresh) tWRH 10 ns WE# setup time (CBR Refresh) tWRP 10 ns

2, 4 Meg x 72 Nonbuffered DRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice. DM60.p65 – Rev. 6/98  1998, Micron Technology, Inc.12 2, 4 MEG x 72 NONBUFFERED DRAM DIMMs OBSOLETE EDO PAGE MODE AC ELECTRICAL CHARACTERISTICS AC CHARACTERISTICS - EDO PAGE MODE OPTION -5 -6 PARAMETER SYMBOL MIN MAX MIN MAX UNITS NOTES Access time from column address tAA 25 30 ns Column-address setup to CAS# precharge tACH 12 15 ns Column-address hold time (referenced to RAS#) tAR 38 45 ns Column-address setup time tASC 0 0 ns Row-address setup time tASR 0 0 ns Column-address to WE# delay time tAWD 42 49 ns 23 Access time from CAS# tCAC 13 15 ns 14 Column-address hold time tCAH 8 10 ns CAS# pulse width tCAS 8 10,000 10 10,000 ns CAS# hold time (CBR Refresh) tCHR 8 10 ns 4 CAS# to output in Low-Z tCLZ 0 0 ns Data output hold after CAS# LOW tCOH 3 3 ns CAS# precharge time tCP 8 10 ns 15 Access time from CAS# precharge tCPA 28 35 ns CAS# to RAS# precharge time tCRP 5 5 ns CAS# hold time tCSH 38 45 ns CAS# setup time (CBR Refresh) tCSR 5 5 ns 4 CAS# to WE# delay time tCWD 28 35 ns 23 WRITE command to CAS# lead time tCWL 8 10 ns Data-in hold time tDH 8 10 ns 22 Data-in setup time tDS 0 0 ns 22 Output disable tOD 0 12 0 15 ns Output enable tOE 12 15 ns OE# hold time from WE# during tOEH 8 10/12* ns 21 READ-MODIFY-WRITE cycle OE# HIGH hold time from CAS# HIGH tOEHC 5 10 ns 21 OE# HIGH pulse width tOEP 5 5 ns OE# LOW to CAS# HIGH setup time tOES 4 5 ns Output buffer turn-off delay tOFF 0 12 0 15 ns 19, 26 OE# setup prior to RAS# tORD 0 0 ns during HIDDEN REFRESH cycle EDO-PAGE-MODE READ or WRITE cycle time tPC 20 25 ns EDO-PAGE-MODE READ-WRITE cycle time tPRWC 47 56 ns Access time from RAS# tRAC 50 60 ns 13 RAS# to column-address delay time tRAD 9 12 ns 17 Row-address hold time tRAH 9 10 ns RAS# pulse width tRAS 50 10,000 60 10,000 ns RAS# pulse width (EDO PAGE MODE) tRASP 50 125,000 60 125,000 ns Random READ or WRITE cycle time tRC 84 104 ns RAS# to CAS# delay time tRCD 11 14 ns 16 READ command hold time (referenced to CAS#) tRCH 0 0 ns 18 READ command setup time tRCS 0 0 ns Refresh period (2,048 cycles) tREF 32 32 ms RAS# precharge time tRP 30 40 ns

2, 4 Meg x 72 Nonbuffered DRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice. DM60.p65 – Rev. 6/98  1998, Micron Technology, Inc.13 2, 4 MEG x 72 NONBUFFERED DRAM DIMMs OBSOLETE EDO PAGE MODE AC ELECTRICAL CHARACTERISTICS AC CHARACTERISTICS - EDO PAGE MODE OPTION -5 -6 PARAMETER SYMBOL MIN MAX MIN MAX UNITS NOTES RAS# to CAS# precharge time tRPC 5 5 ns READ command hold time (referenced to RAS#) tRRH 0 0 ns 18 RAS# hold time tRSH 13 15 ns READ WRITE cycle time tRWC 116 140 ns RAS# to WE# delay time tRWD 67 79 ns 23 WRITE command to RAS# lead time tRWL 13 15 ns Transition time (rise or fall) tT2 5 0 2 5 0 n s WRITE command hold time tWCH 8 10 ns WRITE command hold time (referenced to RAS#) tWCR 38 45 ns WE# command setup time tWCS 0 0 ns 23 Output disable delay from WE# (CAS# HIGH) tWHZ 0 12 0 15 ns WRITE command pulse width tWP 5 5 ns WE# pulse to disable at CAS# HIGH tWPZ 10 10 ns WE# hold time (CBR Refresh) tWRH 8 10 ns WE# setup time (CBR Refresh) tWRP 8 10 ns

2, 4 Meg x 72 Nonbuffered DRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice. DM60.p65 – Rev. 6/98  1998, Micron Technology, Inc.14 2, 4 MEG x 72 NONBUFFERED DRAM DIMMs OBSOLETE SERIAL PRESENCE-DETECT EEPROM OPERATING CONDITIONS (Notes: 1) (VDD = +3.3V ±0.3V) PARAMETER/CONDITION SYMBOL MIN MAX UNITS NOTES SUPPLY VOLTAGE V DD 3 3.6 V INPUT HIGH VOLTAGE: Logic 1; All inputs V IH VDD × 0.7 VDD + 0.5 V INPUT LOW VOLTAGE: Logic 0; All inputs V IL -1 V DD × 0.3 V OUTPUT LOW VOLTAGE: I OUT = 3mA V OL – 0.4 V INPUT LEAKAGE CURRENT: V IN = GND to VDD ILI –1 0 µA OUTPUT LEAKAGE CURRENT: V OUT = GND to VDD ILO –1 0 µA STANDBY CURRENT: I SB –3 0 µA SCL = SDA = VDD - 0.3V; All other inputs = GND or 3.3V +10% POWER SUPPLY CURRENT: I CC –2 m A SCL clock frequency = 100 KHz SERIAL PRESENCE-DETECT EEPROM AC ELECTRICAL CHARACTERISTICS (Notes: 1) (VDD = +3.3V ±0.3V) PARAMETER/CONDITION SYMBOL MIN MAX UNITS NOTES SCL LOW to SDA data-out valid tAA 0.3 3.5 µs Time the bus must be free before a new transition can start tBUF 4.7 µs Data-out hold time tDH 300 ns SDA and SCL fall time tF 300 ns Data-in hold time tHD:DAT 0 µs Start condition hold time tHD:STA 4 µs Clock HIGH period tHIGH 4 µs Noise suppression time constant at SCL, SDA inputs tI 100 ns Clock LOW period tLOW 4.7 µs SDA and SCL rise time tR1 µs SCL clock frequency tSCL 100 KHz Data-in setup time tSU:DAT 250 ns Start condition setup time tSU:STA 4.7 µs Stop condition setup time tSU:STO 4.7 µs WRITE cycle time tWR 10 ms 28

2, 4 Meg x 72 Nonbuffered DRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice. DM60.p65 – Rev. 6/98  1998, Micron Technology, Inc.15 2, 4 MEG x 72 NONBUFFERED DRAM DIMMs OBSOLETE NOTES 1. All voltages referenced to V SS. 2. This parameter is sampled. V DD = +3.3V; f = 1 MHz. 3. I CC is dependent on output loading. Specified values are obtained with minimum cycle time and the outputs open. 4. Enables on-chip refresh and address counters. 5. The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range is ensured. 6. An initial pause of 100 µs is required after power-up, followed by eight RAS# REFRESH cycles (RAS#- ONLY or CBR with WE# HIGH), before proper device operation is ensured. The eight RAS# cycle wake-ups should be repeated any time the tREF refresh requirement is exceeded. 7. AC characteristics assume tT = 5ns for FPM and 2.5ns for EDO. 8. V IH (MIN) and VIL (MAX) are reference levels for measuring timing of input signals. Transition times are measured between V IH and VIL (or between VIL and VIH). 9. In addition to meeting the transition rate specifica- tion, all input signals must transit between VIH and VIL (or between VIL and VIH) in a monotonic manner. 10. If CAS# = VIH, data output is High-Z. 11. If CAS# = VIL, data output may contain data from the last valid READ cycle. 12. Measured with a load equivalent to two TTL gates and 100pF and VOL = 0.8V and VOH = 2V. 13. Requires that tAA and tRAC are not violated. 14. Requires that tAA and tCAC are not violated. 15. If CAS# is LOW at the falling edge of RAS#, Q will be maintained from the previous cycle. To initiate a new cycle and clear the data-out buffer, CAS# must be pulsed HIGH for tCP. 16. The tRCD (MAX) limit is no longer specified. tRCD (MAX) was specified as a reference point only. If tRCD was greater than the specified tRCD (MAX) limit, then access time was controlled exclusively by tCAC (tRAC [MIN] no longer applied). With or without the tRCD (MAX) limit, tAA and tCAC must always be met. 17. The tRAD (MAX) limit is no longer specified. tRAD (MAX) was specified as a reference point only. If tRAD was greater than the specified tRAD (MAX) limit, then access time was controlled exclusively by tAA (tRAC and tCAC no longer applied). With or without the tRAD (MAX) limit, tAA, tRAC and tCAC must always be met. 18. Either tRCH or tRRH must be satisfied for a READ cycle. 19. tOFF (MAX) defines the time at which the output achieves the open circuit condition and is not referenced to V OH or VOL. 20. A HIDDEN REFRESH may also be performed after a WRITE cycle. In this case, WE# = LOW and OE# = HIGH. 21. LATE WRITE and READ-MODIFY-WRITE cycles must have both tOD and tOEH met (OE# HIGH during WRITE cycle) in order to ensure that the output buffers will be open during the WRITE cycle. The DQs will provide the previously read data if CAS# remains LOW and OE# is taken back LOW after tOEH is met. If CAS# goes HIGH prior to OE# going back LOW, the DQs will remain open. 22. These parameters are referenced to CAS# leading edge in EARLY WRITE cycles and WE# leading edge in LATE WRITE or READ-MODIFY-WRITE cycles. 23. tWCS, tRWD, tAWD and tCWD are not restrictive operating parameters. tWCS applies to EARLY WRITE cycles. tRWD, tAWD and tCWD apply to READ-MODIFY-WRITE cycles. If tWCS ≥ tWCS (MIN), the cycle is an EARLY WRITE cycle and the data output will remain an open circuit throughout the entire cycle. If tWCS < tWSC (MIN) and tRWD ≥ tRWD (MIN), tAWD ≥ tAWD (MIN) and tCWD ≥ tCWD (MIN), the cycle is a READ-MODIFY-WRITE and the data output will contain data read from the selected cell. If neither of the above conditions is met, the state of data-out is indeterminate. OE# held HIGH and WE# taken LOW after CAS# goes LOW result in a LATE WRITE (OE#-controlled) cycle. tWCS, tRWD, tCWD and tAWD are not applicable in a LATE WRITE cycle. 24. Column address changed once each cycle. 25. The 3ns minimum parameter guaranteed by design. 26. With the FPM option, tOFF is determined by the first RAS# or CAS# signal to transition HIGH. In compari- son, tOFF on an EDO option is determined by the latter of the RAS# and CAS# signals to transition HIGH. 27. Applies to both FPM and EDO modules.

2, 4 Meg x 72 Nonbuffered DRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice. DM60.p65 – Rev. 6/98  1998, Micron Technology, Inc.16 2, 4 MEG x 72 NONBUFFERED DRAM DIMMs OBSOLETE NOTES (continued) 28. The SPD EEPROM WRITE cycle time (tWR) is the time from a valid stop condition of a write sequence to the end of the EEPROM internal erase/program cycle. During the WRITE cycle, the EEPROM bus interface circuit are disabled, SDA remains HIGH due to pull-up resistor, and the EEPROM does not respond to its slave address. 29. If OE# is tied permanently LOW, LATE WRITE or READ-MODIFY-WRITE operations are not possible. 30. V IH overshoot: VIH (MAX) = VDD + 2V for a pulse width ≤ 10ns, and the pulse width cannot be greater than one third of the cycle rate. VIL undershoot: VIL (MIN) = -2V for a pulse width ≤ 10ns, and the pulse width cannot be greater than one third of the cycle rate.

2, 4 Meg x 72 Nonbuffered DRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice. DM60.p65 – Rev. 6/98  1998, Micron Technology, Inc.17 2, 4 MEG x 72 NONBUFFERED DRAM DIMMs OBSOLETE READ CYCLE 27 /,/, /,/, /,/, /,/,/, /,/, tRRH /,/,/, /,/, tCLZ tCAC tRAC tAA VALID DATA OPEN tOFF tRCH ROW tRCS tASCtRAH tRAD tAR tCAH tRCD tCAS tRSH tCSH tRP tRC tRAS tCRP tASR ROW OPEN RAS# V V IH IL V V IH IL ADDR V V IH IL DQ V V OH OL V V IH IL /,/,/, /,/,/,/, /,/,/, /,/, tODtOE OE# V V IH IL COLUMN /,/,/, /,/,/,/, /,/, CAS# WE# /,/, /,/,/, /,/,/, NOTE 1 tACH DON’T CARE UNDEFINED NOTE: 1. For EDO, tOFF is referenced from rising edge of RAS# or CAS#, whichever occurs last. For FPM, tOFF is referenced from rising edge of RAS# or CAS#, whichever occurs first. *EDO version only tOFF (EDO) 0 12 0 15 ns tOFF (FPM) – – 3 15 ns tRAC 50 60 ns tRAD (EDO) 9 12 ns tRAD (FPM) – 15 ns tRAH 9 10 ns tRAS 50 10,000 60 10,000 ns tRC (EDO) 84 104 ns tRC (FPM) – 110 ns tRCD (EDO) 11 14 ns tRCD (FPM) – 20 ns tRCH 0 0 ns tRCS 0 0 ns tRP 30 40 ns tRRH 0 0 ns tRSH 13 15 ns -5* -6 SYMBOL MIN MAX MIN MAX UNITS FAST PAGE MODE AND EDO PAGE MODE TIMING PARAMETERS -5* -6 SYMBOL MIN MAX MIN MAX UNITS tAA 25 30 ns tACH (EDO) 12 15 ns tAR 38 45 ns tASC 0 0 ns tASR 0 0 ns tCAC 13 15 ns tCAH 8 10 ns tCAS (EDO) 8 10,000 10 10,000 ns tCAS (FPM) – – 15 10,000 ns tCLZ (EDO) 0 0 ns tCLZ (FPM) – 3 ns tCRP 5 5 ns tCSH (EDO) 38 45 ns tCSH (FPM) – 60 ns tOD (EDO) 0 12 0 15 ns tOD (FPM) – – 3 15 ns tOE 12 15 ns

2, 4 Meg x 72 Nonbuffered DRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice. DM60.p65 – Rev. 6/98  1998, Micron Technology, Inc.18 2, 4 MEG x 72 NONBUFFERED DRAM DIMMs OBSOLETE EARLY WRITE CYCLE 27 DON’T CARE UNDEFINED /,/, /,/,/, /,/,/, /,/,/, /,/,/, /,/, /,/, V V IH IL /,/, /,/,/, /,/, /,/, /,/,/, /,/,/, /,/, VALID DATA ROWCOLUMNROW tDS tWP tWCHtWCS tWCR tRWL tCWL tCAHtASC tRAHtASR tRAD tAR tCAS tRSH tCSH tRCDtCRP tRAS tRC tRP V V IH IL ADDR V V IH IL V V IH IL DQ V V IOH IOL V V IH IL RAS# OE# /,/, /,/,/, /,/, /,/,/, /,/,/, /,/,/, /,/,/, /,/,/, /,/, /,/, /,/,/, /,/,/, /,/,/, tDH WE# CAS# tACH /,/,/, /,/,/, /,/, *EDO version only tRAD (EDO) 9 12 ns tRAH 9 10 ns tRAS 50 10,000 60 10,000 ns tRC (FPM) – 110 ns tRC (EDO) 84 104 ns tRCD (FPM) – 20 ns tRCD (EDO) 11 14 ns tRP 30 40 ns tRSH 13 15 ns tRWL 13 15 ns tWCH 8 10 ns tWCR 38 45 ns tWCS 0 0 ns tWP (FPM) – 10 ns tWP (EDO) 5 5 ns FAST PAGE MODE AND EDO PAGE MODE TIMING PARAMETERS -5* -6 SYMBOL MIN MAX MIN MAX UNITS tACH (EDO) 12 15 ns tAR 38 45 ns tASC 0 0 ns tASR 0 0 ns tCAH 8 10 ns tCAS (FPM) – – 15 10,000 ns tCAS (EDO) 8 10,000 10 10,000 ns tCRP 5 5 ns tCSH (FPM) – 60 ns tCSH (EDO) 38 45 ns tCWL (FPM) – 15 ns tCWL (EDO) 8 10 ns tDH 8 10 ns tDS 0 0 ns tRAD (FPM) – 15 ns -5* -6 SYMBOL MIN MAX MIN MAX UNITS

2, 4 Meg x 72 Nonbuffered DRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice. DM60.p65 – Rev. 6/98  1998, Micron Technology, Inc.19 2, 4 MEG x 72 NONBUFFERED DRAM DIMMs OBSOLETE tOE 15 ns tOFF 3 15 ns tPC 35 ns tRAC 60 ns tRAD 15 ns tRAH 10 ns tRASP 60 125,000 ns tRCD 20 ns tRCH 0 ns tRCS 0 ns tRP 40 ns tRRH 0 ns tRSH 15 ns FAST-PAGE-MODE READ CYCLE /,/, /,/, /,/,/, /,/, /,/, /,/, /,/, /,/, /,/, /,/,/, /,/, /,/,/,/, /,/,/, /,/,/, /,/, /, VALID DATA /,/, /,/, VALID DATA /, VALID DATA /,/, /,/, /,/,/, /,/, COLUMNCOLUMNCOLUMNROW ROW tRCS tCAHtASC tCPtCAS tRSH tCPtCAStCPtCAStRCDtCRP tPCtCSH tRASP tRP tCAHtASCtCAHtASC tAR tRAH tRAD tASR tRCS tRCH tRCH tRCS tRRHtRCH tOFF tCAC tCPA tAA tCLZ tOFFtCAC tCPA tAA tCLZ tOFFtCAC tRAC tAA tCLZ tOE tOD tOE tOD tOE tOD OPENOPEN V V IH IL CAS# V V IH IL ADDR V V IH IL WE# V V IH IL DQ V V IOH IOL V V IH IL RAS# OE# DON’T CARE UNDEFINED FAST PAGE MODE TIMING PARAMETERS SYMBOL MIN MAX UNITS tAA 30 ns tAR 45 ns tASC 0 ns tASR 0 ns tCAC 15 ns tCAH 10 ns tCAS 15 10,000 ns tCLZ 3 ns tCP 10 ns tCPA 35 ns tCRP 5 ns tCSH 60 ns tOD 3 15 ns SYMBOL MIN MAX UNITS

2, 4 Meg x 72 Nonbuffered DRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice. DM60.p65 – Rev. 6/98  1998, Micron Technology, Inc.20 2, 4 MEG x 72 NONBUFFERED DRAM DIMMs OBSOLETE EDO-PAGE-MODE READ CYCLE /,/,/, /,/,/, /,/,/, /,/,/, /,/, VALID DATA /,/, /,/, VALID DATA VALID DATA /,/, /,/, /,/, /,/, /,/, /,/,/, COLUMNCOLUMNCOLUMNROW ROW DON’T CARE UNDEFINED /,/, tOD tCAHtASC tCP tRSH tCPtCPtCAStRCDtCRP tPCtCSH tRASP tRP tCAHtASCtCAHtASC tAR tRAH tRAD tASR tRCS tRRH tRCH tOFF tCAC tCPA tAA tCLZtCAC tCPA tAA tCAC tRAC tAA tCLZ tOE tOD tOE tOD OPENOPEN V V IH IL V V IH IL ADDR V V IH IL V V IH IL DQ V V OH OL V V IH IL RAS# OE# tCAS tCAS CAS# WE# tCOH tOEP tOEHC tOES tOES tACHtACH tACH /,/, /,/,/,/, /,/, -5 -6 SYMBOL MIN MAX MIN MAX UNITS tOEHC 5 10 ns tOEP 5 5 ns tOES 4 5 ns tOFF 0 12 0 15 ns tPC 20 25 ns tRAC 50 60 ns tRAD 9 12 ns tRAH 9 10 ns tRASP 50 125,000 60 125,000 ns tRCD 11 14 ns tRCH 0 0 ns tRCS 0 0 ns tRP 30 40 ns tRRH 0 0 ns tRSH 13 15 ns EDO PAGE MODE TIMING PARAMETERS -5 -6 SYMBOL MIN MAX MIN MAX UNITS tAA 25 30 ns tACH 12 15 ns tAR 38 45 ns tASC 0 0 ns tASR 0 0 ns tCAC 13 15 ns tCAH 8 10 ns tCAS 8 10,000 10 10,000 ns tCLZ 0 0 ns tCOH 3 3 ns tCP 8 10 ns tCPA 28 35 ns tCRP 5 5 ns tCSH 38 45 ns tOD 0 12 0 15 ns tOE 12 15 ns

2, 4 Meg x 72 Nonbuffered DRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice. DM60.p65 – Rev. 6/98  1998, Micron Technology, Inc.21 2, 4 MEG x 72 NONBUFFERED DRAM DIMMs OBSOLETE FAST/EDO-PAGE-MODE EARLY WRITE CYCLE 27 /,/, /,/,/, /,/, /,/, /,/, /,/, /,/, /,/, /,/, /,/, /,/, /,/,/, /,/, /,/, /,/, /,/,/, /,/,/, tDS tDH tDS tDH tDS tDH tWCR VALID DATA VALID DATA VALID DATA tRWL tWP tCWL tWCHtWCS tWP tCWL tWCHtWCS tWP tCWL tWCHtWCS tCAHtASCtCAHtASCtCAHtASCtRAHtASR tRAD tACH tACH tACH tAR COLUMNCOLUMNCOLUMNROW ROW tCPtCAS tRSH tCPtCAStCPtCAStRCDtCRP tPCtCSH tRASP tRP V V IH IL CAS# V V IH IL ADDR V V IH IL WE# V V IH IL DQ V V IOH IOL RAS# OE# V V IH IL /,/,/, /,/,/, /,/,/, /,/,/,/, /,/,/,/, /,/,/, /,/,/, /,/, DON’T CARE UNDEFINED /,/,/, /,/, *EDO version only -5* -6 SYMBOL MIN MAX MIN MAX UNITS tPC (FPM) – 35 ns tRAD (EDO) 9 12 ns tRAD (FPM) – 15 ns tRAH 9 10 ns tRASP 50 125,000 60 125,000 ns tRCD (EDO) 11 14 ns tRCD (FPM) – 20 ns tRP 30 40 ns tRSH 13 15 ns tRWL 13 15 ns tWCH 8 10 ns tWCR 38 45 ns tWCS 0 0 ns tWP (EDO) 5 5 ns tWP (FPM) – 10 ns FAST PAGE MODE AND EDO PAGE MODE TIMING PARAMETERS -5* -6 SYMBOL MIN MAX MIN MAX UNITS tACH (EDO) 12 15 ns tAR 38 45 ns tASC 0 0 ns tASR 0 0 ns tCAH 8 10 ns tCAS (EDO) 8 10,000 10 10,000 ns tCAS (FPM) – – 15 10,000 ns tCP 8 10 ns tCRP 5 5 ns tCSH (EDO) 38 45 ns tCSH (FPM) – 60 ns tCWL (EDO) 8 10 ns tCWL (FPM) – 15 ns tDH 8 10 ns tDS 0 0 ns tPC (EDO) 20 25 ns

2, 4 Meg x 72 Nonbuffered DRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice. DM60.p65 – Rev. 6/98  1998, Micron Technology, Inc.22 2, 4 MEG x 72 NONBUFFERED DRAM DIMMs OBSOLETE READ-WRITE CYCLE 27 (LATE WRITE and READ-MODIFY-WRITE cycles) /,/,/, /,/,/, VALID D OUT VALID D IN /,/, /,/, /,/, /,/, ROW /,/,/, /,/,/, /,/, COLUMN ROW /,/, /,/,/, /,/,/, /,/,/,/, V V IH IL V V IH IL ADDR V V IH IL V V IH IL DQ V V IOH IOL V V IH IL RAS# OPENOPEN tOE tOD tCAC tRAC tAA tCLZ tDS tDH tAWD tWP tRWL tCWL tCWD tRWD tRCS tASC tCAH tAR tASR tRAD tCRP tRCD tCAS tRSH tCSH tRAS tRWC tRP tRAH OE# tOEH /,/,/, /,/,/, WE# tACH CAS# /,/, DON’T CARE UNDEFINED /,/, /,/,/,/, /,/, -5* -6 SYMBOL MIN MAX MIN MAX UNITS tOD (EDO) 0 12 0 15 ns tOD (FPM) – – 3 15 ns tOE 12 15 ns tOEH (EDO) 8 10/12** ns tOEH (FPM) – 15 ns tRAC 50 60 ns tRAD (EDO) 9 12 ns tRAD (FPM) – 15 ns tRAH 9 10 ns tRAS 50 10,000 60 10,000 ns tRCD (EDO) 11 14 ns tRCD (FPM) – 20 ns tRCS 0 0 ns tRP 30 40 ns tRSH 13 15 ns tRWC (EDO) 116 140 ns tRWC (FPM) – 155 ns tRWD (EDO) 67 79 ns tRWD (FPM) – 85 ns tRWL 13 15 ns tWP (EDO) 5 5 ns tWP (FPM) – 10 ns FAST PAGE MODE AND EDO PAGE MODE TIMING PARAMETERS -5* -6 SYMBOL MIN MAX MIN MAX UNITS tAA 25 30 ns tACH (EDO) 12 15 ns tAR 38 45 ns tASC 0 0 ns tASR 0 0 ns tAWD (EDO) 42 49 ns tAWD (FPM) – 55 ns tCAC 13 15 ns tCAH 8 10 ns tCAS (EDO) 8 10,000 10 10,000 ns tCAS (FPM) – – 15 10,000 ns tCLZ (EDO) 0 0 ns tCLZ (FPM) – 3 ns tCRP 5 5 ns tCSH (EDO) 38 45 ns tCSH (FPM) – 60 ns tCWD (EDO) 28 35 ns tCWD (FPM) – 40 ns tCWL (EDO) 8 10 ns tCWL (FPM) – 15 ns tDH 8 10 ns tDS 0 0 ns * EDO version only **16MB DIMM

2, 4 Meg x 72 Nonbuffered DRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice. DM60.p65 – Rev. 6/98  1998, Micron Technology, Inc.23 2, 4 MEG x 72 NONBUFFERED DRAM DIMMs OBSOLETE NOTE: 1. tPC is for LATE WRITE cycles only. FAST/EDO-PAGE-MODE READ-WRITE CYCLE 27 (LATE WRITE and READ-MODIFY-WRITE cycles) * EDO version only **16MB DIMM /,/, /,/,/, /,/,/,/, /,/, /,/, /,/, /,/, /,/, /,/, /,/, /,/, /,/, /,/,/, DON’T CARE UNDEFINED /,/, /,/, /,/, /,/, tOEtOEtOE OPEN D OUT VALID DIN VALID D OUT VALID D IN VALID D OUT VALID D IN VALID OPEN tDH tDS tAA tCPA tCLZ tCAC tDH tDS tAA tCPA tCLZ tCAC tDH tDS tAA tCLZ tCAC tRAC tWP tCWL tRWL tCWD tAWD tWP tCWL tCWD tAWD tWP tCWL tCWD tAWD tRCS tRWD tASR tRAH tASC tRAD tAR tCAH tASC tCAH tASC tCAH tCP tCAS tRSH tCP tRPtRASP tCAStCPtCAStRCD tCSH tPC tCRP ROW COLUMN COLUMN COLUMN ROW V V IH IL CAS# V V IH IL ADDR V V IH IL V V IH IL DQ V V IOH IOL V V IH IL RAS# OE# WE# tPRWC /,/,/, tOEH tOD tOD tOD NOTE 1 /,/, /,/,/, -5* -6 SYMBOL MIN MAX MIN MAX UNITS tOD (FPM) – – 3 15 ns tOE 12 15 ns tOEH (EDO) 8 10/12** ns tOEH (FPM) – 15 ns tPC (EDO) 20 25 ns tPC (FPM) – 35 ns tPRWC (EDO) 47 56 ns tPRWC (FPM) – 85 ns tRAC 50 60 ns tRAD (EDO) 9 12 ns tRAD (FPM) – 15 ns tRAH 9 10 ns tRASP 50 125,000 60 125,000 ns tRCD (EDO) 11 14 ns tRCD (FPM) – 20 ns tRCS 0 0 ns tRP 30 40 ns tRSH 13 15 ns tRWD (EDO) 67 79 ns tRWD (FPM) – 85 ns tRWL 13 15 ns tWP (EDO) 5 5 ns tWP (FPM) – 10 ns FAST PAGE MODE AND EDO PAGE MODE TIMING PARAMETERS -5* -6 SYMBOL MIN MAX MIN MAX UNITS tAA 25 30 ns tAR 38 45 ns tASC 0 0 ns tASR 0 0 ns tAWD (EDO) 42 49 ns tAWD (FPM) – 55 ns tCAC 13 15 ns tCAH 8 10 ns tCAS (EDO) 8 10,000 10 10,000 ns tCAS (FPM) – – 15 10,000 ns tCLZ (EDO) 0 0 ns tCLZ (FPM) – 3 ns tCP 8 10 ns tCPA 28 35 ns tCRP 5 5 ns tCSH (EDO) 38 45 ns tCSH (FPM) – 60 ns tCWD (EDO) 28 35 ns tCWD (FPM) – 40 ns tCWL (EDO) 8 10 ns tCWL (FPM) – 15 ns tDH 8 10 ns tDS 0 0 ns tOD (EDO) 0 12 0 15 ns

2, 4 Meg x 72 Nonbuffered DRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice. DM60.p65 – Rev. 6/98  1998, Micron Technology, Inc.24 2, 4 MEG x 72 NONBUFFERED DRAM DIMMs OBSOLETE EDO-PAGE-MODE READ EARLY WRITE CYCLE (Pseudo READ-MODIFY-WRITE) V V IH IL V V IH ILRAS# V V IH ILADDR V V IH ILWE# /,/, tRASP tRP ROW /,/, COLUMN (A) /,/, COLUMN (N) /,/, /,/, ROW V V IH ILOE# V V IOH IOL tCRP tCSH tCAStRCD tASR tRAH tRAD tASC tAR tCAH tASC tCAH tASC tCAH tCP tRSH VALID DATA IN /,/,/, /,/,/,/, /,/, /,/, tRCS tRCH tWCS tOE VALID DATA (B)VALID DATA (A) tWHZ tCAC tCPA tAA tCAC tAA OPENDQ tPC RACt tCOH tWCH tDS tDH tPC COLUMN (B) tACH CAS# tCAStCAStCP tCP DON’T CARE UNDEFINED /,/, /,/, /,/,/, -5 -6 SYMBOL MIN MAX MIN MAX UNITS tOE 12 15 ns tPC 20 25 ns tRAC 50 60 ns tRAD 9 12 ns tRAH 9 10 ns tRASP 50 125,000 60 125,000 ns tRCD 11 14 ns tRCH 0 0 ns tRCS 0 0 ns tRP 30 40 ns tRSH 13 15 ns tWCH 8 10 ns tWCS 0 0 ns tWHZ 0 12 0 15 ns EDO PAGE MODE TIMING PARAMETERS -5 -6 SYMBOL MIN MAX MIN MAX UNITS tAA 25 30 ns tACH 12 15 ns tAR 38 45 ns tASC 0 0 ns tASR 0 0 ns tCAC 13 15 ns tCAH 8 10 ns tCAS 8 10,000 10 10,000 ns tCOH 3 3 ns tCP 8 10 ns tCPA 28 35 ns tCRP 5 5 ns tCSH 38 45 ns tDH 8 10 ns tDS 0 0 ns

2, 4 Meg x 72 Nonbuffered DRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice. DM60.p65 – Rev. 6/98  1998, Micron Technology, Inc.25 2, 4 MEG x 72 NONBUFFERED DRAM DIMMs OBSOLETE /,/, /,/, ROW VALID DATA VALID DATA /,/, /,/,/, /,/, OPEN tCRP tRCD tCAS tRSH tRASP tRP tPC tASC tCAH tAR tASR tRAD tRAH tWCS tWP tRWLtRCS tDHtDS tCAC tOFF V V IH IL CAS# V V IH IL ADDR V V IH IL RAS# DQ V V OH OL WE# V V IH IL /,/, /,/,/, /,/,/, tCSH /,/, /,/,/, /,/, COLUMN tCP tCP tASC tCAH tCWL tWCH tCLZ tAA RAC DON’T CARE UNDEFINED t NOTE 1 /,/, /,/, OE# V V IH IL ROWCOLUMN tCAS FAST-PAGE-MODE READ EARLY WRITE CYCLE (Pseudo READ-MODIFY-WRITE) NOTE: 1. Do not drive data prior to tristate. SYMBOL MIN MAX UNITS tOFF 3 15 ns tPC 35 ns tRAC 60 ns tRAD 15 ns tRAH 10 ns tRASP 60 125,000 ns tRCD 20 ns tRCS 0 ns tRP 40 ns tRSH 15 ns tRWL 15 ns tWCH 10 ns tWCS 0 ns tWP 10 ns FAST PAGE MODE TIMING PARAMETERS SYMBOL MIN MAX UNITS tAA 30 ns tAR 45 ns tASC 0 ns tASR 0 ns tCAC 15 ns tCAH 10 ns tCAS 15 10,000 ns tCLZ 3 ns tCP 10 ns tCRP 5 ns tCSH 60 ns tCWL 15 ns tDH 10 ns tDS 0 ns

2, 4 Meg x 72 Nonbuffered DRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice. DM60.p65 – Rev. 6/98  1998, Micron Technology, Inc.26 2, 4 MEG x 72 NONBUFFERED DRAM DIMMs OBSOLETE EDO READ CYCLE (with WE#-controlled disable) /,/, /,/, /,/,/, /,/, tCLZ tCAC tRAC tAA VALID DATA OPEN tRCHtRCS tASCtRAH tRAD tAR tCAH tRCD tCAS tCSH tCRP tASR ROW OPEN RAS# V V IH IL V V IH IL ADDR V V IH IL DQ V V OH OL V V IH IL /,/,/, /,/,/,/, /,/,/, /,/, tODtOE OE# V V IH IL COLUMN /,/,/, /,/,/,/, WE# tWHZ tWPZ tCP tASC tRCS COLUMN tCLZ DON’T CARE UNDEFINED /,/, CAS# /,/, /,/,/, /,/,/, -5 -6 SYMBOL MIN MAX MIN MAX UNITS EDO PAGE MODE TIMING PARAMETERS -5 -6 SYMBOL MIN MAX MIN MAX UNITS tAA 25 30 ns tAR 38 45 ns tASC 0 0 ns tASR 0 0 ns tCAC 13 15 ns tCAH 8 10 ns tCAS 8 10,000 10 10,000 ns tCLZ 0 0 ns tCP 8 10 ns tCRP 5 5 ns tCSH 38 45 ns tOD 0 12 0 15 ns tOE 12 15 ns tRAC 50 60 ns tRAD 9 12 ns tRAH 9 10 ns tRCD 11 14 ns tRCH 0 0 ns tRCS 0 0 ns tWHZ 0 12 0 15 ns tWPZ 10 10 ns

2, 4 Meg x 72 Nonbuffered DRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice. DM60.p65 – Rev. 6/98  1998, Micron Technology, Inc.27 2, 4 MEG x 72 NONBUFFERED DRAM DIMMs OBSOLETE RAS#-ONLY REFRESH CYCLE 27 /,/,/, /,/,/,/, /,/,/, /,/, ROW V V IH IL CAS# V V IH IL ADDR V V IH IL RAS# tRC tRAS tRP tCRP tASR tRAH ROW OPENDQ V V OH OL tRPC WE# V V IH IL /,/,/, /,/,/,/, /,/,/, /,/,/,/, /,/,/,/, /,/,/,/, /,/, *EDO version only CBR REFRESH CYCLE 27 (Addresses, OE# = DON’T CARE) tRP V V IH ILRAS# tRAS NOTE 1 OPEN tCHRtCSR V V IH IL V V OH OL CAS# DQ tRP tRAS tRPC tCSRtRPC tCHRtCP V V IH IL tWRP tWRH /,/,/, /,/,/, /,/,/, /,/, /,/, /,/,/, /,/, WE# tWRP tWRH DON’T CARE UNDEFINED /,/, /,/, -5* -6 SYMBOL MIN MAX MIN MAX UNITS tRC (FPM) – 110 ns tRC (EDO) 84 104 ns tRP 30 40 ns tRPC (FPM) – 0 ns tRPC (EDO) 5 5 ns tWRH 8 10 ns tWRP 8 10 ns FAST PAGE MODE AND EDO PAGE MODE TIMING PARAMETERS -5* -6 SYMBOL MIN MAX MIN MAX UNITS tASR 0 0 ns tCHR 8 10 ns tCP 8 10 ns tCRP 5 5 ns tCSR 5 5 ns tRAH 9 10 ns tRAS 50 10,000 60 10,000 ns

2, 4 Meg x 72 Nonbuffered DRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice. DM60.p65 – Rev. 6/98  1998, Micron Technology, Inc.28 2, 4 MEG x 72 NONBUFFERED DRAM DIMMs OBSOLETE HIDDEN REFRESH CYCLE 20, 27 (WE# = HIGH; OE# = LOW) /,/,/, /,/, /,/, /,/, DON’T CARE UNDEFINED /,/, tCLZ tOFF /,/,/, /,/,/, /,/,/, /,/,/, /,/, /,/, /,/, /,/, /,/, OPENVALID DATAOPEN COLUMNROW tCAC tRAC tAA tCAHtASCtRAHtASR tRAD tAR tCRP tRCD tRSH tRAS tRC tRP tCHR tRAS DQ V V IOH IOL V V IH ILADDR V V IH ILCAS# V V IH ILRAS# /,/,/, /,/,/,/, /,/,/, V V IH IL tOE tOD OE# tORD FAST PAGE MODE AND EDO PAGE MODE TIMING PARAMETERS -5* -6 SYMBOL MIN MAX MIN MAX UNITS tAA 25 30 ns tAR 38 45 ns tASC 0 0 ns tASR 0 0 ns tCAC 13 15 ns tCAH 8 10 ns tCHR 8 10 ns tCLZ (FPM) – 3 ns tCLZ (EDO) 0 0 ns tCRP 5 5 ns tOD (FPM) – – 3 15 ns tOD (EDO) 0 12 0 15 ns tOE 12 15 ns tOFF (FPM) – – 3 15 ns -5* -6 SYMBOL MIN MAX MIN MAX UNITS tOFF (EDO) 0 12 0 15 ns tORD 0 0 ns tRAC 50 60 ns tRAD (FPM) – 15 ns tRAD (EDO) 9 12 ns tRAH 9 10 ns tRAS 50 10,000 60 10,000 ns tRC (FPM) – 110 ns tRC (EDO) 84 104 ns tRCD (FPM) – 20 ns tRCD (EDO) 11 14 ns tRP 30 40 ns tRSH 13 15 ns *EDO version only

2, 4 Meg x 72 Nonbuffered DRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice. DM60.p65 – Rev. 6/98  1998, Micron Technology, Inc.29 2, 4 MEG x 72 NONBUFFERED DRAM DIMMs OBSOLETE /,/,/,/,/,/, SCL SDA IN SDA OUT tLOW tSU:STA tHD:STA tF tHIGH tR tBUFtDHtAA tSU:STOtSU:DATtHD:DAT UNDEFINED SERIAL PRESENCE-DETECT EEPROM TIMING PARAMETERS SYMBOL MIN MAX UNITS tAA 0.3 3.5 µs tBUF 4.7 µs tDH 300 ns tF 300 ns tHD:DAT 0 µs tHD:STA 4 µs SPD EEPROM tHIGH 4 µs tLOW 4.7 µs tR1 µs tSU:DAT 250 ns tSU:STA 4.7 µs tSU:STO 4.7 µs SYMBOL MIN MAX UNITS

2, 4 Meg x 72 Nonbuffered DRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice. DM60.p65 – Rev. 6/98  1998, Micron Technology, Inc.30 2, 4 MEG x 72 NONBUFFERED DRAM DIMMs OBSOLETE NOTE: 1. All dimensions in inches (millimeters) MAX or typical where noted. MIN 168-PIN DIMM DF-12 (16MB) .200 (5.08) MAX .054 (1.37) .046 (1.17) 1.005 (25.53) .995 (25.27) PIN 1 (PIN 85 on backside) .700 (17.78) TYP.118 (3.00) (2X) .118 (3.00) TYP 4.550 (115.57) .050 (1.27) TYP .118 (3.00) TYP .039 (1.00) TYP .079 (2.00) R (2X) .039 (1.00) R(2X) FRONT VIEW .128 (3.25) .118 (3.00) PIN 84 (PIN 168 ON BACKSIDE) (2X) .250 (6.35) TYP 1.661 (42.18) 2.625 (66.68) 5.256 (133.50) 5.244 (133.20) 168-PIN DIMM DF-13 (32MB) .350 (8.89) MAX .054 (1.37) .046 (1.17) PIN 1 .700 (17.78) TYP .118 (3.00) (2X) .118 (3.00) TYP .250 (6.35) TYP 4.550 (115.57) .050 (1.27) TYP .118 (3.00) TYP .039 (1.00) TYP .079 (2.00) R (2X) .039 (1.00) R(2X) PIN 84 FRONT VIEW BACK VIEW PIN 168 .128 (3.25) .118 (3.00) (2X) PIN 85 2.625 (66.68) 1.661 (42.18) 1.005 (25.53) .995 (25.27) 5.256 (133.50) 5.244 (133.20)