MT9HTF12872AY

MT9HTF6472AY MICRON | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 21

Technical content

Features

• 240-pin, unbuffered dual in-line memory module
• Fast data transfer rates: PC2-3200, PC2-4200, PC2-5300, or PC2-6400
• 256MB (32 Meg x 72), 512MB (64 Meg x 72), or 1GB (128 Meg x 72)
• VDD = VDDQ 1.8V
• VDDSPD = 1.7–3.6V
• JEDEC-standard 1.8V I/O (SSTL_18-compatible)
• Differential data strobe (DQS, DQS#) option
• 4n-bit prefetch architecture
• Single rank
• Multiple internal device banks for concurrent operation
• Programmable CAS latency (CL)
• Posted CAS# additive latency (AL)
• WRITE latency = READ latency - 1 tCK
• Programmable burst lengths (BL): 4 or 8
• Adjustable data-output drive strength
• 64ms, 8192-cycle refresh
• On-die termination (ODT)
• Serial presence detect (SPD) with EEPROM
• Gold edge contacts Figure 1: 240-Pin UDIMM (MO-237 R/C A/F) Module height 30.0mm (1.18in) Options Marking
• Operating temperature – Commercial (0°C ≤ TA ≤ +70°C) None – Industrial (–40°C ≤ TA ≤ +85°C)1 I
• Package – 240-pin DIMM (lead-free) Y
• Frequency/CL2 – 2.5ns @ CL = 5 (DDR2-800)3, 4 -80E – 3.0ns @ CL = 6 (DDR2-667) -667 – 3.75ns @ CL = 5 (DDR2-53E) -53E – 5.0ns @ CL = 5 (DDR2-40E) -40E Notes: 1. Contact Micron for industrial temperature module offerings. 2. CL = CAS (READ) latency. 3. Contact Micron for product availability. 4. Not available in 256MB density. Table 1: Key Timing Parameters Speed Grade Industry Nomenclature Data Rate (MT/s) tRCD (ns) tRP (ns) tRC (ns)CL = 6 CL = 5 CL = 4 CL = 3 -80E PC2-6400 800 800 533 400 12.5 12.5 55 -800 PC2-6400 800 667 533 400 15 15 55 -667 PC2-5300 – 667 553 400 15 15 55 -53E PC2-4200 – – 553 400 15 15 55 -40E PC2-3200 – – 400 400 15 15 55 256MB, 512MB, 1GB (x72, SR, ECC) 240-Pin DDR2 UDIMM

PDF: 09005aef80e8ad4d htf9c32_64_128x72ay – Rev. F 3/10 EN 1 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2003 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice.

Table 2: Addressing Parameter 256MB 512MB 1GB Refresh count 8K 8K 8K Row address 8K A[12:0] 16K A[13:0] 16K A[13:0] Device bank address 4 BA[1:0] 4 BA[1:0] 8 BA[2:0] Device configuration 256Mb (32 Meg x 8) 512Mb (64 Meg x 8) 1Gb (128 Meg x 8) Column address 1K A[9:0] 1K A[9:0] 1K A[9:0] Module rank address 1 S0# 1 S0# 1 S0# Table 3: Part Numbers and Timing Parameters – 256MB Base device: MT47H32M8,1 256Mb DDR2 SDRAM Part Number2 Module Density Configuration Module Bandwidth Memory Clock/ Data Rate Clock Cycles (CL-tRCD-tRP) MT9HTF3272A(I)Y-667__ 256MB 32 Meg x 72 5.3 GB/s 3.0ns/667 MT/s 5-5-5 MT9HTF3272A(I)Y-53E__ 256MB 32 Meg x 72 4.3 GB/s 3.75ns/533 MT/s 4-4-4 MT9HTF3272A(I)Y-40E__ 256MB 32 Meg x 72 3.2 GB/s 5.0ns/400 MT/s 3-3-3 Table 4: Part Numbers and Timing Parameters – 512MB Base device: MT47H64M8,1 512Mb DDR2 SDRAM Part Number2 Module Density Configuration Module Bandwidth Memory Clock/ Data Rate Clock Cycles (CL-tRCD-tRP) MT9HTF6472A(I)Y-80E__ 512MB 64 Meg x 72 6.4 GB/s 2.5ns/800 MT/s 5-5-5 MT9HTF6472A(I)Y-800__ 512MB 64 Meg x 72 6.4 GB/s 2.5ns/800 MT/s 6-6-6 MT9HTF6472A(I)Y-667__ 512MB 64 Meg x 72 5.3 GB/s 3.0ns/667 MT/s 5-5-5 MT9HTF6472A(I)Y-53E__ 512MB 64 Meg x 72 4.3 GB/s 3.75ns/533 MT/s 4-4-4 MT9HTF6472A(I)Y-40E__ 512MB 64 Meg x 72 3.2 GB/s 5.0ns/400 MT/s 3-3-3 256MB, 512MB, 1GB (x72, SR, ECC) 240-Pin DDR2 UDIMM PDF: 09005aef80e8ad4d htf9c32_64_128x72ay – Rev. F 3/10 EN 2 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2003 Micron Technology, Inc. All rights reserved.

Table 5: Part Numbers and Timing Parameters – 1GB Base device: MT47H128M8,1 1Gb DDR2 SDRAM Part Number2 Module Density Configuration Module Bandwidth Memory Clock/ Data Rate Clock Cycles (CL-tRCD-tRP) MT9HTF12872A(I)Y-80E__ 1GB 128 Meg x 72 6.4 GB/s 2.5ns/800 MT/s 5-5-5 MT9HTF12872A(I)Y-800__ 1GB 128 Meg x 72 6.4 GB/s 2.5ns/800 MT/s 6-6-6 MT9HTF12872A(I)Y-667__ 1GB 128 Meg x 72 5.3 GB/s 3.0ns/667 MT/s 5-5-5 MT9HTF12872A(I)Y-53E__ 1GB 128 Meg x 72 4.3 GB/s 3.75ns/533 MT/s 4-4-4 MT9HTF12872A(I)Y-40E__ 1GB 128 Meg x 72 3.2 GB/s 5.0ns/400 MT/s 3-3-3 Notes: 1. The data sheet for the base device can be found on Micron’s Web site. 2. All part numbers end with a two-place code (not shown) that designates component and PCB revisions. Consult factory for current revision codes. Example: MT9HTF6472AY-667C2. 256MB, 512MB, 1GB (x72, SR, ECC) 240-Pin DDR2 UDIMM PDF: 09005aef80e8ad4d htf9c32_64_128x72ay – Rev. F 3/10 EN 3 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2003 Micron Technology, Inc. All rights reserved.

Table 6: Pin Assignments 240-Pin UDIMM Front 240-Pin UDIMM Back Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol

1 VREF 31 DQ19 61 A4 91 VSS 121 VSS 151 VSS 181 VDDQ 211 DM5

2 VSS 32 VSS 62 VDDQ 92 DQS5# 122 DQ4 152 DQ28 182 A3 212 NC

3 DQ0 33 DQ24 63 A2 93 DQS5 123 DQ5 153 DQ29 183 A1 213 VSS

4 DQ1 34 DQ25 64 VDD 94 VSS 124 VSS 154 VSS 184 VDD 214 DQ46

5 VSS 35 VSS 65 VSS 95 DQ42 125 DM0 155 DM3 185 CK0 215 DQ47

6 DQS0# 36 DQS3# 66 VSS 96 DQ43 126 NC 156 NC 186 CK0# 216 VSS

7 DQS0 37 DQS3 67 VDD 97 VSS 127 VSS 157 VSS 187 VDD 217 DQ52

8 VSS 38 VSS 68 NC 98 DQ48 128 DQ6 158 DQ30 188 A0 218 DQ53

9 DQ2 39 DQ26 69 VDD 99 DQ49 129 DQ7 159 DQ31 189 VDD 219 VSS

10 DQ3 40 DQ27 70 A10/AP 100 VSS 130 VSS 160 VSS 190 BA1 220 CK2

11 VSS 41 VSS 71 BA0 101 SA2 131 DQ12 161 CB4 191 VDDQ 221 CK2#

12 DQ8 42 CB0 72 VDDQ 102 NC 132 DQ13 162 CB5 192 RAS# 222 VSS

13 DQ9 43 CB1 73 WE# 103 VSS 133 VSS 163 VSS 193 S0# 223 DM6

14 VSS 44 VSS 74 CAS# 104 DQS6# 134 DM1 164 DM8 194 VDDQ 224 NC

15 DQS1# 45 DQS8# 75 VDDQ 105 DQS6 135 NC 165 NC 195 ODT0 225 VSS

16 DQS1 46 DQS8 76 NC 106 VSS 136 VSS 166 VSS 196 NC/A132 226 DQ54

17 VSS 47 VSS 77 NC 107 DQ50 137 CK1 167 CB6 197 VDD 227 DQ55

18 NC 48 CB2 78 VDDQ 108 DQ51 138 CK1# 168 CB7 198 VSS 228 VSS

19 NC 49 CB3 79 VSS 109 VSS 139 VSS 169 VSS 199 DQ36 229 DQ60

20 VSS 50 VSS 80 DQ32 110 DQ56 140 DQ14 170 VDDQ 200 DQ37 230 DQ61

21 DQ10 51 VDDQ 81 DQ33 111 DQ57 141 DQ15 171 NC 201 VSS 231 VSS

22 DQ11 52 CKE0 82 VSS 112 VSS 142 VSS 172 VDD 202 DM4 232 DM7

23 VSS 53 VDD 83 DQS4# 113 DQS7# 143 DQ20 173 NC 203 NC 233 NC

24 DQ16 54 NC/BA21 84 DQS4 114 DQS7 144 DQ21 174 NC 204 VSS 234 VSS

25 DQ17 55 NC 85 VSS 115 VSS 145 VSS 175 VDDQ 205 DQ38 235 DQ62

26 VSS 56 VDDQ 86 DQ34 116 DQ58 146 DM2 176 A12 206 DQ39 236 DQ63

27 DQS2# 57 A11 87 DQ35 117 DQ59 147 NC 177 A9 207 VSS 237 VSS

28 DQS2 58 A7 88 VSS 118 VSS 148 VSS 178 VDD 208 DQ44 238 VDDSPD

29 VSS 59 VDD 89 DQ40 119 SDA 149 DQ22 179 A8 209 DQ45 239 SA0

30 DQ18 60 A5 90 DQ41 120 SCL 150 DQ23 180 A6 210 VSS 240 SA1

Notes: 1. Pin 54 is NC for 256MB and 512MB or BA2 for 1GB. 2. Pin 196 is NC for 256MB or A13 for 512MB and 1GB. 256MB, 512MB, 1GB (x72, SR, ECC) 240-Pin DDR2 UDIMM Pin Assignments PDF: 09005aef80e8ad4d htf9c32_64_128x72ay – Rev. F 3/10 EN 4 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2003 Micron Technology, Inc. All rights reserved.

The pin description table below is a comprehensive list of all possible pins for all DDR2 modules. All pins listed may not be supported on this module. See Pin Assignments for information specific to this module. Table 7: Pin Descriptions Symbol Type Description Ax Input Address inputs: Provide the row address for ACTIVE commands, and the column ad- dress and auto precharge bit (A10) for READ/WRITE commands, to select one location out of the memory array in the respective bank. A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one bank (A10 LOW, bank selected by BAx) or all banks (A10 HIGH). The address inputs also provide the op-code during a LOAD MODE command. See the Pin Assignments Table for density-specific addressing information. BAx Input Bank address inputs: Define the device bank to which an ACTIVE, READ, WRITE, or PRECHARGE command is being applied. BA define which mode register (MR0, MR1, MR2, and MR3) is loaded during the LOAD MODE command. CKx, CK#x Input Clock: Differential clock inputs. All control, command, and address input signals are sampled on the crossing of the positive edge of CK and the negative edge of CK#. CKEx Input Clock enable: Enables (registered HIGH) and disables (registered LOW) internal circui- try and clocks on the DDR2 SDRAM. DMx, Input Data mask (x8 devices only): DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH, along with that input data, during a write ac- cess. Although DM pins are input-only, DM loading is designed to match that of the DQ and DQS pins. ODTx Input On-die termination: Enables (registered HIGH) and disables (registered LOW) termi- nation resistance internal to the DDR2 SDRAM. When enabled in normal operation, ODT is only applied to the following pins: DQ, DQS, DQS#, DM, and CB. The ODT input will be ignored if disabled via the LOAD MODE command. Par_In Input Parity input: Parity bit for Ax, RAS#, CAS#, and WE#. RAS#, CAS#, WE# Input Command inputs: RAS#, CAS#, and WE# (along with S#) define the command being entered. RESET# Input Reset: Asynchronously forces all registered outputs LOW when RESET# is LOW. This signal can be used during power-up to ensure that CKE is LOW and DQ are High-Z. S#x Input Chip select: Enables (registered LOW) and disables (registered HIGH) the command decoder. SAx Input Serial address inputs: Used to configure the SPD EEPROM address range on the I2C bus. SCL Input Serial clock for SPD EEPROM: Used to synchronize communication to and from the SPD EEPROM on the I2C bus. CBx I/O Check bits. Used for system error detection and correction. DQx I/O Data input/output: Bidirectional data bus. DQSx, DQS#x I/O Data strobe: Travels with the DQ and is used to capture DQ at the DRAM or the con- troller. Output with read data; input with write data for source synchronous opera- tion. DQS# is only used when differential data strobe mode is enabled via the LOAD MODE command. 256MB, 512MB, 1GB (x72, SR, ECC) 240-Pin DDR2 UDIMM Pin Descriptions PDF: 09005aef80e8ad4d htf9c32_64_128x72ay – Rev. F 3/10 EN 5 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2003 Micron Technology, Inc. All rights reserved.

Table 7: Pin Descriptions (Continued) Symbol Type Description SDA I/O Serial data: Used to transfer addresses and data into and out of the SPD EEPROM on the I2C bus. RDQSx, RDQS#x Output Redundant data strobe (x8 devices only): RDQS is enabled/disabled via the LOAD MODE command to the extended mode register (EMR). When RDQS is enabled, RDQS is output with read data only and is ignored during write data. When RDQS is disa- bled, RDQS becomes data mask (see DMx). RDQS# is only used when RDQS is enabled and differential data strobe mode is enabled. Err_Out# Output (open drain) Parity error output: Parity error found on the command and address bus. VDD/VDDQ Supply Power supply: 1.8V ±0.1V. The component VDD and VDDQ are connected to the mod- ule VDD. VDDSPD Supply SPD EEPROM power supply: 1.7–3.6V. VREF Supply Reference voltage: VDD/2. VSS Supply Ground. NC – No connect: These pins are not connected on the module. NF – No function: These pins are connected within the module, but provide no functionality. NU – Not used: These pins are not used in specific module configurations/operations. RFU – Reserved for future use. 256MB, 512MB, 1GB (x72, SR, ECC) 240-Pin DDR2 UDIMM Pin Descriptions PDF: 09005aef80e8ad4d htf9c32_64_128x72ay – Rev. F 3/10 EN 6 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2003 Micron Technology, Inc. All rights reserved.

Figure 2: Functional Block Diagram DQ DQ DQ DQ DQ DQ DQ DQ DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM CS# DQ DQS# DQ DQ DQ DQ DQ DQ DQ DQ DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DM CS# DQ DQS# DQ DQ DQ DQ DQ DQ DQ DQ DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DM CS# DQ DQS# DQ DQ DQ DQ DQ DQ DQ DQ DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DM CS# DQ DQS# DQ DQ DQ DQ DQ DQ DQ DQ DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DM CS# DQ DQS# DQ DQ DQ DQ DQ DQ DQ DQ DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DM CS# DQ DQS# DQ DQ DQ DQ DQ DQ DQ DQ DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DM CS# DQ DQS# DQ DQ DQ DQ DQ DQ DQ DQ DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DM CS# DQ DQS# DQS0# DQS0 DM0 S0# DQS1# DQS1 DM1 DQS2# DQS2 DM2 DQS3# DQS3 DM3 DQS4# DQS4 DM4 DQS5# DQS5 DM5 DQS6# DQS6 DM6 DQS7# DQS7 DM7 DDR SDRAM x 3 CK0 CK0# DDR SDRAM x 3 CK1 CK1# DDR SDRAM x 3 CK2 CK2# SPD EEPROM A1 A2 SA0 SA1 SA2 SDA WP U10 BA[2/1:0] A[13/12:0] RAS# CAS# WE# CKE0 ODT0 BA[2/1:0]: DDR2 SDRAM A[13/12:0]: DDR2 SDRAM RAS#: DDR2 SDRAM CAS#: DDR2 SDRAM WE#: DDR2 SDRAM CKE0: DDR2 SDRAM ODT0: DDR2 SDRAM V REF V SS DDR2 SDRAM DDR2 SDRAM V DD /V DDQ V DDSPD SPD EEPROM DDR2 SDRAM DQ DQ DQ DQ DQ DQ DQ DQ CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 DM CS# DQ DQS# DQS8# DQS8 DM8 V SS SCL 256MB, 512MB, 1GB (x72, SR, ECC) 240-Pin DDR2 UDIMM Functional Block Diagram PDF: 09005aef80e8ad4d htf9c32_64_128x72ay – Rev. F 3/10 EN 7 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2003 Micron Technology, Inc. All rights reserved.

The pin description table below is a comprehensive list of all possible pins for all DDR2 modules. All pins listed may not be supported on this module. See Pin Assignments for information specific to this module. Table 8: Pin Descriptions Symbol Type Description Ax Input Address inputs: Provide the row address for ACTIVE commands, and the column ad- dress and auto precharge bit (A10) for READ/WRITE commands, to select one location out of the memory array in the respective bank. A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one bank (A10 LOW, bank selected by BAx) or all banks (A10 HIGH). The address inputs also provide the op-code during a LOAD MODE command. See the Pin Assignments Table for density-specific addressing information. BAx Input Bank address inputs: Define the device bank to which an ACTIVE, READ, WRITE, or PRECHARGE command is being applied. BA define which mode register (MR0, MR1, MR2, and MR3) is loaded during the LOAD MODE command. CKx, CK#x Input Clock: Differential clock inputs. All control, command, and address input signals are sampled on the crossing of the positive edge of CK and the negative edge of CK#. CKEx Input Clock enable: Enables (registered HIGH) and disables (registered LOW) internal circui- try and clocks on the DDR2 SDRAM. DMx, Input Data mask (x8 devices only): DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH, along with that input data, during a write ac- cess. Although DM pins are input-only, DM loading is designed to match that of the DQ and DQS pins. ODTx Input On-die termination: Enables (registered HIGH) and disables (registered LOW) termi- nation resistance internal to the DDR2 SDRAM. When enabled in normal operation, ODT is only applied to the following pins: DQ, DQS, DQS#, DM, and CB. The ODT input will be ignored if disabled via the LOAD MODE command. Par_In Input Parity input: Parity bit for Ax, RAS#, CAS#, and WE#. RAS#, CAS#, WE# Input Command inputs: RAS#, CAS#, and WE# (along with S#) define the command being entered. RESET# Input Reset: Asynchronously forces all registered outputs LOW when RESET# is LOW. This signal can be used during power-up to ensure that CKE is LOW and DQ are High-Z. S#x Input Chip select: Enables (registered LOW) and disables (registered HIGH) the command decoder. SAx Input Serial address inputs: Used to configure the SPD EEPROM address range on the I2C bus. SCL Input Serial clock for SPD EEPROM: Used to synchronize communication to and from the SPD EEPROM on the I2C bus. CBx I/O Check bits. Used for system error detection and correction. DQx I/O Data input/output: Bidirectional data bus. DQSx, DQS#x I/O Data strobe: Travels with the DQ and is used to capture DQ at the DRAM or the con- troller. Output with read data; input with write data for source synchronous opera- tion. DQS# is only used when differential data strobe mode is enabled via the LOAD MODE command. 256MB, 512MB, 1GB (x72, SR, ECC) 240-Pin DDR2 UDIMM Pin Descriptions PDF: 09005aef80e8ad4d htf9c32_64_128x72ay – Rev. F 3/10 EN 8 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2003 Micron Technology, Inc. All rights reserved.

Table 8: Pin Descriptions (Continued) Symbol Type Description SDA I/O Serial data: Used to transfer addresses and data into and out of the SPD EEPROM on the I2C bus. RDQSx, RDQS#x Output Redundant data strobe (x8 devices only): RDQS is enabled/disabled via the LOAD MODE command to the extended mode register (EMR). When RDQS is enabled, RDQS is output with read data only and is ignored during write data. When RDQS is disa- bled, RDQS becomes data mask (see DMx). RDQS# is only used when RDQS is enabled and differential data strobe mode is enabled. Err_Out# Output (open drain) Parity error output: Parity error found on the command and address bus. VDD/VDDQ Supply Power supply: 1.8V ±0.1V. The component VDD and VDDQ are connected to the mod- ule VDD. VDDSPD Supply SPD EEPROM power supply: 1.7–3.6V. VREF Supply Reference voltage: VDD/2. VSS Supply Ground. NC – No connect: These pins are not connected on the module. NF – No function: These pins are connected within the module, but provide no functionality. NU – Not used: These pins are not used in specific module configurations/operations. RFU – Reserved for future use. 256MB, 512MB, 1GB (x72, SR, ECC) 240-Pin DDR2 UDIMM Pin Descriptions PDF: 09005aef80e8ad4d htf9c32_64_128x72ay – Rev. F 3/10 EN 9 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2003 Micron Technology, Inc. All rights reserved.

DDR2 SDRAM modules are high-speed, CMOS dynamic random access memory mod- ules that use internally configured 4 or 8-bank DDR2 SDRAM devices. DDR2 SDRAM modules use DDR architecture to achieve high-speed operation. DDR2 architecture is essentially a 4n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the DDR2 SDRAM module effectively consists of a single 4n-bit-wide, one-clock-cycle data transfer at the internal DRAM core and eight corresponding n-bit-wide, one-half-clock-cycle data trans- fers at the I/O pins. DDR2 modules use two sets of differential signals: DQS, DQS# to capture data and CK and CK# to capture commands, addresses, and control signals. Differential clocks and data strobes ensure exceptional noise immunity for these signals and provide precise crossing points to capture input signals. A bidirectional data strobe (DQS, DQS#) is trans- mitted externally, along with data, for use in data capture at the receiver. DQS is a strobe transmitted by the DDR2 SDRAM device during READs and by the memory con- troller during WRITEs. DQS is edge-aligned with data for READs and center-aligned with data for WRITEs. DDR2 SDRAM modules operate from a differential clock (CK and CK#); the crossing of CK going HIGH and CK# going LOW will be referred to as the positive edge of CK. Com- mands (address and control signals) are registered at every positive edge of CK. Input data is registered on both edges of DQS, and output data is referenced to both edges of DQS, as well as to both edges of CK. Serial Presence-Detect EEPROM Operation DDR2 SDRAM modules incorporate serial presence-detect. The SPD data is stored in a 256-byte EEPROM. The first 128 bytes are programmed by Micron to identify the mod- ule type and various SDRAM organizations and timing parameters. The remaining 128 bytes of storage are available for use by the customer. System READ/WRITE operations between the master (system logic) and the slave EEPROM device occur via a standard I2C bus using the DIMM’s SCL (clock) SDA (data), and SA (address) pins. Write protect (WP) is connected to VSS, permanently disabling hardware write protection. 256MB, 512MB, 1GB (x72, SR, ECC) 240-Pin DDR2 UDIMM General Description PDF: 09005aef80e8ad4d htf9c32_64_128x72ay – Rev. F 3/10 EN 10 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2003 Micron Technology, Inc. All rights reserved.

Stresses greater than those listed may cause permanent damage to the module. This is a stress rating only, and functional operation of the module at these or any other condi- tions outside those indicated in the device data sheet are not implied. Exposure to absolute maximum rating conditions for extended periods may adversely affect reliability. Table 9: Absolute Maximum Ratings Symbol Parameter Min Max Units VDD/VDDQ VDD/VDDQ supply voltage relative to VSS –0.5 2.3 V VIN, VOUT Voltage on any pin relative to VSS –0.5 2.3 V II Input leakage current; Any input 0V ≤ VIN ≤ VDD; VREF input 0V ≤ VIN ≤ 0.95V; (All other pins not under test = 0V) Command/address, RAS#, CAS#, WE#, S#, CKE, ODT, BA –45 45 µA CK, CK# –15 15 DM –5 5 IOZ Output leakage current; 0V ≤ VOUT; DQ and ODT are disabled DQ, DQS, DQS# –5 5 µA IVREF VREF leakage current; VREF = valid VREF level –18 18 µA TA Module ambient operating temperature Commercial 0 70 °C Industrial –40 85 °C TC2 DDR2 SDRAM component operating tempera- ture1 Commercial 0 85 °C Industrial –40 95 °C Notes: 1. For further information, refer to technical note TN-00-08: "Thermal Applications," avail- able on Micron’s Web site. 2. The refresh rate is required to double when T C exceeds 85°C. 256MB, 512MB, 1GB (x72, SR, ECC) 240-Pin DDR2 UDIMM Electrical Specifications PDF: 09005aef80e8ad4d htf9c32_64_128x72ay – Rev. F 3/10 EN 11 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2003 Micron Technology, Inc. All rights reserved.

Recommended AC operating conditions are given in the DDR2 component data sheets. Component specifications are available on Micron's Web site. Module speed grades cor- relate with component speed grades. Table 10: Module and Component Speed Grades DDR2 components may exceed the listed module speed grades; module may not be available in all listed speed grades Module Speed Grade Component Speed Grade -1GA -187E -80E -25E -800 -25 -667 -3 -53E -37E -40E -5E Design Considerations Simulations Micron memory modules are designed to optimize signal integrity through carefully de- signed terminations, controlled board impedances, routing topologies, trace length matching, and decoupling. However, good signal integrity starts at the system level. Mi- cron encourages designers to simulate the signal characteristics of the system's memo- ry bus to ensure adequate signal integrity of the entire memory system. Power Operating voltages are specified at the DRAM, not at the edge connector of the module. Designers must account for any system voltage drops at anticipated power levels to en- sure the required supply voltage is maintained. 256MB, 512MB, 1GB (x72, SR, ECC) 240-Pin DDR2 UDIMM DRAM Operating Conditions PDF: 09005aef80e8ad4d htf9c32_64_128x72ay – Rev. F 3/10 EN 12 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2003 Micron Technology, Inc. All rights reserved.

Table 11: DDR2 IDD Specifications and Conditions – 256MB Values shown for MT47H32M8 DDR2 SDRAM only and are computed from values specified in the 256Mb (32 Meg x 8) component data sheet Parameter Symbol -667 -53E -40E Units Operating one bank active-precharge current:tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching IDD0 810 720 675 mA Operating one bank active-read-precharge current: IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN (IDD), tRCD = tRCD (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus in- puts are switching; Data pattern is same as IDD4W IDD1 900 810 765 mA Precharge power-down current: All device banks idle; tCK = tCK (IDD); CKE is LOW; Other control and address bus inputs are stable; Data bus inputs are float- ing IDD2P 45 45 45 mA Precharge quiet standby current: All device banks idle; tCK = tCK (IDD); CKE is HIGH, S# is HIGH; Other control and address bus inputs are stable; Data bus inputs are floating IDD2Q 360 315 225 mA Precharge standby current: All device banks idle; tCK = tCK (IDD); CKE is HIGH, S# is HIGH; Other control and address bus inputs are switching; Data bus inputs are switching IDD2N 360 315 270 mA Active power-down current: All device banks open; tCK = tCK (IDD); CKE is LOW; Other control and address bus inputs are stable; Data bus inputs are floating Fast PDN exit MR[12] = 0 IDD3P 270 225 180 mA Slow PDN exit MR[12] = 1 54 54 54 Active standby current: All device banks open; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Other control and address bus inputs are switching; Data bus inputs are switching IDD3N 450 360 270 mA Operating burst write current: All device banks open; Continuous burst writes; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching IDD4W 1710 1440 1125 mA Operating burst read current: All device banks open; Continuous burst read, IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching IDD4R 1620 1350 1035 mA Burst refresh current:tCK = tCK (IDD); REFRESH command at every tRFC (IDD) interval; CKE is HIGH, S# is HIGH between valid commands; Other control and address bus inputs are switching; Data bus inputs are switching IDD5 1620 1530 1485 mA Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and ad- dress bus inputs are floating; Data bus inputs are floating IDD6 45 45 45 mA Operating bank interleave read current: All device banks interleaving reads; IOUT = 0mA; BL = 4, CL = CL (IDD), AL = tRCD (IDD) - 1 × tCK (IDD); tCK = tCK (IDD), tRC = tRC (IDD), tRRD = tRRD (IDD), tRCD = tRCD (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are stable during deselects; Data bus inputs are switching IDD7 2250 2160 2070 mA 256MB, 512MB, 1GB (x72, SR, ECC) 240-Pin DDR2 UDIMM IDD Specifications PDF: 09005aef80e8ad4d htf9c32_64_128x72ay – Rev. F 3/10 EN 13 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2003 Micron Technology, Inc. All rights reserved.

Table 12: DDR2 IDD Specifications and Conditions – 512MB Values shown for MT47H64M8 DDR2 SDRAM only and are computed from values specified in the 512Mb (64 Meg x 8) component data sheet Parameter Symbol -80E/ -800 -667 -53E -40E Units Operating one bank active-precharge current:tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching IDD0 900 810 720 720 mA Operating one bank active-read-precharge current: IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN (IDD), tRCD = tRCD (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data pattern is same as IDD4W IDD1 1035 945 855 810 mA Precharge power-down current: All device banks idle; tCK = tCK (IDD); CKE is LOW; Other control and address bus inputs are stable; Data bus in- puts are floating IDD2P 63 63 63 63 mA Precharge quiet standby current: All device banks idle; tCK = tCK (IDD); CKE is HIGH, S# is HIGH; Other control and address bus inputs are stable; Data bus inputs are floating IDD2Q 450 405 360 315 mA Precharge standby current: All device banks idle; tCK = tCK (IDD); CKE is HIGH, S# is HIGH; Other control and address bus inputs are switching; Da- ta bus inputs are switching IDD2N 495 450 405 360 mA Active power-down current: All device banks open; tCK = tCK (IDD); CKE is LOW; Other control and address bus in- puts are stable; Data bus inputs are floating Fast PDN exit MR[12] = 0 IDD3P 360 315 270 225 mA Slow PDN exit MR[12] = 1 108 108 108 108 Active standby current: All device banks open; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid com- mands; Other control and address bus inputs are switching; Data bus inputs are switching IDD3N 630 58 495 405 mA Operating burst write current: All device banks open; Continuous burst writes; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching IDD4W 1755 1530 1260 1035 mA Operating burst read current: All device banks open; Continuous burst read, IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid com- mands; Address bus inputs are switching; Data bus inputs are switching IDD4R 1845 1620 1305 1035 mA Burst refresh current:tCK = tCK (IDD); REFRESH command at every tRFC (IDD) interval; CKE is HIGH, S# is HIGH between valid commands; Other con- trol and address bus inputs are switching; Data bus inputs are switching IDD5 2070 1620 1530 1485 mA Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and address bus inputs are floating; Data bus inputs are floating IDD6 63 63 63 63 mA 256MB, 512MB, 1GB (x72, SR, ECC) 240-Pin DDR2 UDIMM IDD Specifications PDF: 09005aef80e8ad4d htf9c32_64_128x72ay – Rev. F 3/10 EN 14 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2003 Micron Technology, Inc. All rights reserved.

Table 12: DDR2 IDD Specifications and Conditions – 512MB (Continued) Values shown for MT47H64M8 DDR2 SDRAM only and are computed from values specified in the 512Mb (64 Meg x 8) component data sheet Parameter Symbol -80E/ -800 -667 -53E -40E Units Operating bank interleave read current: All device banks interleaving reads; IOUT = 0mA; BL = 4, CL = CL (IDD), AL = tRCD (IDD) - 1 × tCK (IDD); tCK = tCK (IDD), tRC = tRC (IDD), tRRD = tRRD (IDD), tRCD = tRCD (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are stable during deselects; Data bus inputs are switching IDD7 2700 2160 2025 1980 mA 256MB, 512MB, 1GB (x72, SR, ECC) 240-Pin DDR2 UDIMM IDD Specifications PDF: 09005aef80e8ad4d htf9c32_64_128x72ay – Rev. F 3/10 EN 15 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2003 Micron Technology, Inc. All rights reserved.

Table 13: DDR2 IDD Specifications and Conditions (Die Revision A) – 1GB Values shown for MT47H128M8 DDR2 SDRAM only and are computed from values specified in the 1Gb (128 Meg x 8) com- ponent data sheet Parameter Symbol -80E/ -800 -667 -53E -40E Units Operating one bank active-precharge current:tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching IDD0 900 810 720 630 mA Operating one bank active-read-precharge current: IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN (IDD), tRCD = tRCD (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data pattern is same as IDD4W IDD1 990 900 855 720 mA Precharge power-down current: All device banks idle; tCK = tCK (IDD); CKE is LOW; Other control and address bus inputs are stable; Data bus in- puts are floating IDD2P 63 63 63 63 mA Precharge quiet standby current: All device banks idle; tCK = tCK (IDD); CKE is HIGH, S# is HIGH; Other control and address bus inputs are stable; Data bus inputs are floating IDD2Q 585 495 369 315 mA Precharge standby current: All device banks idle; tCK = tCK (IDD); CKE is HIGH, S# is HIGH; Other control and address bus inputs are switching; Da- ta bus inputs are switching IDD2N 630 540 405 360 mA Active power-down current: All device banks open; tCK = tCK (IDD); CKE is LOW; Other control and address bus in- puts are stable; Data bus inputs are floating Fast PDN exit MR[12] = 0 IDD3P 405 360 315 315 mA Slow PDN exit MR[12] = 1 126 126 126 126 Active standby current: All device banks open; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid com- mands; Other control and address bus inputs are switching; Data bus inputs are switching IDD3N 675 630 495 405 mA Operating burst write current: All device banks open; Continuous burst writes; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching IDD4W 1665 1440 1170 990 mA Operating burst read current: All device banks open; Continuous burst read, IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid com- mands; Address bus inputs are switching; Data bus inputs are switching IDD4R 1710 1440 1305 990 mA Burst refresh current:tCK = tCK (IDD); REFRESH command at every tRFC (IDD) interval; CKE is HIGH, S# is HIGH between valid commands; Other con- trol and address bus inputs are switching; Data bus inputs are switching IDD5 2520 2700 2250 1980 mA Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and address bus inputs are floating; Data bus inputs are floating IDD6 63 63 63 63 mA 256MB, 512MB, 1GB (x72, SR, ECC) 240-Pin DDR2 UDIMM IDD Specifications PDF: 09005aef80e8ad4d htf9c32_64_128x72ay – Rev. F 3/10 EN 16 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2003 Micron Technology, Inc. All rights reserved.

Table 13: DDR2 IDD Specifications and Conditions (Die Revision A) – 1GB (Continued) Values shown for MT47H128M8 DDR2 SDRAM only and are computed from values specified in the 1Gb (128 Meg x 8) com- ponent data sheet Parameter Symbol -80E/ -800 -667 -53E -40E Units Operating bank interleave read current: All device banks interleaving reads; IOUT = 0mA; BL = 4, CL = CL (IDD), AL = tRCD (IDD) - 1 × tCK (IDD); tCK = tCK (IDD), tRC = tRC (IDD), tRRD = tRRD (IDD), tRCD = tRCD (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are stable during deselects; Data bus inputs are switching IDD7 3015 2700 2610 2340 mA 256MB, 512MB, 1GB (x72, SR, ECC) 240-Pin DDR2 UDIMM IDD Specifications PDF: 09005aef80e8ad4d htf9c32_64_128x72ay – Rev. F 3/10 EN 17 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2003 Micron Technology, Inc. All rights reserved.

Table 14: DDR2 IDD Specifications and Conditions (Die Revision E) – 1GB Values shown for MT47H128M8 DDR2 SDRAM only and are computed from values specified in the 1Gb (128 Meg x 8) com- ponent data sheet Parameter Symbol -80E/ -800 -667 -53E -40E Units Operating one bank active-precharge current:tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching IDD0 810 765 630 630 mA Operating one bank active-read-precharge current: IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN (IDD), tRCD = tRCD (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data pattern is same as IDD4W IDD1 990 900 855 810 mA Precharge power-down current: All device banks idle; tCK = tCK (IDD); CKE is LOW; Other control and address bus inputs are stable; Data bus in- puts are floating IDD2P 63 63 63 63 mA Precharge quiet standby current: All device banks idle; tCK = tCK (IDD); CKE is HIGH, S# is HIGH; Other control and address bus inputs are stable; Data bus inputs are floating IDD2Q 450 360 360 315 mA Precharge standby current: All device banks idle; tCK = tCK (IDD); CKE is HIGH, S# is HIGH; Other control and address bus inputs are switching; Da- ta bus inputs are switching IDD2N 450 360 360 315 mA Active power-down current: All device banks open; tCK = tCK (IDD); CKE is LOW; Other control and address bus in- puts are stable; Data bus inputs are floating Fast PDN exit MR[12] = 0 IDD3P 360 270 270 270 mA Slow PDN exit MR[12] = 1 90 90 90 90 Active standby current: All device banks open; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid com- mands; Other control and address bus inputs are switching; Data bus inputs are switching IDD3N 540 495 405 360 mA Operating burst write current: All device banks open; Continuous burst writes; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching IDD4W 1440 1215 1125 945 mA Operating burst read current: All device banks open; Continuous burst read, IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid com- mands; Address bus inputs are switching; Data bus inputs are switching IDD4R 1440 1215 1125 945 mA Burst refresh current:tCK = tCK (IDD); REFRESH command at every tRFC (IDD) interval; CKE is HIGH, S# is HIGH between valid commands; Other con- trol and address bus inputs are switching; Data bus inputs are switching IDD5 2115 1935 1890 1845 mA Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and address bus inputs are floating; Data bus inputs are floating IDD6 63 63 63 63 mA 256MB, 512MB, 1GB (x72, SR, ECC) 240-Pin DDR2 UDIMM IDD Specifications PDF: 09005aef80e8ad4d htf9c32_64_128x72ay – Rev. F 3/10 EN 18 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2003 Micron Technology, Inc. All rights reserved.

Table 14: DDR2 IDD Specifications and Conditions (Die Revision E) – 1GB (Continued) Values shown for MT47H128M8 DDR2 SDRAM only and are computed from values specified in the 1Gb (128 Meg x 8) com- ponent data sheet Parameter Symbol -80E/ -800 -667 -53E -40E Units Operating bank interleave read current: All device banks interleaving reads; IOUT = 0mA; BL = 4, CL = CL (IDD), AL = tRCD (IDD) - 1 × tCK (IDD); tCK = tCK (IDD), tRC = tRC (IDD), tRRD = tRRD (IDD), tRCD = tRCD (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are stable during deselects; Data bus inputs are switching IDD7 3015 2520 2430 2340 mA 256MB, 512MB, 1GB (x72, SR, ECC) 240-Pin DDR2 UDIMM IDD Specifications PDF: 09005aef80e8ad4d htf9c32_64_128x72ay – Rev. F 3/10 EN 19 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2003 Micron Technology, Inc. All rights reserved.

For the latest SPD data, refer to Micron's SPD page: www.micron.com/SPD. Table 15: SPD EEPROM Operating Conditions Parameter/Condition Symbol Min Max Units Supply voltage VDDSPD 1.7 3.6 V Input high voltage: logic 1; All inputs VIH VDDSPD × 0.7 VDDSPD + 0.5 V Input low voltage: logic 0; All inputs VIL –0.6 VDDSPD × 0.3 V Output low voltage: IOUT = 3mA VOL – 0.4 V Input leakage current: VIN = GND to VDD ILI 0.1 3 µA Output leakage current: VOUT = GND to VDD ILO 0.05 3 µA Standby current ISB 1.6 4 µA Power supply current, READ: SCL clock frequency = 100 kHz ICCR 0.4 1 mA Power supply current, WRITE: SCL clock frequency = 100 kHz ICCW 2 3 mA Table 16: SPD EEPROM AC Operating Conditions Parameter/Condition Symbol Min Max Units Notes SCL LOW to SDA data-out valid tAA 0.2 0.9 µs 1 Time bus must be free before a new transition can start tBUF 1.3 – µs Data-out hold time tDH 200 – ns SDA and SCL fall time tF – 300 ns 2 SDA and SCL rise time tR – 300 ns 2 Data-in hold time tHD:DAT 0 – µs Start condition hold time tHD:STA 0.6 – µs Clock HIGH period tHIGH 0.6 – µs Noise suppression time constant at SCL, SDA inputs tI – 50 µs Clock LOW period tLOW 1.3 – µs SCL clock frequency tSCL – 400 kHz Data-in setup time tSU:DAT 100 – ns Start condition setup time tSU:STA 0.6 – µs 3 Stop condition setup time tSU:STO 0.6 – µs WRITE cycle time tWRC – 10 ms 4 Notes: 1. To avoid spurious start and stop conditions, a minimum delay is placed between SCL = 1 and the falling or rising edge of SDA. 2. This parameter is sampled. 3. For a restart condition or following a WRITE cycle. 4. The SPD EEPROM WRITE cycle time ( tWRC) is the time from a valid stop condition of a write sequence to the end of the EEPROM internal ERASE/PROGRAM cycle. During the WRITE cycle, the EEPROM bus interface circuit is disabled, SDA remains HIGH due to pull- up resistance, and the EEPROM does not respond to its slave address. 256MB, 512MB, 1GB (x72, SR, ECC) 240-Pin DDR2 UDIMM Serial Presence-Detect PDF: 09005aef80e8ad4d htf9c32_64_128x72ay – Rev. F 3/10 EN 20 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2003 Micron Technology, Inc. All rights reserved.

Figure 3: 240-Pin DDR2 UDIMM 30.50 (1.20) 29.85 (1.175) Pin 1 17.78 (0.70) TYP 2.50 (0.098) D (2X) 2.30 (0.091) TYP 5.0 (0.197) TYP 123.0 (4.840) TYP 1.0 (0.039) TYP 0.80 (0.031) TYP 2.00 (0.079) R (4X) 0.76 (0.030) R Pin 120 Front view 133.50 (5.256) 133.20 (5.244) 55.0 (2.165) TYP 63.0 (2.48) TYP 10.00 (0.394) TYP Back view Pin 240 Pin 121 1.37 (0.054) 1.17 (0.046) 2.70 (0.106) MAX U1 U2 U3 U4 U10 U6 U7 U8 U9 No components this side of module 2.21 (0.087) TYP 1.0 (0.039) TYP 3.04 (0.1197) TYP 70.66 (2.782) TYP Notes: 1. All dimensions are in millimeters (inches); MAX/MIN or typical (TYP) where noted. 2. The dimensional diagram is for reference only. Refer to the JEDEC MO document for additional design dimensions. 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 www.micron.com/productsupport Customer Comment Line: 800-932-4992 Micron and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered final, these specifications are subject to change, as further product development and data characterization some- times occur. 256MB, 512MB, 1GB (x72, SR, ECC) 240-Pin DDR2 UDIMM Module Dimensions PDF: 09005aef80e8ad4d htf9c32_64_128x72ay – Rev. F 3/10 EN 21 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2003 Micron Technology, Inc. All rights reserved.