MT8VDDT1664A

MT8VDDT3264AG MICRON | Alldatasheet

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• 184-pin dual in-line memory module (DIMM)  Fast data transfer rates: PC2100 or PC2700  Utilizes 266 MT/s and 333 MT/s DDR SDRAM components  128MB (16 Meg x 64), 256MB (32 Meg x 64), and 512MB (64 Meg x 64) DD = VDDQ = +2.5V V DDSPD = +2.3V to +3.6V  2.5V I/O (SSTL_2 compatible)  Commands entered on each positive CK edge  DQS edge-aligned with data for READs; center- aligned with data for WRITEs  Internal, pipelined double data rate (DDR) architecture; two data accesses per clock cycle  Bidirectional data strobe (DQS) transmitted/ received with data—i.e., source-synchronous data capture  Differential clock inputs (CK and CK#)  Four internal device banks for concurrent operation  Programmable burst lengths: 2, 4, or 8  Auto precharge option  Auto Refresh and Self Refresh Modes  15.625µs (128MB), 7.8125µs (256MB, 512MB) maximum average periodic refresh interval  Serial Presence Detect (SPD) with EEPROM  Programmable READ CAS latency G o l d e d g e c o n t a c t s Figure 1: 184-Pin DIMM (MO-206) NOTE: 1. Consult Micron for product availability. 2. CL = CAS (READ) Latency OPTIONS MARKING P a c k a g e 184-pin DIMM (standard) G 184-pin DIMM (lead-free)1 Y  Memory Clock/Speed, CAS Latency 2 6ns (167 MHz), 333 MT/s, CL = 2.5 -335 7.5ns (133 MHz), 266 MT/s, CL = 2 -262 1 7.5ns (133 MHz), 266 MT/s, CL = 2 -26A 1 7.5ns (133 MHz), 266 MT/s, CL = 2.5 -265 P C B Standard 1.25in. (31.75mm) See page 2 note Low-Profile 1.15in. (29.21mm) See page 2 note Standard 1.25in. (31.75mm) Low-Profile 1.15in. (29.21mm) Table 1: Address Table 128MB 256MB 512MB Refresh Count 4K 8K 8K Row Addressing 4K (A0–A11) 8K (A0–A12) 8K (A0–A12) Device Bank Addressing 4 (BA0, BA1) 4 (BA0, BA1) 4 (BA0, BA1) Device Configuration 128Mb (16 Meg x 8) 256Mb (32 Meg x 8) 512Mb (64 Meg x 8) Column Addressing 1K (A0–A9) 1K (A0–A9) 2K (A0–A9, A11) Module Rank Addressing 1 (S0#) 1 (S0#) 1 (S0#)

128MB, 256MB, 512MB (x64, SR) 184-PIN DDR SDRAM UDIMM pdf: 09005aef80867ab3, source: 09005aef80867a99 Micron Technology, Inc., reserves the right to change products or specifications without notice. DD8C16_32_64x64AG.fm - Rev. G 9/04 EN 2 ©2004 Micron Technology. Inc. NOTE: All part numbers end with a two-place code (not shown), designating component and PCB revisions. Consult factory for current revision codes. Example: MT8VDDT3264AG-265A1. Table 2: Part Numbers and Timing Parameters PART NUMBER MODULE DENSITY CONFIGURATION MODULE BANDWITH MEMORYCLOCK/ DATA RATE LATENCY (CL - TRCD - TRP) MT8VDDT1664AG-335__ 128MB 16 Meg x 64 2.7GB/s 6ns/333MT/s 2.5-3-3 MT8VDDT1664AY-335__ 128MB 16 Meg x 64 2.7GB/s 6ns/333MT/s 2.5-3-3 MT8VDDT1664AG-262__ 128MB 16 Meg x 64 2.1GB/s 7.5ns/266MT/s 2-2-2 MT8VDDT1664AY-262__ 128MB 16 Meg x 64 2.1GB/s 7.5ns/266MT/s 2-2-2 MT8VDDT1664AG-26A__ 128MB 16 Meg x 64 2.1GB/s 7.5ns/266MT/s 2-3-3 MT8VDDT1664AY-26A__ 128MB 16 Meg x 64 2.1GB/s 7.5ns/266MT/s 2-3-3 MT8VDDT1664AG-265__ 128MB 16 Meg x 64 2.1GB/s 7.5ns/266MT/s 2.5-3-3 MT8VDDT1664AY-265__ 128MB 16 Meg x 64 2.1GB/s 7.5ns/266MT/s 2.5-3-3 MT8VDDT3264AG-335__ 256MB 32 Meg x 64 2.7GB/s 6ns/333MT/s 2.5-3-3 MT8VDDT3264AY-335__ 256MB 32 Meg x 64 2.7GB/s 6ns/333MT/s 2.5-3-3 MT8VDDT3264AG-262__ 256MB 32 Meg x 64 2.1GB/s 7.5ns/266MT/s 2-2-2 MT8VDDT3264AY-262__ 256MB 32 Meg x 64 2.1GB/s 7.5ns/266MT/s 2-2-2 MT8VDDT3264AG-26A__ 256MB 32 Meg x 64 2.1GB/s 7.5ns/266MT/s 2-3-3 MT8VDDT3264AY-26A__ 256MB 32 Meg x 64 2.1GB/s 7.5ns/266MT/s 2-3-3 MT8VDDT3264AG-265__ 256MB 32 Meg x 64 2.1GB/s 7.5ns/266MT/s 2.5-3-3 MT8VDDT3264AY-265__ 256MB 32 Meg x 64 2.1GB/s 7.5ns/266MT/s 2.5-3-3 MT8VDDT6464AG-335__ 512MB 64 Meg x 64 2.7GB/s 6ns/333MT/s 2.5-3-3 MT8VDDT6464AY-335__ 512MB 64 Meg x 64 2.7GB/s 6ns/333MT/s 2.5-3-3 MT8VDDT6464AG-262__ 512MB 64 Meg x 64 2.1GB/s 7.5ns/266MT/s 2-2-2 MT8VDDT6464AY-262__ 512MB 64 Meg x 64 2.1GB/s 7.5ns/266MT/s 2-2-2 MT8VDDT6464AG-26A__ 512MB 64 Meg x 64 2.1GB/s 7.5ns/266MT/s 2-3-3 MT8VDDT6464AY-26A__ 512MB 64 Meg x 64 2.1GB/s 7.5ns/266MT/s 2-3-3 MT8VDDT6464AG-265__ 512MB 64 Meg x 64 2.1GB/s 7.5ns/266MT/s 2.5-3-3 MT8VDDT6464AY-265__ 512MB 64 Meg x 64 2.1GB/s 7.5ns/266MT/s 2.5-3-3

128MB, 256MB, 512MB (x64, SR) 184-PIN DDR SDRAM UDIMM pdf: 09005aef80867ab3, source: 09005aef80867a99 Micron Technology, Inc., reserves the right to change products or specifications without notice. DD8C16_32_64x64AG.fm - Rev. G 9/04 EN 3 ©2004 Micron Technology. Inc. NOTE: Pin 115 is “No Connect” for 128MB, “A12” for 256MB and 512MB. Figure 2: 184-Pin DIMM Pin Locations Table 3: Pin Assignment (184-Pin DIMM Front) PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL 1V REF 24 DQ17 47 DNU 70 V DD 2D Q 0 25 DQS2 48 A0 71 NC 3V SS 26 V SS 49 DNU 72 DQ48 4D Q 1 27 A9 50 V SS 73 DQ49 5D Q S 0 28 DQ18 51 DNU 74 V SS 6D Q 2 29 A7 52 BA1 75 CK2# 7V DD 30 V DDQ 53 DQ32 76 CK2 8D Q 3 3 1 D Q 1 9 54 V DDQ7 7V DDQ 9N C 32 A5 55 DQ33 78 DQS6

10 NC 33 DQ24 56 DQS4 79 DQ50

11 V SS 34 V SS 57 DQ34 80 DQ51

12 DQ8 35 DQ25 58 V SS 81 V SS

13 DQ9 36 DQS3 59 BA0 82 NC

14 DQS1 37 A4 60 DQ35 83 DQ56

15 V DDQ3 8 V DD 61 DQ40 84 DQ57

16 CK1 39 DQ26 62 V DDQ8 5 V DD

17 CK1# 40 DQ27 63 WE# 86 DQS7

18 V SS 41 A2 64 DQ41 87 DQ58

19 DQ10 42 V SS 65 CAS# 88 DQ59

20 DQ11 43 A1 66 V SS 89 V SS

21 CKE0 44 DNU 67 DQS5 90 NC

22 V DDQ4 5 D N U 68 DQ42 91 SDA

23 DQ16 46 V DD 69 DQ43 92 SCL

Table 4: Pin Assignment (184-Pin DIMM Back) PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL

93 V SS 116 V SS 139 V SS 162 DQ47

94 DQ4 117 DQ21 140 DNU 163 NC

95 DQ5 118 A11 141 A10 164 V DDQ

96 V DDQ 119 DM2 142 DNU 165 DQ52

97 DM0 120 V DD 143 V DDQ 166 DQ53

98 DQ6 121 DQ22 144 DNU 167 NC

99 DQ7 122 A8 145 V SS 168 V DD

100 V SS 123 DQ23 146 DQ36 169 DM6

101 NC 124 V SS 147 DQ37 170 DQ54

102 NC 125 A6 148 V DD 171 DQ55

103 NC 126 DQ28 149 DM4 172 V DD

104 V DDQ 127 DQ29 150 DQ38 173 NC

105 DQ12 128 V DDQ 151 DQ39 174 DQ60

106 DQ13 129 DM3 152 V SS 175 DQ61

107 DM1 130 A3 153 DQ44 176 V SS

108 V DD 131 DQ30 154 RAS# 177 DM7

109 DQ14 132 V SS 155 DQ45 178 DQ62

110 DQ15 133 DQ31 156 V DDQ 179 DQ63

111 DNU 134 DNU 157 S0# 180 V DDQ

112 V DDQ 135 DNU 158 DNU 181 SA0

113 NC 136 V DDQ 159 DM5 182 SA1

114 DQ20 137 CK0 160 V SS 183 SA2

115 NC/A12 138 CK0# 161 DQ46 184 V DDSPD

PIN 93PIN 144PIN 145PIN 184 PIN 1 PIN 52 PIN 53 PIN 92 Indicates a VDD or VDDQ pin Indicates a VSS pin No Components This Side of Module Back View Front View U1 U2 U3 U4 U6 U7 U8 U9 U10 U1 U2 U3 U4 U6 U7 U8 U9 U19 U18 U17 U16 U14 U13 U12 U11 U10 PIN 93PIN 144PIN 145PIN 184 PIN 1 PIN 52 PIN 53 PIN 92 Front View Back View Indicates a VDD or VDDQ pin Indicates a VSS pin

128MB, 256MB, 512MB (x64, SR) 184-PIN DDR SDRAM UDIMM pdf: 09005aef80867ab3, source: 09005aef80867a99 Micron Technology, Inc., reserves the right to change products or specifications without notice. DD8C16_32_64x64AG.fm - Rev. G 9/04 EN 4 ©2004 Micron Technology. Inc. Table 5: Pin Descriptions Pin numbers may not correlate with symbols; refer to Pin Assignment tables on page 3 for more information PIN NUMBERS SYMBOL TYPE DESCRIPTION 63, 65, 154 WE#, CAS#, RAS# Input Command Inputs: RAS#, CAS#, and WE# (along with S#) define the command being entered. 16, 17, 75, 76, 137, 138 CK0, CK0#, CK1, CK1#, CK2, CK2# Input Clock: CK, CK# are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK,and negative edge of CK#. Output data (DQs and DQS) is referenced to the crossings of CK and CK#.

21 CKE0 Input Clock Enable: CKE HIGH activates and CKE LOW deactivates

the internal clock, input buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER-DOWN and SELF REFRESH operations (all device banks idle), or ACTIVE POWER- DOWN (row ACTIVE in any device bank). CKE is synchronous for POWER-DOWN entry and exit, and for SELF REFRESH entry. CKE is asynchronous for SELF REFRESH exit and for disabling the outputs. CKE must be maintained HIGH throughout read and write accesses. Input buffers (excluding CK, CK# and CKE) are disabled during POWER-DOWN. Input buffers (excluding CKE) are disabled during SELF REFRESH. CKE is an SSTL_2 input but will detect an LVCMOS LOW level after V DD is applied and until CKE is first brought HIGH. After CKE is brought HIGH, it becomes an SSTL_2 input only.

157 S0# Input Chip Selects: S# enables (registered LOW) and disables

(registered HIGH) the command decoder. All commands are masked when S# is registered HIGH. S# is considered part of the command code. 52, 59 BA0, BA1 Input Bank Address: BA0 and BA1 define to which device bank an ACTIVE, READ, WRITE, or PRECHARGE command is being applied. 115 (256MB, 512MB), 118, 122, 125, 130, 141 A0–A11 (128MB) A0–A12 (256MB, 512MB) Input Address Inputs: Provide the row address for ACTIVE commands, and the column address and auto precharge bit (A10) for READ/WRITE commands, to select one location out of the memory array in the respective device bank. A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one device bank (A10 LOW, device bank selected by BA0, BA1) or all device banks (A10 HIGH). The address inputs also provide the op-code during a MODE REGISTER SET command. BA0 and BA1 define which mode register (mode register or extended mode register) is loaded during the LOAD MODE REGISTER command. 5, 14, 25, 36, 56, 67, 78, 86 DQS0–DQS7 Input/ Output Data Strobe: Output with READ data, input with WRITE data. DQS is edge-aligned with READ data, centered in WRITE data. Used to capture data. 97, 107, 119, 129, 149, 159, 169, 177 DM0 –DM7 Input Data Write Mask: DQS9–DQS16 function as DM0–DM7. DM LOW allows WRITE operation. DM HIGH blocks WRITE operation. DM lines do not affect READ operation.

128MB, 256MB, 512MB (x64, SR) 184-PIN DDR SDRAM UDIMM pdf: 09005aef80867ab3, source: 09005aef80867a99 Micron Technology, Inc., reserves the right to change products or specifications without notice. DD8C16_32_64x64AG.fm - Rev. G 9/04 EN 5 ©2004 Micron Technology. Inc. 95, 98, 99, 105, 106, 109, 110, 114, 117, 121, 123, 126, 127, 131, 133, 146, 147, 150, 151, 153, 155, 161, 162, 165, 166, 170, 171, 174, 175, 178, 179 DQ0–DQ63 Input/ Output Data I/Os: Data bus.

92 SCL Input Serial Clock for Presence-Detect: SCL is used to synchronize the

presence-detect data transfer to and from the module. 181,182, 183 SA0–SA2 Input Presence-Detect Address Inputs: These pins are used to configure the presence-detect device.

91 SDA Input/

Serial Presence-Detect Data: SDA is a bidirectional pin used to transfer addresses and data into and out of the presence- detect device. REF Supply SSTL_2 reference voltage. 104, 112, 128, 136, 143, 156, 164, 172, 180 VDDQ Supply DQ Power Supply: +2.5V ±0.2V. 7, 38, 46, 70, 85, 108, 120, 148, 168 VDD Supply Power Supply: +2.5V ±0.2V. 66, 74, 81, 89, 93, 100, 116, 124, 132, 139, 145, 152, 160, 176 VSS Supply Ground. 184 V DDSPD Supply Serial EEPROM positive power supply: +2.3V to +3.6V. 44, 45, 47, 49, 51, 111, 134, 135, 140, 142, 144, 158 DNU — Do Not Use: These pins are not connected on these modules, but are assigned pins on other modules in this product family. 9, 10, 71, 82, 90, 101, 102, 103, 113, 115 (128MB), 163, 167, 173 NC — No Connect: These pins should be left unconnected. Table 5: Pin Descriptions (Continued) Pin numbers may not correlate with symbols; refer to Pin Assignment tables on page 3 for more information PIN NUMBERS SYMBOL TYPE DESCRIPTION

128MB, 256MB, 512MB (x64, SR) 184-PIN DDR SDRAM UDIMM pdf: 09005aef80867ab3, source: 09005aef80867a99 Micron Technology, Inc., reserves the right to change products or specifications without notice. DD8C16_32_64x64AG.fm - Rev. G 9/04 EN 6 ©2004 Micron Technology. Inc. Figure 3: Functional Block Diagram – Standard PCB SA0 SERIAL PD U10 SDA SA1 SA2 BA0, BA1 A0-A11 (128MB) A0-A12 (256MB, 512MB) RAS# BA0, BA1: DDR SDRAMS A0-A11: DDR SDRAMS A0-A12: DDR SDRAMS RAS#: DDR SDRAMS CAS#: DDR SDRAMS WE#: DDR SDRAMS CKE0: DDR SDRAMS CAS# WE# CKE0 VREF VSS DDR SDRAMS DDR SDRAMS DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DQ DQ DQ DQ DQ DQ DQ DQ DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ DQ DQ DQ DQ DQ DQ DQ DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ DQ DQ DQ DQ DQ DQ DQ DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ DQ DQ DQ DQ DQ DQ DQ DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ DQ DQ DQ DQ DQ DQ DQ DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DM CS# DQS DQ DQ DQ DQ DQ DQ DQ DQ DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM0 S0# DQ DQ DQ DQ DQ DQ DQ DQ WP SCL DM CS# DQS DM CS# DQS DM CS# DQS DQS0 DM4 DQS4 DM1 DQS1 DM5 DQS5 DM2 DQS2 DM6 DQS6 DM CS# DQS DQ DQ DQ DQ DQ DQ DQ DQ DM CS# DQS DM CS# DQS DM CS# DQS DM3 DQS3 DM7 DQS7 VDDQ VDD DDR SDRAMS DDR SDRAMS DDR SDRAM CK0 CK0# 120Ω DDR SDRAM CK1 CK1# DDR SDRAM CK2 CK2# VDDSPD SPD/EEPROM 5.1Ω 5.1Ω 5.1Ω 5.1Ω 5.1Ω 5.1Ω 6pF 120Ω 4.5pF120Ω 4.5pF NOTE: 1. All resistor values are 22 Ω unless otherwise specified. 2. Per industry standard, Micron utilizes various component speed grades as referenced in the Module Part Numbering Guide at www.micron.com/num- berguide. Standard modules use the following DDR SDRAM devices: MT46V16M8TG (128MB), MT46V32M8TG (256MB); MT46V64M8TG (512MB) Lead-free modules use the following DDR SDRAM devices: MT46V16M8P (128MB), MT46V32M8P (256MB); MT46V64M8P (512MB)

128MB, 256MB, 512MB (x64, SR) 184-PIN DDR SDRAM UDIMM pdf: 09005aef80867ab3, source: 09005aef80867a99 Micron Technology, Inc., reserves the right to change products or specifications without notice. DD8C16_32_64x64AG.fm - Rev. G 9/04 EN 7 ©2004 Micron Technology. Inc. Figure 4: Functional Block Diagram – Low-Profile PCB SA0 SERIAL PD U10 SDA SA1 SA2 BA0, BA1 A0-A11 (128MB) A0-A12 (256MB, 512MB) RAS# BA0, BA1: DDR SDRAMS A0-A11: DDR SDRAMS A0-A12: DDR SDRAMS RAS#: DDR SDRAMS CAS#: DDR SDRAMS CKE0: DDR SDRAMS WE#: DDR SDRAMS CAS# CKE0 WE# VREF VSS DDR SDRAMS DDR SDRAMS DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DQ DQ DQ DQ DQ DQ DQ DQ DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ DQ DQ DQ DQ DQ DQ DQ DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ DQ DQ DQ DQ DQ DQ DQ DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ DQ DQ DQ DQ DQ DQ DQ DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ DQ DQ DQ DQ DQ DQ DQ DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DM CS# DQS DQ DQ DQ DQ DQ DQ DQ DQ DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM0 S0# DQ DQ DQ DQ DQ DQ DQ DQ WP SCL DM CS# DQS DM CS# DQS DM CS# DQS DQS0 DM4 DQS4 DM1 DQS1 DM5 DQS5 DM2 DQS2 DM6 DQS6 DM CS# DQS DQ DQ DQ DQ DQ DQ DQ DQ DM CS# DQS DM CS# DQS DM CS# DQS DM3 DQS3 DM7 DQS7 VDDQ VDD DDR SDRAMS DDR SDRAMS DDR SDRAM X 2CK0 CK0# 120 DDR SDRAM X 3CK1 CK1# 120 DDR SDRAM X 3CK2 CK2# 120 VDDSPD SPD/EEPROM NOTE: 1. All resistor values are 22 Ω unless otherwise specified. 2. Per industry standard, Micron utilizes various component speed grades as referenced in the Module Part Numbering Guide at www.micron.com/num- berguide. 3. To optimize system and loading and signal integrity for -335 speed grade, 3Ω stub resistors may be placed on command/address and control lines. Contact Micron CCG Applications for additional information. Standard modules use the following DDR SDRAM devices: MT46V16M8TG (128MB), MT46V32M8TG (256MB); MT46V64M8TG (512MB) Lead-free modules use the following DDR SDRAM devices: MT46V16M8P (128MB), MT46V32M8P (256MB); MT46V64M8P (512MB)

128MB, 256MB, 512MB (x64, SR) 184-PIN DDR SDRAM UDIMM pdf: 09005aef80867ab3, source: 09005aef80867a99 Micron Technology, Inc., reserves the right to change products or specifications without notice. DD8C16_32_64x64AG.fm - Rev. G 9/04 EN 8 ©2004 Micron Technology. Inc. General Description The MT8VDDT1664A, MT8VDDT3264A, and MT8VDDT6464A are high-speed CMOS, dynamic ran- dom-access, 128MB, 256MB, and 512MB memory modules organized in a x64 configuration. DDR SDRAM modules use internally configured quad-bank DDR SDRAM devices. DDR SDRAM modules use a double data rate archi- tecture to achieve high-speed operation. The double data rate architecture is essentially a 2 n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the DDR SDRAM module effec- tively consists of a single 2 n-bit wide, one-clock-cycle data transfer at the internal DRAM core and two corre- sponding n-bit wide, one-half-clock-cycle data trans- fers at the I/O pins. A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in data capture at the receiver. DQS is an intermittent strobe transmitted by the DDR SDRAM during READs and by the memory controller during WRITEs. DQS is edge-aligned with data for READs and center-aligned with data for WRITEs. DDR SDRAM modules operate from multiple differ- ential clocks (CK and CK#); the crossing of CK going HIGH and CK# going LOW will be referred to as the positive edge of CK. Commands (address and control signals) are registered at every positive edge of CK. Input data is registered on both edges of DQS, and out- put data is referenced to both edges of DQS, as well as to both edges of CK. Read and write accesses to DDR SDRAM modules are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then fol- lowed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the device bank and row to be accessed (BA0, BA1 select device bank; A0–A11 select device row for the 128MB module, A0–A12 select device row for the 256MB and 512MB modules). The address bits registered coincident with the READ or WRITE command are used to select the device bank and the starting device column location for the burst access. DDR SDRAM modules provide for programmable read or write burst lengths of 2, 4, or 8 locations. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. The pipelined, multibank architecture of DDR SDRAM modules allows for concurrent operation, thereby providing high effective bandwidth by hiding row precharge and activation time. An auto refresh mode is provided, along with a power-saving power-down mode. All inputs are com- patible with the JEDEC Standard for SSTL_2. All out- puts are SSTL_2, Class II compatible. For more information regarding DDR SDRAM operation, refer to the 128Mb, 256Mb, or 512Mb DDR SDRAM compo- nent data sheets. Serial Presence-Detect Operation These DDR SDRAM modules incorporate serial presence-detect (SPD). The SPD function is imple- mented using a 2,048-bit EEPROM. This nonvolatile storage device contains 256 bytes. The first 128 bytes can be programmed by Micron to identify the module type and various SDRAM organizations and timing parameters. The remaining 128 bytes of storage are available for use by the customer. System READ/ WRITE operations between the master (system logic) and the slave EEPROM device (DIMM) occur via a standard I 2C bus using the DIMM’ s SCL (clock) and SDA (data) signals, together with SA (2:0), which pro- vide eight unique DIMM/EEPROM addresses. Write protect (WP) is tied to ground on the module, perma- nently disabling hardware write protect. Mode Register Definition The mode register is used to define the specific mode of operation of DDR SDRAM devices. This defi- nition includes the selection of a burst length, a burst type, a CAS latency and an operating mode, as shown in Figure 5, Mode Register Definition Diagram, on page 9. The mode register is programmed via the MODE REGISTER SET command (with BA0 = 0 and BA1 = 0) and will retain the stored information until it is programmed again or the device loses power (except for bit A8, which is self-clearing). Reprogramming the mode register will not alter the contents of the memory, provided it is performed cor- rectly. The mode register must be loaded (reloaded) when all device banks are idle and no bursts are in progress, and the controller must wait the specified time before initiating the subsequent operation. Vio- lating either of these requirements will result in unspecified operation. Mode register bits A0–A2 specify the burst length, A3 specifies the type of burst (sequential or inter- leaved), A4–A6 specify the CAS latency, and A7–A11 (128MB) or A7–A12 (256MB, 512MB) specify the oper- ating mode.

128MB, 256MB, 512MB (x64, SR) 184-PIN DDR SDRAM UDIMM pdf: 09005aef80867ab3, source: 09005aef80867a99 Micron Technology, Inc., reserves the right to change products or specifications without notice. DD8C16_32_64x64AG.fm - Rev. G 9/04 EN 9 ©2004 Micron Technology. Inc. Burst Type Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit M3. T h e o r d e r i n g o f a c c e s s e s w i t h i n a b u r s t i s d e t e r - mined by the burst length, the burst type and the start- ing column address, as shown in Table 6, Burst Definition Table, on page 10. Burst Length Read and write accesses to the DDR SDRAM are burst oriented, with the burst length being program- mable, as shown in Figure 5, Mode Register Definition Diagram. The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE command. Burst lengths of 2, 4, or 8 locations are available for both the sequential and the interleaved burst types. Reserved states should not be used, as unknown operation or incompatibility with future versions may result. When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached. The block is uniquely selected by A1–A i when the burst length is set to two, by A2–Ai w h e n t h e b u r s t l e n g t h i s s e t t o f o u r , a n d b y A3–Ai when the burst length is set to eight (where A i is the most significant column address bit for a given configuration. See Note 5 of Figure 6, Burst Definition Table, on page 10). The remaining (least significant) address bit(s) is (are) used to select the starting loca- tion within the block. The programmed burst length applies to both read and write bursts. Read Latency The READ latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first bit of output data. The latency can be set to 2 or 2.5 clocks, as shown in Figure 6, CAS Latency Diagram, on page 10. I f a R E A D c o m m a n d i s r e g i s t e r e d a t c l o c k e d g e n, and the latency is m clocks, the data will be available nominally coincident with clock edge n + m. Table 7, CAS Latency (CL) Table, on page 10, indicates the operating frequencies at which each CAS latency set- ting can be used. Reserved states should not be used as unknown operation or incompatibility with future versions may result. Figure 5: Mode Register Definition Diagram M3 = 0 Reserved Reserved Reserved Reserved Reserved M3 = 1 Reserved Reserved Reserved Reserved Reserved Operating Mode Normal Operation Normal Operation/Reset DLL All other states reserved Valid Valid Burst Type Sequential Interleaved CAS Latency Reserved Reserved Reserved Reserved Reserved 2.5 Reserved Burst Length Burst LengthCAS Latency BT0* A9 A7 A6 A5 A4 A3A8 A2 A1 A0 Mode Register (Mx) Address Bus 9 7 654 38 2 1 0 M6-M0 M8 M7 Operating Mode A10A12 A11BA0BA1 10111213 * M14 and M13 (BA1 and BA0) must be “0, 0” to select the base mode register (vs. the extended mode register). M9M10M12 M11 Burst LengthCAS Latency BT0*0* A9 A7 A6 A5 A4 A3A8 A2 A1 A0 Mode Register (Mx) Address Bus 9 7 654 38 2 1 0 Operating Mode A10A11BA0BA1 10111213 * M13 and M12 (BA1 and BA0) must be “0, 0” to select the base mode register (vs. the extended mode register). 128MB Module 256MB and 512MB Modules

128MB, 256MB, 512MB (x64, SR) 184-PIN DDR SDRAM UDIMM pdf: 09005aef80867ab3, source: 09005aef80867a99 Micron Technology, Inc., reserves the right to change products or specifications without notice. DD8C16_32_64x64AG.fm - Rev. G 9/04 EN 10 ©2004 Micron Technology. Inc. NOTE: 1. For a burst length of two, A1–Ai select the two- data-element block; A0 selects the first access within the block. 2. For a burst length of four, A2–Ai select the four- data-element block; A0–A1 select the first access within the block. 3. For a burst length of eight, A3–Ai select the eight- data-element block; A0–A2 select the first access within the block. 4. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. 5. i = 9 (128MB, 256MB) i = 9, 11 (512MB) Figure 6: CAS Latency Diagram Operating Mode The normal operating mode is selected by issuing a MODE REGISTER SET command with bits A7 –A11 (128MB), or A7 –A12 (256MB, 512MB) each set to zero, and bits A0–A6 set to the desired values. A DLL reset is initiated by issuing a MODE REGISTER SET command with bits A7 and A9 –A11 (128MB), or A7 and A9 –A12 (256MB, 512MB) each set to zero, bit A8 set to one, and bits A0 –A6 set to the desired values. Although not required by the Micron device, JEDEC specifications recommend when a LOAD MODE REGISTER com- m a n d i s i s s u e d t o r e s e t t h e D L L , i t s h o u l d a l w a y s b e followed by a LOAD MODE REGISTER command to select normal operating mode. All other combinations of values for A7 –A11, or A7 – A12, are reserved for future use and/or test modes. Test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result. Extended Mode Register The extended mode register controls functions beyond those controlled by the mode register; these additional functions are DLL enable/disable and out- put drive strength. These functions are controlled via the bits shown in Figure 7, Extended Mode Register Definition Diagram, on page 11. The extended mode register is programmed via the LOAD MODE REGIS- Table 6: Burst Definition Table BURST LENGTH STARTING COLUMN ADDRESS ORDER OF ACCESSES WITHIN A BURST TYPE = SEQUENTIAL TYPE = INTERLEAVED 2 A0 0 0-1 0-1 1 1-0 1-0

4 A1 A0

8 A2 A1 A0

Table 7: CAS Latency (CL) Table ALLOWABLE OPERATING CLOCK FREQUENCY (MHZ) SPEED CL = 2 CL = 2.5 -335 75 ≤ f ≤ 133 75 ≤ f ≤ 167 -262 75 ≤ f ≤ 133 75 ≤ f ≤ 133 -26A 75 ≤ f ≤ 133 75 ≤ f ≤ 133 -265 75 ≤ f ≤ 100 75 ≤ f ≤ 133 CK CK# COMMAND DQ DQS CL = 2 READ NOP NOP NOP READ NOP NOP NOP Burst Length = 4 in the cases shown Shown with nominal tAC, tDQSCK, and tDQSQ CK CK# COMMAND DQ DQS CL = 2.5 T0 T1 T2 T2n T3 T3n T0 T1 T2 T2n T3 T3n DON’T CARETRANSITIONING DATA

128MB, 256MB, 512MB (x64, SR) 184-PIN DDR SDRAM UDIMM pdf: 09005aef80867ab3, source: 09005aef80867a99 Micron Technology, Inc., reserves the right to change products or specifications without notice. DD8C16_32_64x64AG.fm - Rev. G 9/04 EN 11 ©2004 Micron Technology. Inc. TER command to the mode register (with BA0 = 1 and BA1 = 0) and will retain the stored information until it is programmed again or the device loses power. The enabling of the DLL should always be followed by a LOAD MODE REGISTER command to the mode regis- ter (BA0/BA1 both low) to reset the DLL. The extended mode register must be loaded when all device banks are idle and no bursts are in progress, and the controller must wait the specified time before initiating any subsequent operation. Violating either of these requirements could result in unspecified oper- ation. DLL Enable/Disable The DLL must be enabled for normal operation. DLL enable is required during power-up initialization and upon returning to normal operation after having disabled the DLL for the purpose of debug or evalua- tion. (When the device exits self refresh mode, the DLL is enabled automatically.) Any time the DLL is enabled, 200 clock cycles with CKE HIGH must occur before a READ command can be issued. Figure 7: Extended Mode Register Definition Diagram NOTE: 1. BA1 and BA0 (E13 and E12 for 128MB, E14 and E13 for 256MB and 512MB) must be “0, 1” to select the Extended Mode Register (vs. the base Mode Regis- ter). 2. QFC# is not supported. Operating Mode Reserved Reserved Valid DLL Enable Disable DLL1101 A9 A7 A6 A5 A4 A3A8 A2 A1 A0 Extended Mode Register (Ex) Address Bus 9 7 654 38 2 1 0 E0E1, Operating Mode A10A11A12BA1 BA0 1011121314 E3E4 E6 E5E7E8E9 E10E11 E12 DS DLL1101 A9 A7 A6 A5 A4 A3A8 A2 A1 A0 Extended Mode Register (Ex) Address Bus 9 7 654 38 2 1 0 Operating Mode A10A11BA1 BA0 10111213 DS 128MB Module 256MB and 512MB Modules E22 Drive Strength Normal

128MB, 256MB, 512MB (x64, SR) 184-PIN DDR SDRAM UDIMM pdf: 09005aef80867ab3, source: 09005aef80867a99 Micron Technology, Inc., reserves the right to change products or specifications without notice. DD8C16_32_64x64AG.fm - Rev. G 9/04 EN 12 ©2004 Micron Technology. Inc. Commands T able 8, Commands Truth Table, and T able 9, DM Operation Truth T able, provide a general reference of available commands. For a more detailed description of commands and operations, refer to the 128Mb, 256Mb, or 512Mb DDR SDRAM component data sheet. NOTE: 1. DESELECT and NOP are functionally interchangeable. 2. BA0–BA1 provide device bank address and A0–A11 (128MB) or A0–A12 (256MB, 512MB) provide row address. 3. BA0–BA1 provide device bank address; A0–A9 (128MB, 256MB) or A0–A9, A11 (512MB) provide column address; A10 HIGH enables the auto precharge feature (nonpersistent), and A10 LOW disables the auto precharge feature. 4. Applies only to read bursts with auto precharge disabled; this command is undefined (and should not be used) for READ bursts with auto precharge enabled and for WRITE bursts. 5. A10 LOW: BA0–BA1 determine which device bank is precharged. A10 HIGH: all device banks are precharged and BA0– BA1 are “Don’t Care.” 6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW. 7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE. 8. BA0–BA1 select either the mode register or the extended mode register (BA0 = 0, BA1 = 0 select the mode register; BA0 = 1, BA1 = 0 select extended mode register; other combinations of BA0–BA1 are reserved). A0–A11 (128MB) or A0–A12 (256MB, 512MB) provide the op-code to be written to the selected mode register. Table 8: Commands Truth Table CKE is HIGH for all commands shown except SELF REFRESH; all states and sequences not shown are illegal or reserved NAME (FUNCTION) CS# RAS# CAS# WE# ADDR NOTES DESELECT (NOP) HXXX X 1 NO OPERATION (NOP) LHHH X 1 ACTIVE (Select bank and activate row) L L H H Bank/Row 2 READ (Select bank and column, and start READ burst) LHLH B a n k / C o l 3 WRITE (Select bank and column, and start WRITE burst) L H L L Bank/Col 3 BURST TERMINATE LHHL X 4 PRECHARGE (Deactivate row in bank or banks) L L H L Code 5 AUTO REFRESH or SELF REFRESH (Enter self refresh mode) LLLH X 6 , 7 LOAD MODE REGISTER LLLL O p - Code 8 Table 9: DM Operation Truth Table Used to mask write data; provided coincident with the corresponding data NAME (FUNCTION) DM DQS WRITE Enable L Valid WRITE Inhibit HX

128MB, 256MB, 512MB (x64, SR) 184-PIN DDR SDRAM UDIMM pdf: 09005aef80867ab3, source: 09005aef80867a99 Micron Technology, Inc., reserves the right to change products or specifications without notice. DD8C16_32_64x64AG.fm - Rev. G 9/04 EN 13 ©2004 Micron Technology. Inc. Absolute Maximum Ratings Stresses greater than those listed may cause perma- nent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the opera- tional sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Voltage on V DD Supply Voltage on VDDQ Supply Voltage on VREF and Inputs Voltage on I/O Pins Operating Temperature Table 10: DC Electrical Characteristics and Operating Conditions Notes: 1–5, 14, 48; notes appear on pages 19–22; 0°C ≤ TA ≤ +70°C PARAMETER/CONDITION SYMBOL MIN MAX UNITS NOTES Supply Voltage VDD 2.3 2.7 V 32, 36 I/O Supply Voltage VDDQ 2.3 2.7 V 32, 36, 39 I/O Reference Voltage VREF 0.49 x VDDQ 0.51 x V DDQV 6 , 3 9 I/O Termination Voltage (system) VTT VREF - 0.04 V REF + 0.04 V 7, 39 Input High (Logic 1) Voltage VIH(DC)V REF + 0.15 V DD + 0.3 V 25 Input Low (Logic 0) Voltage VIL(DC)- 0 . 3 V REF - 0.15 V 25 INPUT LEAKAGE CURRENT ANY INPUT 0V ≤ VIN ≤ VDD, VREF PIN 0V ≤ VIN ≤ 1.35V (All other pins not under test = 0V) Command/ Address, RAS#, CAS#, WE#, S#, CKE I I -16 16 µA 47 CK0, CK0# -4 4 CK1, CK1#, CK2, CK2# -6 6 DM -2 2 OUTPUT LEAKAGE CURRENT (DQs are disabled; 0V ≤ VOUT ≤ VDDQ) DQ, DQS IOZ -5 5 µA 47 OUTPUT LEVELS: High Current (VOUT = VDDQ-0.373V, minimum VREF, minimum VTT) Low Current (VOUT = 0.373V, maximum VREF, maximum VTT) IOH -16.8 – mA 33, 34IOL 16.8 – mA Table 11: AC Input Operating Conditions Notes: 1–5, 12, 49; notes appear on pages 19–22; 0°C ≤ TA ≤ +70°C; VDD = VDDQ = +2.5V ±0.2V PARAMETER/CONDITION SYMBOL MIN MAX UNITS NOTES Input High (Logic 1) Voltage VIH(AC)V REF + 0.310 – V 25, 35 Input Low (Logic 0) Voltage VIL(AC)– V REF - 0.310 V 25, 35 I/O Reference Voltage VREF(AC) 0.49 x V DDQ0 . 5 1 x V DDQV 6

128MB, 256MB, 512MB (x64, SR) 184-PIN DDR SDRAM UDIMM pdf: 09005aef80867ab3, source: 09005aef80867a99 Micron Technology, Inc., reserves the right to change products or specifications without notice. DD8C16_32_64x64AG.fm - Rev. G 9/04 EN 14 ©2004 Micron Technology. Inc. Table 12: I DD Specifications and Conditions – 128MB DDR SDRAM components only Notes: 1–5, 8, 10, 12, 48; notes appear on pages 19–22; 0°C ≤ TA ≤ +70°C; VDD = VDDQ = +2.5V ±0.2V MAX PARAMETER/CONDITION SYM -335 -262 -26A/ -265 UNITS NOTES OPERATING CURRENT: One device bank; Active-Precharge; tRC = tRC (MIN); tCK = tCK (MIN); DQ, DM, and DQS inputs changing once per clock cycle; Address and control inputs changing once every two clock cycles I DD0 1,000 880 840 mA 20, 42 OPERATING CURRENT: One device bank; Active-Read-Pre-charge; Burst = 2; tRC = tRC (MIN); tCK = tCK (MIN); IOUT = 0mA; Address and control inputs changing once per clock cycle IDD1 1,080 960 960 mA 20, 42 PRECHARGE POWER-DOWN STANDBY CURRENT: All device banks idle; Power-down mode; tCK = tCK (MIN); CKE = LOW IDD2P 24 24 24 mA 21, 28, IDLE STANDBY CURRENT: CS# = HIGH; All device banks idle; tCK = tCK (MIN); CKE = HIGH; Address and other control inputs changing once per clock cycle. VIN = VREF for DQ, DQS, and DM IDD2F 360 360 320 mA 45 ACTIVE POWER-DOWN STANDBY CURRENT: One device bank active; Power-down mode; tCK = tCK (MIN); CKE = LOW IDD3P 200 200 160 mA 21, 28, ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One device bank; Active-Precharge; tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle IDD3N 400 400 360 mA 20, 41 OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); IOUT = 0mA IDD4R 1,120 1,040 1,000 mA 20, 42 OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle IDD4W 1,120 1,000 960 mA 20 AUTO REFRESH CURRENT tREFC = tRFC (MIN) IDD5 2,120 1,760 1,760 mA 20, 44 tREFC = 15.625µs IDD5A 40 40 40 mA 24, 44 SELF REFRESH CURRENT: CKE ≤ 0.2V IDD6 24 24 16 mA 9 OPERATING CURRENT: Four device bank interleaving READs (BL= 4) with auto precharge, tRC = minimum tRC allowed; tCK = tCK (MIN); Address and control inputs change only during Active, READ, or WRITE commands IDD7 2,840 2,640 2,600 mA 20, 43

128MB, 256MB, 512MB (x64, SR) 184-PIN DDR SDRAM UDIMM pdf: 09005aef80867ab3, source: 09005aef80867a99 Micron Technology, Inc., reserves the right to change products or specifications without notice. DD8C16_32_64x64AG.fm - Rev. G 9/04 EN 15 ©2004 Micron Technology. Inc. Table 13: I DD Specifications and Conditions – 256MB DDR SDRAM components only Notes: 1–5, 8, 10, 12, 48; notes appear on pages 19–22; 0°C ≤ TA ≤ +70°C; VDD = VDDQ = +2.5V ±0.2V MAX PARAMETER/CONDITION SYM -335 -262 -26A/ -265 UNITS NOTES OPERATING CURRENT: One device bank; Active-Precharge; tRC = tRC (MIN); tCK = tCK (MIN); DQ, DM, and DQS inputs changing once per clock cycle; Address and control inputs changing once every two clock cycles IDD0 1,000 1,000 960 mA 20, 42 OPERATING CURRENT: One device bank; Active-Read-Pre-charge; Burst = 4; tRC = tRC (MIN); tCK = tCK (MIN); IOUT = 0mA; Address and control inputs changing once per clock cycle IDD1 1,360 1,280 1,160 mA 20, 42 PRECHARGE POWER-DOWN STANDBY CURRENT: All device banks idle; Power-down mode; tCK = tCK (MIN); CKE = LOW IDD2P 32 32 32 mA 21, 28, IDLE STANDBY CURRENT: CS# = HIGH; All device banks idle; tCK = tCK (MIN); CKE = HIGH; Address and other control inputs changing once per clock cycle. VIN = VREF for DQ, DQS, and DM IDD2F 400 360 360 mA 45 ACTIVE POWER-DOWN STANDBY CURRENT: One device bank active; Power-down mode; tCK = tCK (MIN); CKE = LOW IDD3P 240 200 200 mA 21, 28, ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One device bank; Active-Precharge; tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle IDD3N 480 400 400 mA 20 , 41 OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); IOUT = 0mA IDD4R 1,400 1,200 1,200 mA 20, 42 OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle IDD4W 1,400 1,200 1,200 mA 20 AUTO REFRESH CURRENT tREFC = tRFC (MIN) IDD5 2,040 1,880 1,880 mA 20, 44 tREFC = 7.8125µs IDD5A 48 48 48 mA 24, 44 SELF REFRESH CURRENT: CKE ≤ 0.2V IDD6 32 32 32 mA 9 OPERATING CURRENT: Four device bank interleaving READs (BL= 4) with auto precharge,tRC = minimum tRC allowed; tCK = tCK (MIN); Address and control inputs change only during Active, READ, or WRITE commands IDD7 3,280 2,800 2,800 mA 20, 43

128MB, 256MB, 512MB (x64, SR) 184-PIN DDR SDRAM UDIMM pdf: 09005aef80867ab3, source: 09005aef80867a99 Micron Technology, Inc., reserves the right to change products or specifications without notice. DD8C16_32_64x64AG.fm - Rev. G 9/04 EN 16 ©2004 Micron Technology. Inc. Table 14: I DD Specifications and Conditions – 512MB DDR SDRAM components only Notes: 1–5, 8, 10, 12, 48; notes appear on pages 19–22; 0°C ≤ TA ≤ +70°C; VDD = VDDQ = +2.5V ±0.2V MAX PARAMETER/CONDITION SYM -335 -262 -26A/ -265 UNITS NOTES OPERATING CURRENT: One device bank; Active-Precharge; tRC = tRC (MIN); tCK = tCK (MIN); DQ, DM, and DQS inputs changing once per clock cycle; Address and control inputs changing once every two clock cycles IDD0 1,040 1,040 920 mA 20, 42 OPERATING CURRENT: One device bank; Active-Read-Pre-charge; Burst = 4; tRC = tRC (MIN); tCK = tCK (MIN); IOUT = 0mA; Address and control inputs changing once per clock cycle IDD1 1,280 1,280 1,160 mA 20, 42 PRECHARGE POWER-DOWN STANDBY CURRENT: All device banks idle; Power-down mode; tCK = tCK (MIN); CKE = LOW IDD2P 40 40 40 mA 21, 28, IDLE STANDBY CURRENT: CS# = HIGH; All device banks idle; tCK = tCK (MIN); CKE = HIGH; Address and other control inputs changing once per clock cycle. VIN = VREF for DQ, DQS, and DM IDD2F 360 360 320 mA 45 ACTIVE POWER-DOWN STANDBY CURRENT: One device bank active; Power-down mode; tCK = tCK (MIN); CKE = LOW IDD3P 280 280 240 mA 21, 28, ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One device bank; Active-Precharge; tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle IDD3N 400 400 360 mA 41 OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); IOUT = 0mA IDD4R 1,320 1,320 1,160 mA 20, 42 OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle IDD4W 1,400 1,240 1,080 mA 20 AUTO REFRESH CURRENT tREFC = tRFC (MIN) IDD5 2,320 2,320 2,240 mA 20, 44 tREFC = 7.8125µs IDD5A 80 80 80 mA 24, 44 SELF REFRESH CURRENT: CKE ≤ 0.2V IDD6 40 40 40 mA 9 OPERATING CURRENT: Four device bank interleaving READs (BL = 4) with auto precharge, tRC = minimum tRC allowed; tCK = tCK (MIN); Address and control inputs change only during Active, READ, or WRITE commands IDD7 3,240 3,200 2,800 mA 20, 43 Table 15: Capacitance Note: 11; notes appear on pages 19–22 PARAMETER SYMBOL MIN MAX UNITS Input/Output Capacitance: DQ, DQS CIO 4.0 5.0 pF Input Capacitance: Command and Address, S#, CKE CI11 6 . 0 2 4 . 0 p F Input Capacitance: CK0, CK0# (Standard PCB) CI21 0 . 0 1 2 . 0 p F Input Capacitance: CK1, CK1#; CK2, CK2# (Standard PCB) CI3 9.0 12.0 pF

128MB, 256MB, 512MB (x64, SR) 184-PIN DDR SDRAM UDIMM pdf: 09005aef80867ab3, source: 09005aef80867a99 Micron Technology, Inc., reserves the right to change products or specifications without notice. DD8C16_32_64x64AG.fm - Rev. G 9/04 EN 17 ©2004 Micron Technology. Inc. Table 16: DDR SDRAM Component Electrica l Characteristics and Recommended AC Operating Conditions Notes: 1–5, 12–15, 29, 49; notes appear on pages 19–22; 0°C ≤ TA ≤ +70°C; VDD = VDDQ = +2.5V ±0.2V AC CHARACTERISTICS -335 -262 -26A/-265 UNITS NOTESPARAMETER SYM MIN MAX MIN MAX MIN MAX Clock cycle time CL = 2.5 tCK (2.5) 6 12 7.5 13 7.5 13 ns 40, 46 CL = 2 tCK (2) 7.5 12 7.5/10 13 7.5/10 13 ns 40, 46 DQ and DM input hold time relative to DQS tDH 0.45 0.5 0.5 ns 23, 27 DQ and DM input setup time relative to DQS tDS 0.45 0.5 0.5 ns 23, 27 DQ and DM input pulse width (for each input) tDIPW 1.75 1.75 1.75 ns 27 DQS input high pulse width tDQSH 0.35 0.35 0.35 tCK DQS input low pulse width tDQSL 0.35 0.35 0.35 tCK DQS-DQ skew, DQS to last DQ valid, per group, per access tDQSQ 0.45 0.5 0.5 ns 22, 23 Write command to first DQS latching transition DQS falling edge to CK rising - setup time tDSS 0.2 0.2 0.2 tCK DQS falling edge from CK rising - hold time tDSH 0.2 0.2 0.2 tCK Half clock period tHP tCH, tCL tCH, tCL tCH, tCL ns 30 Data-outhigh-impedancewindowfromCK/ CK# tHZ +0.70 +0.75 +0.75 ns 16, 37 Data-outlow-impedancewindowfromCK/CK# tLZ -0.70 -0.75 -0.75 ns 16, 37 Address and control input hold time (fast slew rate) tIHF 0.75 0.90 0.90 ns 12 Address and control input setup time (fast slew rate) tISF 0.75 0.90 0.90 ns 12 Address and control input hold time (slow slew rate) tIHS 0.80 1 1 ns 12 Address and control input setup time (slow slew rate) tISS 0.80 1 1 ns 12 Address and Control input pulse width (for each input) tIPW 2.2 2.2 2.2 ns LOAD MODE REGISTER command cycle time tMRD 12 15 15 ns DQ-DQS hold, DQS to first DQ to go non- valid, per access tQH tHP - tQHS tHP - tQHS tHP - tQHS ns 22, 23 Data hold skew factor tQHS 0.55 0.75 0.75 ns ACTIVE to PRECHARGE command tRAS 42 70,000 40 120,000 40 120,000 ns 31, 49 ACTIVE to READ with auto precharge command tRAP 15 15 20 ns ACTIVEto ACTIVE/AUTO REFRESH command period tRC 60 60 65 ns AUTO REFRESH command period tRFC 72 75 75 ns 44 ACTIVE to READ or WRITE delay tRCD 15 15 20 ns PRECHARGE command period tRP 15 15 20 ns

128MB, 256MB, 512MB (x64, SR) 184-PIN DDR SDRAM UDIMM pdf: 09005aef80867ab3, source: 09005aef80867a99 Micron Technology, Inc., reserves the right to change products or specifications without notice. DD8C16_32_64x64AG.fm - Rev. G 9/04 EN 18 ©2004 Micron Technology. Inc. ACTIVE bank a to ACTIVE bank b command tRRD 12 15 15 ns DQS write preamble tWPRE 0.25 0.25 0.25 tCK DQS write preamble setup time tWPRES 0 0 0 ns 18, 19 Write recovery time tWR 15 15 15 ns Internal WRITE to READ command delay tWTR 1 1 1 tCK Data valid output window na tQH -tDQSQ tQH - tDQSQ tQH - tDQSQ ns 22 REFRESH to REFRESH command interval 128MB tREFC 140.6 140.6 140.6 µs 21 256MB, 512MB 70.3 70.3 70.3 µs 21 Average periodic refresh interval 128MB tREFI 15.6 15.6 15.6 µs 21 256MB, 512MB 7.8 7.8 7.8 µs 21 Terminating voltage delay to VDD tVTD 0 0 0 ns Exit SELF REFRESH to non-READ command tXSNR 75 75 75 ns Exit SELF REFRESH to READ command tXSRD 200 200 200 tCK Table 16: DDR SDRAM Component Electrica l Characteristics and Recommended AC Operating Conditions (Continued) Notes: 1–5, 12–15, 29, 49; notes appear on pages 19–22; 0°C ≤ TA ≤ +70°C; VDD = VDDQ = +2.5V ±0.2V AC CHARACTERISTICS -335 -262 -26A/-265 UNITS NOTESPARAMETER SYM MIN MAX MIN MAX MIN MAX

128MB, 256MB, 512MB (x64, SR) 184-PIN DDR SDRAM UDIMM pdf: 09005aef80867ab3, source: 09005aef80867a99 Micron Technology, Inc., reserves the right to change products or specifications without notice. DD8C16_32_64x64AG.fm - Rev. G 9/04 EN 19 ©2004 Micron Technology. Inc. Notes 1. All voltages referenced to V SS. 2. T ests for AC timing, Idd, and electrical AC and DC characteristics may be conducted at nominal ref- erence/supply voltage levels, but the related spec- ifications and device operation are guaranteed for the full voltage range specified. 3. Outputs measured with equivalent load: 4. AC timing and I DD tests may use a V IL-to-VIH s w i n g o f u p t o 1 . 5 V i n t h e t e s t e n v i r o n m e n t , b u t input timing is still referenced to V REF (or to the crossing point for CK/CK#), and parameter speci- fications are guaranteed for the specified AC input levels under normal use conditions. The mini- mum slew rate for the input signals used to test the device is 1V/ns in the range between V IL(AC) and VIH(AC). 5. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e., the receiver will effectively switch as a result of the signal crossing the AC input level, and will remain in that state as long as the signal does not ring back above [below] the DC input LOW [HIGH] level). 6. V REF is expected to equal VddQ/2 of the transmit- ting device and to track variations in the DC level of the same. Peak-to-peak noise (non-common mode) on V REF may not exceed ±2 percent of the DC value. From V DDQ/2, VREF is allowed ±25mV for DC error and an additional ±25mV for AC noise, measured at the nearest V REF bypass capac- itor. 7. V TT is not applied directly to the device. V TT is a system supply for signal termination resistors, is expected to be set equal to V REF, and must track variations in the DC level of VREF. 8. I DD is dependent on output loading and cycle rates. Specified values are obtained with mini- mum cycle time at CL = 2 for -26A and CL = 2.5 for -335 and -265 with the outputs open. 9. Enables on-chip refresh and address counters. 10. I DD specifications are tested after the device is properly initialized, and is averaged at the defined cycle rate. 11. This parameter is sampled. V DD = +2.5V ±0.2V, VDDQ = +2.5V ±0.2V, VREF = Vss, f = 100 MHz, T A = 25°C, VOUT(DC) = V DDQ/2, VOUT (peak to peak) = 0.2V . DM input is grouped with I/O pins, reflecting the fact that they are matched in loading. 12. For slew rates < 1 V/ns and ≥ 0.5 Vns. If slew rate is less than 0.5 V/ns, timing must be derated: tIS has an additional 50ps per each 100 mV/ns reduction in slew rate from 500 mV/ns, while tIH is unaf- fected. If slew rate exceeds 4.5V/ns, functionality is uncertain. 13. The CK/CK# input reference level (for timing ref- erenced to CK/CK#) is the point at which CK and CK# cross; the input reference level for signals other than CK/CK# is V REF. 14. Inputs are not recognized as valid until V REF stabi- lizes. Exception: during the period before Vref sta- bilizes, CKE ≤ 0.3 x V DDQ is recognized as LOW. 15. The output timing reference level, as measured at the timing reference point indicated in Note 3, is V TT. 16. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referenced to a specific voltage level, but specify when the device output is no longer driving (HZ) or begins driving (LZ). 17. The intent of the Don’t Care state after completion of the postamble is the DQS-driven signal should either be high, lo w , or high-Z and that any signal transition within the input switching region must follow valid input requirements. That is, if DQS transitions high (above V IHDC (MIN) then it must not transition low (below V IHDC) prior to tDQSH (MIN). 18. This is not a device limit. The device will operate with a negative value, but system performance could be degraded due to bus turnaround. 1 9 . I t i s r e c o m m e n d e d t h a t D Q S b e v a l i d ( H I G H o r LOW) on or before the WRITE command. The case shown (DQS going from High-Z to logic LOW) applies when no WRITEs were previously in progress on the bus. If a previous WRITE was in progress, DQS could be HIGH during this time, depending on tDQSS. 20. MIN ( tRC or tRFC) for I DD measurements is the smallest multiple of tCK that meets the minimum absolute value for the respective parameter. tRAS (MAX) for IDD measurements is the largest multi- ple of tCK that meets the maximum absolute value for tRAS. 21. The refresh period 64ms. This equates to an aver- age refresh rate of 15.625µs (128MB), or 7.8125µs (256MB, 512MB). However, an AUTO REFRESH command must be asserted at least once every 140.6µs (128MB) or 70.3µs (256MB, 512MB); burst Output (VOUT) Reference Point 50Ω VTT 30pF

128MB, 256MB, 512MB (x64, SR) 184-PIN DDR SDRAM UDIMM pdf: 09005aef80867ab3, source: 09005aef80867a99 Micron Technology, Inc., reserves the right to change products or specifications without notice. DD8C16_32_64x64AG.fm - Rev. G 9/04 EN 20 ©2004 Micron Technology. Inc. refreshing or posting by the DRAM controller greater than eight refresh cycles is not allowed. 22. The valid data window is derived by achieving other specifications: tHP (tCK/2), tDQSQ, and tQH (tQH = tHP - tQHS). The data valid window derates directly porportional with the clock duty cycle and a practical data valid window can be derived. The clock is allowed a maximum duty cycle varia- tion of 45/55, beyond which functionality is uncertain. Figure 8, Derating Data Valid Window, shows derating curves for duty cycles ranging between 50/50 and 45/55. 23. Each byte lane has a corresponding DQS. 24. This limit is actually a nominal value and does not r e s u l t i n a f a i l v a l u e . C K E i s H I G H d u r i n g REFRESH command period ( tRFC [MIN]) else CKE is LOW (i.e., during standby). 25. To maintain a valid level, the transitioning edge of the input must: a. Sustain a constant slew rate from the current AC level through to the target AC level, V IL(AC) or VIH(AC). b. Reach at least the target AC level. c. After the AC target level is reached, continue to maintain at least the target DC level, VIL(DC) or VIH(DC). 26. CK and CK# input slew rate must be ≥ 1V/ns (≤2V/ ns differentially). 27. DQ and DM input slew rates must not deviate from DQS by more than 10 percent. If the DQ/ DM/DQS slew rate is less than 0.5V/ns, timing must be derated: 50ps must be added to tDS and tDH for each 100mv/ns reduction in slew rate. If slew rate exceeds 4 V/ns, functionality is uncer- tain. 28. V DD must not vary more than 4 percent if CKE is not active while any bank is active. 2 9 . T h e c l o c k i s a l l o w e d u p t o ± 1 5 0 p s o f j i t t e r . E a c h timing parameter is allowed to vary by the same amount. 30. tHP min is the lesser of tCL minimum and tCH minimum actually applied to the device CK and CK# inputs, collectively during bank active. Figure 8: Derating Data Valid Window (tQH - tDQSQ) 3.750 3.700 3.650 3.600 3.550 3.500 3.450 3.400 3.350 3.300 3.250 2.500 2.463 2.425 2.388 2.350 2.313 2.275 2.238 2.200 2.163 2.125 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 Clock Duty Cycle ns -335 @ tCK = 6ns N/A

128MB, 256MB, 512MB (x64, SR) 184-PIN DDR SDRAM UDIMM pdf: 09005aef80867ab3, source: 09005aef80867a99 Micron Technology, Inc., reserves the right to change products or specifications without notice. DD8C16_32_64x64AG.fm - Rev. G 9/04 EN 21 ©2004 Micron Technology. Inc. 31. READs and WRITEs with auto precharge are not allowed to be issued until tRAS(min) can be satis- fied prior to the internal precharge command being issued. 32. Any positive glitch in the nominal voltage must be less than 1/3 of the clock and not more than +400mV or 2.9V , whichever is less. Any negative glitch must be less than 1/3 of the clock cycle and not exceed either -300mV or 2.2V , whichever is more positive. 33. Normal Output Drive Curves: a. The full variation in driver pull-down current from minimum to maximum process, temper- ature and voltage will lie within the outer bounding lines of the V-I curve of Figure 9, Pull-Down Characteristics. b. The variation in driver pull-down current within nominal limits of voltage and tempera- ture is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve of Figure 9, Pull-Down Characteristics. c. The full variation in driver pull-up current from minimum to maximum process, temper- ature and voltage will lie within the outer bounding lines of the V-I curve of Figure 10, Pull-Up Characteristics. d. The variation in driver pull-up current within nominal limits of voltage and temperature is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve of Figure 10, Pull-Up Characteristics. e. The full variation in the ratio of the maximum to minimum pull-up and pull-down current should be between 0.71 and 1.4, for device drain-to-source voltages from 0.1V to 1.0V , and at the same voltage and temperature. f. The full variation in the ratio of the nominal pull-up to pull-down current should be unity ±10 percent, for device drain-to-source volt- ages from 0.1V to 1.0V . 34. The voltage levels used are derived from a mini- mum V DD level and the referenced test load. In practice, the voltage levels obtained from a prop- erly terminated bus will provide significantly dif- ferent voltage values. 35. V IH overshoot: VIH(MAX) = VDDQ + 1.5V for a pulse width ≤ 3ns and the pulse width cannot be greater than 1/3 of the cycle rate. V IL undershoot: V IL (MIN) = -1.5V for a pulse width ≤ 3ns and the pulse width cannot be greater than 1/3 of the cycle rate. 36. V DD and VDDQ must track each other. 37. tHZ (MAX) will prevail over tDQSCK (MAX) + tRPST (MAX) condition. tLZ (MIN) will prevail over tDQSCK (MIN) + tRPRE (MAX) condition. 38. tRPST end point and tRPRE begin point are not referenced to a specific voltage level but specify when the device output is no longer driving tRPST), or begins driving (tRPRE). 39. During initialization, V DDQ, V TT, and V REF must be equal to or less than V DD + 0.3V . Alternatively, VTT may be 1.35V maximum during power up, even if VDD/VDDQ are 0V , provided a minimum of 42Ω of series resistance is used between the V TT supply and the input pin. 40. The current Micron part operates below the slow- est JEDEC operating frequency of 83 MHz. As such, future die may not reflect this option. 41. For the -335, -262, -26A and -265 modules, I DD3N is specified to be 35mA per DDR SDRAM device at 100 MHz. 42. Random addressing changing and 50 percent of data changing at every transfer. Figure 9: Pull-Down Characteristics Figure 10: Pull-Up Characteristics 160 140IOUT (mA) VOUT (V) Nominal low Minimum Nominal high Maximum 120 100 VOUT (V) -20 IOUT (mA) Nominal low Minimum Nominal high Maximum -40 -60 -80 -100 -120 -140 -160 -180 -200 VDDQ - VOUT (V)

128MB, 256MB, 512MB (x64, SR) 184-PIN DDR SDRAM UDIMM pdf: 09005aef80867ab3, source: 09005aef80867a99 Micron Technology, Inc., reserves the right to change products or specifications without notice. DD8C16_32_64x64AG.fm - Rev. G 9/04 EN 22 ©2004 Micron Technology. Inc. 43. Random addressing changing and 100 percent of data changing at every transfer. 44. CKE must be active (high) during the entire time a refresh command is executed. That is, from the time the AUTO REFRESH command is registered, CKE must be active at each rising clock edge, until tRFC has been satisfied. 45. I DD2N specifies the DQ, DQS, and DM to be driven to a valid high or low logic level. I DD2Q is similar to I DD2F except I DD2Q specifies the address and control inputs to remain stable. Although I DD2F , IDD2N, and I DD2Q are similar, IDD2F is “worst case.” 46. Whenever the operating frequency is altered, not including jitter, the DLL is required to be reset, fol- lowed by 200 clock cycles before any READ com- mand. 47. Leakage number reflects the worst case leakage possible through the module pin, not what each memory device contributes. 4 8 . W h e n a n i n p u t s i g n a l i s H I G H o r L O W , i t i s defined as a steady state logic HIGH or LOW . 49. The -335 speed grade will operate with tRAS (MIN) = 40ns and tRAS (MAX) = 120,000ns at any slower frequency.

128MB, 256MB, 512MB (x64, SR) 184-PIN DDR SDRAM UDIMM pdf: 09005aef80867ab3, source: 09005aef80867a99 Micron Technology, Inc., reserves the right to change products or specifications without notice. DD8C16_32_64x64AG.fm - Rev. G 9/04 EN 23 ©2004 Micron Technology. Inc. Initialization T o ensure device operation the DRAM must be ini- tialized as described below: 1. Simultaneously apply power to V DD and VDDQ. 2. Apply V REF and then VTT power. 3. Assert and hold CKE at a LVCMOS logic low. 4. Provide stable CLOCK signals. 5. Wait at least 200µs. 6. Bring CKE high and provide at least one NOP or DESELECT command. At this point the CKE input changes from a LVCMOS input to a SSTL2 input only and will remain a SSTL_2 input unless a power cycle occurs. 7. Perform a PRECHARGE ALL command. 8. Wait at least tRP time, during this time NOPs or DESELECT commands must be given. 9. Using the LMR command program the Extended Mode Register (E0 = 0 to enable the DLL and E1 = 0 for normal drive or E1 = 1 for reduced drive, E2 through En must be set to 0; where n = most sig- nificant bit). 10. Wait at least tMRD time, only NOPs or DESELECT commands are allowed. 11. Using the LMR command program the Mode Reg- ister to set operating parameters and to reset the DLL. Note at least 200 clock cycles are required between a DLL reset and any READ command. 12. Wait at least tMRD time, only NOPs or DESELECT commands are allowed. 13. Issue a PRECHARGE ALL command. 14. Wait at least tR P t i m e , o n l y N O P s o r D E S E L E C T commands are allowed. 15. Issue an AUTO REFRESH command (Note this may be moved prior to step 13). 16. Wait at least tRFC time, only NOPs or DESELECT commands are allowed. 17. Issue an AUTO REFRESH command (Note this may be moved prior to step 13). 18. Wait at least tRFC time, only NOPs or DESELECT commands are allowed. 19. Although not required by the Micron device, JEDEC requires a LMR command to clear the DLL bit (set M8 = 0). If a LMR command is issued the same operating parameters should be utilized as in step 11. 20. Wait at least tMRD time, only NOPs or DESELECT commands are allowed. 21. At this point the DRAM is ready for any valid com- mand. Note 200 clock cycles are required between step 11 (DLL Reset) and any READ command. Figure 11: Initialization Flow Diagram VDD and VDDQ Ramp Apply VREF and VTT CKE must be LVCMOS Low Apply stable CLOCKs Bring CKE High with a NOP command Wait at least 200us PRECHARGE ALL Assert NOP or DESELECT for tRP time Configure Extended Mode Register Configure Load Mode Register and reset DLL Assert NOP or DESELECT for tMRD time Assert NOP or DESELECT for tMRD time PRECHARGE ALL Issue AUTO REFRESH command Assert NOP or DESELECT for tRFC time Optional LMR command to clear DLL bit Assert NOP or DESELECT for tMRD time DRAM is ready for any valid command Step Assert NOP or DESELECT commands for tRFC Issue AUTO REFRESH command Assert NOP or DESELECT for tRP time

128MB, 256MB, 512MB (x64, SR) 184-PIN DDR SDRAM UDIMM pdf: 09005aef80867ab3, source: 09005aef80867a99 Micron Technology, Inc., reserves the right to change products or specifications without notice. DD8C16_32_64x64AG.fm - Rev. G 9/04 EN 25 ©2004 Micron Technology. Inc. Figure 15: SPD EEPROM Timing Diagram Table 17: EEPROM Device Select Code Most significant bit (b7) is sent first SELECT CODE DEVICE TYPE IDENTIFIER CHIP ENABLE RW b7 b6 b5 b4 b3 b2 b1 b0 Memory Area Select Code (two arrays) 1010 S A 2 S A 1 S A 0 R W Protection Register Select Code 0110 S A 2 S A 1 S A 0 R W Table 18: EEPROM Operating Modes MODE RW BIT WC BYTES INITIAL SEQUENCE Current Address Read 1V IH or VIL 1 START, Device Select, RW = “1” Random Address Read 0V IH or VIL 1 START, Device Select, RW = “0”, Address 1V IH or VIL 1 reSTART, Device Select, RW = “1” Sequential Read 1V IH or VIL ≥ 1 Similar to Current or Random Address Read Byte Write 0V IL 1 START, Device Select, RW = “0” Page Write 0V IL ≤ 16 START, Device Select, RW = “0” SCL SDA IN SDA OUT tLOW tSU:STA tHD:STA tF tHIGH tR tBUFtDHtAA tSU:STOtSU:DATtHD:DAT UNDEFINED

128MB, 256MB, 512MB (x64, SR) 184-PIN DDR SDRAM UDIMM pdf: 09005aef80867ab3, source: 09005aef80867a99 Micron Technology, Inc., reserves the right to change products or specifications without notice. DD8C16_32_64x64AG.fm - Rev. G 9/04 EN 26 ©2004 Micron Technology. Inc. NOTE: 1. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL = 1 and the falling or rising edge of SDA. 2. This parameter is sampled. 3. For a reSTART condition, or following a WRITE cycle. 4. The SPD EEPROM WRITE cycle time ( tWRC) is the time from a valid stop condition of a write sequence to the end of the EEPROM internal erase/program cycle. During the WRITE cycle, the EEPROM bus interface circuit is disabled, SDA remains HIGH due to pull-up resistor, and the EEPROM does not respond to its slave address. Table 19: Serial Presence-Detect EEPROM DC Operating Conditions All voltages referenced to VSS; VDDSPD = +2.3V to +3.6V PARAMETER/CONDITION SYMBOL MIN MAX UNITS SUPPLY VOLTAGE VDDSPD 2.3 3.6 V INPUT HIGH VOLTAGE: Logic 1; All inputs Vih V DDSPD × 0.7 V DDSPD + 0.5 V INPUT LOW VOLTAGE: Logic 0; All inputs VIL -1 V DDSPD × 0.3 V OUTPUT LOW VOLTAGE: IOUT = 3mA VOL –0 . 4 V INPUT LEAKAGE CURRENT: VIN = GND to VDD ILI –1 0 µ A OUTPUT LEAKAGE CURRENT: VOUT = GND to VDD ILO –1 0 µ A STANDBY CURRENT: SCL = SDA = VDD - 0.3V; All other inputs = VDD or VSS ISB –3 0 µ A POWER SUPPLY CURRENT: SCL clock frequency = 100 KHz ICC –2 m A Table 20: Serial Presence-Detect EEPROM AC Operating Conditions All voltages referenced to VSS; VDDSPD = +2.3V to +3.6V PARAMETER/CONDITION SYMBOL MIN MAX UNITS NOTES SCL LOW to SDA data-out valid tAA 0.2 0.9 µs 1 Time the bus must be free before a new transition can start tBUF 1.3 µs Data-out hold time tDH 200 ns SDA and SCL fall time tF 300 ns 2 Data-in hold time tHD:DAT 0 µs Start condition hold time tHD:STA 0.6 µs Clock HIGH period tHIGH 0.6 µs Noise suppression time constant at SCL, SDA inputs tI5 0 n s Clock LOW period tLOW 1.3 µs SDA and SCL rise time tR0 . 3 µ s 2 SCL clock frequency fSCL 400 KHz Data-in setup time tSU:DAT 100 ns Start condition setup time tSU:STA 0.6 µs 3 Stop condition setup time tSU:STO 0.6 µs WRITE cycle time tWRC 10 ms 4

128MB, 256MB, 512MB (x64, SR) 184-PIN DDR SDRAM UDIMM pdf: 09005aef80867ab3, source: 09005aef80867a99 Micron Technology, Inc., reserves the right to change products or specifications without notice. DD8C16_32_64x64AG.fm - Rev. G 9/04 EN 27 ©2004 Micron Technology. Inc. Table 21: Serial Presence-Detect Matrix “1”/”0”: Serial Data, “driven to HIGH”/”driven to LOW”;notes appear on page 28 BYTE DESCRIPTION ENTRY(VERSION) MT8VDDT1664A MT8VDDT3264A MT8VDDT6464A

0 Number of SPD Bytes Used by Micron 1 2 8 8 08 08 0

1 Total Number of Bytes in SPD Device 2 5 6 0 80 80 8

2 Fundamental Memory Type SDRAM DDR 07 07 07

3 Number of Row Addresses on Assembly 12 or 13 0C 0D 0D

4 Number of Column Addresses on

5 Number of Physical Ranks on DIMM 1 0 10 10 1

6 Module Data Width 64 40 40 40

7 Module Data Width (Continued) 0 0 00 00 0

8 Module Voltage Interface Levels SSTL 2.5V 04 04 04

9 SDRAM Cycle Time, tCK, (CAS Latency =

2.5) (See note 1) 6ns (-335) 7ns (-262/-26A) 7.5ns (-265)

10 SDRAM Access From Clock,

tAC, (CAS Latency = 2.5) (See note 1) 0.70ns (-335)

11 Module Configuration Type Unbuffered 00 00 00

12 Refrsh Rate/Type 15.6 or 7.81µs/SELF 80 82 82

13 SDRAM Device Width (Primary SDRAM) 8 0 80 80 8

14 Error-checking SDRAM Data Width None 00 00 00

15 Minimum Clock Delay, Back-to-Back

16 Burst Lengths Supported 2, 4, 8 0E 0E 0E

17 Number of Banks on SDRAM Device 4 0 40 40 4

18 CAS Latencies Supported 2, 2.5 0C 0C 0C

19 CS Latency 0 0 10 10 1

20 WE Latency 1 0 20 20 2

21 SDRAM Module Attributes 20 20 20

22 SDRAM Device Attributes: General Fast / Concurrent

23 SDRAM Cycle Time, tCK (CAS Latency =

2) (See note 1) 10ns (-265)

24 SDRAM Access From CK, tAC (CAS

Latency = 2) (See note 1) 7ns (-335)

25 SDRAM Cycle Time, tCK, (CAS Latency =

1.5) – 0 00 00 0

26 SDRAM Access From CK, tAC, (CAS

Latency = 1.5) – 0 00 00 0

27 Minimum Row Precharge Time, tRP (see

note 4) 18ns (-335) 15ns (-262) 20ns (-26A/-265)

28 MInimum Row Active To Row Active,

12ns (-335)

29 Minimum RAS# to CAS# Delay, tRCD

(see note 4) 18ns (-335) 20ns (-26A/-265)

30 Minimum RAS# Pulse Width, tRAS

(See note 2) 42ns (-335)

128MB, 256MB, 512MB (x64, SR) 184-PIN DDR SDRAM UDIMM pdf: 09005aef80867ab3, source: 09005aef80867a99 Micron Technology, Inc., reserves the right to change products or specifications without notice. DD8C16_32_64x64AG.fm - Rev. G 9/04 EN 28 ©2004 Micron Technology. Inc. NOTE: 2. The value of tRAS for -26A and -265 modules is calculated from tRC - tRP. Actual device spec. value is 40ns. 3. The JEDEC SPD specification allows fast or slow slew rate values for these bytes. The worst-case (slow slew rate) value is represented here. Systems requiring the fast slew rate setup and hold values are supported, provided the faster minimum slew rate is met. 4. The value of tRP, tRCD and tRAP for -335 modules indicated as 18ns to align with industry specifications; actual DDR SDRAM device specification is 15ns.

31 Module Rank Density 128MB, 256MB,

32 Address And Command Setup Time, tIS

(See note 3) 0.8ns (-335)

33 Address And Command Hold Time, tIH

(See note 3) 0.8ns (-335) 34 Data/data Mask Input Setup Time, tDS 0.45ns (-335) 35 Data/Data Mask Input Hold Time, tDH 0.45ns (-335) 36-40 Reserved 00 00 00

41 Minimum Active/ Auto Refresh Time,

60ns (-335/-262) 65ns (-26A/-265)

42 Minimum Auto Refresh To Active/ Auto

Refresh Command Period, tRFC 72ns (-335)

43 Maximum Cycle Time, tCK (MAX) 12ns (-335)

44 Maximum DQS-DQ Skew Time, tDQSQ 0.45ns (-335)

45 Maximum Read Data Hold Skew Factor,

0.55ns (-335)

46 Reserved 00 00 00

47 DIMM Height Standard/Low-Profile 01/11 01/11 01/11

48–61 Reserved 00 00 00

63 Checksum For Bytes 0-62 -335

-262 -26A -265 97/A7 C4/D4 F4/04 BA/CA E7/F7 FB/0B

64 Manufacturer’s JEDEC ID Code MICRON 2C 2C 2C

65-71 Manufacturer’s JEDEC ID Code (cont’d) (continued) FF FF FF

72 Manufacturing Location 1 - 12 01 - 0C 01 - 0C 01 - 0C

73-90 Module Part Number (ASCII) Variable Data Variable Data Variable Data

91 PCB Identification Code Variable Data Variable Data Variable Data

92 Identification Code (continued) 0 0 00 00 0

93 Year of Manufacture In BCD Variable Data Variable Data Variable Data

94 Week of Manufacture In BCD Variable Data Variable Data Variable Data

95-98 Module Serial Number Variable Data Variable Data Variable Data 99-127 Manufacturer-Specific Data (RSVD) ––– Table 21: Serial Presence-Detect Matrix “1”/”0”: Serial Data, “driven to HIGH”/”driven to LOW”;notes appear on page 28 BYTE DESCRIPTION ENTRY(VERSION) MT8VDDT1664A MT8VDDT3264A MT8VDDT6464A

128MB, 256MB, 512MB (x64, SR) 184-PIN DDR SDRAM UDIMM pdf: 09005aef80867ab3, source: 09005aef80867a99 Micron Technology, Inc., reserves the right to change products or specifications without notice. DD8C16_32_64x64AG.fm - Rev. G 9/04 EN 29 ©2004 Micron Technology. Inc. Figure 16: 184-Pin DIMM Dimensions – Standard PCB NOTE: All dimensions are in inches (millimeters); or typical where noted. U1 U2 U3 U4 U6 U7 U8 U9 No Components This Side of Module U10 1.255 (31.88) 1.245 (31.62) PIN 1 0.700 (17.78) TYP. 0.098 (2.50) D (2X) 0.091 (2.30) TYP. 0.250 (6.35) TYP. 4.750 (120.65) 0.050 (1.27) TYP. 0.091 (2.30) TYP. 0.040 (1.02) TYP. 0.079 (2.00) R (4X) 0.035 (0.90) R PIN 92 FRONT VIEW BACK VIEW 0.054 (1.37) 0.046 (1.17) 5.256 (133.50) 5.244 (133.20) PIN 184 PIN 930.150 (3.80) 0.150 (3.80) TYP. 0.394 (10.00) TYP. 0.125 (3.18) MAX MAX MIN

8000 S. Federal Way, P .O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992 Micron, the M logo, and the Micron logo are trademarks and/or service marks of Micron Technology, Inc. 128MB, 256MB, 512MB (x64, SR) 184-PIN DDR SDRAM UDIMM pdf: 09005aef80867ab3, source: 09005aef80867a99 Micron Technology, Inc., reserves the right to change products or specifications without notice.. DD8C16_32_64x64AG.fm - Rev. G 9/04 EN 30 ©2004 Micron Technology, Inc Figure 17: 184-Pin DIMM Dimensions – Low-Profile PCB NOTE: All dimensions in inches (millimeters); or typical where noted. Data Sheet Designation Released: This data sheet contains minimum and maximum limits specified over the complete power supply and temperature range for production devices. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. U1 U2 U3 U4 U6 U7 U8 U9 U10 PIN 1 0.700 (17.78) TYP. 0.098 (2.50) D (2X) 0.091 (2.30) TYP. 0.250 (6.35) TYP. 0.050 (1.27) TYP. 0.091 (2.30) TYP. 0.040 (1.02) TYP. 0.079 (2.00) R (4X) 0.035 (0.90) R PIN 92 FRONT VIEW BACK VIEW 5.256 (133.50) 5.244 (133.20) 2.55 (64.77) TYP. 1.95 (49.53) TYP. PIN 184 PIN 93 0.150 (3.80) TYP. 0.394 (10.00) TYP. 1.156 (29.36) 1.144 (29.06) 0.054 (1.37) 0.046 (1.17) 0.125 (3.18) MAX No components This Side of Module MAX MIN