MT8LSDT3264AG-133

MT8LSDT3264A MICRON | Alldatasheet

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• PC100- and PC133-compliant  JEDEC-standard 168-pin, dual in-line memory module (DIMM) U n b u f f e r e d  256MB (32 Meg x 64), 512MB (64 Meg x 64)  Single +3.3V ±0.3V power supply  Fully synchronous; all signals registered on positive edge of system clock  Internal pipelined operation; column address can be changed every clock cycle  Internal SDRAM banks for hiding row access/precharge  Programmable burst length s: 1, 2, 4, 8, or full page  Auto Precharge, including Concurrent Auto Precharge, and Auto Refresh Modes  64ms, 8,192 cycle Auto Refresh cycle  Self Refresh Mode  LVTTL-compatible inputs and outputs  Serial Presence-Detect (SPD) Figure 1: 168-Pin DIMM (MO–161) OPTIONS MARKING P a c k a g e Unbuffered A 168-pin DIMM (gold) G O p e r a t i n g T e m p e r a t u r e R a n g e Commercial (0°C to +70°C) None Industrial (-40°C to +85°C)1 NOTE: 1. Consult Micron for availability; Industrial Tempera- ture Option available in -133 speed only. I  Memory Clock/CAS Latency (133 MHz)/CL = 2 -13E (133 MHz)/CL = 3 -133 (100 MHz)/CL = 2 -10E Table 1: Address Table 256MB MODULE 512MB MODULE Refresh Count 8K 8K Device Banks 4 (BA0, BA1) 4 (BA0, BA1) Device Configuration 32 Meg x 8 32 Meg x 8 Row Addressing 8K (A0–A12) 8K (A0–A12) Column Addressing 1K (A0–A9) 1K (A0–A9) Module Banks 1 (S0,S2) 2 (S0,S2; S1,S3) Table 2: Timing parameters MODULE MARKINGS PC100 CL - tRCD - tRP PC133 CL - tRCD - tRP -13E 2 - 2 - 2 2 - 2 - 2 -133 2 - 2 - 2 3 - 3 - 3 -10E 2 - 2 - 2 NA Table 3: Part Numbers PARTNUMBER1 NOTE: 1. The designators for component and PCB revision are the last two characters of each part number. Consult factory for current revision codes. Example: MT8LSDT3264AG-133B1 CONFIGURATION SYSTEM BUS SPEED MT8LSDT3264AG-13E_ 32 Meg x 64 133 MHz MT8LSDT3264AG(I)-133_ 32 Meg x 64 133 MHz MT8LSDT3264AG-10E_ 32 Meg x 64 100 MHz MT16LSDT6464AG-13E_ 64 Meg x 64 133 MHz MT16LSDT6464AG(I)-133_ 64 Meg x 64 133 MHz MT16LSDT6464AG-10E_ 64 Meg x 64 100 MHz Standard Low Profile

256MB / 512MB (x64) 168-PIN SDRAM DIMMs 32,64 Meg x 64 SDRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice. SD8_16C32_64x64AG_C.fm - Rev. C 11/02 2 ©2002, Micron Technology Inc. Figure 2: PIN Locations (168-PIN DIMM) Table 4: Pin Assignment, Standard PCB (168-Pin DIMM Front) PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL 1V SS 22 NC 43 V SS 64 V SS 2D Q 0 23 V SS 44 NC 65 DQ21 3D Q 1 24 NC 45 S2# 66 DQ22 4D Q 2 25 NC 46 DQMB2 67 DQ23 5D Q 3 26 V DD 47 DQMB3 68 V SS 6V DD 27 WE# 48 NC 69 DQ24 7D Q 4 28 DQMB0 49 V DD 70 DQ25 8D Q 5 29 DQMB1 50 NC 71 DQ26 9D Q 6 30 S0# 51 NC 72 DQ27

10 DQ7 31 NC 52 NC 73 V DD

11 DQ8 32 V SS 53 NC 74 DQ28

12 V SS 33 A0 54 V SS 75 DQ29

13 DQ9 34 A2 55 DQ16 76 DQ30

14 DQ10 35 A4 56 DQ17 77 DQ31

15 DQ11 36 A6 57 DQ18 78 V SS

16 DQ12 37 A8 58 DQ19 79 CK2

17 DQ13 38 A10 59 V DD 80 NC

18 V DD 39 BA1 60 DQ20 81 NC

19 DQ14 40 V DD 61 NC 82 SDA

20 DQ15 41 V DD 62 NC 83 SCL

21 NC 42 CK0 63 CKE1 84 V DD

Table 5: Pin Assignment, Standard PCB (168-Pin DIMM Back) PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL

85 V SS 106 NC 127 V SS 148 V SS

86 DQ32 107 V SS 128 CKE0 149 DQ53

87 DQ33 108 NC 129 S3# 150 DQ54

88 DQ34 109 NC 130 DQMB6 151 DQ55

89 DQ35 110 V DD 131 DQMB7 152 V SS

90 V DD 111 CAS# 132 NC 153 DQ56

91 DQ36 112 DQMB4 133 V DD 154 DQ57

92 DQ37 113 DQMB5 134 NC 155 DQ58

93 DQ38 114 S1# 135 NC 156 DQ59

94 DQ39 115 RAS# 136 NC 157 V DD

95 DQ40 116 V SS 137 NC 158 DQ60

96 V SS 117 A1 138 V SS 159 DQ61

97 DQ41 118 A3 139 DQ48 160 DQ62

98 DQ42 119 A5 140 DQ49 161 DQ63

99 DQ43 120 A7 141 DQ50 162 V SS

100 DQ44 121 A9 142 DQ51 163 CK3

101 DQ45 122 BA0 143 V DD 164 NC

102 V DD 123 A11 144 DQ52 165 SA0

103 DQ46 124 V DD 145 NC 166 SA1

104 DQ47 125 CK1 146 NC 167 SA2

105 NC 126 A12 147 NC 168 V DD

Back View (Populated only for 512MB module) Indicates a VDD pin Indicates a VSS pin PIN 1 PIN 41 PIN 84 PIN 85PIN125PIN 168 U1 U2 U3 U4 U6 U7 U8 U9 U10 U11 U12 U13 U14 U16 U17 U18 U19 See Figure 10, 256MB Module Dimensions, on page 23 and Figure 11, 512MB Module Dimensions, on page 24 for module dimensions.

256MB / 512MB (x64) 168-PIN SDRAM DIMMs 32,64 Meg x 64 SDRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice. SD8_16C32_64x64AG_C.fm - Rev. C 11/02 3 ©2002, Micron Technology Inc. Table 6: Pin Descriptions Pin numbers may not correlate with symbols. Refer to the Pin Assignment table for pin number and symbol information. PIN NUMBERS SYMBOL TYPE DESCRIPTION 27, 111, 115 RAS#, CAS#, WE# Input Command Inputs: RAS#, CAS#, and WE# (along with S#) define the command being entered. 42, 79, 125, 163 CK0-CK3 Input Clock: CK is driven by the system clock. All SDRAM input signals are sampled on the positive edge of CK. CK also increments the internal burst counter and controls the output registers. 63, 128 CKE0, CKE1 Input Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CK signal. Deactivating the clock provides PRECHARGE POWER-DOWN and SELF REFRESH operation (all device banks idle) or CLOCK SUSPEND OPERATION (burst access in progress). CKE is synchronous except after the device enters power- down and self refresh modes, where CKE becomes asynchronous until after exiting the same mode. The input buffers, including CK, are disabled during power-down and self refresh modes, providing low standby power. 30, 45,114, 129 S0# -S3# Input Chip Select: S# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when S# is registered HIGH. S# is considered part of the command code. 28, 29, 46, 47, 112, 113, 130, 131 DQMB0-DQMB7 Input Input/Output Mask: DQMB is an input mask signal for write accesses and an output enable signal for read accesses. Input data is masked when DQMB is sampled HIGH during a WRITE cycle. The output buffers are placed in a High-Z state (two- clock latency) when DQMB is sampled HIGH during a READ cycle. 39, 122 BA0, BA1 Input Bank Address: BA0 and BA1 define to which device bank the ACTIVE, READ, WRITE, or PRECHARGE command is being applied. 33 - 38, 117 - 121, 123, 126 A0-A12 Input Address Inputs: Provide the row address for ACTIVE commands, and the column address and auto prcharge bit (A10) for READ/WRITE commands, to select one location out of the memory arrary in the respective device bank. A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one device bank (A10 LOW, device bank selected by BA0, BA1) or all device banks (A10 HIGH). The address inputs also provide the op-code during a MODE REGISTER SET command.

83 SCL Input Serial Clock for Presence-Detect: SCL is used to synchronize

the presence-detect data transfer to and from the module. 165-167 SA0-SA2 Input Presence-Detect Address Inputs: These pins are used to configure the presence-detect device. 139-142, 144, 149-151, 153-156,158-161 DQ0-DQ63 Input/ Output Data I/O: Data bus.

82 SDA Input/

Serial Presence-Detect Data: SDA is a bidirectional pin used to transfer addresses and data into and out of the presence- detect portion of the module.

256MB / 512MB (x64) 168-PIN SDRAM DIMMs 32,64 Meg x 64 SDRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice. SD8_16C32_64x64AG_C.fm - Rev. C 11/02 4 ©2002, Micron Technology Inc. 84, 90, 102, 110, 124, 133, 143, 157, 168 VDD Supply Power Supply: +3.3V ±0.3V. 78, 85, 96, 107, 116, 127, 138, 148, 152, 162 VSS Supply Ground. 108-109, 132, 134-137, 145-147, 164 NC – Not Connected: These pins are not connected on these modules. Table 6: Pin Descriptions (Continued) Pin numbers may not correlate with symbols. Refer to the Pin Assignment table for pin number and symbol information. PIN NUMBERS SYMBOL TYPE DESCRIPTION

256MB / 512MB (x64) 168-PIN SDRAM DIMMs 32,64 Meg x 64 SDRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice. SD8_16C32_64x64AG_C.fm - Rev. C 11/02 5 ©2002, Micron Technology Inc. Figure 3: Functional Block Diagram Single Bank Modules DQM CS# SA0 SPD SDA SA1 SA2 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DQMB7 DQM CS# DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQMB6 DQM CS# DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQMB5 DQM CS# DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQMB4 DQM CS# DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQMB3 DQM CS# DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQMB2 DQM CS# DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQMB1 DQM CS# DQ DQ DQ DQ DQ DQ DQ DQ DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQMB0 S2# S0# RAS# CAS# CKE0 WE# RAS#: SDRAMs CAS#: SDRAMs CKE0: SDRAMs WE#: SDRAMs A0-A11: SDRAMs BA0: SDRAMs BA1: SDRAMs A0-A11 BA0 BA1 VDD VSS SDRAMs SDRAMs 10pF CK1, CK3 CK0 CK2 3.3pF SCL WP U10 DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ Notes: All resistor values are 10/g87/g32unless otherwise specified. Per industry standard, Micron modules use various component speed grades as referenced in the module part numbering guide at: www.micron.com/numberguide. SDRAMs = MT48LC32M8A2TG, Commercial Temperature SDRAMs = MT48LC32M8A2TG-75 IT, Industrial Temperature

256MB / 512MB (x64) 168-PIN SDRAM DIMMs 32,64 Meg x 64 SDRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice. SD8_16C32_64x64AG_C.fm - Rev. C 11/02 6 ©2002, Micron Technology Inc. Figure 4: Functional Block Diagram Dual Bank Modules DQM CS# DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DQMB7 DQM CS# DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQMB6 DQM CS# DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQMB5 DQM CS# DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQMB4 DQM CS# DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQMB3 DQM CS# DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQMB2 DQM CS# DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQMB1 DQM CS# DQ DQ DQ DQ DQ DQ DQ DQ DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQMB0 S2# S0# DQM CS# U12 DQM CS# U14 DQM CS# U16 DQM CS# U18 S1# DQM CS# U11 DQM CS# U13 DQM CS# U17 DQM CS# U19 S3# SA0 SPD SDA SA1 SA2 CKE1 CKE0 CAS# RAS# WE# CKE: SDRAMs U11-U19 CKE: SDRAMs U1-U9 CAS#: SDRAMs RAS#: SDRAMs WE#: SDRAMs A0-A11: SDRAMs BA0: SDRAMs BA1: SDRAMs A0-A11 BA0 BA1 VDD VSS SDRAMs SDRAMs VDD 10K Ω SCL WP U10 CK0 CK2 3.3pF U11 U12 U13 U14 CK3 3.3pF U15 U16 U17 U18 U19 CK1 DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ Notes: All resistor values are 10/g87/g32unless otherwise specified. Per industry standard, Micron modules use various component speed grades as referenced in the module part numbering guide at: www.micron.com/numberguide SDRAMs = MT48LC32M8A2TG, Commercial Temperature SDRAMs = MT48LC32M8A2TG-75 IT, Industrial Temperature

256MB / 512MB (x64) 168-PIN SDRAM DIMMs 32,64 Meg x 64 SDRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice. SD8_16C32_64x64AG_C.fm - Rev. C 11/02 7 ©2002, Micron Technology Inc. General Description The MT8LSDT13264A(I) and MT16LSDT6464A(I) are high-speed CMOS, dynamic random-access, 256MB and 512MB memory modules organized in x64 configurations. These modules use internally config- ured quad-bank SDRAMS with a synchronous inter- face (all signals are registered on the positive edge of the clock signals CK0-CK3). Read and write accesses to the SDRAM modules are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the regis- tration of an ACTIVE command, which is then fol- lowed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the device bank and row to be accessed (BA0, BA1 select the device bank; A0–A12 select the device row). The address bits registered coincident with the READ or WRITE command are used to select the starting column location for the burst access. The modules provide for programmable READ or WRITE burst length of 1, 2, 4, or 8 locations, or the full page, with a burst terminate option. An AUTO PRE- CHARGE function may be enabled to provide a self- timed row precharge that is initiateda the end of the burst sequence. The modules use an internal pipelined architecture to achieve high-speed operation. This architecture is compatible with the 2 n rule of prefetch architectures, but it also allows the column address to be changed on every clock cycle to achieve a high-speed, fully random access. Precharging one device bank while accessing one of the other three device banks will hide the pre- charge cycles and provide seamless, high-speed, ran- dom-access operation. The modules are designed to operate in 3.3V , low- power memory systems. An auto refresh mode is pro- vided, along with a power-saving, power-down mode. All inputs and outputs are LVTTL-compatible. SDRAM modules offer substantial advances in DRAM operating performance, including the ability to syncronously burst data at a high data rate with auto- matic column-address generation, the ability to inter- leave between intenal banks in order to hide precharge time and the capability to randomly change column addresses on each clock cycle during a burst access. For more information regarding SDRAM operation, refer to the 256Mb SDRAM component data sheet. Serial Presence-Detect Operation These modules incorporate serial presence-detect (SPD). The SPD function is implemented using a 2,048-bit EEPROM. This nonvolatile storage device contains 256 bytes. The first 128 bytes can be pro- g r a m m e d b y M i c r o n t o i d e n t i f y t h e m o d u l e t y p e a n d various SDRAM organizations and timing parameters. The remaining 128 bytes of storage are available for use by the customer. System READ/WRITE operations between the master (system logic) and the slave EEPROM device (DIMM) occur via a standard I 2C bus using the DIMM’ s SCL (clock) and SDA (data) signals, together with SA (2:0), which provide eight unique DIMM/EEPROM addresses. SDRAM Functional Description In general, the 256Mb SDRAMs are quad-bank DRAMs that operate at 3.3V and include a synchro- nous interface (all signals are registered on the positive edge of the clock signal, CLK). The four banks of the x8 configured devices used for these modules are config- ured as 8,192 bit-rows by 1,024 bit-columns, by 8 input/output bits. Read and write accesses to the SDRAM are burst ori- ented; accesses start at a selected location and con- tinue for a programmed number of locations in a programmed sequence. Accesses begin with the regis- tration of an ACTIVE command, which is then fol- lowed by a READ or WRITE command. The address bits registered coincident with the active command are used to select the device bank and row to be accessed; BA0 and BA1 select the devi ce bank, A0–A12 select the device row. The address bits A0–A9 registered coinci- d e n t w i t h t h e R E A D o r W R I T E c o m m a n d a r e u s e d t o select the starting device column location for the burst access. Prior to normal operation, the SDRAM must be ini- tialized. The following sections provide detailed infor- mation covering device initialization, register definition, command descriptions and device opera- tion. Initialization SDRAMS must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined opera- tion. Once power is applied to V DD and VDDQ (simulta- neously) and the clock is stable (stable clock is defined as a signal cycling within timing constrants specified for the clock pin), the SDRAM requires a 100µs delay prior to issuing any command other than a COM-

256MB / 512MB (x64) 168-PIN SDRAM DIMMs 32,64 Meg x 64 SDRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice. SD8_16C32_64x64AG_C.fm - Rev. C 11/02 8 ©2002, Micron Technology Inc. MAND INHIBIT or NOP . Starting at some point during this 100µs period and continuing at least through the end of this period, COMMAND INHIBIT or NOP com- mands should be applied. Once the 100µs delay has been satisfied with at least one COMMAND INHIBIT or NOP command having been applied, a PRECHARGE command should be applied. All device banks must then be precharged, thereby placing the device in the all banks idle state. Once in the idle state, two AUTO REFRESH cycles must be performed. After the AUTO REFRESH cycles are complete, the SDRAM is ready for mode register programming. Because the mode register will power u p i n a n u n k n o w n s t a t e , i t s h o u l d b e l o a d e d p r i o r t o applying any operational command. Mode Register Definition The mode register is used to define the specific mode of operation of the SDRAM. This definition includes the selection of a burst length, a burst type, a CAS latency, an operating mode and a write burst mode, as shown in Figure 5, Mode Register Definition Diagram, on page 8. The mode register is programmed via the LOAD MODE REGISTER command and will retain the stored information until it is programmed again or the device loses power. Mode register bits M0–M2 specify the burst length, M3 specifies the type of burst (sequential or inter- leaved), M4–M6 specify the CAS latency, M7 and M8 specify the operating mode, M9 specifies the write burst mode, and M10 and M11 are reserved for future use. The mode register must be loaded when all device banks are idle, and the controller must wait the speci- fied time before initiating the subsequent operation. Violating either of these requirements will result in unspecified operation. Burst Length Read and write accesses to the SDRAM are burst ori- ented, with the burst length being programmable, as shown in Figure 5, Mode Register Definition Diagram, on page 8. The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE command. Burst lengths of 1, 2, 4, or 8 locations are available for both the sequential and the interleaved burst types, and a full-page burst is available for the sequential type. The full-page burst is used in conjunction with the BURST TERMINATE command to generate arbitrary burst lengths. Reserved states should not be used, as unknown operation or incompatibility with future versions may result. When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached, as shown in the Burst Definition T able. The block is uniquely selected by A1– A9 when the burst length is set to two; A2–A9 when the burst length is set to four; and by A3–A9 when the burst length is set to eight. The remaining (least significant) address bit(s) is (are) used to select the starting loca- tion within the block. Full-page bursts wrap within the p ag e i f t h e b o u nd a ry is r e ac he d , a s sh o w n in T a b l e 7 , Burst Definitions, on page 9. Burst Type Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit M3. The ordering of the accesses within a burst is deter- mined by the burst length, the burst type, and the starting column adress, as shown in Table 7, Burst Def- initions, on page 9.Figure 5: Mode Register Definition

256MB / 512MB (x64) 168-PIN SDRAM DIMMs 32,64 Meg x 64 SDRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice. SD8_16C32_64x64AG_C.fm - Rev. C 11/02 9 ©2002, Micron Technology Inc. Diagram NOTE: 1. For full-page accesses: y = 1,024 2. For a burst length of two, A1–A9 select the block of two burst; A0 selects the starting column within the block. 3. For a burst length of four, A2–A9 select the block of four burst; A0–A1 select the starting column within the block. 4. For a burst length of eight, A3–A9 select the block of eight burst; A0–A2 select the starting column within the block. 5. For a full-page burst, the full row is selected and A0–A9 select the starting column. 6. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. 7. For a burst length of one, A0–A9 select the unique column to be accessed, and Mode Register bit M3 is ignored. For a full-page burst, the full row is selected and A0–A8 select the starting column. Table 7: Burst Definitions BURST LENGTH STARTING COLUMN ADDRESS ORDER OF ACCESSES WITHIN A BURST TYPE = SEQUENTIAL TYPE = INTERLEAVED 00 - 1 0 - 1 11 - 0 1 - 0 A1 A0 A2 A1 A0 Full Page (y) n= A0-A11/9/8 (location 0 - y) Cn, Cn+1, Cn+2 Cn+3, Cn+4... Not Supported

256MB / 512MB (x64) 168-PIN SDRAM DIMMs 32,64 Meg x 64 SDRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice. SD8_16C32_64x64AG_C.fm - Rev. C 11/02 10 ©2002, Micron Technology Inc. CAS Latency The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first piece of output data. The latency can be set to two or three clocks. I f a R E A D c o m m a n d i s r e g i s t e r e d a t c l o c k e d g e n, and the latency is m clocks, the data will be available by clock edge n + m. The DQs will start driving as a result of the clock edge one cycle earlier ( n + m - 1), and provided that the relevant access times are met, the data will be valid by clock edge n + m. For example, assuming that the clock cycle time is such that all rele- vant access times are met, if a READ command is regis- tered at T0 and the latency is programmed to two clocks, the DQs will start driving after T1 and the data will be valid by T2, as shown in Figure 6, CAS Latency Diagram. Table 8, CAS Latency Table, indicates the operating frequencies at which each CAS latency set- ting can be used. Reserved states should not be used as unknown operation or incompatibility with future versions may result. Figure 6: CAS Latency Diagram Operating Mode T h e n o r m a l o p e r a t i n g m o d e i s s e l e c t e d b y s e t t i n g M7 and M8 to zero; the other combinations of values for M7 and M8 are reserved for future use and/or test modes. The programmed burst length applies to both READ and WRITE bursts. Test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result. Write Burst Mode When M9 = 0, the burst length programmed via M0– M2 applies to both READ and WRITE bursts; when M9 = 1, the programmed burst length applies to READ bursts, but write accesses are single-location (non- burst) accesses. CLK DQ T2T1 T3T0 CAS Latency = 3 LZ DOUT tOHt COMMAND NOPREAD tAC NOP NOP DON’T CARE UNDEFINED CLK DQ T2T1 T3T0 CAS Latency = 2 LZ DOUT tOHt COMMAND NOPREAD tAC NOP Table 8: CAS Latency Table ALLOWABLE OPERATING CLOCK FREQUENCY (MHZ) SPEED CAS LATENCY = 2 CAS LATENCY = 3 -13E /g163 133 /g163 143 -133 /g163 100 /g163 133 -10E /g163 100 NA

256MB / 512MB (x64) 168-PIN SDRAM DIMMs 32,64 Meg x 64 SDRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice. SD8_16C32_64x64AG_C.fm - Rev. C 11/02 11 ©2002, Micron Technology Inc. Commands The Truth Table provides a quick reference of avail- able commands. This is followed by written descrip- t io n o f e ac h c o m m a nd . F o r a m o r e d e t ai l e d d e s c rip - tion of commands and operations, refer to the 256Mb SDRAM component data sheet. NOTE: 1. A0–A12 provide row address; BA0–BA1 determine which device bank is made active. 2. A0–A9 provide column address; A10 HIGH enables the auto-precharge feature (nonpersistent), while A10 LOW dis- ables the auto-precharge feature; BA0-BA1 determine which device bank is being read from or written to. 3. A10 LOW: BA0–BA1 determine which device bank is being precharged. A10 HIGH: all device banks are precharged and BA0, BA1 are “Don’t Care.” 4. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW. 5. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE. 6. A0–A11 define the op-code written to the mode register and A12 should be driven LOW. 7. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock delay). Table 9: Truth Table – SDRAM Commands and DQMB Operation CKE is HIGH for all commands shown except SELF REFRESH; notes appear following the Truth Table NAME (FUNCTION) CS# RAS# CAS# WE# DQMB ADDR DQ NOTES COMMAND INHIBIT (NOP) HXXX X X X NO OPERATION (NOP) LHHH X X X ACTIVE (Select bank and activate row) L L H H X Bank/Row X 1 READ (Select bank and column, and start READ burst) L H L H L/H Bank/Col X 2 WRITE (Select bank and column, and start WRITE burst) L H L L L/H Bank/Col Valid 2 BURST TERMINATE LHHL X X A c t i v e PRECHARGE (Deactivate row in bank or banks) L L H L X Code X 3 AUTO REFRESH or SELF REFRESH (Enter self refresh mode) LLLHX X X 4 , 5 LOAD MODE REGISTER L L L L X Op-code X 6 Write Enable/Output Enable –––– L – A c t i v e7 Write Inhibit/Output High-Z –––– H –H i g h - Z 7

256MB / 512MB (x64) 168-PIN SDRAM DIMMs 32,64 Meg x 64 SDRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice. SD8_16C32_64x64AG_C.fm - Rev. C 11/02 12 ©2002, Micron Technology Inc. Absolute Maximum Ratings Stresses greater than those listed may cause perma- nent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the opera- tional sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Voltage on V DD, VDDQ Supply Voltage on Inputs NC or I/O Pins Operating Temperature Table 10: DC Electrical Characteristics and Operating Conditions – 256MB Module Notes: 1, 5, 6; notes appear on page 17; VDD, VDDQ = +3.3V ±0.3V PARAMETER/CONDITION SYMBOL MIN MAX UNITS NOTES SUPPLY VOLTAGE VDD, VDDQ 33 . 6V INPUT HIGH VOLTAGE: Logic 1; All inputs VIH 2V DD + 0.3 V 22 INPUT LOW VOLTAGE: Logic 0; All inputs VIL -0.3 0.8 V 22 INPUT LEAKAGE CURRENT: Any input 0V /g163 VIN /g163 VDD (All other pins not under test = 0V) Command and Address Inputs, CKE II -40 40 µA 33 CK, S# -20 20 µA DQ, DQMB -5 5 µA OUTPUT LEAKAGE CURRENT: DQ pins are disabled; 0V /g163 VOUT /g163 VDDQ IOZ -5 5 µA 33 OUTPUT LEVELS: Output High Voltage (IOUT = -4mA) Output Low Voltage (IOUT = 4mA) VOH 2.4 – V VOL –0 . 4V Table 11: DC Electrical Characteristics and Operating Conditions – 512MB Module Notes: 1, 5, 6; notes appear on page 17; VDD, VDDQ = +3.3V ±0.3V PARAMETER/CONDITION SYMBOL MIN MAX UNITS NOTES SUPPLY VOLTAGE VDD, VDDQ 33 . 6V INPUT HIGH VOLTAGE: Logic 1; All inputs VIH 2V DD + 0.3 V 22 INPUT LOW VOLTAGE: Logic 0; All inputs VIL -0.3 0.8 V 22 INPUT LEAKAGE CURRENT: Any input 0V /g163 VIN /g163 VDD (All other pins not under test = 0V) Command and Address Inputs, CKE II -80 80 µA 33 CK, S# -20 20 µA DQ, DQMB -10 10 µA OUTPUT LEAKAGE CURRENT: DQ pins are disabled; 0V /g163 VOUT /g163 VDDQ IOZ -10 10 µA 33 OUTPUT LEVELS: Output High Voltage (IOUT = -4mA) Output Low Voltage (IOUT = 4mA) VOH 2.4 – V VOL –0 . 4V

256MB / 512MB (x64) 168-PIN SDRAM DIMMs 32,64 Meg x 64 SDRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice. SD8_16C32_64x64AG_C.fm - Rev. C 11/02 13 ©2002, Micron Technology Inc. NOTE: a - Value calculated as one module bank in this condition, and all other module banks in Power-Down Mode (IDD2). b - Value calculated reflects all module banks in this condition. Table 12: I DD Specifications and Conditions – 256MB Module Notes: 1, 5, 6, 11, 13; notes appear on page 17; VDD, VDDQ = +3.3v ±0.3v; SDRAM component values only MAX PARAMETER/CONDITION SYMBOL -13E -133 -10E UNITS NOTES OPERATING CURRENT: Active Mode; Burst = 2; READ or WRITE; tRC = tRC (MIN) IDD1 1,080 1,080 1,080 mA 3, 18,19, 22 STANDBY CURRENT: Power-Down Mode; All device device banks idle; CKE = LOW IDD2 16 16 16 mA 22 STANDBY CURRENT: Active Mode;CKE = HIGH; CS# = HIGH; All device banks active after tRCD met; No accesses in progress IDD3 320 320 320 mA 3, 12, 19, 22 OPERATING CURRENT: Burst Mode; Continuous burst; READ or WRITE; All device banks active IDD4 1,080 1,080 1,080 mA 3, 18, 19, 22 AUTO REFRESH CURRENT tRFC = tRFC (MIN) IDD5 2,280 2,160 2,160 mA 3, 12 CKE = HIGH; CS# = HIGH tRFC = 7.8125µs IDD6 28 28 28 mA 18, 19, 22, 31 SELF REFRESH CURRENT: CKE /g163 0.2V IDD7 20 20 20 mA 4 Table 13: I DD Specifications and Conditions – 512MB Module Notes: 1, 6, 11, 13; notes appear on page 17; VDD, VDDQ = +3.3V ±0.3V; SDRAM component values only MAX PARAMETER/CONDITION SYMBOL -13E -133 -10E UNITS NOTES OPERATING CURRENT: Active Mode; Burst = 2; READ or WRITE; tRC = tRC (MIN) IDD1a 1,096 1,016 1,016 mA 3, 18,19, 22 STANDBY CURRENT: Power-Down Mode; All device device banks idle; CKE = LOW IDD2b 32 32 32 mA 22 STANDBY CURRENT: Active Mode; CKE = HIGH; CS# = HIGH; All device banks active after tRCD met; No accesses in progress IDD3a 336 336 336 mA 3, 12, 19, 22 OPERATING CURRENT: Burst Mode; Continuous burst; READ or WRITE; All device banks active IDD4a 1,096 1,096 1,096 mA 3, 18, 19, 22 AUTO REFRESH CURRENT tRFC = tRFC (MIN) IDD5b 4,560 4,320 4,320 mA 3, 12 CKE = HIGH; CS# = HIGH tRFC = 7.8125µs IDD6b 56 56 56 mA 18, 19, 22, 31 SELF REFRESH CURRENT: CKE /g163/g320.2V IDD7b 40 40 40 mA 4

256MB / 512MB (x64) 168-PIN SDRAM DIMMs 32,64 Meg x 64 SDRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice. SD8_16C32_64x64AG_C.fm - Rev. C 11/02 14 ©2002, Micron Technology Inc. Table 14: Capacitance – 256MB Module Note 2; notes appear on page 17 PARAMETER SYMBOL MIN MAX UNITS Input Capacitance: A0-A12, BA0, BA1, RAS#, CAS#, WE# CI1 20 30.4 pF Input Capacitance: CK CI2 13.3 17.3 pF Input Capacitance: S# CI3 10 15.2 pF Input Capacitance: CKE CI4 20 30.4 pF Input Capacitance: DQMB CI5 2.5 3.8 pF Input/Output Capacitance: SCL, SA, SDA CI6 –1 0 p F Input/Output Capacitance: DQ CI0 46 p F Table 15: Capacitance – 512MB Module Note 2; notes appear on page 17 PARAMETER SYMBOL MIN MAX UNITS Input Capacitance: A0-A12, BA0, BA1, RAS#, CAS#, WE# CI1 40 60.8 pF Input Capacitance: CK CI2 13.3 17.3 pF Input Capacitance: S# CI3 10 15.2 pF Input Capacitance: CKE CI4 20 30.4 pF Input Capacitance: DQMB CI5 57 . 6 p F Input/Output Capacitance: SCL, SA, SDA CI6 –1 0 p F Input/Output Capacitance: DQ CIO 81 2 p F

256MB / 512MB (x64) 168-PIN SDRAM DIMMs 32,64 Meg x 64 SDRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice. SD8_16C32_64x64AG_C.fm - Rev. C 11/02 15 ©2002, Micron Technology Inc. Table 16: Electrical Characteristics and Recommended AC Operating Conditions Notes: 5, 6, 8, 9, 11; notes appear on page 17 Module AC timing parameters comply with PC100 and PC133 Design Specs, based on component parameters ACCHARACTERISTICS -13E -133 -10E PARAMETER SYMBOL MIN MAX MIN MAX MIN MAX UNITS NOTES Access timefrom CLK (pos.edge) CL=3 tAC(3) 5.4 5.4 6 ns 27 CL=2 tAC(2) 5.4 6 6 ns Address hold time tAH 0.8 0.8 1 ns Address setup time tAS 1.5 1.5 2 ns CLK high-level width tCH 2.5 2.5 3 ns CLK low-level width tCL 2.5 2.5 3 ns Clock cycle time CL=3 tCK(3) 77 . 58 n s 2 3 CL = 2 tCK(2) 7.5 10 10 ns 23 CKE hold time tCKH 0.8 0.8 1 ns CKE setup time tCKS 1.5 1.5 2 ns CS#, RAS#, CAS#, WE#, DQM hold time tCMH 0.8 0.8 1 ns CS#, RAS#, CAS#, WE#, DQM setup time tCMS 1.5 1.5 2 ns Data-in hold time tDH 0.8 0.8 1 ns Data-in setup time tDS 1.5 1.5 2 ns Data-out high-impedance time CL = 3 tHZ(3) 5.4 5.4 6 ns 10 CL = 2 tHZ(2) 5.4 6 6 ns 10 Data-out low-impedance time tLZ 111 n s Data-out hold time (load) tOH 333 n s Data-out hold time (no load) tOHN 1.8 1.8 1.8 ns 28 ACTIVE to PRECHARGE command tRAS 37 120,000 44 120,000 50 120,000 ns 29 ACTIVE to ACTIVE command period tRC 60 66 70 ns ACTIVE to READ or WRITE delay tRCD 15 20 20 ns Refresh period (8,192 rows) tREF 64 64 64 ms AUTOREFRESH period tRFC 66 66 70 ns PRECHARGE command period tRP 15 20 20 ns ACTIVE bank a to ACTIVE bank b command tRRD 14 15 20 ns WRITE recovery time tWR 1 CLK

1 CLK

7ns 7.5ns 7ns 14 15 15 ns 25 Exit SELF REFRESH to ACTIVE command tXSR 67 75 80 ns 20

256MB / 512MB (x64) 168-PIN SDRAM DIMMs 32,64 Meg x 64 SDRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice. SD8_16C32_64x64AG_C.fm - Rev. C 11/02 16 ©2002, Micron Technology Inc. Table 17: AC Functional Characteristics Notes: 5, 6, 7, 8, 9, 11; notes appear on page 17 PARAMETER SYMBOL -13E -133 -10E UNITS NOTES READ/WRITE command to READ/WRITE command tCCD 111 tCK 17 CKE to clock disable or power-down entry mode tCKED 111 tCK 14 CKE to clock enable or power-down exit setup mode tPED 111 tCK 14 DQM to input data delay tDQD 000 tCK 17 DQM to data mask during WRITEs tDQM 000 tCK 17 DQMto data high-impedance during READs tDQZ 222 tCK 17 WRITE command to input data delay tDWD 000 tCK 17 Data-into ACTIVE command tDAL 454 tCK 15, 21 Data-into PRECHARGE command tDPL 222 tCK 16, 21 Last data-in to burst STOP command tBDL 111 tCK 17 Last data-in to new READ/WRITE command tCDL 111 tCK 17 Lastdata-into PRECHARGE command tRDL 222 tCK 16, 21 LOADMODEREGISTER command to ACTIVE or REFRESH command tMRD 222 tCK 26 Data-out to high-impedance from PRECHARGE command CL = 3 tROH(3) 333 tCK 17 CL = 2 tROH(2) 222 tCK 17

256MB / 512MB (x64) 168-PIN SDRAM DIMMs 32,64 Meg x 64 SDRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice. SD8_16C32_64x64AG_C.fm - Rev. C 11/02 17 ©2002, Micron Technology Inc. Notes 1. All voltages referenced to V SS. 2. This parameter is sampled. V DD, V DDQ = +3.3V; TA = 25°C; pin under test biased at 1.4; f = 1 MHz. 3. IDD is dependent on output loading and cycle rates. Specified values are obtained with mini- mum cycle time and the outputs open. 4. Enables on-chip refresh and address counters. 5. The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range is ensured (Com- mercial T emperature: 0°C /g163 TA +70°C and Indus- trial Temperature: -40°C /g163/g32/g84/g65/g32/g163/g32+85/g176C). 6. An initial pause of 100µs is required after power-up, followed by two AUTO REFRESH commands, before proper device operation is ensured. (V DD and V DDQ must be powered up simultaneously. V SS and V SSQ must be at same potential.) The two AUTO REFRESH command wake-ups should be repeated any time the tREF refresh requirement is exceeded. 7. AC characteristics assume tT = 1ns. 8. In addition to meeting the transition rate specifi- cation, the clock and CKE must transit between V IH and V IL (or between V IL and V IH) in a mono- tonic manner. 9. Outputs measured at 1.5V with equivalent load: 10. tHZ defines the time at which the output achieves the open circuit condition; it is not a reference to V OH or VOL. The last valid data element will meet tOH before going High-Z. 11. AC timing and I DD tests have V IL = 0V and V IH = 3V , with timing referenced to 1.5V crossover point. If the input transition time is longer than 1ns, then the timing is referenced at V IL (MAX) and VIH (MIN) and no longer at the 1.5V crossover point. 12. Other input signals are allowed to transition no more than once every two clocks and are other- wise at valid V IH or VIL levels. 13. I DD specifications are tested after the device is properly initialized. 14. Timing actually specified by t CKS; clock(s) speci- fied as a reference only at minimum cycle rate. 15. Timing actually specified by tWR plus tRP; clock(s) specified as a reference only at minimum cycle rate. 16. Timing actually specified by tWR. 17. Required clocks are specified by JEDEC function- ality and are not dependent on any timing param- eter. 18. The I DD current will increase or decrease propor- tionally according to the amount of frequency alteration for the test condition. 19. Address transitions average one transition every two clocks. 20. CLK must be toggled a minimum of two times during this period. 21. Based on tCK = 10ns for -10E, and tCK = 7.5ns for - 133 and -13E. 22. V IH overshoot: VIH (MAX) = V DDQ + 2V for a pulse width /g163 3ns, and the pulse width cannot be greater than one third of the cycle rate. V IL under- shoot: VIL (MIN) = -2V for a pulse width /g163 3ns. 23. The clock frequency must remain constant (stable clock is defined as a signal cycling within timing constraints specified for the clock pin) during access or precharge states (READ, WRITE, includ- ing tWR, and PRECHARGE commands). CKE may be used to reduce the data rate. 24. Auto precharge mode only. The precharge timing budget ( tRP) begins 7ns for -13E; 7.5ns for -133 and 7ns for -10E after the first clock delay, after the last WRITE is executed. May not exceed limit set for precharge mode. 25. Precharge mode only. 26. JEDEC and PC100 specify three clocks. 27. tAC for -133/-13E at CL = 3 with no load is 4.6ns and is guaranteed by design. 28. Parameter guaranteed by design. 29. The value of tRAS used in -13E speed grade mod- ule SPDs is calculated from tRC - tRP = 45ns. 30. For -10E, CL= 2 and tCK = 10ns; for -133, CL = 3 and tCK = 7.5ns; for -13E, CL = 2 and tCK = 7.5ns. 31. CKE is HIGH during refresh command period tRFC (MIN) else CKE is LOW . The I DD6 limit is actually a nominal value and does not result in a fail value. 32. Leakage number reflects the worst-case leakage possible through the module pin, not what each memory device contributes. 33. Leakage number reflects the worst-case leakage possible through the module pin, not what each memory device contributes. Q 50pF

256MB / 512MB (x64) 168-PIN SDRAM DIMMs 32,64 Meg x 64 SDRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice. SD8_16C32_64x64AG_C.fm - Rev. C 11/02 19 ©2002, Micron Technology Inc. Table 18: EEPROM Device Select Code The most significant bit (b7) is sent first DEVICE TYPE IDENTIFIER CHIP ENABLE RW b7 b6 b5 b4 b3 b2 b1 b0 Memory Area Select Code (two arrays) 1 0 1 0 SA2 SA1 SA0 RW Protection Register Select Code 0 1 1 0 SA2 SA1 SA0 RW Table 19: EEPROM Operating Modes MODE RW BIT WC BYTES INITIAL SEQUENCE Current Address Read 1 VIH or VIL 1 Start, Device Select, RW = 1 RandomAddressRead 0 VIH or VIL 1 Start, Device Select, RW= 0, Address

1 VIH or VIL RESTART, Device Select, RW= 1

Sequential Read 1 VIH or VIL /g179/g321 Similar to Current or Random Address Read Byte Write 0V IL 1 START, Device Select, RW = 0 Page Write 0V IL /g163/g3216 START, Device Select, RW = 0 Table 20: SERIAL Presence-Detect EEPROM DC Operating Conditions VDD = +3.3V ±0.3V; All voltages referenced to VSS PARAMETER/CONDITION SYMBOL MIN MAX UNITS SUPPLY VOLTAGE VDD 33 . 6 V INPUT HIGH VOLTAGE: Logic 1; All inputs VIH VDD x 0.7 V DD + 0.5 V INPUT LOW VOLTAGE: Logic 0; All inputs VIL -1 V DD x 0.3 V OUTPUT LOW VOLTAGE: IOUT = 3mA VOL –0 . 4 V INPUT LEAKAGE CURRENT: VIN = GND to VDD ILI –1 0 µ A OUTPUT LEAKAGE CURRENT: VOUT = GND to VDD ILO –1 0 µ A STANDBY CURRENT: SCL = SDA = VDD - 0.3V; All other inputs = GND or 3.3V ±10% ICCS –3 0 µ A POWER SUPPLY CURRENT: SCL Clock frequency = 100 KHz ICC Write ICC Read mA

256MB / 512MB (x64) 168-PIN SDRAM DIMMs 32,64 Meg x 64 SDRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice. SD8_16C32_64x64AG_C.fm - Rev. C 11/02 20 ©2002, Micron Technology Inc. SPD EEPROM TIMING DIAGRAM NOTE: 1. The SPD EEPROM WRITE cycle time (tWRC) is the time from a valid stop condition of a write sequence to the end of the EEPROM internal erase/program cycle. During the WRITE cycle, the EEPROM bus interface circuit is disabled, SDA remains HIGH due to pull-up resistor, and the EEPROM does not respond to its slave address. SCL SDA IN SDA OUT tLOW tSU:STA tHD:STA tF tHIGH tR tBUFtDHtAA tSU:STOtSU:DATtHD:DAT UNDEFINED Table 21: Serial Presence-Detect EEPROM AC Operating Conditions VDD = +3.3V ±0.3V; All voltages referenced to VSS PARAMETER/CONDITION SYMBOL MIN MAX UNITS NOTES SCL LOW to SDA data-out valid tAA 0.3 3.5 µs Time the bus must be free before a new transition can start tBUF 4.7 – µs Data-out hold time tDH 300 ns SDA and SCL fall time tF 300 ns Data-in hold time tHD:DAT 0µ s Start condition hold time tHD:STA 4µ s ClockHIGHperiod tHIGH 4µ s Noise suppression time constant at SCL, SDA inputs tI 100 ns Clock LOW period tLOW 4.7 µs SDA and SCL rise time tR 1µ s SCL clock frequency fSCL 100 KHz Data-in setup time tSU:DAT 250 ns Start condition setup time tSU:STA 4.7 µs Stop condition setup time tSU:STO 4.7 µs WRITE cycle time tWRC 10 ms 1

256MB / 512MB (x64) 168-PIN SDRAM DIMMs 32,64 Meg x 64 SDRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice. SD8_16C32_64x64AG_C.fm - Rev. C 11/02 21 ©2002, Micron Technology Inc. Table 22: Serial Presence-Detect Matrix VDD = +3.3V ±0.3V; “1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW” BYTE DESCRIPTION ENTRY (VERSION) MT8LSDT3264A(I) MT16LSDT6464A(I)

0 NUMBER OF BYTES USED BY MICRON 128 80 80

1 TOTAL NUMBER OF SPD MEMORY BYTES 256 08 08

2 MEMORY TYPE SDRAM 04 04

3 NUMBER OF ROWADDRESSES 13 0D 0D

4 NUMBER OF COLUMN ADDRESSES 10 0A 0A

5 NUMBER OF MODULE BANKS 1 or 2 01 02

6 MODULE DATA WIDTH 64 40 40

7 MODULE DATA WIDTH (continued) 00 0 0 0

8 MODULE VOLTAGE INTERFACE LEVELS LVTTL 01 01

9 SDRAM CYCLE TIME, tCK

(CAS LATENCY = 3) 7ns (-13E) 7.5ns (-133) 8ns (-10E)

10 SDRAM ACCESS FROM CLK, tAC

(CAS LATENCY = 3) 5.4ns (-13E/-133) 6ns (-10E)

11 MODULE CONFIGURATION TYPE NONPARITY 00 00

12 REFRESH RATE/TYPE 7.8125µs/SELF 82 82

13 SDRAM WIDTH (PRIMARY SDRAM) 80 8 0 8

14 ERROR-CHECKING SDRAM DATA WIDTH NONE 00 00

15 MINIMUM CLOCK DELAY FROM BACK-TO-BACK

RANDOM COLUMN ADDRESSES,tCCD 10 1 0 1

16 BURST LENGTHS SUPPORTED 1, 2, 4, 8, PAGE 8F 8F

17 NUMBER OF BANKS ONS DRAM DEVICE 40 4 0 4

18 CAS LATENCIES SUPPORTED 2, 3 06 06

19 CS LATENCY 00 1 0 1

20 WE LATENCY 00 1 0 1

21 SDRAM MODULE ATTRIBUTES UNBUFFERED 00 00

22 SDRAM DEVICE ATTRIBUTES:GENERAL 0E 0E 0E

23 SDRAM CYCLE TIME , tCK

(CAS LATENCY = 2) 10 (-133/-10E) A0 7.5ns (13E) 10ns (-133/-10E)

24 SDRAMACCESSFROMCLK, tAC

(CAS LATENCY = 2) 5.4ns (-13E) 6ns (-133/-10E)

25 SDRAM CYCLE TIME, tCK

(CAS LATENCY = 1) 00 00

26 SDRAM ACCESS FROM CLK, tAC

(CAS LATENCY = 1) 00 00

27 MINIMUM ROW PRECHARGE TIME, tRP 15ns (-13E)

20ns (-133/-10E)

28 MINIMUM ROW ACTIVE TO ROW ACTIVE, tRRD 14ns (-13E)

15ns (-133) 20ns (-10E)

29 MINIMUM RAS# TO CAS# DELAY , tRCD 15ns (-13E)

20ns (-133/-10E)

30 MINIMUM RAS# PULSE WIDTH, tRAS (See note 1) 45ns (-13E)

44ns (133) 50ns (-10E)

256MB / 512MB (x64) 168-PIN SDRAM DIMMs 32,64 Meg x 64 SDRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice. SD8_16C32_64x64AG_C.fm - Rev. C 11/02 22 ©2002, Micron Technology Inc. NOTE: 1. The value of tRAS used for -13E modules is calculated from tRC - tRP. Actual device spec. value is 37ns.

31 MODULE BANK DENSITY 256MB 40 40

32 COMMAND AND ADDRESS SETUP TIME, tAS, tCMS 1.5ns (-13E/-133) 2ns (-10E) 33 COMMAND AND ADDRESS HOLD TIME, tAH, tCMH 0.8ns (-13E/-133) 1ns (-10E) 34 DATA SIGNAL INPUT SETUP TIME, tDS 1.5ns (-13E/-133) 2ns (-10E) 35 DATA SIGNAL INPUT HOLD TIME, tDH 0.8ns (-13E/-133) 1ns (-10E) 36-61 RESERVED 00 00 62 SPD REVISION REV. 1.2 12 12

63 CHECKSUM FOR BYTES 0-62 (-13E)

(-133) (-10E)

64 MANUFACTURER’S JEDEC ID CODE MICRON 2C 2C

65-71 MANUFACTURER’S JEDEC ID CODE(CONT.) FF FF

72 MANUFACTURING LOCATION 01 - 06 01 - 06

73-90 MODULE PART NUMBER (ASCII) Variable Data Variable Data

91 PCB IDENTIFICATION CODE 01-04 01-04

92 IDENTIFICATION CODE (CONT.) 00 0 0 0

93 YEAR OF MANUFACTURE IN BCD Variable Data Variable Data

94 WEEK OF MANUFACTURE IN BCD Variable Data Variable Data

95-98 MODULE SERIAL NUMBER Variable Data Variable Data 99-125 MANUFACTURER-SPECIFIC DATA (RSVD)

126 SYSTEM FREQUENCY 100 MHz (-13E/

-133/-10E) 64 64

127 SDRAM COMPONENT & CLOCK DETAIL AF FF

Table 22: Serial Presence-Detect Matrix (Continued) VDD = +3.3V ±0.3V; “1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW” BYTE DESCRIPTION ENTRY (VERSION) MT8LSDT3264A(I) MT16LSDT6464A(I)

256MB / 512MB (x64) 168-PIN SDRAM DIMMs 32,64 Meg x 64 SDRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice. SD8_16C32_64x64AG_C.fm - Rev. C 11/02 23 ©2002, Micron Technology Inc. Figure 10: 256MB Module Dimensions NOTE: All dimensions in inches (millimeters) or typical where noted. .125 (3.18) MAX .054 (1.37) .046 (1.17) PIN 1 (PIN 85 ON BACKSIDE) .700 (17.78) TYP.118 (3.00) (2X) .118 (3.00) TYP 4.550 (115.57) .050 (1.27) TYP .118 (3.00) TYP .039 (1.00) TYP .079 (2.00) R (2X) .039 (1.00)R (2X) FRONT VIEW .128 (3.25) .118 (3.00) PIN 84 (PIN 168 ON BACKSIDE) (2X) .250 (6.35) TYP 1.661 (42.18) 2.625 (66.68) 1.380 (35.05) 1.370 (34.80) 5.256 (133.50) 5.244 (133.20) U1 U2 U3 U4 U6 U7 U8 U9 U10 STANDARD PCB .125 (3.18) MAX .054 (1.37) .046 (1.17) PIN 1 (PIN 85 ON BACKSIDE) .700 (17.78) TYP.118 (3.00) (2X) .118 (3.00) TYP 4.550 (115.57) .050 (1.27) TYP .118 (3.00) TYP .039 (1.00) TYP .079 (2.00) R (2X) .039 (1.00)R (2X) FRONT VIEW .128 (3.25) .118 (3.00) PIN 84 (PIN 168 ON BACKSIDE) (2X) .250 (6.35) TYP 1.661 (42.18) 2.625 (66.68) 1.131 (28.73) 1.119 (28.42) 5.256 (133.50) 5.244 (133.20) U1 U2 U3 U4 U6 U7 U8 U9 U10 LOW PROFILE PCB MAX MIN

8000 S. Federal Way, P .O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992 Micron and the M logo are registered trademarks and the Micron logo is a trademark of Micron Technology, Inc. 256MB / 512MB (x64) 168-PIN SDRAM DIMMs 32,64 Meg x 64 SDRAM DIMMs ©2002, Micron Technology Inc. SD8_16C32_64x64AG_C.fm - Rev. C 11/02 24 Figure 11: 512MB Module Dimensions NOTE: All dimensions in inches (millimeters) or typical where noted. .157 (3.99) MAX .054 (1.37) .046 (1.17) PIN 1 .700 (17.78) TYP.118 (3.00) (2X) .118 (3.00) TYP 4.550 (115.57) .050 (1.27) TYP .118 (3.00) TYP .039 (1.00) TYP .079 (2.00) R (2X) .039 (1.00)R (2X) FRONT VIEW .128 (3.25) .118 (3.00)PIN 84 (2X) .250 (6.35) TYP 1.661 (42.18) 2.625 (66.68) 1.131 (28.73) 1.119 (28.42) 5.256 (133.50) 5.244 (133.20) U1 U2 U3 U4 U6 U7 U8 U9 U10 LOW PROFILE PCB U11 U12 U13 U14 U16 U17 U18 U19 PIN 85PIN 168 BACK VIEW .157 (3.99) MAX .054 (1.37) .046 (1.17) PIN 1 .700 (17.78) TYP.118 (3.00) (2X) .118 (3.00) TYP 4.550 (115.57) .050 (1.27) TYP .118 (3.00) TYP .039 (1.00) TYP .079 (2.00) R (2X) .039 (1.00)R (2X) FRONT VIEW .128 (3.25) .118 (3.00)PIN 84 (2X) .250 (6.35) TYP 1.661 (42.18) 2.625 (66.68) 1.380 (35.05) 1.370 (34.80) 5.256 (133.50) 5.244 (133.20) U1 U2 U3 U4 U6 U7 U8 U9 U10 STANDARD PCB U11 U12 U13 U14 U16 U17 U18 U19 PIN 85PIN 168 BACK VIEW MAX MIN