MT8LD864A

MT32LD3264A MICRON | Alldatasheet

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8, 16, 32 Meg x 64 Nonbuffered DRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice. DM78.p65 – Rev. 2/99 ©1999, Micron Technology, Inc. 8, 16, 32 MEG x 64 NONBUFFERED DRAM DIMMs KEY TIMING PARAMETERS SPEED tRC tRAC tPC tAA tCAC tCAS -5 84ns 50ns 20ns 25ns 13ns 8ns -6 104ns 60ns 25ns 30ns 15ns 10ns DRAM MODULE MT8LD864A X, MT16LD1664A X, MT32LD3264A X For the latest data sheet, please refer to the Micron Web site: www.micronsemi.com/datasheets/datasheet.html PIN ASSIGNMENT (Front View)FEATURES

• Eight-CAS# ECC pinout in a 168-pin, dual in-line memory module (DIMM)  64MB (8 Meg x 64), 128MB (16 Meg x 64), and 256MB (32 Meg x 64)  Nonbuffered  High-performance CMOS silicon-gate process  Single +3.3V ±0.3V power supply  All inputs, outputs and clocks are LVTTL- compatible  4,096-cycle CAS#-BEFORE-RAS# (CBR) refresh distributed across 64ms  Extended Data-Out (EDO) PAGE MODE access cycle  Serial presence-detect (SPD) OPTIONS MARKING  Package 168-pin DIMM (gold) G  Timing 50ns access -5 60ns access -6  Access Cycle EDO PAGE MODE X PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL 1V SS 43 V SS 85 V SS 127 V SS

2 DQ0 44 OE2# 86 DQ32 128 RFU

3 DQ1 45 RAS2# 87 DQ33 129 NC/RAS3#**

4 DQ2 46 CAS2# 88 DQ34 130 CAS6#

5 DQ3 47 CAS3# 89 DQ35 131 CAS7#

6V DD 48 WE2# 90 V DD 132 RFU

7 DQ4 49 V DD 91 DQ36 133 V DD

8 DQ5 50 N C 92 DQ37 134 N C

9 DQ6 51 N C 93 DQ38 135 N C

10 DQ7 52 N C 94 DQ39 136 N C

11 DQ8 53 N C 95 DQ40 137 N C

12 V SS 54 V SS 96 V SS 138 V SS

13 DQ9 55 DQ16 97 DQ41 139 DQ48

14 DQ10 56 DQ17 98 DQ42 140 DQ49

15 DQ11 57 DQ18 99 DQ43 141 DQ50

16 DQ12 58 DQ19 100 DQ44 142 DQ51

17 DQ13 59 V DD 101 DQ45 143 V DD

18 V DD 60 DQ20 102 V DD 144 DQ52

19 DQ14 61 N C 103 DQ46 145 N C

20 DQ15 6 2 RFU 104 DQ47 146 RFU

2 1 NC 6 3 NC 1 0 5 NC 1 4 7 NC

22 N C 64 V SS 106 N C 148 V SS

23 V SS 65 DQ21 107 V SS 149 DQ53

24 N C 66 DQ22 108 N C 150 DQ54

25 N C 67 DQ23 109 N C 151 DQ55

26 V DD 68 V SS 110 V DD 152 V SS

27 WE0# 69 DQ24 111 RFU 153 DQ56

28 CAS0# 70 DQ25 112 CAS4# 154 DQ57

29 CAS1# 71 DQ26 113 CAS5# 155 DQ58

30 RAS0# 72 DQ27 114 NC/RAS1#** 156 DQ59

31 OE0# 73 V DD 115 RFU 157 V DD

32 V SS 74 DQ28 116 V SS 158 DQ60

33 A0 75 DQ29 117 A1 159 DQ61

34 A2 76 DQ30 118 A3 160 DQ62

35 A4 77 DQ31 119 A5 161 DQ63

36 A6 78 V SS 120 A7 162 V SS

37 A8 79 N C 121 A9 163 N C

38 A10 80 N C 122 A11 164 N C

39 NC (A12) 81 NC 123 NC (A13) 165 SA0

40 V DD 8 2 SDA 124 V DD 166 SA1

41 V DD 83 SCL 125 RFU 167 SA2

42 R F U 84 V DD 126 RFU 168 V DD

** 256MB version only 168-Pin DIMM (H-14; 64MB) (H-17; 128MB) (H-30; 256MB) PART NUMBERS PART NUMBER CONFIGURATION SPEED MT8LD864AG-5 X 8 Meg x 64 50ns MT8LD864AG-6 X 8 Meg x 64 60ns MT16LD1664AG-5 X 16 Meg x 64 50ns MT16LD1664AG-6 X 16 Meg x 64 60ns MT32LD3264AG-5 X* 32 Meg x 64 50ns MT32LD3264AG-6 X* 32 Meg x 64 60ns *Contact factory for availability NOTE: Pin symbols in parentheses are not used on these modules but may be used for other modules in this product family. They are for reference only. Micron is a registered trademark of Micron Technology, Inc.

8, 16, 32 Meg x 64 Nonbuffered DRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice. DM78.p65 – Rev. 2/99 ©1999, Micron Technology, Inc. 8, 16, 32 MEG x 64 NONBUFFERED DRAM DIMMs toggle from valid data to High-Z and back to the same valid data. If OE# is toggled or pulsed after CAS# goes HIGH while RAS# remains LOW, data will transition to and remain High-Z. During an application, if the DQ outputs are wire OR’d, OE# must be used to disable idle banks of DRAMs. Alternatively, pulsing WE# to the idle banks during CAS# HIGH time will also tristate the outputs. Inde- pendent of OE# control, the outputs will disable after tOFF, which is referenced from the rising edge of RAS# or CAS#, whichever occurs last. (Refer to the 16 Meg x 4 [MT4LC16M4H9] DRAM data sheet for additional information on EDO functionality.) REFRESH Returning RAS# and CAS# HIGH terminates a memory cycle and decreases chip current to a reduced standby level. Also, the chip is preconditioned for the next cycle during the RAS# HIGH time. Correct memory cell data is preserved by maintaining power and ex- ecuting any RAS# cycle (READ, WRITE) or RAS# RE- FRESH cycle (RAS#-ONLY, CBR or HIDDEN) so that all combinations of RAS# addresses (A0-A10/A11) are executed at least every tREF, regardless of sequence. The CBR REFRESH cycle will invoke the internal refresh counter for automatic RAS# addressing. SERIAL PRESENCE-DETECT OPERATION This module family incorporates serial presence- detect (SPD). The SPD function is implemented using a 2,048-bit EEPROM. This nonvolatile storage device contains 256 bytes. The first 128 bytes can be pro- grammed by Micron to identify the module type and various DRAM organizations and timing parameters. The remaining 128 bytes of storage are available for use by the customer. System READ/WRITE operations be- tween the master (system logic) and the slave EEPROM device (DIMM) occur via a standard IIC bus using the DIMM’s SCL (clock) and SDA (data) signals, together with SA(2:0), which provide 8 unique DIMM/EEPROM addresses. GENERAL DESCRIPTION The Micron ® MT8LD864A X, MT16LD1664A X and MT32LD3264A X are randomly accessed 64MB, 128MB and 256MB memories organized in a x64 con- figuration. They are specially processed to operate from 3V to 3.6V for low-voltage memory systems. During READ or WRITE cycles, each bit is uniquely addressed through the 22/23 address bits, which are entered 12 bits (A0-A11) at RAS# time and 11/12 bits (A0-A11) at CAS# time. READ and WRITE cycles are selected with the WE# input. A logic HIGH on WE# dictates read mode, while a logic LOW on WE# dictates write mode. During a WRITE cycle, data-in (D) is latched by the falling edge of WE# or CAS#, whichever occurs last. An EARLY WRITE occurs when WE# is taken LOW prior to CAS# falling. A LATE WRITE or READ-MODIFY-WRITE oc- curs when WE# falls after CAS# was taken LOW. During EARLY WRITE cycles, the data-outputs (Q) will remain High-Z regardless of the state of OE#. During LATE WRITE or READ-MODIFY-WRITE cycles, OE# must be taken HIGH to disable the data-outputs prior to applying input data. If a LATE WRITE or READ- MODIFY-WRITE is attempted while keeping OE# LOW, no WRITE will occur, and the data-outputs will drive read data from the accessed location. EDO PAGE MODE EDO PAGE MODE is an accelerated FAST-PAGE- MODE cycle. The primary advantage of EDO is the availability of data-out even after CAS# goes back HIGH. EDO provides for CAS# precharge time ( tCP) to occur without the output data going invalid. This elimination of CAS# output control provides for pipe- line READs. FAST-PAGE-MODE modules have traditionally turned the output buffers off (High-Z) with the rising edge of CAS#. EDO-PAGE-MODE DRAMs operate like FAST-PAGE-MODE DRAMs, except data will remain valid or become valid after CAS# goes HIGH during READs, provided RAS# and OE# are held LOW. If OE# is pulsed while RAS# and CAS# are LOW, data will

8, 16, 32 Meg x 64 Nonbuffered DRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice. DM78.p65 – Rev. 2/99 ©1999, Micron Technology, Inc. 8, 16, 32 MEG x 64 NONBUFFERED DRAM DIMMs FUNCTIONAL BLOCK DIAGRAM MT8LD864A X (64MB) DQ0-DQ7 DQ8-DQ15 DQ16-DQ23 DQ24-DQ31 DQ32-DQ39 DQ40-DQ47 DQ48-DQ55 DQ56-DQ63 A0-A11 OE2# WE2# CAS4# RAS2# CAS5# CAS7# CAS6# U1-U8 = MT4LC8M8C2 OE0# WE0# CAS0# RAS0# CAS1# CAS3# CAS2# 12 12 12 12 12 12 12 DQ0-DQ7 A0ÐA11 WE# OE# RAS# CAS# DQ0-DQ7 A0ÐA11 WE# OE# RAS# CAS# DQ0-DQ7 A0ÐA11 WE# OE# RAS# CAS# DQ0-DQ7 A0ÐA11 WE# OE# RAS# CAS# DQ0-DQ7 A0ÐA11 WE# OE# RAS# CAS# DQ0-DQ7 A0ÐA11 WE# OE# RAS# CAS# DQ0-DQ7 A0ÐA11 WE# OE# RAS# CAS# DQ0-DQ7 A0ÐA11 WE# OE# RAS# CAS# SPD SCL VDD VSS U1-U8 U1-U8 SDA SA0 SA1 SA2 A0 A1 A2

8, 16, 32 Meg x 64 Nonbuffered DRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice. DM78.p65 – Rev. 2/99 ©1999, Micron Technology, Inc. 8, 16, 32 MEG x 64 NONBUFFERED DRAM DIMMs FUNCTIONAL BLOCK DIAGRAM MT16LD1664A X (128MB) DQ0-DQ3 DQ4-DQ7 DQ8-DQ11 DQ12-DQ15 DQ16-DQ19 DQ20-DQ23 DQ24-DQ27 DQ28-DQ31 DQ32-DQ35 DQ36-DQ39 DQ40-DQ43 DQ44-DQ47 DQ48-DQ51 DQ52-DQ55 DQ56-DQ59 DQ60-DQ63 U1-U16 = MT4LC16M4H9 12 12 12 12 12 12 12 12 12 12 12 12 12 12 OE0# CAS1# CAS2# CAS3# WE0# CAS0# OE2# CAS5# CAS6# CAS7# WE2# CAS4# A0-A11 RAS0# RAS2# SPD SCL SDA A0 A1 A2 SA0 SA1 SA2 WE# OE# RAS# CAS# DQ0-DQ3 A0ÐA11 WE# OE# RAS# CAS# DQ0-DQ3 A0ÐA11 WE# OE# RAS# CAS# DQ0-DQ3 A0ÐA11 WE# OE# RAS# CAS# DQ0-DQ3 A0ÐA11 WE# OE# RAS# CAS# DQ0-DQ3 A0ÐA11 WE# OE# RAS# CAS# DQ0-DQ3 A0ÐA11 WE# OE# RAS# CAS# DQ0-DQ3 A0ÐA11 WE# OE# RAS# CAS# DQ0-DQ3 A0ÐA11WE# OE# RAS# CAS# DQ0-DQ3 A0ÐA11 WE# OE# RAS# CAS# DQ0-DQ3 U10 A0ÐA11 WE# OE# RAS# CAS# DQ0-DQ3 U11 A0ÐA11 WE# OE# RAS# CAS# DQ0-DQ3 U12 A0ÐA11 WE# OE# RAS# CAS# DQ0-DQ3 U13 A0ÐA11 WE# OE# RAS# CAS# DQ0-DQ3 U14 A0ÐA11 WE# OE# RAS# CAS# DQ0-DQ3 U15 A0ÐA11 WE# OE# RAS# CAS# DQ0-DQ3 U16 A0ÐA11 VDD VSS U1-U16 U1-U16

8, 16, 32 Meg x 64 Nonbuffered DRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice. DM78.p65 – Rev. 2/99 ©1999, Micron Technology, Inc. 8, 16, 32 MEG x 64 NONBUFFERED DRAM DIMMs FUNCTIONAL BLOCK DIAGRAM MT32LD3264A X (256MB) U1-U32 = MT4LC16M4H9 12 12 12 12 12 12 12 12 12 12 12 12 12 12 RAS1# RAS3# SA0 SPD SCL SDA SA1 SA2 WE# OE# RAS# CAS# WE# OE# RAS# CAS# WE# OE# RAS# CAS# WE# OE# RAS# CAS# DQ0-DQ3 DQ0-DQ3 DQ0-DQ3 DQ0-DQ3 U2 U3 U4 12 12 12 12 12 12 12 A0ÐA11 A0 ÐA11 A0 ÐA11 A0 ÐA11 WE# OE# RAS# CAS# A0ÐA11 WE# OE# RAS# CAS# A0ÐA11 WE# OE# RAS# CAS# A0ÐA11 WE# OE# RAS# CAS# A0ÐA11 12 12 12 12 12 12 12 OE0# CAS1# CAS2# CAS3# WE0# CAS0# OE2# CAS5# CAS6# CAS7# WE2# CAS4# A0-A11 RAS0# RAS2# U5 U6 U7 WE# OE# RAS# CAS# WE# OE# RAS# CAS# WE# OE# RAS# CAS# WE# OE# RAS# CAS#A0ÐA11 A0 ÐA11 A0 ÐA11 A0 ÐA11 WE# OE# RAS# CAS# A0ÐA11 WE# OE# RAS# CAS# A0ÐA11 WE# OE# RAS# CAS# A0ÐA11 WE# OE# RAS# CAS# A0ÐA11 WE# OE# RAS# CAS# WE# OE# RAS# CAS# WE# OE# RAS# CAS# WE# OE# RAS# CAS#A0ÐA11 A0 ÐA11 A0 ÐA11 A0 ÐA11 WE# OE# RAS# CAS# A0ÐA11 WE# OE# RAS# CAS# A0ÐA11 WE# OE# RAS# CAS# A0ÐA11 WE# OE# RAS# CAS# A0ÐA11 WE# OE# RAS# CAS# WE# OE# RAS# CAS# WE# OE# RAS# CAS# WE# OE# RAS# CAS#A0ÐA11 A0 ÐA11 A0 ÐA11 A0 ÐA11 WE# OE# RAS# CAS# A0ÐA11 WE# OE# RAS# CAS# A0ÐA11 WE# OE# RAS# CAS# A0ÐA11 WE# OE# RAS# CAS# A0ÐA11 U9 U10 U11 U12 U13 U14 U15 U16 U17 U18 U19 U20 U21 U22 U23 U25 U26 U27 U28 U29 U30 U31 U24 U32 VDD VSS U1-U32 U1-U32 DQ0-DQ3 DQ0-DQ3 DQ0-DQ3 DQ0-DQ3 DQ0-DQ3 DQ0-DQ3 DQ0-DQ3 DQ0-DQ3 DQ0-DQ3 DQ0-DQ3 DQ0-DQ3 DQ0-DQ3 DQ0-DQ3 DQ0-DQ3 DQ0-DQ3 DQ0-DQ3 DQ0-DQ3 DQ0-DQ3 DQ0-DQ3 DQ0-DQ3 DQ0-DQ3 DQ0-DQ3 DQ0-DQ3 DQ0-DQ3 DQ0-DQ3 DQ0-DQ3 DQ0-DQ3 DQ0-DQ3 DQ0-DQ3 DQ4-DQ7 DQ8-DQ11 DQ12-DQ15 DQ16-DQ19 DQ20-DQ23 DQ24-DQ27 DQ28-DQ31 DQ32-DQ35 DQ36-DQ39 DQ40-DQ43 DQ44-DQ47 DQ48-DQ51 DQ52-DQ55 DQ56-DQ59 DQ60-DQ63 DQ0-DQ3 DQ4-DQ7 DQ8-DQ11 DQ12-DQ15 DQ16-DQ19 DQ20-DQ23 DQ24-DQ27 DQ28-DQ31 DQ32-DQ35 DQ36-DQ39 DQ40-DQ43 DQ44-DQ47 DQ48-DQ51 DQ52-DQ55 DQ56-DQ59 DQ60-DQ63

8, 16, 32 Meg x 64 Nonbuffered DRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice. DM78.p65 – Rev. 2/99 ©1999, Micron Technology, Inc. 8, 16, 32 MEG x 64 NONBUFFERED DRAM DIMMs PIN DESCRIPTIONS PIN NUMBERS SYMBOL TYPE DESCRIPTION 30, 45, 114, 129 RA S0#-RAS3# Input Row-Address Strobe: RAS# is used to clock-in the row-address bits. Two RAS# inputs allow for one x64 bank or two x32 banks. 28, 29, 46, 47, 112, CA S0#-CAS7# Input Column-Address Strobe: CAS# is used to clock-in the 113, 130, 131 column-address bits, enable the DRAM output buffers and strobe the data inputs on WRITE cycles. Eight CAS# inputs allow byte access control for any memory bank configuration. 27, 48 WE0#, WE2# Input Write Enable: WE# is the READ/WRITE control for the DQ pins. WE0# controls DQ0-DQ31. WE2# controls DQ32-DQ63. If WE# is LOW prior to CAS# going LOW, the access is an EARLY WRITE cycle. If WE# is HIGH while CAS# is LOW, the access is a READ cycle, provided OE# is also LOW. If WE# goes LOW after CAS# goes LOW, then the cycle is a LATE WRITE cycle. A LATE WRITE cycle is generally used in conjunction with a READ cycle to form a READ-MODIFY-WRITE cycle. 31, 44 OE0#, OE2# Input Output Enable: OE# is the input/output control for the DQ pins. OE0# controls DQ0-DQ31. OE2# controls DQ32-DQ63. These signals may be driven, allowing LATE WRITE cycles. 33-38, 117-122 A0-A11 Input Address Inputs: These inputs are multiplexed and clocked by RAS# and CAS#. 2-5, 7-11, 13-17, 19-20, DQ0-DQ63 Input/ D ata I/O: For WRITE cycles, DQ0-DQ63 act as inputs 55-58, 60, 65-67, 69-72, Output to the addressed DRAM location. BYTE WRITEs may 74-77, 86-89,91-95, be performed by using the corresponding CAS# 97-101, 103-104, select (x64 mode only). For READ access cycles, 139-142, 144, 149-151, DQ0-DQ63 act as outputs for the addressed DRAM 153-156, 158-161 location. 42, 62, 111, 115, RFU – Reserved for Future Use: These pins should be left 125-126, 128, 132, 146 unc onnected. 6, 18, 26, 40, 41, 49, 59, V DD Supply Power Supply: +3.3V ±0.3V. 73, 84, 90, 102, 110, 124, 133, 143, 157, 168 1, 12, 23, 32, 43, 54, 64, V SS Supply Ground. 68, 78, 85, 96, 107, 116, 127, 138, 148, 152, 162 82 SDA Input/Output Serial Presence-Detect Data. SDA is a bidirectional pin used to transfer addresses and data into and data out of the presence-detect portion of the module. 83 SCL Input Serial Clock for Presence-Detect. SCL is used to synchronize the presence-detect data transfer to and from the module. 165-167 SA0-SA2 Input Presence-Detect Address Inputs. These pins are used to configure the presence-detect device.

8, 16, 32 Meg x 64 Nonbuffered DRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice. DM78.p65 – Rev. 2/99 ©1999, Micron Technology, Inc. 8, 16, 32 MEG x 64 NONBUFFERED DRAM DIMMs SERIAL PRESENCE-DETECT MATRIX BYTE DESCRIPTION ENTRY (V ERSION) BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 HEX

0 NUMBER OF BYTES USED BY MICRON 128 10000000 8 0

1 TOTAL NUMBER OF SPD MEMORY BYTES 256 00001000 0 8

2 MEMORY TYPE EDO PAGE MODE 00000010 0 2

3 NUMBER OF ROW ADDRESSES 12 00001100 0 C

4 NUMBER OF COLUMN ADDRESSES 11 (64MB) 00001011 0 B

12 (128MB, 256MB) 00001100 0 C

5 NUMBER OF BANKS 1 (64MB, 128MB) 00000001 0 1

2 (256MB) 00000010 0 2

6 DATA WIDTH x64 01000000 4 0

7 DATA WIDTH (continued) NONE 00000000 0 0

8 VOLTAGE INTERFACE LVTTL 00000001 0 1

9 RAS# ACCESS TIME ( tRAC) 50ns (-5) 00110010 3 2

60ns (-6) 00111100 3 C

10 CAS# ACCESS TIME ( tCAC) 13ns (-5) 00001101 0 D

15ns (-6) 00001111 0 F

11 MODULE CONFIGURATION TYPE NONPARITY 00000000 0 0

12 REFRESH RATES 15.625µ s/NORMAL 00000000 0 0

13 DRAM WIDTH (PRIMARY DRAM) x8 (64MB) 00001000 0 8

x4 (128MB, 256MB) 00010000 1 0

14 ERROR CHECKING DRAM DATA WIDTH NONE 00000000 0 0

15-61 RESERVED 00000000 0 0 62 SPD REVISION REV. 0 00000000 0 0

63 CHECKSUM FOR BYTES 0-62 64MB -5 00101010 2 A

64 MANUFACTURER ’S JEDEC ID CODE MI CRON 00101100 2 C

65-71 MANUFACTURER ’S JEDEC CODE (CONT.) 11111111 F F

72 MANUFACTURING LOCATION 00000001 0 1

73-90 MODULE PART NUMBER (ASCII) xxxxxxxx x x

91 PCB IDENTIFICATION CODE 1 00000001 0 1

92 IDENTIFICATION CODE (CONT.) 0 00000000 0 0

93 YEAR OF MANUFACTURE IN BCD xxxxxxxx x x

94 WEEK OF MANUFACTURE IN BCD xxxxxxxx x x

95-98 MODULE SERIAL NUMBER xxxxxxxx x x 99-125 MANUFACTURE SPECIFIC DATA (RSVD) ––––––––– NOTE: 1. “1”/“0”: Serial Data, “driven to HIGH ”/“driven to LOW. ” 2. x = Variable Data.

8, 16, 32 Meg x 64 Nonbuffered DRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice. DM78.p65 – Rev. 2/99 ©1999, Micron Technology, Inc. 8, 16, 32 MEG x 64 NONBUFFERED DRAM DIMMs ABSOLUTE MAXIMUM RATINGS* Voltage on Inputs or I/O Pins Operating Temperature, T A (ambient) .. 0°C to +70°C *Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other condi- tions above those indicated in the operational sections of this specification is not implied. Exposure to abso- lute maximum rating conditions for extended periods may affect reliability. DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS (Notes: 1) (VDD = +3.3V ±0.3V) PARAMETER/CONDITION SYMBOL SIZE MIN MAX UNITS NOTES SUPPLY VOLTAGE V DD ALL 3 3.6 V INPUT HIGH VOLTAGE: Logic 1; All inputs V IH ALL 2 V DD + 0.3 V 30 INPUT LOW VOLTAGE: Logic 0; All inputs V IL ALL -0.5 0.8 V 30 INPUT LEAKAGE CURRENT 64MB -2 2 Any input 0V ≤ VIN ≤ VDD + 0.3V CAS0#-CAS7# I I1 128MB -4 4 µA (All other pins not under test = 0V) 256MB -8 8 64MB -16 16 A0-A11 I I2 128MB -32 32 µA 256MB -64 64 64MB -8 8 WE0#, WE2#, I I3 128MB -16 16 µA OE0#, OE2# 256MB -32 32 64MB -8 8 RAS0#-RAS3# I I4 128MB -16 16 µA 256MB -16 16 OUTPUT LEAKAGE CURRENT: 64MB -5 5 DQ is disabled; 0V ≤ VOUT ≤ VDD + 0.3V DQ0-DQ63 I OZ 128MB -5 5 µA 256MB -10 10 OUTPUT LEVELS: V OH ALL 2.4 – V Output High Voltage (IOUT = -2mA) Output Low Voltage (IOUT = 2mA) V OL ALL – 0.4 V

8, 16, 32 Meg x 64 Nonbuffered DRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice. DM78.p65 – Rev. 2/99 ©1999, Micron Technology, Inc. 8, 16, 32 MEG x 64 NONBUFFERED DRAM DIMMs ICC OPERATING CONDITIONS AND MAXIMUM LIMITS (Notes: 1, 5, 6) (V DD = +3.3V ±0.3V) PARAMETER/CONDITION SYMBOL SIZE -5 -6 UNITS NOTES STANDBY CURRENT: TTL 64MB 8 8 (RAS# = CAS# = V IH)I CC1 128MB 16 16 mA 256MB 32 32 STANDBY CURRENT: CMOS 64MB 4 4 (RAS# = CAS# = V DD - 0.2V) I CC2 128MB 8 8 mA 256MB 16 16 OPERATING CURRENT: Random READ/WRITE 64MB 1,400 1,320 Average power supply current I CC3 128MB 2,720 2,560 mA 3, 24 (RAS#, CAS#, address cycling: tRC = tRC [MIN]) 256MB 2,736 2,576 OPERATING CURRENT: EDO PAGE MODE 64MB 1,240 1,000 Average power supply current I CC4 128MB 2,400 1,920 mA 3, 24 (RAS# = V IL, CAS#, address cycling: tPC = tPC [MIN]) 256MB 2,416 1,936 REFRESH CURRENT: RAS#-ONLY 64MB 1,400 1,320 Average power supply current I CC5 128MB 2,720 2,560 mA 3, 24 (RAS# cycling, CAS# = V IH: tRC = tRC [MIN]) 256MB 2,736 2,576 REFRESH CURRENT: CBR 64MB 1,320 1,240 Average power supply current I CC6 128MB 2,560 2,400 mA 3, 4 (RAS#, CAS#, address cycling: tRC = tRC [MIN]) 256MB 2,576 2,416 MAX CAPACITANCE PARAMETER SYMBOL 64MB 128MB 256MB UNITS NOTES Input Capacitance: A0-A11 C I1 46 86 168 pF 2 Input Capacitance: WE0#, WE2#, OE0#, OE2# C I2 32 60 118 pF 2 Input Capacitance: RAS0#-RAS3# C I3 32 60 60 pF 2 Input Capacitance: CAS0#-CAS7# C I4 10 18 32 pF 2 Input Capacitance: SCL, SA0-SA2 C I5 666 p F 2 Input/Output Capacitance: DQ0-DQ63, SDA C IO 12 12 22 pF 2 MAX

8, 16, 32 Meg x 64 Nonbuffered DRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice. DM78.p65 – Rev. 2/99 ©1999, Micron Technology, Inc. 8, 16, 32 MEG x 64 NONBUFFERED DRAM DIMMs EDO PAGE MODE AC ELECTRICAL CHARACTERISTICS AC CHARACTERISTICS -5 -6 PARAMETER SYMBOL MIN MAX MIN MAX UNITS NOTES Access time from column address tAA 25 30 ns Column-address setup to CAS# tACH 12 15 ns precharge during writes Column-address hold time (referenced to RAS#) tAR 38 45 ns Column-address setup time tASC 0 0 ns Row-address setup time tASR 0 0 ns Column address to WE# delay time tAWD 42 49 ns 23 Access time from CAS# tCAC 13 15 ns 14 Column-address hold time tCAH 8 10 ns CAS# pulse width tCAS 8 10,000 10 10,000 ns CAS# hold time (CBR Refresh) tCHR 8 10 ns 4 CAS# to output in Low-Z tCLZ 0 0 ns Data output hold after CAS# LOW tCOH 3 3 ns CAS# precharge time tCP 8 10 ns 15 Access time from CAS# precharge tCPA 28 35 ns CAS# to RAS# precharge time tCRP 5 5 ns CAS# hold time tCSH 38 45 ns CAS# setup time (CBR Refresh) tCSR 5 5 ns 4 CAS# to WE# delay time tCWD 30 35 ns 23 WRITE command to CAS# lead time tCWL 8 10 ns Data-in hold time tDH 8 10 ns 22 Data-in setup time tDS 0 0 ns 22 Output disable tOD 0 12 0 15 ns Output enable tOE 12 15 ns OE# hold time from WE# during tOEH 8 10 ns READ-MODIFY-WRITE cycle OE# HIGH hold time from CAS# HIGH tOEHC 5 10 ns OE# HIGH pulse width tOEP 5 5 ns OE# LOW to CAS# HIGH setup time tOES 4 5 ns Output buffer turn-off delay tOFF 0 12 0 15 ns 19, 27 OE# setup prior to RAS# tORD 0 0 ns 19 during HIDDEN REFRESH cycle EDO-PAGE-MODE READ or WRITE cycle time tPC 20 25 ns EDO-PAGE-MODE READ-WRITE cycle time tPRWC 47 56 ns Access time from RAS# tRAC 50 60 ns 13 RAS# to column-address delay time tRAD 9 12 ns 17 Row-address hold time tRAH 9 10 ns RAS# pulse width tRAS 50 10,000 60 10,000 ns RAS# pulse width (EDO PAGE MODE) tRASP 50 125,000 60 125,000 ns Random READ or WRITE cycle time tRC 84 104 ns RAS# to CAS# delay time tRCD 11 14 ns 16 READ command hold time (referenced to CAS#) tRCH 0 0 ns 18 READ command setup time tRCS 0 0 ns

8, 16, 32 Meg x 64 Nonbuffered DRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice. DM78.p65 – Rev. 2/99 ©1999, Micron Technology, Inc. 8, 16, 32 MEG x 64 NONBUFFERED DRAM DIMMs EDO PAGE MODE AC ELECTRICAL CHARACTERISTICS AC CHARACTERISTICS -5 -6 PARAMETER SYMBOL MIN MAX MIN MAX UNITS NOTES Refresh period (4,096 cycles) tREF 64 64 ms RAS# precharge time tRP 30 40 ns RAS# to CAS# precharge time tRPC 5 5 ns READ command hold time (referenced to RAS#) tRRH 0 0 ns 18 RAS# hold time tRSH 13 15 ns READ-WRITE cycle time tRWC 116 140 ns RAS# to WE# delay time tRWD 67 79 ns 23 WRITE command to RAS# lead time tRWL 13 15 ns Transition time (rise or fall) tT25 025 0 n s WRITE command hold time tWCH 8 10 ns WRITE command hold time (referenced to RAS#) tWCR 38 45 ns WE# command setup time tWCS 0 0 ns Output disable delay from WE# (CAS# HIGH) tWHZ 12 15 ns WRITE command pulse width tWP 5 5 ns WE# pulse width for output tWPZ 10 10 ns disable when CAS# HIGH WE# hold time (CBR Refresh) tWRH 8 10 ns WE# setup time (CBR Refresh) tWRP 8 10 ns

8, 16, 32 Meg x 64 Nonbuffered DRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice. DM78.p65 – Rev. 2/99 ©1999, Micron Technology, Inc. 8, 16, 32 MEG x 64 NONBUFFERED DRAM DIMMs SERIAL PRESENCE-DETECT EEPROM OPERATING CONDITIONS (Notes: 1) (V DD = +3.3V ±0.3V) PARAMETER/CONDITION SYMBOL MIN MAX UNITS NOTES SUPPLY VOLTAGE V DD 3 3.6 V INPUT HIGH VOLTAGE: Logic 1; All inputs V IH VDD x 0.7 V DD + 0.5 V INPUT LOW VOLTAGE: Logic 0; All inputs V IL -1 V DD x 0.3 V OUTPUT LOW VOLTAGE: IOUT = 3mA V OL – 0.4 V INPUT LEAKAGE CURRENT: VIN = GND to VDD ILI – 10 µA OUTPUT LEAKAGE CURRENT: VOUT = GND to VDD ILO – 10 µA STANDBY CURRENT: I SB – 30 µA SCL = SDA = VDD - 0.3V; All other inputs = GND or 3.3V +10% POWER SUPPLY CURRENT: I CC – 2m A SCL clock frequency = 100 KHz SERIAL PRESENCE-DETECT EEPROM AC ELECTRICAL CHARACTERISTICS (Notes: 1) (V DD = +3.3V ±0.3V) PARAMETER/CONDITION SYMBOL MIN MAX UNITS NOTES SCL LOW to SDA data-out valid tAA 0.3 3.5 µs Time the bus must be free before a new transition can start tBUF 4.7 µs Data-out hold time tDH 300 ns SDA and SCL fall time tF 300 ns Data-in hold time tHD:DAT 0 µs Start condition hold time tHD:STA 4 µs Clock HIGH period tHIGH 4 µs Noise suppression time constant at SCL, SDA inputs tI 100 ns Clock LOW period tLOW 4.7 µs SDA and SCL rise time tR1 µ s SCL clock frequency tSCL 100 KHz Data-in setup time tSU:DAT 250 ns Start condition setup time tSU:STA 4.7 µs Stop condition setup time tSU:STO 4.7 µs WRITE cycle time tWR 10 ms 28

8, 16, 32 Meg x 64 Nonbuffered DRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice. DM78.p65 – Rev. 2/99 ©1999, Micron Technology, Inc. 8, 16, 32 MEG x 64 NONBUFFERED DRAM DIMMs 19.tOFF (MAX) defines the time at which the output achieves the open circuit condition and is not referenced to V OH or VOL. 20.A HIDDEN REFRESH may also be performed after a WRITE cycle. In this case, WE# = LOW and OE# = HIGH. 21.The maximum current ratings are based with the memory operating or being refreshed in the x64 mode. The stated maximums may be reduced by approximately one-half when used in the x32 mode. 22.These parameters are referenced to CAS# leading edge in EARLY WRITE cycles and WE# leading edge in LATE WRITE or READ-MODIFY-WRITE cycles. 23. tWCS, t RWD, t AWD and t CWD are not restrictive operating parameters. t WCS applies to EARLY WRITE cycles. If tWCS > tWCS (MIN), the cycle is an EARLY WRITE cycle and the data output will remain an open circuit throughout the entire cycle. t RWD, t AWD and t CWD define READ- MODIFY-WRITE cycles. Meeting these limits allows for reading and disabling output data and then applying input data. OE# held HIGH and WE# taken LOW after CAS# goes LOW result in a LATE WRITE (OE#-controlled) cycle. t WCS, t RWD, tCWD and t AWD are not applicable in a LATE WRITE cycle. 24.Column address changed once each cycle. 25.The 3ns minimum parameter guaranteed by design. 26.Measured with the specified current load and 100pF. 27. tOFF on an EDO module is determined by the latter of the RAS# and CAS# signals to transition HIGH. 28.The SPD EEPROM WRITE cycle time ( tWR) is the time from a valid stop condition of a write sequence to the end of the EEPROM internal erase/ program cycle. During the WRITE cycle, the EEPROM bus interface circuit are disabled, SDA remains HIGH due to pull-up resistor, and the EEPROM does not respond to its slave address. 29.If OE# is tied permanently LOW, LATE WRITE or READ-MODIFY-WRITE operations are not possible. 30. V IH overshoot: VIH (MAX) = VDD + 2V for a pulse width ≤ 10ns, and the pulse width cannot be greater than one third of the cycle rate. VIL undershoot: VIL (MIN) = -2V for a pulse width ≤ 10ns, and the pulse width cannot be greater than one third of the cycle rate. NOTES 1. All voltages referenced to V SS. 2. This parameter is sampled. V DD = +3.3V; f = 1 MHz. 3. I CC is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time and the outputs open. 4. Enables on-chip refresh and address counters. 5. The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range is ensured. 6. An initial pause of 100µs is required after power- up, followed by eight RAS# REFRESH cycles (RAS#-ONLY or CBR with WE# HIGH), before proper device operation is ensured. The eight RAS# cycle wake-ups should be repeated any time the tREF refresh requirement is exceeded. 7. AC characteristics assume tT = 2ns for -5 and 2.5ns for -6. 8. V IH (MIN) and VIL (MAX) are reference levels for measuring timing of input signals. Transition times are measured between V IH and VIL (or between VIL and VIH). 9. In addition to meeting the transition rate specification, all input signals must transit between V IH and VIL (or between VIL and VIH) in a mono- tonic manner. 10.If CAS# and RAS# = V IH, data output is High-Z. 11.If CAS# = V IL, data output may contain data from the last valid READ cycle. 12.Measured with a load equivalent to two TTL gates and 100pF and VOL = 0.8V and VOH = 2V. 13.Requires that tAA and tCAC are not violated. 14.Requires that tAA and tRAC are not violated. 15.If CAS# is LOW at the falling edge of RAS#, output data will be maintained from the previous cycle. To initiate a new cycle and clear the data- out buffer, CAS# must be pulsed HIGH for tCP. 16.The tRCD (MAX) limit is no longer specified. tRCD (MAX) was specified as a reference point only. If tRCD was greater than the specified tRCD (MAX) limit, then access time was controlled exclusively by tCAC (tRAC [MIN] no longer applied). With or without the tRCD (MAX) limit, tAA and tCAC must always be met. 17.The tRAD (MAX) limit is no longer specified. tRAD (MAX) was specified as a reference point only. If tRAD was greater than the specified tRAD (MAX) limit, then access time was controlled exclusively by tAA (tRAC and tCAC no longer applied). With or without the tRAD (MAX) limit, tAA, tRAC and tCAC must always be met. 18.Either tRCH or tRRH must be satisfied for a READ cycle.

8, 16, 32 Meg x 64 Nonbuffered DRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice. DM78.p65 – Rev. 2/99 ©1999, Micron Technology, Inc. 8, 16, 32 MEG x 64 NONBUFFERED DRAM DIMMs READ CYCLE tRRH tCLZ tCAC tRAC tAA VALID DATA OPEN tOFF tRCH ROW tRCS tASC tRAH tRAD tAR tCAH tRCD tCAS tRSH tCSH tRP tRC tRAS tCRP tASR ROW OPEN RAS# V VIH IL V VIH IL ADDR V VIH IL DQ V VOH OL V VIH IL tODtOE OE# V VIH IL COLUMN CAS# WE# NOTE 1 tACH DON’T CARE UNDEFINED NOTE: 1. tOFF is referenced from rising edge of RAS# or CAS#, whichever occurs last. tOFF 0 12 0 15 ns tRAC 50 60 ns tRAD 9 12 ns tRAH 9 10 ns tRAS 50 10,000 60 10,000 ns tRC 84 104 ns tRCD 11 14 ns tRCH 0 0 ns tRCS 0 0 ns tRP 30 40 ns tRRH 0 0 ns tR S H 1 31 5n s -5 -6 SYMBOL MIN MAX MIN MAX UNITS TIMING PARAMETERS -5 -6 SYMBOL MIN MAX MIN MAX UNITS tAA 25 30 ns tACH 12 15 ns tAR 38 45 ns tASC 0 0 ns tASR 0 0 ns tCAC 13 15 ns tCAH 8 10 ns tCAS 8 10,000 10 10,000 ns tCLZ 0 0 ns tCRP 5 5 ns tCSH 38 45 ns tOD 0 12 0 15 ns tOE 12 15 ns

8, 16, 32 Meg x 64 Nonbuffered DRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice. DM78.p65 – Rev. 2/99 ©1999, Micron Technology, Inc. 8, 16, 32 MEG x 64 NONBUFFERED DRAM DIMMs EARLY WRITE CYCLE DON’T CARE UNDEFINED V VIH IL VALID DATA ROWCOLUMNROW tDS tWP tWCHtWCS tWCR tRWL tCWL tCAHtASCtRAHtASR tRAD tAR tCAS tRSH tCSH tRCDtCRP tRAS tRC tRP V VIH IL ADDR V VIH IL V VIH IL DQ V VIOH IOL V VIH IL RAS# OE# tDH WE# CAS# tACH -5 -6 SYMBOL MIN MAX MIN MAX UNITS tRAH 9 10 ns tRAS 50 10,000 60 10,000 ns tRC 84 104 ns tRCD 11 14 ns tRP 30 40 ns tR S H 1 31 5n s tRWL 13 15 ns tWCH 8 10 ns tWCR 38 45 ns tWCS 0 0 ns tWP 5 5 ns TIMING PARAMETERS -5 -6 SYMBOL MIN MAX MIN MAX UNITS tACH 12 15 ns tAR 38 45 ns tASC 0 0 ns tASR 0 0 ns tCAH 8 10 ns tCAS 8 10,000 10 10,000 ns tCRP 5 5 ns tCSH 38 45 ns tCWL 8 10 ns tDH 8 10 ns tDS 0 0 ns tRAD 9 12 ns

8, 16, 32 Meg x 64 Nonbuffered DRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice. DM78.p65 – Rev. 2/99 ©1999, Micron Technology, Inc. 8, 16, 32 MEG x 64 NONBUFFERED DRAM DIMMs EDO-PAGE-MODE READ CYCLE VALID DATA VALID DATA VALID DATA COLUMNCOLUMNCOLUMNROW ROW DON’T CARE UNDEFINED tOD tCAHtASC tCP tRSH tCPtCPtCAStRCDtCRP tPCtCSH tRASP tRP tCAHtASCtCAHtASC tAR tRAH tRAD tASR tRCS tRRH tRCH tOFF tCAC tCPA tAA tCLZtCAC tCPA tAA tCAC tRAC tAA tCLZ tOE tOD tOE tOD OPENOPEN V VIH IL V VIH IL ADDR V VIH IL V VIH IL DQ V VOH OL V VIH IL RAS# OE# tCAS tCAS CAS# WE# tCOH tOEP tOEHC tOES tOES tACHtACH tACH -5 -6 SYMBOL MIN MAX MIN MAX UNITS tOEHC 5 10 ns tOEP 5 5 ns tOES 4 5 ns tOFF 0 12 0 15 ns tPC 20 25 ns tRAC 50 60 ns tRAD 9 12 ns tRAH 9 10 ns tRASP 50 125,000 60 125,000 ns tRCD 11 14 ns tRCH 0 0 ns tRCS 0 0 ns tRP 30 40 ns tRRH 0 0 ns tR S H 1 31 5n s TIMING PARAMETERS -5 -6 SYMBOL MIN MAX MIN MAX UNITS tAA 25 30 ns tACH 12 15 ns tAR 38 45 ns tASC 0 0 ns tASR 0 0 ns tCAC 13 15 ns tCAH 8 10 ns tCAS 8 10,000 10 10,000 ns tCLZ 0 0 ns tCOH 3 3 ns tCP 8 10 ns tCPA 28 35 ns tCRP 5 5 ns tCSH 38 45 ns tOD 0 12 0 15 ns tOE 12 15 ns

8, 16, 32 Meg x 64 Nonbuffered DRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice. DM78.p65 – Rev. 2/99 ©1999, Micron Technology, Inc. 8, 16, 32 MEG x 64 NONBUFFERED DRAM DIMMs EDO-PAGE-MODE EARLY WRITE CYCLE tDS tDH tDS tDH tDS tDH tWCR VALID DATA VALID DATA VALID DATA tRWL tWP tCWL tWCHtWCS tWP tCWL tWCHtWCS tWP tCWL tWCHtWCS tCAHtASCtCAHtASCtCAHtASCtRAHtASR tRAD tACH tACH tACHtAR COLUMNCOLUMNCOLUMNROW ROW tCPtCAS tRSH tCPtCAStCPtCAStRCDtCRP tPCtCSH tRASP tRP V VIH IL CAS# V VIH IL ADDR V VIH IL WE# V VIH IL DQ V VIOH IOL RAS# OE# V VIH IL DON’T CARE UNDEFINED -5 -6 SYMBOL MIN MAX MIN MAX UNITS tPC 20 25 ns tRAD 9 12 ns tRAH 9 10 ns tRASP 50 125,000 60 125,000 ns tRCD 11 14 ns tRP 30 40 ns tR S H 1 31 5n s tRWL 13 15 ns tWCH 8 10 ns tWCR 38 45 ns tWCS 0 0 ns tWP 5 5 ns TIMING PARAMETERS -5 -6 SYMBOL MIN MAX MIN MAX UNITS tACH 12 15 ns tAR 38 45 ns tASC 0 0 ns tASR 0 0 ns tCAH 8 10 ns tCAS 8 10,000 10 10,000 ns tCP 8 10 ns tCRP 5 5 ns tCSH 38 45 ns tCWL 8 10 ns tDH 8 10 ns tDS 0 0 ns

8, 16, 32 Meg x 64 Nonbuffered DRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice. DM78.p65 – Rev. 2/99 ©1999, Micron Technology, Inc. 8, 16, 32 MEG x 64 NONBUFFERED DRAM DIMMs READ-WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE cycles) VALID D OUT VALID D IN ROW COLUMN ROW V VIH IL V VIH IL ADDR V VIH IL V VIH IL DQ V VIOH IOL V VIH IL RAS# OPENOPEN tOE tOD tCAC tRAC tAA tCLZ tDS tDH tAWD tWP tRWL tCWL tCWD tRWD tRCS tASC tCAH tAR tASR tRAD tCRP tRCD tCAS tRSH tCSH tRAS tRWC tRP tRAH OE# tOEH WE# tACH CAS# DON’T CARE UNDEFINED -5 -6 SYMBOL MIN MAX MIN MAX UNITS tOD 0 12 0 15 ns tOE 12 15 ns tOEH 8 10 ns tRAC 50 60 ns tRAD 9 12 ns tRAH 9 10 ns tRAS 50 10,000 60 10,000 ns tRCD 11 14 ns tRCS 0 0 ns tRP 30 40 ns tR S H 1 31 5n s tRWC 116 140 ns tR W D 6 77 9n s tRWL 13 15 ns tWP 5 5 ns TIMING PARAMETERS -5 -6 SYMBOL MIN MAX MIN MAX UNITS tAA 25 30 ns tACH 12 15 ns tAR 38 45 ns tASC 0 0 ns tASR 0 0 ns tAWD 42 49 ns tCAC 13 15 ns tCAH 8 10 ns tCAS 8 10,000 10 10,000 ns tCLZ 0 0 ns tCRP 5 5 ns tCSH 38 45 ns tC W D 3 03 5n s tCWL 8 10 ns tDH 8 10 ns tDS 0 0 ns

8, 16, 32 Meg x 64 Nonbuffered DRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice. DM78.p65 – Rev. 2/99 ©1999, Micron Technology, Inc. 8, 16, 32 MEG x 64 NONBUFFERED DRAM DIMMs EDO-PAGE-MODE READ-WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE cycles) DON’T CARE UNDEFINED tOEtOEtOE OPEN D OUT VALID DIN VALID D OUT VALID D IN VALID D OUT VALID D IN VALID OPEN tDH tDS tAA tCPA tCLZ tCAC tDH tDS tAA tCPA tCLZ tCAC tDH tDS tAA tCLZ tCAC tRAC tWP tCWL tRWL tCWD tAWD tWP tCWL tCWD tAWD tWP tCWL tCWD tAWD tRCS tRWD tASR tRAH tASC tRAD tAR tCAH tASC tCAH tASC tCAH tCP tCAS tRSH tCP tRPtRASP tCAStCPtCAStRCD tCSH tPC tCRP ROW COLUMN COLUMN COLUMN ROW V VIH IL CAS# V VIH IL ADDR V VIH IL V VIH IL DQ V VIOH IOL V VIH IL RAS# OE# WE# tPRWC tOEH tOD tOD tOD NOTE 1 NOTE: 1. tPC is for LATE WRITE cycles only. -5 -6 SYMBOL MIN MAX MIN MAX UNITS tOD 0 12 0 15 ns tOE 12 15 ns tOEH 8 10 ns tPC 20 25 ns tPRWC 47 56 ns tRAC 50 60 ns tRAD 9 12 ns tRAH 9 10 ns tRASP 50 125,000 60 125,000 ns tRCD 11 14 ns tRCS 0 0 ns tRP 30 40 ns tR S H 1 31 5n s tR W D 6 77 9n s tRWL 13 15 ns tWP 5 5 ns TIMING PARAMETERS -5 -6 SYMBOL MIN MAX MIN MAX UNITS tAA 25 30 ns tAR 38 45 ns tASC 0 0 ns tASR 0 0 ns tAWD 42 49 ns tCAC 13 15 ns tCAH 8 10 ns tCAS 8 10,000 10 10,000 ns tCLZ 0 0 ns tCP 8 10 ns tCPA 28 35 ns tCRP 5 5 ns tCSH 38 45 ns tC W D 3 03 5n s tCWL 8 10 ns tDH 8 10 ns tDS 0 0 ns

8, 16, 32 Meg x 64 Nonbuffered DRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice. DM78.p65 – Rev. 2/99 ©1999, Micron Technology, Inc. 8, 16, 32 MEG x 64 NONBUFFERED DRAM DIMMs EDO-PAGE-MODE READ EARLY WRITE CYCLE (Pseudo READ-MODIFY-WRITE) V VIH IL V VIH ILRAS# V VIH ILADDR V VIH ILWE# tRASP tRP ROW COLUMN (A) COLUMN (N) ROW V VIH ILOE# V VIOH IOL tCRP tCSH tCAStRCD tASR tRAH tRAD tASC tAR tCAH tASC tCAH tASC tCAH tCP tRSH VALID DATA IN tRCS tRCH tWCS tOE VALID DATA (B)VALID DATA (A) tWHZ tCAC tCPA tAA tCAC tAA OPENDQ tPC RACt tCOH tWCH tDS tDH tPC COLUMN (B) tACH CAS# tCAStCAStCP tCP DON’T CARE UNDEFINED -5 -6 SYMBOL MIN MAX MIN MAX UNITS tOE 12 15 ns tPC 20 25 ns tRAC 50 60 ns tRAD 9 12 ns tRAH 9 10 ns tRASP 50 125,000 60 125,000 ns tRCD 11 14 ns tRCH 0 0 ns tRCS 0 0 ns tRP 30 40 ns tR S H 1 31 5n s tWCH 8 10 ns tWCS 0 0 ns tWHZ 12 15 ns TIMING PARAMETERS -5 -6 SYMBOL MIN MAX MIN MAX UNITS tAA 25 30 ns tACH 12 15 ns tAR 38 45 ns tASC 0 0 ns tASR 0 0 ns tCAC 13 15 ns tCAH 8 10 ns tCAS 8 10,000 10 10,000 ns tCOH 3 3 ns tCP 8 10 ns tCPA 28 35 ns tCRP 5 5 ns tCSH 38 45 ns tDH 8 10 ns tDS 0 0 ns

8, 16, 32 Meg x 64 Nonbuffered DRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice. DM78.p65 – Rev. 2/99 ©1999, Micron Technology, Inc. 8, 16, 32 MEG x 64 NONBUFFERED DRAM DIMMs EDO READ CYCLE (with WE#-controlled disable) tCLZ tCAC tRAC tAA VALID DATA OPEN tRCHtRCS tASCtRAH tRAD tAR tCAH tRCD tCAS tCSH tCRP tASR ROW OPEN RAS# V VIH IL V VIH IL ADDR V VIH IL DQ V VOH OL V VIH IL tODtOE OE# V VIH IL COLUMN WE# tWHZ tWPZ tCP tASC tRCS COLUMN tCLZ DON’T CARE UNDEFINED CAS# -5 -6 SYMBOL MIN MAX MIN MAX UNITS tOD 0 12 0 15 ns tOE 12 15 ns tRAC 50 60 ns tRAD 9 12 ns tRAH 9 10 ns tRCD 11 14 ns tRCH 0 0 ns tRCS 0 0 ns tWHZ 12 15 ns tWPZ 10 10 ns TIMING PARAMETERS -5 -6 SYMBOL MIN MAX MIN MAX UNITS tAA 25 30 ns tAR 38 45 ns tASC 0 0 ns tASR 0 0 ns tCAC 13 15 ns tCAH 8 10 ns tCAS 8 10,000 10 10,000 ns tCLZ 0 0 ns tCP 8 10 ns tCRP 5 5 ns tCSH 38 45 ns

8, 16, 32 Meg x 64 Nonbuffered DRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice. DM78.p65 – Rev. 2/99 ©1999, Micron Technology, Inc. 8, 16, 32 MEG x 64 NONBUFFERED DRAM DIMMs RAS#-ONLY REFRESH CYCLE ROW V VIH IL CAS# V VIH IL ADDR V VIH IL RAS# tRC tRAS tRP tCRP tASR tRAH ROW OPENDQ V VOH OL tRPC WE# V VIH IL CBR REFRESH CYCLE (Addresses, OE# = DON’T CARE) tRP V VIH ILRAS# tRAS OPEN tCHRtCSR V VIH IL V VOH OL CAS# DQ tRP tRAS tRPC tCSRtRPC tCHRtCP V VIH IL tWRP tWRH tWRP tWRH WE# DON’T CARE UNDEFINED NOTE 1 -5 -6 SYMBOL MIN MAX MIN MAX UNITS tRAS 50 10,000 60 10,000 ns tRC 84 104 ns tRP 30 40 ns tRPC 5 5 ns tWRH 8 10 ns tWRP 8 10 ns TIMING PARAMETERS -5 -6 SYMBOL MIN MAX MIN MAX UNITS tASR 0 0 ns tCHR 8 10 ns tCP 8 10 ns tCRP 5 5 ns tCSR 5 5 ns tRAH 9 10 ns

8, 16, 32 Meg x 64 Nonbuffered DRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice. DM78.p65 – Rev. 2/99 ©1999, Micron Technology, Inc. 8, 16, 32 MEG x 64 NONBUFFERED DRAM DIMMs HIDDEN REFRESH CYCLE 20 (WE# = HIGH; OE# = LOW) DON’T CARE UNDEFINED tCLZ tOFF OPENVALID DATAOPEN COLUMNROW tCAC tRAC tAA tCAHtASCtRAHtASR tRAD tAR tCRP tRCD tRSH tRAS tRC tRP tCHR tRAS DQ V VIOH IOL V VIH ILADDR V VIH ILCAS# V VIH ILRAS# -5 -6 SYMBOL MIN MAX MIN MAX UNITS tOFF 0 12 0 15 ns tORD 0 0 ns tRAC 50 60 ns tRAD 9 12 ns tRAH 9 10 ns tRAS 50 10,000 60 10,000 ns tRC 84 104 ns tRCD 11 14 ns tRP 30 40 ns tR S H 1 31 5n s TIMING PARAMETERS -5 -6 SYMBOL MIN MAX MIN MAX UNITS tAA 25 30 ns tAR 38 45 ns tASC 0 0 ns tASR 0 0 ns tCAC 13 15 ns tCAH 8 10 ns tCHR 8 10 ns tCLZ 0 0 ns tCRP 5 5 ns tOD 0 12 0 15 ns tOE 12 15 ns

8, 16, 32 Meg x 64 Nonbuffered DRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice. DM78.p65 – Rev. 2/99 ©1999, Micron Technology, Inc. 8, 16, 32 MEG x 64 NONBUFFERED DRAM DIMMs SPD EEPROM SCL SDA IN SDA OUT tLOW tSU:STA tHD:STA tF tHIGH tR tBUFtDHtAA tSU:STOtSU:DATtHD:DAT UNDEFINED SERIAL PRESENCE-DETECT EEPROM TIMING PARAMETERS SYMBOL MIN MAX UNITS tAA 0.3 3.5 µs tBUF 4.7 µs tDH 300 ns tF 300 ns tHD:DAT 0 µs tHD:STA 4 µs tHIGH 4 µs tLOW 4.7 µs tR1 µ s tSU:DAT 250 ns tSU:STA 4.7 µs tSU:STO 4.7 µs SYMBOL MIN MAX UNITS

8, 16, 32 Meg x 64 Nonbuffered DRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice. DM78.p65 – Rev. 2/99 ©1999, Micron Technology, Inc. 8, 16, 32 MEG x 64 NONBUFFERED DRAM DIMMs 168-PIN DIMM DF-16 (64MB) .200 (5.08) MAX .054 (1.37) .046 (1.17) 1.105 (28.07) 1.095 (27.81) PIN 1 (PIN 85 ON BACKSIDE) .700 (17.78) TYP.118 (3.00) (2X) .118 (3.00) TYP 4.550 (115.57) .050 (1.27) TYP .118 (3.00) TYP .039 (1.00) TYP .079 (2.00) R (2X) .039 (1.00)R (2X) FRONT VIEW .128 (3.25) .118 (3.00) PIN 84 (PIN 168 ON BACKSIDE) (2X) .250 (6.35) TYP 1.661 (42.18) 2.625 (66.68) 5.256 (133.50) 5.244 (133.20) 168-PIN DIMM DF-27 (128MB) .350 (8.89) MAX .054 (1.37) .046 (1.17) 1.255 (31.88) 1.245 (31.62) PIN 1 (PIN 85 ON BACKSIDE) .700 (17.78) TYP.118 (3.00) (2X) .118 (3.00) TYP 4.550 (115.57) .050 (1.27) TYP .118 (3.00) TYP .039 (1.00) TYP .079 (2.00) R (2X) .039 (1.00)R (2X) FRONT VIEW .128 (3.25) .118 (3.00) PIN 84 (PIN 168 ON BACKSIDE) (2X) .250 (6.35) TYP 1.661 (42.18) 2.625 (66.68) 5.256 (133.50) 5.244 (133.20) NOTE: All dimensions in inches (millimeters) MAX or typical where noted. MIN

8, 16, 32 Meg x 64 Nonbuffered DRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice. DM78.p65 – Rev. 2/99 ©1999, Micron Technology, Inc. 8, 16, 32 MEG x 64 NONBUFFERED DRAM DIMMs 168-PIN DIMM DF-41 (256MB) .350 (8.89) MAX .054 (1.37) .046 (1.17) 2.005 (51.93) 1.995 (50.67) PIN 1 (PIN 85 ON BACKSIDE) .700 (17.78) TYP.118 (3.00) (2X) .118 (3.00) TYP 4.550 (115.57) .050 (1.27) TYP .118 (3.00) TYP .039 (1.00) TYP .079 (2.00) R (2X) .039 (1.00)R (2X) FRONT VIEW .128 (3.25) .118 (3.00) PIN 84 (PIN 168 ON BACKSIDE) (2X) .250 (6.35) TYP 1.661 (42.18) 2.625 (66.68) 5.256 (133.50) 5.244 (133.20) 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 E-mail: prodmktg@micronsemi.com, Internet: http://www.micronsemi.com, Customer Comment Line: 800-932-4992 Micron is a registered trademark of Micron Technology, Inc. NOTE: All dimensions in inches (millimeters) MAX or typical where noted. MIN