Memory

MT8D132

Micron Technology

1 MEG, 2 MEG x 32 DRAM MODULES

Manufacturer: Micron Technology

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ICRON MT8D132(X), MT16D232(X) Mi . 1 MEG, 2 MEG x 32 DRAM MODULES DRAM 1 MEG, 2 MEG x 32 M ODU LE 4, 8 MEGABYTE, 5V, FAST PAGE OR EDO PAGE MODE FEATURES - * JEDEC- and industry-standard pinout in a 72-pin, PIN ASSIGNMENT (Front View) single-in-line memory module (SIMM) © High-performance CMOS silicon-gate process. 72-Pin SIMM * Single +5V +10% power supply 7 « All device pins are TTL-compatible (DD-3) 1 Meg x 32 + Low power, 48mW standby; 1,824mW active, typical (DD-4) 2 Meg x 32 Zz (8MB) * Refresh modes: RAS ONLY, CAS-BEFORE-RAS (CBR) f and HIDDEN | lw} * Multiple RAS lines allow x16 or x32 width lo} lo a * 1,024-cycle refresh distributed across 16ms > + FAST PAGE MODE (FPM) operating mode or rome Extended Data-Out (EDO) PAGE MODE operating ' oF z\\=e mode [Ee EL eae) rae [TT re. TPT NTT] on [ve [ie {nc [a [nc [ss [ oo | | =e ng MARRS | FERS Hee ee eee | 60ns access 4 a 70ns access (FAST PAGE MODE only) 7 [5 | pare [23 | poze | si [case | so [vo | OT * Packages a A 72-pin SIMM M Hee eae ot pon] 72-pin SIMM (gold) S a + Opens eee ee eee FAST PAGE MODE Blank Cis [apa sor ar] EDO PAGE MODE x [ia [ ae [ae [9 [502s [sen] KEY TIMING PARAMETERS Heo | Seta | ER Ci] [ase [ee | EDO Operating Mode Hee bse ae | [ sreeo | ‘ne | ‘mac | tec [ian | ‘ac | ‘cas | “M6 version ty [6 [tions [éons | Bans | Sons | 7n= | tans FPM Operating Mode [ speco | trc | ‘rac [tc [ ‘aa | ‘cac | tap | -6 | tions | 6ons_| 36ns |" 30ns | 15ns | 40ns | [=| 90ns | ons] 40ns | ans] 20ns “J sons |

MICRON MT8D132(X), MT16D232(X)

1 MEG, 2 MEG x 32 DRAM MODULES

PART NUMBERS followed by a column-address strobed-in by CAS, CAS EDO Operating Mode may be toggled-in by holding RAS LOW and strobing-in different column-addresses, thus executing faster memory [ PARTNUMBER —_—s| ‘DESCRIPTION = ss cycles. Returning RAS HIGH terminates the FAST PAGE MODE operation. EDO PAGE MODE EDO PAGE MODE, designated by the “X” version, is an x= speed accelerated FAST PAGE MODE cycle. The primary advan- tage of EDO is the availability of data-out even after CAS FPM Operating Mode goes back HIGH. EDO provides for CAS precharge time (‘CP) to occur without the output data going invalid. This elimination of CAS output control provides for pipeline | READ FAST PAGE MODE modules have traditionally tured is] the output buffers off (High-Z) with the rising edge of Dy CAS. EDO operates as any DRAM READ or FAST-PAGE- X= speed MODE READ, except data will be held valid after CAS > goes HIGH, as long as RAS and OE are held LOW and WE = GENERAL DESCRIPTION is held HIGH (reference MT4C4007] DRAM data sheet for The MT8D132(X) and MT16D232(X) are randomly ac-__dditional information on EDO functionality), QD) cessed 4MB and 8MB solid-state memories organized in a = x32 configuration. During READ or WRITE cycles each bit REFRESH is uniquely addressed through the 20 address bits; which Returning RAS and CAS HIGH terminates a memory &\\ areentered 10bits(A0-A9) atatime.RASisusedtolatchthe __cycleand decreaseschip current toa reduced standby level. first 10 bits and CAS the latter 10 bits. A READ or WRITE Also, the chip is preconditioned for the next cycle during cycle is selected with the WE input. A logic HIGH on WE the RAS HIGH time. Memory cell data is retained in its dictates READ mode while a logic LOW on WE dictates correct state by maintaining power and executing any WRITE mode. During a WRITE cycle, data-in (D) is latched RAS cycle (READ, WRITE) or RAS refresh cycle (RAS. by the falling edge of WE or TAS. whichever occurs lest ONLY, CBR or HIDDEN) so that all 1,024 combination of EARLY WRITE occurs when WE goes LOW prior to CAS. RAS addresses (A0-A9) are executed at least every 16ms, going LOW, the output pin(s) remain open (High-Z) until _regardless of sequence. the next CAS cycle. x16 CONFIGURATION FAST PAGE MODE : For x16 applications, the corresponding DQ and CAS FAST PAGE MODE operations allow faster data opera- pins must be connected together (DQ1 to DQ17, DQ2 to tions (READ or WRITE) within a row-address-defined DQI8 and so forth, and CASO to CAS2 and CAST to (A0-A9) page boundary. The FAST PAGE MODE cycle is CAS3). Each RAS is then a bank select for the x16 memory always initiated with a row-address strobed-in by RAS _ organization. eae rere 5-18 Ti aay Fo mara nso SS AS

MT8D132(X), MT16D232(X MICRON 1 MEG, 2 MEG x 32 ORAM MODULeE FUNCTIONAL BLOCK DIAGRAM MT8D132(X) (4MB) DQ ssrereseenressereeeeereees DOS DOQQ ----orerereeeeeeroeee DQIE, Hi Hi ttt Hu aa CL __ ie 3 DQI7 werteereeenneeerenenns DOG DQ25 --+20-0----0--2eeeeeees DQBZ = tH Hu He ene 7) —_ us Fw * wf = sos FAST PAGE MODE U1-U8 = MT4C4001JDJ EDO PAGE MODE U1-U8 = MT4C4007JDJ

MT8D132(X), MT16D232(X) MICRON 1 MEG, 2 MEG x 32 DRAM MODULES FUNCTIONAL BLOCK DIAGRAM MT16D232(X) (8MB) Mt Hi Hh ! = i [oe [1% ore ——— | it i Hi Hu > om oa oa om = = re ea = a eee = = ies i c= Ca 2 ee oS eS i ttt i {tht Wit tt tit nea Ml —_—

ICRON MT8D132(X), MT16D232(X) mM won 1 MEG, 2 MEG x 32 DRAM MODULES TRUTH TABLE es ee FUNCTION us | os [we [a | © | voor | [standby ex | x xh taeay Sid | ROW | cor | ato] leamyware || ow [con] atin | EDOIFAST.PAGE- MODE READ (X version) EOORASTPAGE [stove [1 | wa | 2 | now | co | oan | move eaRywaiTe| ange [Lt [ He [ta | cou [bain | gy [RASOmvnerRESH | | | x | Row | ne | wine HIDDEN [ews [iowa |e [ [row | cou [panow | 3D REFRESH [ware fire |e [tow [con [Daten | [opaaerresH SP | PT x | x | iz | Q JEDEC DEFINED = PRESENCE-DETECT - MT8D132(X) (4MB) rr JEDEC DEFINED PRESENCE-DETECT - MT16D232(X) (8MB) [sven pms | | 7 | Pcheealert aad 5-21 ‘avn Tetley tenes Pt change Pn os ee Teareoge

ICRON MT8D132(X), MT16D232(X) Mi 1 MEG, 2 MEG x 32 DRAM MODULES ABSOLUTE MAXIMUM RATINGS* *Stresses greater than those listed under “Absolute Maxi- Voltage on Vcc Supply Relative to V5 w.sneuns “LV t0+7V mum Ratings” may cause permanent damage to the device. Storage Temperature (plastic) mn. “BB°C to +125°C device at these or any other conditions above those indi- Power Dissipation .sinnsnaneninnaniemnemueinesen SW cated in the operational sections of this specification is not Short Circuit Output Current cscs SOMA implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS (Notes: 1, 3, 6) (Vcc = +5V +10%) PARAMETER/CONDITION SYMBOL | MIN | MAX | UNITS | NOTES | Supply Voltage | voc [as [ss |v [| —— [input High (Logic 1) Voltage, allinputs | vm | 24 [Veo v [| TH | inputLow (Logic 0) Vottage, allinputs | ve | -10 {os |v [| SX | INPUT LEAKAGE CURRENT casocass| im | -¢ | @ | wa | | 5 | Any input ov svi < Ver +1.0V AO-AG, WE |e | 2 | a2] pa | 28] = (All other pins not under test = OV) |RASO-RASS| ts | 8 |e | uA | 25 | OUTPUT LEAKAGE CURRENT Dat-Das2 HA on (Qis disabled; OV < Vout < 5.5V) S | ourpur eves | vow [24 [| |v | = High Voltage (lout = -5mA) Voi v & | Low Voltage (lour = 4.2mA) PARAMETER/CONDITION symeot| size | -6 | -7 |UNITS| NOTES | STANDBY CURRENT: (TTL) Iec1 4MB 16 16 mA (RAS = CAS = Vin) 8MB 32 32 STANDBY CURRENT: (CMOS) lcce2 | 4MB 8 mA RAS = CAS = other inputs = Voc -0.2V) 8MB | 16 . OPERATING CURRENT: Random READ/WRITE Average power supply current os | SMB] feo | ere | (RAS, CAS, address cycling: 'RC = "RC [MIN}) OPERATING CURRENT: FAST PAGE MODE Average power supply current toce | SMe | O80 | 860 | mA (RAS = Vit, CAS, address cycling: 'PC = 'PC [MIN]) OPERATING CURRENT; EDO PAGE MODE Icos, Average power supply current (X only) ve eid ma (RAS = Vix, CAS, address cycling: 'PC = ‘PC [MIN]) REFRESH CURRENT: RAS ONLY Average power supply current loos one ee ae mA | 2,24 (RAS cycling, CAS = Vin: "RC = 'RC [MIN}} REFRESH CURRENT: CBR Average power supply current oor we ee eo RAS, CAS, address cycling: 'RC = 'RC [MIN}} =o 5-22 Ta mane RS WH 6321549 00135b3 129

MICRON MT8D132(X), MT16D232(X) " 1 MEG, 2 MEG x 32 DRAM MODULES CAPACITANCE [Max | [PARAMETERS SYMBOL | AMB | OMB | UNITS [NOTES Input Capacitance: A0-A9 [on | 48 | 95 [pe [17 | Input Capacitance: WE [ce | 64 | te7 | pr | 17 | Input Capacitance: RASO-RASS [cw | 32 | 32 | pr | 17 | Input Capacitance: CASO-CASS- [cs [16 | 32 | pr | 17 | FAST PAGE MODE Zz ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS is) Ta CHARACTERISTICS - FAST PAGE WODE OPTION a ae [ewer || [Access tmetromcoumnadaress i ATT oT Ts | {columns noite (terensoa DRA] [ aa [ase eg [Ccolumn-aderess setup ime | “aso_{o | [0 || ns | | [Rowadsress soup time eo fe [hoooss time fom CRS cn fs ["Column-adcrssholsine oa | Ps | [[cxE ise wan | rs | 15 | Yom00 | 20 10000 [nsf [CRS hold tine (CBRREFRESH] | to tos [[CkStocuipdintow2Z ou fo fo fs | [Acooss time om CRS precharge Si PAT Ts | [CAS to RAS prechargetme SS oP oT Os | | [eaShodime sf ff [GAS setup imo (COR REFRESH) | esa_[ 10 | | 0 [ [rs [9 [wie commandte CRSeadtine | om [1s [| 2 || me [| [Datacnnoidtime i tof ts | | [Detain oldie (cforencedto RAS) [ ona | as [ss fs [Daiinsouptine | so fo os P| [ouput utter wmotdelay | OFF [sf | | | ne | 8 28 [FASTPAGEMODEREAD WATE Goetme ec | as || wo | [ns | | [AooossiimetomRAS TP TOs | | [RAS to colunn-aderese delaytme————SSCS~ RDP |S ss |e [‘Rowaddresshodtime —————SSSS~d rv [to to [CCoumn-address to RASTead me maf | a os [RAS puso wan eas | 00 | rope | 70 | foo00 | ns | | [RAS puce wan FASTPAGE WODE) | TRasP [60] 700.000 70 | 100,00 | rs [| [Random READ or WATTE cycletime | wc [wo { | 10] | ns |_| {Reed conmand old time WterencedwGAS) [won| o [| o |_| ms | 14 | [Read command etupiime | wes| 0 | | 0 | [rs |_| [Retesh period hoaeeycie) ————SC~i Se |) Te | @@ 6111549 0013564 965

MT8D132(X), MT16D232(X) MICRON 1 MEG, 2 MEG x 32 DRAM MODULES a FAST PAGE MODE ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS [ACCHARACTERISTICS-FASTPAGEMODEOPMON TTT dT id [panamereR |] [OTS [WES [FAS prechargetime TT fT Od ns Td [RAS 10 CAS prochargetime | Po} | Cd | Cd nf id [Read commandhodtime | ARH [oT | ds (| a [RAS hoidtime aH is a Ts id [ Write commandtoRASTeadime | a [ ts —+| 20 |_| rs |_| [Transition time (ise orfa) | ff 0 | 38 | 80 ns | id [Write command holdtime | WOH | 10] S| is rs | Cd [ Wite command hold time (eferenced io FAS) ‘| wor | 45_| | 65 |_| re |_| [ We commandsetptime | wos | 0 | «| oi} ns PY =] | Write command pulse width | we to fT is [| Tos (| SC 0 [We hoidtime aR REFRESH) (wart 10 | 0 rs D> [WE soupsime CoRRErRESH [wap [to |] 0 |] re Q Err YM M@@ 6121549 0013565 87) mm

MT8D132(X), MT16D232(X) MICRON 1 MEG, 2 MEG x 32 DRAM MODULES EDO PAGE MODE ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS [Acouanacrenisnes-epopasewoneommow Sd dT i 7 [PARAMETER iSCSI OMX [UNS | NOTES | | RAS prechargetime TTT ts STC [RAStoCAS prechargetime | TSC ts] SCS | Readcommandhoidtime TR [Ts Tt [ RAShoidime as ts ns | Write commandtoRASieadtime | mm TS Tos STS | Transition time (rise orfal) | tS | OTC S| | Write commandhokdime | WH | TCTs S| Si [ Write command hoid time (referenced to RAS) | WOR | 5] ms |S | Wecommandsetuptime | wes | TCT rs | CC © (citer cst sty rom WE CAS IGE ae 8 8 | wa | Write commandpuisewidth | SP Tt || ts | Sid D> [WE pulse width for ouiput dsablewhenCASHIGH SSS | 0] —SidY Sons | id = | WEhoidtime(CBRREFRESH) | WR | tT |S [[WE setup tine (CBR REFRESH) ire 10 rs Q mm 6212545 0013567 &74 a

MICRON MT8D132(X), MT16D232(X) mon 1 MEG, 2 MEG x 32 DRAM MODULES NOTES 1. All voltages referenced to Vss. 14. Bither ‘RCH or ‘RRH must be satisfied for a READ 2. Iccis dependent on output loading and cycle rates. cycle. Specified values are obtained with minimum cycle 15. These parameters are referenced to CAS leading edge time and the output open. in EARLY WRITE cycles. 3. An initial pause of 1001s is required after power-up 16. In addition to meeting the transition rate specifica- followed by eight RAS refresh cycles (RAS ONLY or tion, all input signals must transit between Vii and CBR with WE HIGH) before proper device operation ‘Vit (or between Vit. and Vii) in a monotonic manner. is assured. The eight RAS cycle wake-ups should be 17. This parameter is sampled. Capacitance is measured repeated any time the 'REF refresh requirement is. using MIL-STD-883C, Method 3012.1 (1 MHz AC, exceeded. Vee = 4.5V, DC bias = 2.4V at 15mV RMS). 4. AC characteristics assume 'T = Sns for FAST PAGE, 18. IF CAS is LOW at the falling edge of RAS, data-out MODE and ‘T = 1.5ns for EDO PAGE MODE. (Q) will be maintained from the previous cycle. To 5. Vin (MIN) and Vi. (MAX) are reference levels for initiate a new cycle and clear the data-out buffer, CAS ll measuring timing of input signals. Transition times must be pulsed HIGH for ‘CP. are measured between Vin and VIL. 19. On-chip refresh and address counters are enabled. J 6. The minimum specifications are used only to indicate 20. A HIDDEN REFRESH may also be performed after a Fy cycle time at which proper operation over the full WRITE cycle. In this case, WE = LOW. temperature range (0°C < T, $ 70°C) is assured. 21. LATE WRITE, READ WRITE or READ-MODIEY- > 7. Measured with a load equivalent to two TTL gates WRITE cycles are not available due to OE being = and 100pF. grounded on U1-U8/U16. 8. Assumes that ‘RCD < ‘RCD (MAX). If ‘RCD is greater 22. Operation within the ‘RAD (MAX) limit ensures that (f) than the maximum recommended value shown in this 'RCD (MAX) can be met. "RAD (MAX) is specified as === table, RAC will increase by the amount that ‘RCD a reference point only; if RAD is greater than the = exceeds the value shown. specified ‘RAD (MAX) limit, then access time is = 9. Assumes that ‘RCD 2 ‘RCD (MAX). controlled exclusively by ‘AA. 10. If CAS and RAS = Vin, data output is High-Z. 23. The 3ns minimum is a parameter guaranteed by 11. If CAS = Vi, data output may contain data from the design. last valid READ cycle. 24. Column-address changed once each cycle. 12. ‘OFF (MAX) defines the time at which the output 25. 4MB module values will be half of those shown. achieves the open circuit condition and is not 26. For FAST PAGE MODE option, ‘OFF is determined referenced to Vox or Vou. by the first RAS or CAS signal to transition HIGH. In 13. Operation within the RCD (MAX) limit ensures that comparison, ‘OFF on an EDO option is determined by *RAC (MAX) can be met. ‘RCD (MAX) is specified as the latter of the RAS and CAS signal to transition a reference point only; if "RCD is greater than the HIGH. specified "RCD (MAX) limit, then access time is 27. Applies to both EDO and FAST PAGE MODES. controlled exclusively by CAC. noe reas 5-27 a ero a A ta MM 6131549 o0735K8 Soo

MT8D132(X), MT16D232(X: MICRON 1 MEG, 2 MEG x 32 Ca woDuCeS READ CYCLE (FAST PAGE MODE Module) Rie me vi T = "ns [tee ae We | ; as, ee | ‘ASR RAM asc ‘CAH 9 n/n a , now > ee = * * YM | ; WLLL. (¢p] i tea = to, | DONT CARE BY unveFineo FAST PAGE MODE TIMING PARAMETERS. [bf Poe] Eee ——} far art a a oa Paseo] Pras 00 rao | 0 |r, 000-|—s— a a [cas | ~isrop00 | “20 roee | ne} oH 0] 0 | a a beset te] Ge pe} a MH 61113549 0013569 447

MT8D132(X), MT16D232(X) MICRON 1 MEG, 2 MEG x 32 DRAM MODULES READ CYCLE (EDO PAGE MODE Module) ‘ac IAS ‘AP we VET Si i ‘ew ‘eco co | St KY 4; avon Yt! 77) peeves HUTT how iw] ap | | WR ‘ROS. ‘ROH wv we Y 7 ! 7 His vere = ee a 2) DONT CARE = BY unberinen NOTE: 1. Although WE Is a “don't care” at RAS time during an access cycle (READ or WRITE), the system designer should implement ‘WE HIGH for ‘WRP and ‘WRH. This design implementation will facilitate compatibility with future EDO DRAMs. 2. ‘OFF is referenced from rising edge of RAS or CAS, whichever occurs last. EDO PAGE MODE TIMING PARAMETERS a bs) P| [aa 0s | a to [aR af RAL os [aso os | as 6001000 [as | [ase os | Po a rr [casi | toc [ns] | PROS of ns | a EO on Desh gre} RSs as [or ts | mo as [RAG eos wn os | [Rap ES 80s | M™ 6321549 0013570 165

MT8D132(X), MT16D232(X) MICRON 1 MEG, 2 MEG x 32 DRAM MODULES EARLY WRITE CYCLE2” tee as, we mas vy T = ‘ee eo __ [Tes TS yy = - we a. 1 ea FS = Mom

2 Ye ILE xz, + UDA — MUM MMM@q@HH MVM

MT8D132(X), MT16D232(X) MICRON 1 MEG, 2 MEG x 32 DRAM MODULES Oo FAST-PAGE-MODE READ CYCLE oe ee eS er] eres le 8, “Le cca use| == a = Eee || bee ‘ el Pod Ped ie be = "|| | 0 S| be S| bee eed |e wl] ee wl " > cont care ” Bl unoerineo = FAST PAGE MODE TIMING PARAMETERS a A OO [se] ar a a a pee ee) Pee [ean [a0 iss) as 00 [fon 00] 70 [0,600] “ns [eas [is | 000 [20 | Fomoo| ns} «= [aco [20 [as [2050 Ls Pez os | cw oo a A a a beep oe | Pre pe Dorr [3 [is [3 | fe | MM 6321549 0013572 T3) a

MT8D132(X), MT16D232(X) MICRON 1 MEG, 2 MEG x 32 DRAM MODULES eee EDO-PAGE-MODE READ CYCLE p> $$$ tse was Vit ‘esi ee | \\ % “ % “ cae Ro eas ie Tas oe cas {fe mS eS | ‘aa | mo ‘aA | "| pane) ee == ID

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‘6 ‘oxo — Pa el | ie “= aaa — DON'T CARE = Ei user NOTE: 1. Although WE is a “don't care” at RAS time during an access cycle (READ or WRITE), the system designer should implement WE HIGH for ‘WAP and 'WRH. This design implementation will facilitate compatibility with future EDO DRAMs. EDO PAGE MODE TIMING PARAMETERS a OO | [svat max Tors | a a [ec a ns | PAR as as [Rag 0s [aso st [RAD 5 30 ns pwasA os [ARAH 0 ns a CB PRA 0 ns | a OS [Rasp 60] 100,000 | ns | [cas 3] 70,000 [ns | [aco 2045s | fio rs [ach os} [oon ss] [acs os | [icp to re) [wep aos [cpa sn [RRR [fcrp ts | a ee [css as Ss [torr nsf wre 0 @™B 6111549 0013573 975

MT8D132(X), MT16D232(X) MICRON 1 MEG, 2 MEG x 32 DRAM MODULES FAST-PAGE-MODE EARLY-WRITE CYCLE a ‘pase tae ett LT ed soon Yet “7K pow Kc} CLD) - TKO row Ra pe Gees ape Zz a ee ‘os i jel 2 ee MMMM, Sree //, Lc 1/7, vauo vara LLL = @ cont care Hf morncn FAST PAGE MODE TIMING PARAMETERS a A SG a [asc [ o [UT co Ts | [Ran | to [| 0 os | [ase to To ns | [Rac | 30 | Ts ns Leas is rees 0promo is} Reo ae fas aoa ne [icp to PT to Ps fap [| 40 || 80 Ts | [orp [to [Tt ns [ash | is 0 ns [eso | 60 [| | 70 [| ns | Paw | ts fo ns | fom | is [| [20 | ns | [wee | to [| 1s [ns | [oH | to fT ts ns | [wer | 45 | {| 6 | | ons | ee oe Re ee bee} beet tt 44 oe MH 6121549 0013574 604 me

MT8D132(X), MT16D232(X) MICRON 1 MEG, 2 MEG x 32 DRAM MODULES EDO-PAGE-MODE EARLY-WRITE CYCLE we 7 | | weet fel | ele, | ee y, aa pir wn 8 TR MOIR HUNK OTR" VOLK weal ea] ees _ |. Sy Eas es Fs ote ll SL LMM << /) RT), TO (¢p) (oon care = BB unoceneo = NOTE: 1. Although WE is a “don't care” at RAS time during an access cycle (READ or WRITE), the system designer should implement WE HIGH for 'WRP and 'WRH. This design implementation will facilitate compatibility with future EDO DRAMs. EDO PAGE MODE TIMING PARAMETERS a SO SO” [ss] i | ae a a ee a [aS a a | Oe a a a a [Rest i 0 i] a a a a a a a M@@ 6311549 0013575 740

MT8D132(X), MT16D232(X) MICRON 1 MEG, 2 MEG x 32 DRAM MODULES EDO-PAGE-MODE READ-EARLY-WRITE CYCLE (Pseudo READ-MODIFY-WRITE) a TOL mms yet a two tec tas | tone | tnoo |" teas to fas toe || teas tor oe Ye LY j \\ i soon LK = VU MULT 2s XT. 0008 SLL row is) me toPA = Jcon | twee] [¢2]

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= MT8D132(X), MT16D232(X) Mi RON 1 MEG, 2 MEG x 32 DRAM MODULES . FAST-PAGE-MODE READ-EARLY-WRITE CYCLE (Pseudo READ-MODIFY-WRITE) ‘nase tne mas Ut = \\ ‘RSH ‘con tec | ‘RP tre. toa ‘op tcas. ‘ce. ee | en fee | eee | eee Pl ed ome VS tas iea0 ‘eau | ‘ash || pan, {4s0, | oan. asc, | TAH, | a FJ | = > | wa = we WES i ‘cac = ce Yet rar RR FA vauopara | i DONT CARE NOTE: 1. Donot drive data prior to tristate. UNDEFINED FAST PAGE MODE TIMING PARAMETERS po es TF | sym fin [wax [Min Tmax [ows | [sym in Max [WAX | UNITS | a pec as ao ns | a [rac eo 0s [asc To os] 3 pase oo sf panto tos] [tcac is ao ns} a0 ss | [Roan Po Tis Ts | rasp [60 [100,000| 70 | 700,000] ns _ | Teas [v5] 1000] 20 [Toe Tre] §— ROD [a0 pas 20] 80 ne] Poz fo os | acs oo ns eA OD | fpf ao Tso ns) [cre | to [to Pas] [ash [is [20s] [icsH 60 0s | [awe is ao ns Pom as 20 as) A | beet} —p ot Re at ae tf a Soe 6 rn aero WH 6221549 0013577 513

MT8D132(X), MT16D232(X) MICRON 1 MEG, 2 MEG x 32 DRAM MODULES EDO READ CYCLE (with WE-controlled disable) ms WT ‘est j-—{RP | ‘RD teas tcp oS eS Q f} ‘aR. tase mAb ‘asc oat tase, | = Sn ////), Sn e/a YY a WE Ym 1 ws) oe Nore | es > oh faz WH, Nouz ¢?) DON'T CARE, = (BY unverIned NOTE: 1. Although WE is a “don’t care” at FAS time during an access cycle (READ or WRITE), the system designer should implement WE HIGH for 'WRP and 'WRH. This design implementation will facilitate compatibility with future EDO DRAMs. EDO PAGE MODE TIMING PARAMETERS a SO rs [Sym INT MAX | UNITS | [sym Tmax UNITS | [aA 90 ns [wrac 80 ns | far a Ts | [RAD ts a0 ns Paso os | [Ran ts | [asa ns | [aco 20 as ns | [teagan | [ach os | [aq tos | acs ns [was 340,000 T ns [waz sas | [iowz ns [wer ts | [op to Tas | [WwRH to Ts | [orp tons [wae ts J [osh s s | MMH 6111549 0033578 4ST

MT8D132(X), MT16D232(X) MICRON 1 MEG, 2 MEG x 32 DRAM MODULES RAS-ONLY REFRESH CYCLE” es "= i ws Yt a} les - et LF wes “ULL LL z CBR REFRESH CYCLE 2 = (Addresses = DON'T CARE) o ‘ee teas ‘ee ‘nas, = ‘op |) tose || oun ‘neo, tose || tour a i wml wala wal vet LE woes “TELL MMM DONT CARE [RQ unverineo NOTE: 1. Although WE is a “don't care” at RAS time during an access cycle (READ or WRITE), the system designer should implement WE HIGH for 'WRP and 'WRH. This design implementation will facilitate compatibility with future EDO DRAMs. FAST PAGE MODE AND EDO PAGE MODE TIMING PARAMETERS a SN A S| [sym [win mma | win [Max | UNITS | [sym ain [ax | in Tax | UNITS | [fask fo Pos a0 90s | A [apf ao sons | [op to tos] [’aec(rem) [oo nsf a SC | 'apc(epo) [sf = ns | bee epee Pie ta rrr Ta M@™@ 6111549 0013579 356

MT8D132(X), MT16D232(X) MICRON 1 MEG, 2 MEG x 32 DRAM MODULES HIDDEN REFRESH CYCLE ®°.27 (WE = HIGH) jRAS {Re ‘RAS. me tore. ‘rcp ‘RSH we ‘CHR: vec y tage | [Tia 750, ||_ean = TAA ao . 8 bee ee z YZ vontcare ZS [RY unverineo = FAST PAGE MODE AND EDO PAGE MODE TIMING PARAMETERS a SN A [sym [min [MAX [MIN [MAK [UNS |= | sym min’ | MAK [WIN [WAX | UNITS | [aa | so Ts ns _| [ork ta Ts | sf 20 Tons _| [an as so ns [Rac TT eo TT 0 Ts [asc fo To TT ns a [asa fo TT oe TT ns [Ran to fo ns) [oactrom | | is [| 2 [ws | [Ra [ao | [as | | ns | [factepoy | [a7 {| = [ns] [Ras 60 10.000 [70 | 10.000 | ns _| [ican to is Ts | [aco | 20 | 45 [20 | 50 | ns | a a [apf ao feo ns | Dees pe] Pas is i M@@ 6111549 0013580 008

Product Information

MT8D132 specifications and overview.

Summary

1 MEG, 2 MEG x 32 DRAM MODULES

Description

1 MEG, 2 MEG x 32 DRAM MODULES

Source title MT8D132 Datasheet(PDF) - Micron Technology

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