MT62901

MT62901 AEROFLEX | Alldatasheet

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I —t— aD —— MT62901_ ARINC629_ENCODER/DECODER Micro Ci E = ‘exc rn CRQMHZ RICK RESYNC7E ERROR LBLRCVO GaTRcVO (eR ENCODER bts TXLABEL ConTao. N “es =. —s TX STOPN +——— REGISTER BIPERR sm [Te CONTRO } PARERR iwrenrace |, Ot ——{ERIFT REGISTER]. (GHIET REGISTER] ov oerere | = = [BUF FER_REGISTER ] SYave 0-F——} OEN NOUFFULL = mae wc Te-15 PURSTN tmnt RESET «0 GENERAL __FEATURES COMPLIANT TO ARINC629. 2 MBIT DATA RATE. 40/48 PIN DIL OR 44 PIN CHIP CARRIER. LOW POWER CMOS TECHNOLOGY. ENCODER BRECODER STARTS TRANSMISSION ON COMMAND. OPERATES WITH EITHER PHASE OF INPUT DATA. TRANSMITS MESSAGES OF ANY LENGTH. OPERATES WITH OR WITHOUT PRE-PRESYNC & PRESYNC. GENERATES PRE-PRESYNC & PRESYNC AT START OF MESSAGE. DETECTS ERRORS IN SYNC, BIPHASE & PARITY. GENERATES LABEL/DATA SYNC & PARITY. OPTIONAL SEPARATE ERROR REGISTER OUTPUTS. GENERATES INTER-STRING GAPS FOR MONITOR OUTPUTS INDICATE WHEN RECEIVING MULTIPLE WORDSTRING MESSAGES. LABEL OR DATA WORD. GENERATES TX ACTIVE OUTPUT DURING BUILT-IN CLOCK REGENERATION CIRCUIT. TRANSMISSION. BUILT-IN BUS QUIET DETECTION CIRCUIT. ABORTS TRANSMISSION ON REQUEST. GENERAL_ DESCRIPTION The Encoder and Decoder sections of the chip are independent except for sharing a common 16 bit parallel data highway. The Decoder receives serial data from an ARINC629 SIM and returns the regenerated clock signal. The serial data is decoded and presented on a 16 bit parallel highway with a label or data strobe for each word received. Label words containing errors are rejected. Data words containing errors set an error output. Devices in 48 pin packages have additional separate outputs to flag parity errors, bi-phase errors and data-sync errors. Monitor outputs indicate when a valid label is being received, and when a data word is being received. A Bus Quiet detector detects the end of each word received and sets bus quiet (BQ) active for 2.5 bit times (1.25 micro sec.). After this time, BQ remains set until activity is detected on the bus. The Encoder generates TXO, TXN and TXHB (TX High impedance on Bus) signals to drive an ARINC629 SIM. Sixteen bit parallel words loaded into a buffer register j are converted into ARINC629 label/data format with sync & parity, and transmitted | on the serial databus. A pulse on TXGO immediately initiates transmission of a message. Each message begins with pre-presync and presync pulses followed by a label word taken from the buffer register. Transmission continues with data or label words as long as the buffer register is refilled with fresh data. Data words follow with no gap, label words follow after a 4 bit-time gap to indicate the start of a new wordstring. The message transmission ends when no more data is loaded in the buffer register. \\ MT62901 ARINC 629 Encoder/Decoder Data Sheet - June 1992 Page 1 |

TXO & TXN Manchester II encoded serial data outputs to the SIM (Serial Interface Module). These signals are both low when the encoder is not transmitting. TXO & TXN are valid from at least 12n8 before until 2nS after the falling edge of XICK. xICK . Arinc terminal transmit clock Xtal oscillator input. 32Mhz for 2MBit data rate. The low and high pulse width must be at least 12.5nS. TXHB TX High Impedance on Bus output to control SIM output drivers. TXHB is brought low at the same time as TXO goes high at the start of a wordstring. It remains low until the last transition of TXO or TXN at the end of the wordstring. It will go low again at the start of any subsequent wordstrings in the same message. NLDBUFF Active low input asynchronously strobes parallel data into the encoder buffer register and strobes the state of TXLABEL into an internal latch. Data must be valid on TO-15 & TXLABEL from at least 8nS before until 12nS after the rising (trailing) edge of NLDBUFF. Minimum pulse width is 25ns. NBUFFULL Active low output asserted (low) on the rising (trailing) edge of NLDBUFF to indicate that the encoder buffer register has been loaded with a word for transmission. The word is transferred to the transmitter shift register during transmission of the sync pattern, and at this point, NBUFFULL is reset (high). If a further word is to be transmitted in the same message, it must be loaded within 6.25uS of NBUFFULL going high. The trailing edge (0->1) of the NLDBUFF strobe must occur at least 250nS after NBUFFULL goes high. TXLABEL Input to the encoder, strobed with NLDBUFF (see above). TXLABEL=1 if the word being loaded is a label. TXLABEL=0 if the word being loaded is a data word. TXLABEL is ignored for the first word of a message - the first word is always treated as a label word. TXGO Active high input to the encoder. A high level on this input initiates transmission of a message. To guarantee recognition of TXGO in a specific (XICK) clock cycle, it should be asserted from 8nS before until 12nS after the falling clock edge. Transmission of pre-presync will begin asynchronously immediately TXGO is asserted. The end of pre-presync will eccur 9 clock cycles ater the falling XICK clock edge on which TXGO is recognised. Note that transmission will begin even if the encoder buffer register is empty. In this case, the buffer must be loaded (with the first label to be transmitted) within 44 clock cycles of asserting TXGO. TX ACTIVE (available on 48 pin package only) This output is brought high immediately TxGO is received and remains high until 250nS after TXHB goes high at the end of the message. Note that TX ACTIVE remains high between wordstrings in the same message. TXSTOPN (available on 44 & 48 pin packages only) Active low input with high value internal pullup resistor. When asserted this input, aborts current transmission within 1.5 bit times. Transmission will re-start on the next TXGO. (ENCODER OPERATION a - a | TeLABEL LAgELS Datal LADELE teas a a a aT i dS n° 2: PRED, SYNC ne LABEL | rn $Y HC ne CATAL ee GAP SYNC re ABLE ee | UTE pe COCO Coo a ees | MT62901 ARINC 629 Enceder/Decoder Data Sheet ~ June 1992 Page 2 '

RXI & RXN Manchester II encoded serial data received from the SIM (Serial Interface Module). Phase of these signals is not important, and may change from one word-string to the next. The only requirement is that each transition or current doublet on the Bus causes one or both signals to change state. The SIM must detect bus quiet and set RXI@RXN on the fourth rising edge of RXCK after the last complementary RXI/RXN transition of a wordstring. RXI & RXN may be asynchronous with RICK. The total combined skew between them pluc the time distortion of the databus signal should not exceed 75nS for correct data decoding. To maximise tolerance to signal distortion on the data bus, skew between nominally simultaneous transitions on RXI & RXN should be less than i5ns. If RXI and RXN are synchronous with RICK, then they should be valid from 5nS before until 10nS after the falling edge of RICK to guarantee recognition on that specific clock edge. RXCK Regenerated clock output at twice data rate (4MHz) and phase locked to the received data. This signal is principally used to drive the SIM bus quiet timer. The SIM should signal bus quiet (i.e. set RXI*=RXN) on the fourth rising edge of RXCK after the last transition on RXI/RXN. The chip will tolerate variations of up to +62.5nS in the interval between successive changes on RXI/RXN without error or loss of data. RICK Arinc terminal receive clock Xtal oscillator input. Set to 32 Mhz for 2 MBit data rate. The low and high pulse width must be at least 12.5nS. PWRSTN Active low system/power-up reset input. MONLBL Monitor output. This signal is asserted (high) as long as the decoder is receiving a valid label word. Sync, biphase encoding or parity errors . detected in the label cause this output to be reset immediately. MONIBL is set high when the centre transition of the label sync (H-L) field is detected. If no errors are detected, MONLBL is reset at the end of the LBLRCVD pulse. . MONDAT - Monitor output. This signal is asserted (high) as long as the decoder is receiving data words. Biphase and parity errors do not affect this output. MONDAT is set high when the centre transition of the dataword sync (L-H) field is detected. It remains high until the end of the next DATRCVD pulse. If an invalid data sync pattern is received, MONDAT goes low for the remainder of the wordstring. LBLRCVD Label received output. A 250 nS (nominal) wide active high pulse is generated at the end of each error-free label word received. DATRCVD Data received output. A 250 nS (nominal) wide active high pulse is generated at the end of each data word received. Note that the error output must be examined to see if the data word contained a biphase encoding or parity error. ERROR Active high error output indicating the decoder has detected an error in a data word. For parity and biphase errors, the error output is sat at the same time as DATRCVD is asserted. A datasync error following a valid label or data word will set the error output up to 4 cycles of the RXCK clock (nominally 1uS) after LBLRCVD or DATRCVD is asserted. ERROR remains set until the next DATRCVD or LBLRCVD pulse. : t MT62901 ARINC 629 Encoder/Decoder Data Sheet - June 1992 Page 3 H i i

output enable. Active low input enables the tristate output buffers on the parallel data bua. Output data is valid 35nS after OEN is asserted (50pF load). The bus is high-Z 10nS after OEN is taken high. TO -T15 Parallel data bus. 115 is the most significant bit. When the OEN input is held low, decoder output data is valid 30nS after the leading edge of each LBERCVD and DATRCVD pulse and remains valid until the next LBLRCVD or DATRCVD pulse. BQ Bus Quiet - active high output. ‘This output is asserted six cycles of the RICK clock after the end of each label) or data word received (see timing diagram) and remains active for at least 2.5 bit times (1.25 micro sec. with 32 MHz RICK). After this time BQ is reset immediately activity is detected on the Bus (i.e. RXI not equal RXN). WDEHEN (available on 48 pin package only) This input has an internal high value pullup resistor. Tie this pin high for standard ARINC 629 operation. Pulling WDEHEN low enables a proprietry error detection function which is not compatible with the current issue of ARINC 629. BIPERR (available on 44 & 48 pin packages only) This output is set high as soon as a bi-phase encoding error is detected whilst receiving a dataword (NOT label). It will remain set for at least 6 cycles of RXCK (nominally 1.5uS) after DATRCVD is asserted at the end of the d@atavord containing the error. PARERR (available on 44 & 48 pin packages only) This output is set high at the same time as DATRCVD is asserted when the dataword contains a parity error. It will remain set for at least 6 cycles of RXCK (nominally 1.5uS). DSYNERR (available on 44 & 48 pin packages only) This output is set high if a word is immediately followed by an invalid datasync pattern The device continues to wonitor the bus for 2 bit tines after the end of the word and reports any illegal states. Note: under sone conditions this may indicate the preceeding word contained an error which could not be detected by parity or bi-phase checks. DSYNERR is asserted up to 4 cycles of RXCK (nominally 1uS) after LBLRCVD or DATRCVD is asserted and remains set until at least 6 cycles of RXCK (1.545) after the start of - DATRCVD or LBLRCVD. Note: BIPERR and DSYNERR together detect all cases of too few or too many bits in a word. WDERERR (available on 48 pin package only) Error output associated with the WDEHEN function. This output is not used for standard ARINC 629 operation. SALORERATION coneanc meaty Os Ts a | a aa. » ESE en | CN IEEE a. OO I a TRU aerae a arava wesenee I eee bie ay Serer ie ear ee i Ge eS : LT wel ABSOLUTE MAXIMUM RATINGS (a1) Voltages Relative to VSS=ov) Min. Maxe Units Supply Voltage (VDD) 70.3 7.0 v. I/P Voltage VSS-0.3 VDD+0.3 v. H 0/P Current Low — 15 BA, i O/P Current High — 15 mA. | Storage Temperature -65 +150 "cc I MT62901 ARINC 629 Encoder/Decoder Data Sheet - June 1992 Page 4 i we a j

RECOMMENDED OPERATING CONDITIONS ; Min pais Pa Max. Units Supply Voltage (vnD) 4.5 5.0 5.5 Vv. Case Temp. (Commercial) ° 25 70 "ca, Case Temp. (MIL & BS) “55 25 +125 "cc DC_CHARACTERISTICS Min. mM, Max. Units VDD supply current 10 20 BA. Low level I/P voltage oo 0.4 0.8 v. High level I/P voltage 2.0 2.4 — Vv. T/P current (ne pullup) 5 ~~ +5 BA. I/P current (pullup, Vin=0v) -35 ~112 =370 BA. Low level 0/P voltage -—- — 0.4 ve. High level 0/P voltage 2.4 won _ v. O/P current (Vout=2.4v) -- 74.0 “2.9 mA. O/P current (Vout=0.4v) 3.2 4.0 —_ mA. I/P capacitance 5 pr. I/O capacitance 10 pr. AC CHARACTERISTICS Timing parameters are specified for the following conditions unless otherwise stated: Recommended operating temperature range. Recommended operating voltage range. Output load capacitance SopF. Rising edge measurements made at Voh = 2.0v. Falling edge measurements made at Vol = 0.8v. ciCODER TinING 4b 2am max (200F Lose? Ligne Max (200F Loaad Liang nex (300F Leaa iss Max (300F Losa) N.S. The PRE-PRESYNC pulee starts seunchrenously on TXGO snd ands 3 clock cycles after the -ve XICK edee on which TXGO is detected. To Guarantes TXGO receenition in a specific clock cycle it should be stable from @nS before until 12n8 after the KICK -ve edee. RECOQER TIMING MIDOLE OF PARITY BIT ENO OF PARITY BIT + ’ ere NTU AALS i z { Te-18 previous Valve" SR5 Tabet! valve HI i i eee REE ee eee eee eee ' a : | 2508 “hae eset he in H i . lax. i te (300F Load) } 20nS Max. (SeeF Load + (3@eF Load) i N.G. RXI & RXN Are sampled on the -ve RICK edee. } Taming of DATRCUD & MONOAT ie identical to LBLRCUD & HONLEL. | BO will be set Lou uithin 22n8 ef anw activity (1.0. RXI # RYN ) on RXIZREN (30eF Load). t MT62901 ARINC 629 Encoder/Decoder Data Sheet - June 1992 Page 5 |

LASSIGNMENTS (40 Pin DIL Package) PIM_ASSIGNMENTS (48 Pin DIL Package) . RXI 21 T3 1 RICK 25 T3 RICK 22 T2 2 MONLEL 26 T2 MONLEL 23 Tl 3 PARERR 27 T1 MONDAT 24 «TO 4 BIPERR 28 «TO VDD (+5v) 25 VDD (+5v) s MONDAT 29 «TX ACTIVE VSS (Ov) 26 VSS (Ov) 6 VDD (+5v) 30 VOD (+5v) OEN 27 > ~DATRCVD 7 TXSTOPN 31 VSS (0v) ERROR 28 = LBLRCVD 8 WOEHEN 32 DATRCVD Tis 29 «BQ 9 OEN 33 LBLRCVD T14 30 PWRSTN 10 WDEHERR 34 BQ 713 31 0 Txo 11 ERROR 35 PWRSTN 712 32 0 TXN 120 °«T15 36 DSYNERR T11 33 XICK 13 T14 37 TXO T10 34 ‘'TXHB 140«T23 38° «=TXN Ts 35 NBUFFULL 1s T12 39 XICK 738 36 NLDBUFF 160-11 40 = TXEB 17 37 TXGO 17 T10 41 NBUFFOLL T6 38 TXLABEL 18 TS 42 VSS (Ov) TS 39 RXCK 19 VSS (Ov) 43 NLDBUFF TT 40 = -RXN 20 «8 44 TXGO 21 #77 45 TXLABEL 22. «76 46 © RXCK

23 TS 47 RXN

240¢~«*TAS 48 = RXI NLASSIGNMENTS (44 Pin Quad J-Lead Package) 1.670 RXI 23° «74 . = RICK 24 T3 im MONLBL 25 «2 PARERR 260-11 a | cate | BIPERR 27 «TO | MONDAT 28 VDD (+5v) —T wD rey) 3 DarRev> 40 PTW OIL CERAMIC PACKAGE LBLRY Tor view OEN 31 Bg ERROR 32) -PWRSTN - 715 33° DSYNERR othe S1.Bine T14 34 TXO . | f | T13 35 TXN ~ nen a 1 912 36 -XICK | . | sma 37 TXHB rate tS sftber vs.toee f

3 TIO 38 «© NBUFFULL | |

“99 39 VSS (Ov) cE aly =

3 VSS (Ov) 40 NLDBUFF an) 19

18 41 TXGO 44, PIN J-LEAD PACKAGE 40 PIN OIL CERAMIC PacKeoe > 97 42 TXLABEL tor urew Tor vtew : T6 43 RXCK > TS 44° RXN RDERING INFORMATION he table below gives the MCE part number for each package/screening flow option. Package 48 pin ceramic DIL 44 pin Cerquad J iead | wrszsoisz9 (| wrezo0isz2___| wrezaoisz4 | 40 pin ceramic DIL | re Alexandra Way. Ashchurch. Tewkesbury Gloucestershire GL20 8TB Yo Telephone Tewkesbury (0684) 297777 ; } . Telex 437233 Fax (0684) 209435 | abextaryat 9 9 V.AT. Reg. No, 225 6019 77 | ‘ths industries Pubuc Limned Company Registered in England 1047586 | MT62901 ARINC 629 Encoder/Decoder Data Sheet - June 1992 Page 6 |