MT5VDDT1672A

MT5VDDT3272AG MICRON | Alldatasheet

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PDF: 09005aef808143d9/Source: 09005aef806e1c40 Micron Technology, Inc., reserves the right to change products or specifications without notice. DD5C8_16_32x72A.fm - Rev. F 10/07 EN 1 ©2002 Micron Technology, Inc. All rights reserved. DDR SDRAM UDIMM MT5VDDT872A – 64MB1 MT5VDDT1672A – 128MB2 MT5VDDT3272A – 256MB2 For component data sheets, refer to Micron’s Web site: www.micron.com

• 184-pin, unbuffered dual in-line memory module (UDIMM)  Fast data transfer rates: PC2100, PC2700, or PC3200  64MB (8 Meg x 72), 128MB (16 Meg x 72), and 256MB (32 Meg x 72)  Supports ECC error detection and correction DD = VDDQ = +2.5V (-40B: VDD = VDDQ = +2.6V) V DDSPD = +2.3V to +3.6V  2.5V I/O (SSTL_2-compatible)  Internal, pipelined double data rate (DDR) 2n-prefetch architecture  Bidirectional data strobe (DQS) transmitted/ received with data—that is, source-synchronous data capture  Differential clock inputs (CK and CK#)  Multiple internal device banks for concurrent operation  Single rank  Selectable burst lengths (BL): 2, 4, or 8  Auto precharge option  Auto refresh and self refresh modes: 64MB = 15.625µs and 128MB, 256MB = 7.8125µs maximum average periodic refresh interval  Serial presence-det ect (SPD) with EEPROM  Selectable CAS latency (CL) for maximum compatibility  Gold edge contacts Figure 1: 184-Pin UDIMM (MO-206 R/C C) Notes: 1. End of life. 2. Not recommended for new designs. 3. Contact Micron for industrial temperature module offerings. Options Marking  Operating temperature 3 – Commercial (0°C ≤ TA ≤ +70°C) None – Industrial (–40°C ≤ TA ≤ +85°C) I P a c k a g e – 184-pin DIMM (standard) G – 184-pin DIMM (Pb-free) Y  Memory clock, speed, CAS latency – 5.0ns (200 MHz), 400 MT/s, CL = 3.0 -40B – 6.0ns (167 MHz), 333 MT/s, CL = 2.5 -335 – 7.5ns (133 MHz), 266 MT/s, CL = 2.0 -262 – 7.5ns (133 MHz), 266 MT/s, CL = 2.0 -26A – 7.5ns (133 MHz), 266 MT/s, CL = 2.5 -265 PCB height: 31.75mm (1.25in) Notes: 1. The values of tRCD and tRP for -335 modules show 18ns to align with industry specifications; actual DDR SDRAM device specifications are 15ns. Table 1: Key Timing Parameters Speed Grade Industry Nomenclature Data Rate (MT/s) tRCD (ns) tRP (ns) tRC (ns) NotesCL = 3 CL = 2.5 CL = 2 -40B PC3200 400 333 266 15 15 55 -335 PC2700 – 333 266 18 18 60 1 -262 PC2100 – 266 266 15 15 60 -26A PC2100 – 266 266 20 20 65 -265 PC2100 – 266 200 20 20 65

PDF: 09005aef808143d9/Source: 09005aef806e1c40 Micron Technology, Inc., reserves the right to change products or specifications without notice. DD5C8_16_32x72A.fm - Rev. F 10/07 EN 2 ©2002 Micron Technology, Inc. All rights reserved. 64MB, 128MB, 256MB (x72, ECC, SR) 184-Pin DDR SDRAM UDIMM Notes: 1. Data sheets for the base device s can be found on Micron’s Web site. 2. All part numbers end with a two-place code (not shown) that designates component and PCB revisions. Consult factory for current revision codes. Example: MT5VDDT1672AY-335F3. Table 2: Addressing Parameter 64MB 128MB 256MB Refresh count 4K 8K 8K Row address 4K (A0–A11) 8K (A0–A12) 8K (A0–A12) Device bank address 4 (BA0, BA1) 4 (BA0, BA1) 4 (BA0, BA1) Device configuration 128Mb (8 Meg x 16) 256Mb (16 Meg x 16) 512Mb (32 Meg x 16) Column address 512 (A0–A8) 512 (A0–A8) 1K (A0–A9) Module rank address 1 (S0#) 1 (S0#) 1 (S0#) Table 3: Part Numbers and Timing Parameters – 64MB Modules Base device: MT46V8M16,1 128Mb DDR SDRAM Part Number2 Module Density Configuration Module Bandwidth Memory Clock/ Data Rate Clock Cycles (CL-tRCD-tRP) MT5VDDT872AG-335__ 64MB 8 Meg x 72 2.7 GB/s 6.0ns/333 MT/s 2.5-3-3 MT5VDDT872AG-262__ 64MB 8 Meg x 72 2.1 GB/s 7.5ns/266 MT/s 2-2-2 MT5VDDT872AG-26A__ 64MB 8 Meg x 72 2.1 GB/s 7.5ns/266 MT/s 2-3-3 MT5VDDT872AG-265__ 64MB 8 Meg x 72 2.1 GB/s 7.5ns/266 MT/s 2.5-3-3 Table 4: Part Numbers and Timing Parameters – 128MB Modules Base device: MT46V16M16,1 256Mb DDR SDRAM Part Number2 Module Density Configuration Module Bandwidth Memory Clock/ Data Rate Clock Cycles (CL-tRCD-tRP) MT5VDDT1672AG-40B__ 128MB 16 Meg x 72 3.2 GB/s 5.0ns/400 MT/s 3-3-3 MT5VDDT1672AG-335__ 128MB 16 Meg x 72 2.7 GB/s 6.0ns/333 MT/s 2.5-3-3 MT5VDDT1672AY-335__ 128MB 16 Meg x 72 2.7 GB/s 6.0ns/333 MT/s 2.5-3-3 MT5VDDT1672AG-262__ 128MB 16 Meg x 72 2.1 GB/s 7.5ns/266 MT/s 2-2-2 MT5VDDT1672AG-26A__ 128MB 16 Meg x 72 2.1 GB/s 7.5ns/266 MT/s 2-3-3 MT5VDDT1672AG-265__ 128MB 16 Meg x 72 2.1 GB/s 7.5ns/266 MT/s 2.5-3-3 Table 5: Part Numbers and Timing Parameters – 256MB Modules Base device: MT46V32M16,1 512Mb DDR SDRAM Part Number2 Module Density Configuration Module Bandwidth Memory Clock/ Data Rate Clock Cycles (CL-tRCD-tRP) MT5VDDT3272AG-40B__ 256MB 32 Meg x 72 3.2 GB/s 5.0ns/400 MT/s 3-3-3 MT5VDDT3272AY-40B__ 256MB 32 Meg x 72 3.2 GB/s 5.0ns/400 MT/s 3-3-3 MT5VDDT3272AG-335__ 256MB 32 Meg x 72 2.7 GB/s 6.0ns/333 MT/s 2.5-3-3 MT5VDDT3272AY-335__ 256MB 32 Meg x 72 2.7 GB/s 6.0ns/333 MT/s 2.5-3-3 MT5VDDT3272AG-265__ 256MB 32 Meg x 72 2.1 GB/s 7.5ns/266 MT/s 2.5-3-3

PDF: 09005aef808143d9/Source: 09005aef806e1c40 Micron Technology, Inc., reserves the right to change products or specifications without notice. DD5C8_16_32x72A.fm - Rev. F 10/07 EN 3 ©2002 Micron Technology, Inc. All rights reserved. 64MB, 128MB, 256MB (x72, ECC, SR) 184-Pin DDR SDRAM UDIMM Pin Assignments and Descriptions Pin Assignments and Descriptions Table 6: Pin Assignments 184-Pin DDR UDIMM Front 184-Pin DDR UDIMM Back Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol 1V REF 24 DQ17 47 DQS8 70 V DD 93 V SS 116 V SS 139 V SS 162 DQ47

2 DQ0 25 DQS2 48 A0 71 NC 94 DQ4 117 DQ21 140 DM8/

3V SS 26 V SS 49 CB2 72 DQ48 95 DQ5 118 A11 141 A10 164 V DDQ

4 DQ1 27 A9 50 V SS 73 DQ49 96 V DDQ 119 DM2/

142 CB6 165 DQ52

5D Q S 0 2 8 D Q 1 8 5 1C B 37 4 V SS 97 DM0/ DQS9

120 V DD 143 V DDQ 166 DQ53

6 DQ2 29 A7 52 BA1 75 CK2# 98 DQ6 121 DQ22 144 CB7 167 NC

7V DD 30 V DDQ 53 DQ32 76 CK2 99 DQ7 122 A8 145 V SS 168 V DD

8 DQ3 31 DQ19 54 V DDQ7 7V DDQ 100 V SS 123 DQ23 146 DQ36 169 DM6/

9 NC 32 A5 55 DQ33 78 DQS6 101 NC 124 V SS 147 DQ37 170 DQ54

10 NC 33 DQ24 56 DQS4 79 DQ50 102 NC 125 A6 148 V DD 171 DQ55

11 V SS 34 V SS 57 DQ34 80 DQ51 103 NC 126 DQ28 149 DM4/

172 V DDQ

12 DQ8 35 DQ25 58 V SS 81 V SS 104 V DDQ 127 DQ29 150 DQ38 173 NC

13 DQ9 36 DQS3 59 BA0 82 NC 105 DQ12 128 V DDQ 151 DQ39 174 DQ60

14 DQS1 37 A4 60 DQ35 83 DQ56 106 DQ13 129 DM3/

152 V SS 175 DQ61

15 V DDQ3 8 V DD 61 DQ40 84 DQ57 107 DM1/

130 A3 153 DQ44 176 V SS

16 CK1 39 DQ26 62 V DDQ8 5 V DD 108 V DD 131 DQ30 154 RAS# 177 DM7/

17 CK1# 40 DQ27 63 WE# 86 DQS7 109 DQ14 132 V SS 155 DQ45 178 DQ62

18 V SS 41 A2 64 DQ41 87 DQ58 110 DQ15 133 DQ31 156 V DDQ 179 DQ63

19 DQ10 42 V SS 65 CAS# 88 DQ59 111 NC 134 CB4 157 S0# 180 V DDQ

20 DQ11 43 A1 66 V SS 89 V SS 112 V DDQ 135 CB5 158 NC 181 SA0

21 CKE0 44 CB0 67 DQS5 90 NC 113 NC 136 V DDQ 159 DM5/

182 SA1

22 V DDQ 45 CB1 68 DQ42 91 SDA 114 DQ20 137 CK0 160 V SS 183 SA2

23 DQ16 46 V DD 69 DQ43 92 SCL 115 A12 138 CK0# 161 DQ46 184 V DDSPD

PDF: 09005aef808143d9/Source: 09005aef806e1c40 Micron Technology, Inc., reserves the right to change products or specifications without notice. DD5C8_16_32x72A.fm - Rev. F 10/07 EN 4 ©2002 Micron Technology, Inc. All rights reserved. 64MB, 128MB, 256MB (x72, ECC, SR) 184-Pin DDR SDRAM UDIMM Pin Assignments and Descriptions Table 7: Pin Descriptions Symbol Type Description A0–A12 Input Address inputs: Provide the row address for ACTIVE commands, and the column address and auto precharge bit (A10) for READ/WRITE commands, to select one location out of the memory array in the respective device bank. A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one device bank (A10 LOW, device bank selected by BA0, BA1) or all device banks (A10 HIGH). The address inputs also provide the op-code during a MODE REGISTER SET command. BA0 and BA1 define which mode register (mode register or extended mode register) is loaded during the LOAD MODE REGISTER command. A0–A11 (64MB) and A0–A12 (128MB, 256MB). BA0, BA1 Input Bank address: BA0 and BA1 define to which device bank an ACTIVE, READ, WRITE, or PRECHARGE command is being applied. CK0, CK0#, CK1, CK1#, CK2, CK2# Input Clock: CK and CK# are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and the negative edge of CK#. Output data (DQ and DQS) is referenced to the crossings of CK and CK#. CKE1 Input Clock enable: CKE (registered HIGH) activates and CKE (registered LOW) deactivates the internal clock, input buffers, and output drivers. DM0–DM8 (DQS9–DQS17) Input Data input mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH, along with that input data, during a write access. DM is sampled on both edges of DQS. Although DM pins are input-only, the DM loading is designed to match that of DQ and DQS pins. RAS#, CAS#, WE# Input Command inputs: RAS#, CAS#, and WE# (along with S#) define the command being entered. S0# Input Chip selects: S# (registered LOW) enables and (registered HIGH) disables the command decoder. SA0–SA2 Input Presence-detect address inputs: These pins are used to configure the presence-detect device. SCL Input Serial clock for presence-detect: SCL is used to synchronize the presence- detect data transfer to and from the module. CB0–CB7 I/O Check bits. DQ0–DQ63 I/O Data input/output: Data bus. DQS0–DQS7 I/O Data strobe: Output with read data, input with write data. DQS is edge- aligned with read data, center-aligned with write data. Used to capture data. SDA I/O Serial presence-detect data: SDA is a bidirectional pin used to transfer addresses and data into and out of the presence-detect portion of the module. V VDDSPD Supply Serial EEPROM positive power supply: +2.3V to +3.6V. VREF Supply SSTL_2 reference voltage (VDD/2). VSS Supply Ground. NC – No connect: These pins are not connected on the module.

PDF: 09005aef808143d9/Source: 09005aef806e1c40 Micron Technology, Inc., reserves the right to change products or specifications without notice. DD5C8_16_32x72A.fm - Rev. F 10/07 EN 5 ©2002 Micron Technology, Inc. All rights reserved. 64MB, 128MB, 256MB (x72, ECC, SR) 184-Pin DDR SDRAM UDIMM Functional Block Diagram Functional Block Diagram Figure 2: Functional Block Diagram DM3/DQS12 DM2/DQS11 DQ0 DQ1 DQ2 DQ3 DM0/DQS9 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ DQ DQ DQ DQ12 DQ13 DQ14 DQ15 DQ DQ DQ DQ DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ40 DQ41 DQ42 DQ43 DM4/DQS13 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DM1/DQS10 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DM5/DQS14 DM6/DQS15 DM7/DQS16 S0#S0# S0# DQ DQ DQ DQ DQ DQ DQ DQ LDM UDM S0# BA0–BA1 RAS# CAS# WE# CKE0 DDR SDRAM CK1 CK2 DDR SDRAM U1, U2 DDR SDRAM U4, U5 DQS0 UDQS DQS1 LDQS DQS2 DQS3 DQS7 DQS6 DQS5 DQS4 CK2# CK1# A0–A11/A12 DDR SDRAM DDR SDRAM DDR SDRAM DDR SDRAM DDR SDRAM S0# SA0 SPD EEPROM SDA SA1 SA2 WP SCL VREF VSS DDR SDRAM DDR SDRAM VDDSPD SPD EEPROM DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ LDM UDM UDQS LDQS DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ LDM UDM UDQS LDQS DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ LDM UDM UDQS LDQS VDD/VDDQ DDR SDRAM DM8/DQS17 CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 V DD S0# VSS DQS8 DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ LDM UDM UDQS LDQS NC NC NC NC NC NC NC NC CK0 DDR SDRAM U3CK0# VSS A0–A11/A12

PDF: 09005aef808143d9/Source: 09005aef806e1c40 Micron Technology, Inc., reserves the right to change products or specifications without notice. DD5C8_16_32x72A.fm - Rev. F 10/07 EN 6 ©2002 Micron Technology, Inc. All rights reserved. 64MB, 128MB, 256MB (x72, ECC, SR) 184-Pin DDR SDRAM UDIMM General Description General Description The MT5VDDT872A, MT5VDDT1672A, and MT5VDDT3272A are high-speed CMOS, dynamic random access 64MB, 128MB, and 256MB memory modules organized in a x72 configuration. These modules use DDR SDRAM devices with four internal banks. DDR SDRAM modules use a double data rate architecture to achieve high-speed opera- tion. The double data rate architecture is essentially a 2n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for DDR SDRAM modules effectively consists of a single 2n-bit-wide, one-clock-cycle data transfer at the internal DRAM core and two corre- sponding n-bit-wide, one-half-clock-cycle data transfers at the I/O pins. A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in data capture at the receiver. DQS is a strobe transmitted by the DDR SDRAM during READs and by the memory controller during WRITEs. DQS is edge-aligned with data for READs and center-aligned with data for WRITEs. DDR SDRAM modules operate from differential clock inputs (CK and CK#); the crossing of CK going HIGH and CK# going LOW will be referred to as the positive edge of CK. Commands are registered at every positive edge of CK. Input data is registered on both edges of DQS, and output data is referenced to both edges of DQS, as well as to both edges of CK. Serial Presence-Detect Operation DDR SDRAM modules incorporate serial presence-detect (SPD). The SPD function is implemented using a 2,048-bit EEPROM. This nonvolatile storage device contains 256 bytes. The first 128 bytes are programmed by Micron to identify the module type and various SDRAM organizations and timing parameters. The remaining 128 bytes of storage are available for use by the customer. System READ/WRITE operations between the master (system logic) and the slave EEPROM device (DIMM) occur via a standard I bus using the DIMM’ s SCL (clock) and SDA (data) signals, together with SA (2:0), which provide eight unique DIMM/EEPROM addresses. Write protect (WP) is tied to VSS on the module, permanently disabling hardware write protect.

PDF: 09005aef808143d9/Source: 09005aef806e1c40 Micron Technology, Inc., reserves the right to change products or specifications without notice. DD5C8_16_32x72A.fm - Rev. F 10/07 EN 7 ©2002 Micron Technology, Inc. All rights reserved. 64MB, 128MB, 256MB (x72, ECC, SR) 184-Pin DDR SDRAM UDIMM Electrical Specifications Electrical Specifications Stresses greater than those listed in Table 8 may cause permanent damage to the module. This is a stress rating only, and functional operation of the module at these or any other conditions outside those indicated on the device data sheet is not implied. Exposure to absolute maximum rating conditions for extended periods may adversely affect reliability. Notes: 1. For further information, refer to technical note TN-00-08: “Thermal Applications,” available on Micron’s Web site. Input Capacitance Micron encourages designers to simulate the performance of the module to achieve optimum values. Simulations are significantly more accurate and realistic than a gross estimation of module capacitance when inductance and delay parameters associated with trace lengths are used in simulations. JEDEC modules are currently designed using simulations to close timing budgets. Component AC Timing and Operating Conditions Recommended AC operating conditions are given in the DDR component data sheets. Component specifications are available on Micron’ s Web site. Module speed grades correlate with component speed grades, as shown in Table 9. Table 8: Absolute Maximum Ratings Symbol Parameter Min Max Units VDD/VDDQ VDD/VDDQ supply voltage relative to VSS –1.0 +3.6 V VIN, VOUT Voltage on any pin relative to VSS –0.5 +3.2 V II Input leakage current; Any input 0V ≤ VIN ≤ VDD; VREF input 0V ≤ VIN ≤ 1.35V (All other pins not under test = 0V) Address inputs, RAS#, CAS#, WE#, BA, S#, CKE –10 +10 µA CK0, CK0# –2 +2 CK1, CK1#, CK2, CK2# –4 +4 DM –2 +2 IOZ Output leakage current; 0V ≤ VOUT ≤ VDDQ; DQ are disabled DQ, DQS –5 +5 µA TA DRAM ambient operating temperature1 Commercial 0+ 7 0 ° C Industrial –40 +85 °C Table 9: Module and Component Speed Grades Module Speed Grade Component Speed Grade -40B -5B -335 -6 -262 -75E -26A -75Z -265 -75

PDF: 09005aef808143d9/Source: 09005aef806e1c40 Micron Technology, Inc., reserves the right to change products or specifications without notice. DD5C8_16_32x72A.fm - Rev. F 10/07 EN 8 ©2002 Micron Technology, Inc. All rights reserved. 64MB, 128MB, 256MB (x72, ECC, SR) 184-Pin DDR SDRAM UDIMM Electrical Specifications IDD Specifications Table 10: I DD Specifications and Conditions – 64MB Values are shown for the MT46V8M16 DDR SDRAM only and are computed from values specified in the 128Mb (8 Meg x 16) component data sheet Parameter/Condition Symbol -335 -262 -26A/ -265 Units Operating one bank active-precharge current: tRC = tRC (MIN); tCK = tCK (MIN); DQ, DM, and DQS inputs changing once per clock cycle; Address and control inputs changing once every two clock cycles IDD0 625 575 550 mA Operating one bank active-read-precharge current: BL = 2; tRC = tRC (MIN); tCK = tCK (MIN); IOUT = 0mA; Address and control inputs changing once per clock cycle IDD1 675 675 625 mA Precharge power-down standby current: All device banks idle; Power- down mode; tCK = tCK (MIN); CKE = LOW IDD2P 15 15 15 mA Idle standby current: CS# = HIGH; All device banks idle; tCK = tCK (MIN); CKE = HIGH; Address and other control inputs changing once per clock cycle; VIN =V REF for DQ, DQS, and DM IDD2F 225 225 200 mA Active power-down standby current: One device bank active; Power- down mode; tCK = tCK (MIN); CKE = LOW IDD3P 125 125 100 mA Active standby current: CS# = HIGH; CKE = HIGH; One device bank active; tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle IDD3N 250 250 225 mA Operating burst read current: BL = 2; Continuous burst reads; One device bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); IOUT =0 m A IDD4R 725 700 675 mA Operating burst write current: BL = 2; Continuous burst writes; One device bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle IDD4W 775 675 650 mA Auto refresh current tREFC = tRFC (MIN) IDD5 1,325 1,250 1,250 mA tREFC = 15.625µs IDD5A 25 25 25 mA Self refresh current: CKE ≤ 0.2V IDD6 1 51 51 0 m A Operating bank interleave read current: Four device bank interleaving reads; BL = 4 with auto precharge; tRC = tRC (MIN); tCK = tCK (MIN); Address and control inputs change only during active READ or WRITE commands IDD7 1,925 1,875 1,875 mA

PDF: 09005aef808143d9/Source: 09005aef806e1c40 Micron Technology, Inc., reserves the right to change products or specifications without notice. DD5C8_16_32x72A.fm - Rev. F 10/07 EN 9 ©2002 Micron Technology, Inc. All rights reserved. 64MB, 128MB, 256MB (x72, ECC, SR) 184-Pin DDR SDRAM UDIMM Electrical Specifications Table 11: I DD Specifications and Conditions – 128MB Values are shown for the MT46V16M16 DDR SDRAM only and are computed from values specified in the 256Mb (16 Meg x 16) component data sheet Parameter/Condition Symbol -40B -335 -262 -26A/ -265 Units Operating one bank active-precharge current: tRC = tRC (MIN); tCK = tCK (MIN); DQ, DM, and DQS inputs changing once per clock cycle; Address and control inputs changing once every two clock cycles IDD0 675 625 625 600 mA Operating one bank active-read-precharge current: BL = 2; tRC = tRC (MIN); tCK = tCK (MIN); IOUT = 0mA; Address and control inputs changing once per clock cycle IDD1 925 900 850 775 mA Precharge power-down standby current: All device banks idle; Power-down mode; tCK = tCK (MIN); CKE = LOW IDD2P 20 20 20 20 mA Idle standby current: CS# = HIGH; All device banks idle; tCK = tCK (MIN); CKE = HIGH; Address and other control inputs changing once per clock cycle; VIN =V REF for DQ, DQS, and DM IDD2F 300 250 225 225 mA Active power-down standby current: One device bank active; Power-down mode; tCK = tCK (MIN); CKE = LOW IDD3P 200 150 125 125 mA Active standby current: CS# = HIGH; CKE = HIGH; One device bank active; tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle IDD3N 350 300 250 250 mA Operating burst read current: BL = 2; Continuous burst reads; One device bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); IOUT =0 m A IDD4R 1,300 1,100 925 925 mA Operating burst write current: BL = 2; Continuous burst writes; One device bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle IDD4W 1,075 975 800 800 mA Auto refresh current tREFC = tRFC (MIN) IDD5 1,300 1,275 1,175 1,175 mA tREFC = 7.8125µs IDD5A 30 30 30 30 mA Self refresh current: CKE ≤ 0.2V IDD6 2 02 02 02 0 m A Operating bank interleave read current: Four device bank interleaving reads; BL = 4 with auto precharge; tRC = tRC (MIN); tCK = tCK (MIN); Address and control inputs change only during active READ or WRITE commands IDD7 2,550 2,200 1,900 1,900 mA

PDF: 09005aef808143d9/Source: 09005aef806e1c40 Micron Technology, Inc., reserves the right to change products or specifications without notice. DD5C8_16_32x72A.fm - Rev. F 10/07 EN 10 ©2002 Micron Technology, Inc. All rights reserved. 64MB, 128MB, 256MB (x72, ECC, SR) 184-Pin DDR SDRAM UDIMM Electrical Specifications Table 12: I DD Specifications and Conditions – 256MB Values are shown for the MT46V32M16 DDR SDRAM only and are computed from values specified in the 512Mb (32 Meg x 16) component data sheet Parameter/Condition Symbol -40B -335 -265 Units Operating one bank active-precharge current: tRC = tRC (MIN); tCK = tCK (MIN); DQ, DM, and DQS inputs changing once per clock cycle; Address and control inputs changing once every two clock cycles IDD0 775 650 575 mA Operating one bank active-read-precharge current: BL = 2; tRC = tRC (MIN); tCK = tCK (MIN); IOUT = 0mA; Address and control inputs changing once per clock cycle IDD1 975 800 725 mA Precharge power-down standby current: All device banks idle; Power- down mode; tCK = tCK (MIN); CKE = LOW IDD2P 25 25 25 mA Idle standby current: CS# = HIGH; All device banks idle; tCK = tCK (MIN); CKE = HIGH; Address and other control inputs changing once per clock cycle; VIN =V REF for DQ, DQS, and DM IDD2F 275 225 200 mA Active power-down standby current: One device bank active; Power- down mode; tCK = tCK (MIN); CKE = LOW IDD3P 225 175 150 mA Active standby current: CS# = HIGH; CKE = HIGH; One device bank active; tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle IDD3N 300 250 225 mA Operating burst read current: BL = 2; Continuous burst reads; One device bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); IOUT =0 m A IDD4R 1,050 825 725 mA Operating burst write current: BL = 2; Continuous burst writes; One device bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle IDD4W 1,075 975 675 mA Auto refresh current tREFC = tRFC (MIN) IDD5 1,725 1,450 1,400 mA tREFC = 7.8125µs IDD5A 55 50 50 mA Self refresh current: CKE ≤ 0.2V IDD6 3 02 52 5 m A Operating bank interleave read current: Four device bank interleaving reads; BL = 4 with auto precharge; tRC = tRC (MIN); tCK = tCK (MIN); Address and control inputs change only during active READ or WRITE commands IDD7 2,400 2,025 1,750 mA

PDF: 09005aef808143d9/Source: 09005aef806e1c40 Micron Technology, Inc., reserves the right to change products or specifications without notice. DD5C8_16_32x72A.fm - Rev. F 10/07 EN 11 ©2002 Micron Technology, Inc. All rights reserved. 64MB, 128MB, 256MB (x72, ECC, SR) 184-Pin DDR SDRAM UDIMM Serial Presence-Detect Serial Presence-Detect Notes: 1. To avoid spurious start and stop conditions, a minimum delay is placed between SCL = 1 and the falling or rising edge of SDA. 2. This parameter is sampled. 3. For a restart condition or following a WRITE cycle. 4. The SPD EEPROM WRITE cycle time ( tWRC) is the time from a valid stop condition of a write sequence to the end of the EEPROM internal ERASE/PROGRAM cycle. During the WRITE cycle, the EEPROM bus interface circuit is disabled, SDA remains HIGH due to pull-up resis- tance, and the EEPROM does not respond to its slave address. Serial Presence-Detect Data For the latest serial presence-detect data, refer to Micron’ s SPD page: www.micron.com/SPD. Table 13: Serial Presence-Detec t EEPROM DC Operating Conditions Parameter/Condition Symbol Min Max Units Supply voltage VDDSPD 2.3 3.6 V Input high voltage: Logic 1; All inputs VIH VDDSPD × 0.7 V DDSPD + 0.5 V Input low voltage: Logic 0; All inputs VIL –1.0 V DDSPD × 0.3 V Output low voltage: IOUT = 3mA VOL –0 . 4 V Input leakage current: VIN = GND to VDD ILI –1 0 µ A Output leakage current: VOUT = GND to VDD ILO –1 0 µ A Standby current: SCL = SDA = VDD - 0.3V; All other inputs = VSS or VDD ISB –3 0 µ A Power supply current: SCL clock frequency = 100 kHz ICC –2 . 0 m A Table 14: Serial Presence-Detec t EEPROM AC Operating Conditions Parameter/Condition Symbol Min Max Units Notes SCL LOW to SDA data-out valid tAA 0.2 0.9 µs 1 Time the bus must be free before a new transition can start tBUF 1.3 – µs Data-out hold time tDH 200 – ns SDA and SCL fall time tF – 300 ns 2 Data-in hold time tHD:DAT 0 – µs Start condition hold time tHD:STA 0.6 – µs Clock HIGH period tHIGH 0.6 – µs Noise suppression time constant at SCL, SDA inputs tI– 5 0 n s Clock LOW period tLOW 1.3 – µs SDA and SCL rise time tR– 0 . 3 µ s2 SCL clock frequency fSCL – 400 kHz Data-in setup time tSU:DAT 100 – ns Start condition setup time tSU:STA 0.6 – µs 3 Stop condition setup time tSU:STO 0.6 – µs WRITE cycle time tWRC – 10 ms 4

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 prodmktg@micron.com www.micron.com Customer Comment Line: 800-932-4992 Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. 64MB, 128MB, 256MB (x72, ECC, SR) 184-Pin DDR SDRAM UDIMM Module Dimensions PDF: 09005aef808143d9/Source: 09005aef806e1c40 Micron Technology, Inc., reserves the right to change products or specifications without notice. DD5C8_16_32x72A.fm - Rev. F 10/07 EN 12 ©2002 Micron Technology, Inc. All rights reserved. Module Dimensions Figure 3: 184-Pin DDR UDIMM Notes: 1. All dimensions are in millimeters (i nches); MAX/MIN or typical (TYP) where noted. 2. The dimensional diagram is fo r reference only. Refer to the JEDEC MO document for addi- tional design dimensions. U1 U2 U4 U5 No components this side of module 31.90 (1.256) 31.60 (1.244) 17.78 (0.70) TYP 2.0 (0.079) R (4X) Pin 92 Front view Back view 1.37 (0.054) 1.17 (0.046) 133.50 (5.256) 133.20 (5.244) 10.0 (0.394) TYP 3.18 (0.125) MAX Pin 1 2.5 (0.098) D (2X) 2.31 (0.091) TYP 6.35 (0.25) TYP 120.65 (4.75) 1.27 (0.05) TYP TYP 0.9 (0.035) R 64.77 (2.55) TYP 49.53 (1.95) TYP Pin 184 Pin 93 1.0 (0.039) TYP 73.28 (2.88) TYP 3.8 (0.15) TYP