MT5C64K16A13A MICRON | Alldatasheet

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No SSSSSSssSsSSSSSSSSSSSSSSSSSSSSSSSSSSSSsssss 128K x 8, 64K x 16 oo SSSeSSSSSSSSSSSSSSe

FEATURES

  • Single +3.3V or +5V power supply DIE OUTLINE (Top View) * 5V tolerant I/O * Individual byte controls for both READ and WRITE cycles 3303 3302 * High-performance, low-power, CMOS double-metal s_3 2 ma) 2 process cao a) + Allinputs and outputs are TTL-compatible as}0 ol2s GENERAL PHYSICAL SPECIFICATIONS iad bad bd bl * Wafer thickness = 18.5 mils +0.5 mils * Backside wafer surface of polished bare silicon 70 Ol} * Typical metalization thickness 10K angstroms for the top level of metalization iad ed ale * Typical lower-level metal thickness is 5.5K angstroms 210 ole * Metalization composition: 99.5% Al and 0.5% Cu over titanium elo ole + Typical topside passivation 6K angstroms phospho- DIE DATA BASE $13A rous doped oxide with 6K angstroms of nitride over alg 3/2 oxide 8] g|2 * Typical passivation openings: 5.1 x 5.1 mil 2/8 RY 130 x 130 ym “jo a)" . alo 16 OPTIONS ORDER NUMBER ° + Speed probing* 3.3V 5v alo Of1s No speed probing none none 12ns access n/a -12* “re al ia 15ns access -15* -15* ela ‘3 20ns access 20% -20 9 25ns access 25 n/a F s/o O}2 * Form Die D s/o oj. Wafer (6" wafer) Ww fo.o000000a0 cao * Testing levels ee Standard probe cl Speed probe c2 “Refer to “S| Probing" secti of this data sheet. Speed desi ite =. Refer to “Die Testing Procedures” section of this data sheet. 5.842 x 12.725 wm Available as C2 level product only. ‘See Bond Pad Location and Identification Table. ORDER INFORMATION ; KAM Gan MTSL Ceakelenasi3¢ | pronvers | [ ronw | + 64K x16 (+3.3V) MTSLC64K16D4S13A proouet® || oaragase ||_romm || "Esra |[ seeco | * 128K x8 (45V) MTSC128K8A1S13A + 128Kx8 (43.3V) MTSLC128K8D4S13A MT5LC64K16D4S13ADC2-15 S134 1 Mion Semonductr, le, reserves Ihe night fo change products spectators wind pote. Rev ae ‘oe mien Semcon Cenc ncnnnnen

Micron has established three testing levels for die prod- level, the C2-level die has not received burn-in and there- ucts. Most Micron products are tested to Standard Probe fore is still subject to infant mortality failures. (CI) level. Selected products are available at Speed Probe (C2) level. Known Good Die (C3) level product is available KNOWN GOOD DIE (C3) on selected products as market demand dictates. Level C2 Inorder toprovide the customer with fully warranted die and C3 products are designed to provide customers with product, Micron has developed a Known Good Die process improved yields over C1. designed to provide customers with die products of equal quality and reliability to packaged product. Micron’s STANDARD PROBE (C1) KGD"=" process allows Micron to fully test and burn-in die Micron probes wafers at a temperature with limits product. guardbanded to assure product performance from 0°C to 70°C on Micron’s standard package. Since the package FUNCTIONAL SPECIFICATIONS environment is not within Micron’s control, the user must Please refer to the packaged product data sheets found in determine the necessary heat sinking requirements to en- the applicable Micron data book, for functional and para- sure that the junction die temperature remains within speci- metric specifications. The specifications are provided for fied limits. A high voltage functional stress test will be reference only on C1-and C2-level die product. OnC2-level performed at probe to assure minimum junction break- product 'AA is guaranteed. C3-level product is warranted down integrity. Ves (substrate bias voltage) is a forced to the data sheet. condition at wafer probe. Wafer probe consists of various functional and paramet- BONDING INSTRUCTIONS tic tests of each die. Test patterns, timing, voltage margins, The $13A SRAM die has 52 bond pads. Refer to the bond limits and test sequence are determined by individual pad location and identification table for a complete list of product yields and reliability data. bond pads and coordinates. Micron retains a wafer map of each wafer as part of the The S13A SRAM die has an internal substrate bias gen- probe records along with a lot summary of wafer yields for erator for normal operation, bond pad 6 is used for manu- each lot probed. Micron reserves the right to change the facturing tests only. Normal bonding leaves bond pad 6 probe program at any time to improve the reliability, pack- open (not bonded). Micron recommends using,a bond wire aged device yield or performance of the product. on each Vec and Vss bond pad for improved noise immu- nity. It is important that the back of the die be kept isolated SPEED PROBE (C2) from any other devices sharing a common package or In addition to the testing performed at Standard Probe substrate, since the die substrate is internally driven to a (C1), Micron also offers Speed Probe (C2). Micron’s Hot negative voltage. Chuck Speed Probe assures the speed performance of die The 1 Meg SRAM device operates from a single +5V or products for the fastest speed grades. Although this testing 3.3V power supply and all inputs and outputs are fully level may increase the yield a customer may see over Cl- TTL- compatible. fer 2 Ne NO ee 8 cy Seiconacta KGO™ 6 auscemath of Mason Semcnduca Ine ee

BOND PAD LOCATION AND IDENTIFICATION TABLE es a 2 | DIE OUTLINE (Top View) [seg cate | we ete ce IMTSLC64K16D4S13A| MTSLC128K8D4S13A. INCHES MICRONS Ca] oe Tar 0.000 F 0.000 | o00 000 | 33 3 93 2 [3 [as [a6 | 0.000 | 0.040 [000 | fore _| oo 8 oo 9 [4 [as as 0.000 | 0.060 | 090 [ 1.524 [5 [pny as 0.000 | -0.075 [000 [1.905] 25] 0 Oo} fo |e +t 000 | 0.158 | 000 | 4013 | [a0] ata 0.000] 0.178 [0004521] 97] 0 oles [aia 00027-0196 686 [4 978 | [afte «005 | o.t96 | i372 | 4978 | [14] 02 at 031 | 0.196 | 3327] 4978 30 | los [16 [oa 002 10.190 [0.196 [4.826 [4.978] [arf vec {vec {0218 | 0.196 | 5537 | -4978 | 40/0 ales +e {vee [vec 0228 | 0196 | 5.791 | 4978 | [ves [vec 0237 [-0:196-| 6.020 [4978] 1} DIED, ale [20 sss oer ais [eae Taam] GDI DATABASESISA Gy [2 [wes ves__ [0267 [0.196 | 6782 | 4978] 4318 Bits [25 [por | pos | 0354 | 0.196 | 8992 | -4978 | «7|ca alts [29 [ais ts 0485 |. {12319 | 1547 | ao] “ [af ais | ats. |-0485 | -o.121 | ta319 | 3073 | [32 [a2 | at «0485 | 0.068 | 12319 | -1.727 | sola ols [34 [aio [ato 0.485 T9003 Pasta | 564_| [735 [ag as Tas Fors | it633 [356 | 6 |g ali [3s as a8 1 0430 | oor | 10922 | 366 | [3s_[-——po10 [pas }-o.354 |~o.o1a {e992 [a6] ) 9 [39 [por | omy | 0329 | oor | 8357 | 256 | Leones es oe ps] Lke 2 2 @eo oe ooo [a [voc [vee 90.267 | o.014 | 6.782 | 356_| ve se se 7 eet [a {vec vec i ozs7 | oors | 6528 | 356 | [a3 [vec [vec | -oza7 | oora | 6.274 | 356_| [4 {vss | vss | 0237 | oor | 6020 | 256 | [45 [vss | vss} 0228 | oor | 5791 | 256 Wafer diameter: 150mm [46 [vss vss zis | oot T5537 [356] Wafer thickness: 18.5 mil +0.5 mil [a7 [pois | barf o.t90 | o01s | 4926 | 356 | Die size: 230 x 501 mil [as [po {pau | -0.156 | oo14 | 3.962 | 356 | {stepping interval) [49 [pois | 00a + ora | oors | 3327 | 356_| [-so_|~— pos [nu ‘| 0097 | nora | 2464 | 356_| 5,842 x 12,725 um [51 |e ios | ord | 1372 | 356_| Bond padsize: 5.8 x 5.8 mil (52 [pee p02? ore T6061 356] 146 x 146 jum ““DNU" standsfordonotuse Passivation Openings (typical): 5.1x 5.1 mil 130 x 130 um Ba RS ne i