MT58L128V36F1 MICRON | Alldatasheet
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Technical content
4Mb: 256K x 18, 128K x 32/36 cro FLOW-THROUGH SYNCBURST SRAM 4Mb SYNCBURST™ MT58L256L18F1, MT58L128L32F1, MT58L128L36F1; MT58L256V18F1, SRAM MT58L128V32F1, MT58L128V36F1 3.3V Vop, 3.3V or 2.5V I/O, Flow-Through
FEATURES
- Fast clock and OE# access times 100-Pin TQFP! * Single +3.3V +0.3V/-0.16SV power supply (Vpp) * Separate +3.3V or +2.SV isolated output buffer supply (VpDQ) * SNOOZE MODE for reduced-power standby * Common data inputs and data outputs * Individual BYTE WRITE control and GLOBAL WRITE ae * Three chip enables for simple depth expansion > ee and address pipelining > ee * Clock-controlled and registered addresses, data > <<“ 1/Os and control signals ee * Internally self-timed WRITE cycle * Burst control pin (interleaved or linear burst)
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° iés-pin FBGA package 165-Pin FBGA * 100-pin TQFP package . Low capacitive bus loading “eS ~ © x18, x32, and x36 versions available L a oN OPTIONS MARKING “ * Timing (Access/Cycle/MHz) ~ 6.8ns/7.Sns/133 MHz 68 SS 7.Sns/8.8ns/113 MHz 75 SS * 8.Sns/10ns/100 MHz 8.5 A 10ns/15ns/66 MHz “10 SH * Configurations aN oe 18 MTS8L2S6L18F1 NOTE: 1. JEDEC-standard MS-026 BHA (LQFP). 128K x 32 MTS8L128L32F1 128K x 36 MTS8L128L36F1 2sv yO GENERAL DESCRIPTION asekx 18 eelasevien The Micron® SyncBurst™ SRAM family employs 128K x 36 MTS8L128V36F1 high-speed, low-power CMOS designs that are fabri- © Pack cated using an advanced CMOS process. 100 aR TOFP T Micron’s 4Mb SyncBurst SRAMs integrate a 256K x 165. bin FBGA Ft 18, 128K x 32, or 128K x 36 SRAM core with advanced P synchronous peripheral circuitry anda 2-bit burst counter. . ps sa Aen Seema None All synchronous inputs pass through registers con- Ome a= AN trolled by a positive-edge-triggered single clock input Industrial (40°C to +85°C) iT (CLK). The synchronous inputs include all addresses, all Part Nuanber Example: data inputs, active LOW chip enable (CE#), two addi- MTS58L256L18F1T-8.5 tional chip enables for easy depth expansion (CE2#, * A Part Marking Guide for the FBGA devices can be found on Micron’s CE2), burst control inputs (ADSC#, ADSP#, ADV), byte * Industrial temperature range offered in specific speed grades and configurations. Contact factory for more information. Baa RRL nN TLS pes av 22 ‘ekea uereomay he.
awe | aan ar ome dtl tH otic | rp FE wits F Ll se srh s wns Mii = nl Fa wien FE an l= Dtl’D [ wattedien FETT) cad Ot ly FUNCTIONAL BLOCK DIAGRAM 128K x 32/36 oe we — i D a2 | pee es a | on ie on mu DDT IL enone HED FI = ond TIN orc! we Di) Hd enc | aad pa sresoe & a p>" NOTE: Functional block diagrams illustrate simplified device operation. See truth tables, pin descriptions, and timing diagrams for detailed information.
4Mb: 256K x 18, 128K x 32/36 cro FLOW-THROUGH SYNCBURST SRAM GENERAL DESCRIPTION (continued) Asynchronous inputs include the output enable BWa# controls DQa pins and DQPa; BWb# controls (OE#), clock (CLK) and snooze enable (ZZ). Thereis also DQb pins and DQPb. During WRITE cycles on the x32 a burst mode input (MODE) that selects between inter- and x36 devices, BWa# controls DQa pins and DQPa; leaved and linear burst modes. The data-out (Q), en- BWb# controls DQb pins and DQPb; BWc# controls abled by OE#, is also asynchronous. WRITE cycles can DQc pins and DQPc; BWd# controls DQd pins and be from one to two bytes wide (x18) or from one to four DQPd. GW LOW causes all bytes to be written. Parity bytes wide (x32/x36), as controlled by the write control bits are only available on the x18 and x36 versions. inputs. Micron's 4Mb SyncBurst SRAMs operate from a Burst operation can be initiated with either address +3.3V Von power supply, and all inputs and outputs are status processor (ADSP#) or address status controller TTL-compatible. Users can choose either a 2.SV or 3.3V (ADSC#) inputs. Subsequent burst addresses can be V/O version. The device is ideally suited for 486, internally generated as controlled by the burst advance Pentium®, and PowerPC systems and those systems input (ADV4). that benefit from a wide synchronous data bus. The Address and write control are registered on-chip to device is also ideal in generic 16-, 18-, 32-, 36-, 64-, and simplify WRITE cycles. This allows self-timed WRITE 72-bit-wide applications. cycles. Individual byte enables allow individual bytes Please refer to Micron’s Website (www.micron.com/ to be written. During WRITE cycles on the x18 device, Stamds) for the latest data sheet. TQFP PIN ASSIGNMENT TABLE [PIN xis | «3236 | Pina] x18 | x32h36 | Pinal x18 | x32/x36 | pine] xt | x32h36 | [a [NC [NcDOPc*| [26 [ss [si [NC |NCDOPa*| [7 [Vs | [2 {nc [bc | [27 {VooQ | [s2 {nc | Qa | [77 | VorQ | [3 [Nc Tbe | [2s | Nc 7 Dad | es [78 | NC T DQb | [4 { VcoQ™ | [2a | nc_ | DQd_| [sa [ VooQ | [7a {nc [ DQb | [6 {NC [bg | [31 [MODE | [36 [NC [ 0Qa | fer {sa [7 [Nc | ge | [32 [SA [s7 [nc | Daa | 2 a | 8] bob | bac | [33 [SA [ssf DOs [a3 [ADVE [9 [bgp [bg | [34 [sa [so [Qa [ea | ADSP# | [to [ss [35 [SA [eo [vs [as | ADSce | [i {VeoQ” | [36 [SAT [si [Voog [a6 [Ore | [iz [bgp TT gc | [37 [SAO [a [ga [37 | awe | [13 [bgp [bg | [3s {NU [es [ Qa [es | Gwe | [ta [ss [39 [NT se a [is [Von [49 [vss [es [Von [99 [Vs [te [NC [ay | Von | [se [NC [or | Voo | [iw[ vss [az [Nes [a [Vs [92 [cee | [is | bob TT baa | [a3 [Nes | [ss [Dos] DQb | [93 | BWak | [19 [bob [bad | [ag {sa [es { dos | bab | [oa | BWbe_ | [20 [ VcoQ | [as [SA [7 [oo [9s | NC] ewer | [2i{ vss [ag {SA [a [ Vs | [96 | Nc | Bwat | [22 [bob T bad | cs a [72 [bos T bQb | [23 [dob [bad | a [73 [doa | 0Qb | [oa [ces [async [bad | [so[ SA] Ls] Ne [qb | [oof SA *No Connect (NC) is used on the x32 version. Parity (DQPx) is used on the x36 version. **Pins 43 and 42 are reserved for address expansion, 8Mb and 16Mb respectively. SN a eet aes MATS EAL U6 pet 32 (O02 Miran Tecate