MT48H32M16LFCJ-8L

MT48H32M16LF MICRON | Alldatasheet

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PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT48H32M16LF_1.fm - Rev. H 6/07 EN 1 ©2005 Micron Technology, Inc. All rights reserved. Mobile SDRAM MT48H32M16LF – 8 Meg x 16 x 4 banks MT48H16M32LF/LG – 4 Meg x 32 x 4 banks

• Endur-IC™ technology  Fully synchronous; all signals registered on positive edge of system clock V DD = 1.7–1.95V; VDDQ = 1.7–1.95V  Internal, pipelined operat ion; column address can be changed every clock cycle  Four internal banks for concurrent operation  Programmable burst lengths: 1, 2, 4, 8, and continuous  Auto precharge, includes concurrent auto precharge  Auto refresh and self refresh modes  LVTTL-compatible inputs and outputs  On-chip temperature sensor to control refresh rate  Partial-array self refresh (PASR)  Deep power-down (DPD)  Selectable output drive (DS) Table 1: Configuration Addressing DQ Bus Width Architecture JEDEC- Standard Option Reduced Page-Size Option2 Number of banks 4 4 Bank address balls BA0, BA1 BA0, BA1 x16 Row address balls A0–A12 – Column address balls A0–A9 – x32 Row address balls A0–A12 A0–A13 Column address balls A0–A8 A0–A7 Table 2: Key Timing Parameters CL = CAS (READ) latency Speed Grade Clock Rate (MHz) Access Time CL = 2 CL = 3 CL = 2 CL = 3 -75 104 133 9ns 6ns -8 100 125 9ns 7ns Notes: 1. For continuous page burst, contact factory for availability. 2. For reduced page-size option, contact fac- tory for availability. 3. LG is a reduced page-size option. Contact factory for availability. 4. Only available for x32 configuration. 5. Only available for x16 configuration. Options Marking V DD/VDDQ – 1.8V/1.8V H R o w s i z e o p t i o n – Standard addressing option LF – Reduced page-size option LG 3, 4  Configuration – 32 Meg x 16 (8 Meg x 16 x 4 banks) 32M16 – 16 Meg x 32 (4 Meg x 32 x 4 banks) 16M32  Plastic “green” packages – 54-Ball VFBGA (10mm x 11.5mm) CJ – 90-Ball VFBGA (10mm x 13mm) CM 3  Timing – cycle time – 7.5ns at CL = 3 -75 – 8ns at CL = 3 -8 P o w e r –S t a n d a r d I DD2P/IDD7N o n e –L o w IDD2P/IDD7L  Operating temperature range – Commercial (0°C to +70°C) None – Industrial (–40°C to +85°C) IT D e s i g n r e v i s i o n : A

PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT48H32M16LF_1.fm - Rev. H 6/07 EN 2 ©2005 Micron Technology, Inc. All rights reserved. 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM Table of Contents Table of Contents

PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT48H32M16LF_1.fm - Rev. H 6/07 EN 4 ©2005 Micron Technology, Inc. All rights reserved. 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM List of Tables List of Tables

PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT48H32M16LF_1.fm - Rev. H 6/07 EN 5 ©2005 Micron Technology, Inc. All rights reserved. 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM General Description Figure 1: 512Mb Mobile SDRAM Part Numbering General Description The Micron® 512Mb Mobile SDRAM is a high-speed CMOS, dynamic random-access memory containing 536,870,912-bits. It is internally configured as a quad-bank DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the x16’ s 134,217,728-bit banks is organized as 8,192 rows by 1K columns by 16 bits. Each of the x32’ s 134,217,728-bit banks is organized as 8,192 rows by 512 columns by 32 bits. In a reduced page-size option, each of the x32’ s 134,217,728-bit banks is organized as 16,384 rows by 256 columns x32 bits. Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA0, BA1 select the bank; A0–A12 select the row). The address bits registered coincident with the READ or WRITE command are used to select the starting column location for the burst access. The SDRAM provides for programmable read or write burst lengths (BL) of 1, 2, 4, or 8 locations with a read burst terminate option. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. The 512Mb SDRAM uses an internal pipelined architecture to achieve high-speed oper- ation. This architecture is compatible with the 2n rule of prefetch architectures, but it also allows the column address to be changed on every clock cycle to achieve a high- speed, fully random access. Precharging one bank while accessing one of the other three banks will hide the PRECHARGE cycles and provide seamless high-speed, random- access operation. Speed Grade tCK = 7.5ns tCK = 8.0ns -75 IT Operating Temp. Commercial Industrial L Power Standard I DD2/IDD7 Low IDD2/IDD7 Example Part Number: MT48H16M32LFCM-75IT:A Mobile ConfigurationMT48 Package Speed Temp. Power Package 54-Ball (10 x 11.5 VFBGA) Pb–free CJ 90-Ball (10 x 13 VFBGA) Pb–free CM H VDD/ VDDQ VDD/VDDQ 1.8V/1.8V Configuration

32 Meg x 16

16 Meg x 32

:A Design revision

PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT48H32M16LF_1.fm - Rev. H 6/07 EN 6 ©2005 Micron Technology, Inc. All rights reserved. 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM Functional Block Diagrams The 512Mb SDRAM is designed to operate in 1.8V low-power memory systems. An auto refresh mode is provided, along with a power-saving deep power-down mode. All inputs and outputs are LVTTL-compatible. SDRAMs offer substantial advances in DRAM operating performance, including the ability to synchronously burst data at a high data rate with automatic column-address generation, the ability to interleave between internal banks in order to hide precharge time, and the capability to randomly change column addresses on each clock cycle during a burst access. Functional Block Diagrams Figure 2: 32 Meg x 16 SDRAM RAS# CAS# CLK CS# WE# CKE CONTROL LOGIC MODE REGISTER COMMAND DECODE A0–A12, BA0, BA1 DQML, DQMH 1,024 (x16) 16,384 I/O GATING DQM MASK LOGIC READ DATA LATCH WRITE DRIVERS COLUMN DECODER BANK0 MEMORY ARRAY (8,192 x 1,024 x 16) BANK0 ROW- ADDRESS LATCH AND DECODER 8,192 SENSE AMPLIFIERS DQ0– DQ15 BANK1 BANK2 BANK3 2 2 EXT MODE REGISTER BA1 BA0 Bank 0 0 0 0 1 1 1 0 2 1 1 3 DATA OUTPUT REGISTER DATA INPUT REGISTER ROW- ADDRESS MUX REFRESH COUNTER ADDRESS REGISTER BANK CONTROL LOGIC COLUMN- ADDRESS COUNTER/ LATCH

PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT48H32M16LF_1.fm - Rev. H 6/07 EN 7 ©2005 Micron Technology, Inc. All rights reserved. 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM Functional Block Diagrams Figure 3: 16 Meg x 32 SDRAM 0 0 0 0 1 1 1 0 2 1 1 3 BA1 BA0 Bank RAS# CAS# ROW- ADDRESS MUX CLK CS# WE# CKE CONTROL LOGIC COLUMN- ADDRESS COUNTER/ LATCH MODE REGISTER COMMAND DECODE A0–A12, BA0, BA1 DQM0–313 ADDRESS REGISTER 15 512 (x32) 16,384 I/O GATING DQM MASK LOGIC READ DATA LATCH WRITE DRIVERS COLUMN DECODER BANK0 MEMORY ARRAY (8,192 x 512 x 32) BANK0 ROW- ADDRESS LATCH AND DECODER 8,192 SENSE AMPLIFIERS BANK CONTROL LOGIC DQ0– DQ31 BANK1 BANK2 BANK3 4 4 REFRESH COUNTER EXT MODE REGISTER DATA INPUT REGISTER DATA OUTPUT REGISTER

PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT48H32M16LF_1.fm - Rev. H 6/07 EN 8 ©2005 Micron Technology, Inc. All rights reserved. 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM Ball Assignments Ball Assignments Figure 4: 54-Ball FBGA (Top View) – 10mm x 11.5mm Notes: 1. The E2 pin is a test pin and must be tied to VSSQ in normal operation. 1 2 3 4 6 7 8 9 5 A B C D E F G H J VSSQ Vss CKE V SS DQ14 DQ12 DQ10 DQ8 UDQM A12 V SS DQ15 DQ13 DQ11 DQ9 V SSQ1 CLK A11 V DDQ VDDQ VSSQ VDD CAS# BA0 DQ0 DQ2 DQ4 DQ6 LDQM RAS# BA1 V DD DQ1 DQ3 DQ5 DQ7 WE# CS# A10 V DD VDDQV SSQ VSSQ VDDQ

PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT48H32M16LF_1.fm - Rev. H 6/07 EN 9 ©2005 Micron Technology, Inc. All rights reserved. 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM Ball Assignments Figure 5: 90-Ball VFBGA (Top View) – 10mm x 13mm Notes: 1. The K2 “DNU” ball should not be used in the application. However, it may be connected to VSS (ground). 1 2 3 4 6 7 8 9 5 DQ26 DQ28 V SS Q V SS Q V DD Q V SS CLK DQM1 V DD Q V SS Q V SS Q DQ11 DQ13 DQ24 V DD Q DQ27 DQ29 DQ31 DQM3 CKE DQ8 DQ10 DQ12 V DD Q DQ15 V SS V SS Q DQ25 DQ30 NC A12 NC V SS DQ9 DQ14 V SS Q V SS V DD V DD Q DQ22 DQ17 NC A10 A13/NC BA0 CAS# V DD DQ6 DQ1 V DD Q V DD DQ21 DQ19 V DD Q V DD Q V SS Q V DD A11 RAS# DQM0 V SS Q V DD Q V DD Q DQ4 DQ2 DQ23 V SS Q DQ20 DQ18 DQ16 DQM2 BA1 CS# WE# DQ7 DQ5 DQ3 V SS Q DQ0 A B C D E F G H J K L M N P R DNU1

PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT48H32M16LF_1.fm - Rev. H 6/07 EN 10 ©2005 Micron Technology, Inc. All rights reserved. 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM Ball Descriptions Ball Descriptions Table 3: VFBGA Ball Descriptions 54-Ball VFBGA 90-Ball VFBGA Symbol Type Description F2 J1 CLK Input Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the positive edge of CLK. CLK also increments the internal burst counter and controls the output registers. F3 J2 CKE Input Clock enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal. Deactivating the clock provides precharge power- down and SELF REFRESH operation (all banks idle), active power- down (row active in any bank), deep power-down (all banks idle), or CLOCK SUSPEND operation (burst/access in progress). CKE is synchronous except after the device enters power-down and self refresh modes, where CKE becomes asynchronous until after exiting the same mode. The input buffers, including CLK, are disabled during power-down and self refresh modes, providing low standby power. G9 J8 CS# Input Chip select: CS# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when CS# is registered HIGH. CS# provides for external bank selection on systems with multiple banks. CS# is considered part of the command code. F7, F8, F9 J9, K7, K8 CAS#, RAS#, WE# Input Command inputs: RAS#, CAS#, and WE# (along with CS#) define the command being entered. E8, F1 K9, K1, F8, F2 DQM0–3, LDQM, UDQM Input Input/Output mask: DQM is sampled HIGH and is an input mask signal for write accesses and an output enable signal for read accesses. Input data is masked during a WRITE cycle. The output buffers are placed in a High-Z state (two-clock latency) during a READ cycle. For the x16, LDQM corresponds to DQ0–DQ7 and HDQM corresponds to DQ8–DQ16. For the x32, DQM0 corresponds to DQ0–DQ7, DQM1 corresponds to DQ8–DQ15, DQM2 corresponds to DQ16–DQ23, and DQM3 corresponds to DQ24–DQ31. DQM0–3 (or LDQM and HDQM if x16) are considered same state when referenced as DQM. G7, G8 J7, H8 BA0, BA1 Input Bank address input(s): BA0 and BA1 define to which bank the ACTIVE, READ, WRITE, or PRECHARGE command is being applied. BA0 and BA1 become “don’t care” when registering an ALL BANK PRECHARGE (A10 HIGH). H7, H8, J8, J7, J3, J2, H3, H2, H1, G3, H9, G2, G8, G9, F7, F3, G1, G2, G3, H1, H2, J3, G7, H9, A0–A12 Input Address inputs: A0–A12 are sampled during the ACTIVE command (row-address A0–A12) and READ/WRITE command [column-address A0–A8 (x32); column-address A0–A9 (x16); with A10 defining auto precharge] to select one location out of the memory array in the respective bank. A10 is sampled during a PRECHARGE command to determine if all banks are to be precharged (A10 HIGH) or bank selected by BA0, BA1. The address inputs also provide the op-code during a LOAD MODE REGISTER command. – H7 A13/NC Input H7 is used for the LG, reduced page-size, option (see Table 1 on page 1); otherwise, leave as NC.

PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT48H32M16LF_1.fm - Rev. H 6/07 EN 11 ©2005 Micron Technology, Inc. All rights reserved. 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM Ball Descriptions A8, B9, B8, C9, C8, D9, D8, E9, E1, D2, D1, C2, C1, B2, B1, A2 R8, N7, R9, N8, P9, M8, M7, L8, L2, M3, M2, P1, N2, R1, N3, R2, E8, D7, D8, B9, C8, A9, C7, A8, A2, C3, A1, C2, B1, D2, D3, E2 DQ0–DQ31 I/O Data input/output: Data bus. A7, B3, C7, D3 B2, B7, C9, D9, E1, L1, M9, N9, P2, P7 VDDQ Supply DQ power: Provide isolated power to DQ for improved noise immunity. A3, B7, C3, D7 B8, B3, C1, D1, E9, L9, M1, N1, P3, P8 VssQ Supply DQ ground: Provide isolated ground to DQ for improved noise immunity. A9, E7, J9 A7, F9, L7, R7 V DD Supply Core power supply. A1, E3, J1 A3, F1, L3, R3 V SS Supply Ground. – E3, E7, K3 NC – Internally not connected: These balls could be left unconnected, but it is recommended they be connected to Vss. E2 – V SSQ– This TEST pin must be tied to VSS or VSSQ in normal operation. K2 DNU – Should not be used in the application. However, it may be connected to Vss (ground). Table 3: VFBGA Ball Descriptions (Continued) 54-Ball VFBGA 90-Ball VFBGA Symbol Type Description

PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT48H32M16LF_1.fm - Rev. H 6/07 EN 12 ©2005 Micron Technology, Inc. All rights reserved. 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM Functional Description Functional Description In general, the 512Mb SDRAMs (4 Meg x 32 x 4 banks) are quad-bank DRAMs that operate at 1.8V and include a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA0 and BA1 select the bank, A0–A12 select the row). The address bits (A0–A9 for x16 and A0–A8 for x32) registered coincident with the READ or WRITE command are used to select the starting column location for the burst access. Prior to normal operation, the SDRAM must be initialized. The following sections provide detailed information covering device initialization, register definition, command descriptions, and device operation. Initialization SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. Once the power is applied to V DD and VDDQ (simultaneously) and the clock is stable (stable clock is defined as a signal cycling within timing constraints specified for the clock ball), the SDRAM requires a 100µs delay prior to issuing any command other than a COMMAND INHIBIT or NOP . Starting at some point during this 100µs period and continuing at least through the end of this period, COMMAND INHIBIT or NOP commands should be applied. Once the 100µs delay has been satisfied with at least one COMMAND INHIBIT or NOP command having been applied, a PRECHARGE command must be applied. All banks must then be precharged, thereby placing the device in the all banks idle state. Once in the idle state, two AUTO REFRESH cycles must be performed. After the AUTO REFRESH cycles are complete, the SDRAM is ready for programming the mode registers. Because the mode registers will power up in an unknown state, they should be loaded prior to applying any operational command. Register Definition Mode Register There are two mode registers in the component: mode register and extended mode register (EMR). The mode register is illustrated in Figure 6 on page 14. The mode register is used to define the specific mode of operation of the SDRAM. This definition includes the selection of a burst length (BL), a burst type, a CAS latency (CL), an operating mode and a write burst mode, as shown in Figure 6 on page 14. The mode register is programmed via the LOAD MODE REGISTER command and will retain the stored information until it is programmed again or the device loses power. Mode register bits M0–M2 specify the BL, M3 specifies the type of burst, M4–M6 specify the CL, M7 and M8 specify the operating mode, M9 specifies the write burst mode, and M10 and M11 should be set to zero. M12 and M13 should be set to zero to prevent the extended mode register from being programmed.

PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT48H32M16LF_1.fm - Rev. H 6/07 EN 13 ©2005 Micron Technology, Inc. All rights reserved. 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM Register Definition The mode registers must be loaded when all banks are idle, and the controller must wait tMRD before initiating the subsequent operation. Violating either of these requirements will result in unspecified operation. Burst Length (BL) Read and write accesses to the SDRAM are burst oriented, with the BL being program- mable, as shown in Figure 6 on page 14. The BL determines the maximum number of column locations that can be accessed for a given READ or WRITE command. BL = 1, 2, 4, 8, or continuous locations are available for both the sequential and the interleaved burst types, and a continuous-page burst is available for the sequential type. The contin- uous-page burst is used in conjunction with the BURST TERMINATE command to generate arbitrary BLs. Reserved states should not be used, as unknown operation or incompatibility with future versions may result. When a READ or WRITE command is issued, a block of columns equal to the BL is effec- tively selected. All accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached. The block is uniquely selected by A1–A8 when BL = 2, A2–A8 when BL = 4, and A3–A8 when BL = 8. The remaining (least significant) address bit(s) is (are) used to select the starting location within the block. Burst Type Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit M3. The ordering of accesses within a burst is determined by the BL, the burst type, and the starting column address, as shown in Table 4 on page 15.

PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT48H32M16LF_1.fm - Rev. H 6/07 EN 14 ©2005 Micron Technology, Inc. All rights reserved. 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM Register Definition Figure 6: Mode Register Definition Notes: 1. Should be programmed to “0” to en sure compatibility with future devices. M3 = 0 Reserved Reserved Reserved Reserved M3 = 1 Reserved Reserved Reserved Reserved Burst Type Sequential Interleaved CAS Latency Reserved Reserved Reserved Reserved Reserved Reserved Burst Length Mode Register (Mx) Address Bus 9 7 6 5 4 3 8 2 1 Burst Length CAS Latency BTOp Mode Reserved1 WB0 A11 M11 A10 M10 10 11 13 BA0 M13 BA1 M14 14 0 Operating Mode Normal operation All other states reserved Mode Register Definition Base mode register Reserved Extended mode register Reserved M14 M13 Write Burst Mode Programmed burst length Single location access A12 M12

PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT48H32M16LF_1.fm - Rev. H 6/07 EN 15 ©2005 Micron Technology, Inc. All rights reserved. 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM Register Definition CAS Latency (CL) The CL is the delay, in clock cycles, between the registration of a READ command and the availability of the first piece of output data. The latency can be set to two or three clocks. If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available by clock edge n + m. The DQs will start driving as a result of the clock edge one cycle earlier (n + m - 1), and provided that the relevant access times are met, the data will be valid by clock edge n + m. For example, assuming that the clock cycle time is such that all relevant access times are met, if a READ command is registered at T0 and the latency is programmed to two clocks, the DQs will start driving after T1 and the data will be valid by T2, as shown in Figure 7 on page 16. Reserved states should not be used as unknown operation or incompatibility with future versions may result. Operating Mode The normal operating mode is selected by setting M7 and M8 to zero; the other combi- nations of values for M7 and M8 are reserved for future use. Reserved states should not be used because unknown operation or incompatibility with future versions may result. Write Burst Mode When M9 = 0, the BL programmed via M0–M2 applies to both READ and WRITE bursts; when M9 = 1, the programmed BL applies to READ bursts, but write accesses are single- location accesses. Table 4: Burst Definition Table Burst Length Starting Column Address Order of Accesses Within a Burst Type = Sequential Type = Interleaved 2A 0 00 - 1 0 - 1 11 - 0 1 - 0 4A 1 A 0

8 A 2A 1A 0

PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT48H32M16LF_1.fm - Rev. H 6/07 EN 16 ©2005 Micron Technology, Inc. All rights reserved. 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM Register Definition Extended Mode Register (EMR) The EMR controls the functions beyond those controlled by the mode register. These additional functions are special features of the mobile device that helps reduce overall system power consumption. They include temperature-compensated self refresh (TCSR) control, partial-array self refresh (PASR), and output drive strength. The EMR is programmed via the MODE REGISTER SET command (BA1 = 1, BA0 = 0) and retains the stored information until it is programmed again or the device loses power. Figure 7: CAS Latency Notes: 1. Each READ command may be to any bank. DQM is LOW. 2. For CL = 2, DQM should be ta ken LOW at READ command. For CL = 3, DQM should be taken LOW one cycle after the READ command. CLK DQ T2 T1 T3 T0 CL = 3 LZ DOUT t OH t COMMAND NOP READ tAC tAC NOP NOP DON’T CARE UNDEFINED CLK DQ T2 T1 T 3 T0 CL = 2 LZ DOUT t OH t COMMAND NOP READ NOP

PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT48H32M16LF_1.fm - Rev. H 6/07 EN 17 ©2005 Micron Technology, Inc. All rights reserved. 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM Register Definition Figure 8: EMR Definition Notes: 1. On-die temperature sensor is used in plac e of TCSR. Setting these bits will have no effect. The extended mode register must be programmed with E7 through E12 set to “0.” It must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the specified time before initiating any subsequent operation. Violating either of these requirements results in unspecified operation. Once the values are entered, the extended mode register settings will be retained even after exiting deep power-down mode. Temperature-Compensated Self Refresh (TCSR) On this version of the Mobile DDR SDRAM, a temperature sensor is implemented for automatic control of the self refresh oscillator. Programming of the TCSR bits will have no effect on the device. The self refresh oscillator will continue refresh at the factory programmed optimal rate for the device temperature. Partial-Array Self Refresh (PASR) For further power savings during self refresh, the partial-array self refresh (PASR) feature allows the controller to select the amount of memory that will be refreshed during self refresh. The following refresh options are available. 1. All banks (banks 0, 1, 2, and 3). 2. Two banks (banks 0 and 1; BA1=0). 3. One bank (bank 0; BA1 = BA0 = 0). 4. Half bank (bank 0; BA1 = BA0 = row address MSB = 0). 5. Quarter bank (bank 0; BA1 = BA0; row address MSB = row address MSB - 1 = 0). Extended Mode Register Address Bus 9 7 6 5 4 3 8 2 1 PASR TCSR1DS set to “0” 0 E12 A11 E11 A10 E10 10 11 12 Partial-Array Self Refresh Coverage Full array Half array Quarter array Reserved Reserved One-eighth array One-sixteenth array Reserved Driver Strength Full-strength driver Half-strength driver Quarter-strength driver One eighth-strength driver BA0 A12 E13 BA1 E14 13 14 Mode Register Definintion Standard mode register Reserved Extended mode register Reserved E14 E13 E11 E12 E10 Normal operation All other states reserved

PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT48H32M16LF_1.fm - Rev. H 6/07 EN 18 ©2005 Micron Technology, Inc. All rights reserved. 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM Register Definition WRITE and READ commands occur to any bank selected during standard operation, but only the selected banks or segments of a bank in PASR will be refreshed during self refresh. It is important to note that data in unused banks or portions of banks will be lost when PASR is used. Driver Strength Bits E5 and E6 of the extended mode register can be used to select the driver strength of the DQ outputs. This value should be set according to the application’ s requirements.

PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT48H32M16LF_1.fm - Rev. H 6/07 EN 19 ©2005 Micron Technology, Inc. All rights reserved. 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM Commands Commands Table 5 provides a quick reference of available commands. This is followed by a written description of each command. Three additional Truth Tables appear on pages 41–44; these tables provide current state/next state information. Notes: 1. COMMAND INHIBIT and NOP ar e functionally interchangeable. 2. BA0–BA1 provide bank address and A0–A12 provide row address. 3. BA0–BA1 provide bank address; A0–A9 provide column address; A10 HIGH enables the auto precharge feature (nonpersistent), and A10 LOW disables the auto precharge feature. 4. CKE is HIGH for all commands shown except SELF REFRESH and deep power-down. 5. All states and sequences not show n are reserved and/or illegal. 6. The purpose of the BURST TERMINATE command is to stop a data burst, thus the command could coincide with data on the bus. However, the DQs column reads a don’t care state to illustrate that the BURST TERMINATE command can occur when there is no data present. 7. Applies only to read and writ e bursts with auto precharge disabled; this command is unde- fined and should not be used for READ bursts with auto precharge enabled. 8. This command is a BURST TERMINATE if CKE is HIGH, deep power-down if CKE is LOW. 9. A10 LOW: BA0–BA1 determine which bank is precharged. A10 HIGH: all banks are pre- charged and BA0–BA1 are “Don’t Care.” 10. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW. 11. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE. 12. BA0–BA1 select either the standard mode regist er or the extended mode register (BA0 = 0, BA1 = 0 select the standard mode register; BA0 = 0, BA1 = 1 select extended mode register; other combinations of BA0–BA1 are reserved.) A0–A12 provide the op-code to be written to the selected mode register. COMMAND INHIBIT The COMMAND INHIBIT function prevents new commands from being executed by the SDRAM, regardless of whether the CLK signal is enabled. The SDRAM is effectively dese- lected. Operations already in progress are not affected. Table 5: Truth Table – Commands and DQM Operation Notes 4 and 5 apply to all commands Name (Function) CS# RAS# CAS# WE# DQM ADDR DQs Notes COMMAND INHIBIT (NOP) HXXXX X X 1 NO OPERATION (NOP) LHHHX X X 1 ACTIVE (Select bank and activate row) L L H H X Bank/Row X 2 READ (Select bank and column, and start READ burst) LHLH L / H B a n k / C o l X 3 WRITE (Select bank and column, and start WRITE burst) L H L L L/H Bank/Col Valid 3 BURST TERMINATE or deep power-down (Enter deep power-down mode) L H H L X X X 6, 7, 8 PRECHARGE (Deactivate row in bank or banks) LLHLXC o d e X 9 AUTO REFRESH or SELF REFRESH (Enter self refresh mode) L L L H X X X 10, 11 LOAD MODE REGISTER LLLLX O p - C o d e X 1 2 Write enable/output enable XXXXL XA c t i v e Write inhibit/output High-Z XXXXH XH i g h - Z

PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT48H32M16LF_1.fm - Rev. H 6/07 EN 20 ©2005 Micron Technology, Inc. All rights reserved. 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM Commands NO OPERATION (NOP) The NO OPERATION (NOP) command is used to perform a NOP to an SDRAM which is selected (CS# is LOW). This prevents unwanted commands from being registered during idle or wait states. Operations already in progress are not affected. Load Mode Register The mode register is loaded via inputs A0–A12, BA0, and BA1. (See "Mode Register" on page 12.) The LOAD MODE REGISTER and LOAD EXTENDED MODE REGISTER commands can only be issued when all banks are idle, and a subsequent executable command cannot be issued until tMRD is met. ACTIVE The ACTIVE command is used to open (or activate) a row in a particular bank for a subsequent access. The value on the BA0, BA1 inputs selects the bank, and the address provided selects the row. This row remains active (or open) for accesses until a PRECHARGE command is issued to that bank. A PRECHARGE command must be issued before opening a different row in the same bank. READ The READ command is used to initiate a burst read access to an active row. The value on the BA0, BA1 inputs selects the bank, and the address provided selects the starting column location. The value on input A10 determines whether or not auto precharge is used. If auto precharge is selected, the row being accessed will be precharged at the end of the read burst; if auto precharge is not selected, the row will remain open for subse- quent accesses. Read data appears on the DQs subject to the logic level on the DQM inputs two clocks earlier. If a given DQM signal was registered HIGH, the corresponding DQs will be High-Z two clocks later; if the DQM signal was registered LOW, the DQs will provide valid data. WRITE The WRITE command is used to initiate a burst write access to an active row. The value on the BA0, BA1 inputs selects the bank, and the address provided selects the starting column location. The value on input A10 determines whether or not auto precharge is used. If auto precharge is selected, the row being accessed will be precharged at the end of the write burst; if auto precharge is not selected, the row will remain open for subse- quent accesses. Input data appearing on the DQs is written to the memory array subject to the DQM input logic level appearing coincident with the data. If a given DQM signal is registered LOW, the corresponding data will be written to memory; if the DQM signal is registered HIGH, the corresponding data inputs will be ignored, and a write will not be executed to that byte/column location. PRECHARGE The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row access a specified time ( tRP) after the precharge command is issued. Input A10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs BA0, BA1 select the bank. Otherwise BA0, BA1 are treated as “Don’t Care.” Once a bank has been precharged, it is in the idle state and must be acti- vated prior to any READ or WRITE commands being issued to that bank.

PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT48H32M16LF_1.fm - Rev. H 6/07 EN 21 ©2005 Micron Technology, Inc. All rights reserved. 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM Commands Auto Precharge Auto precharge is a feature which performs the same individual-bank precharge func- tion described above, without requiring an explicit command. This is accomplished by using A10 to enable auto precharge in conjunction with a specific READ or WRITE command. A precharge of the bank/row that is addressed with the READ or WRITE command is automatically performed upon completion of the READ or WRITE burst. Auto precharge is non persistent in that it is either enabled or disabled for each indi- vidual READ or WRITE command. Auto precharge ensures that the precharge is initiated at the earliest valid stage within a burst. The user must not issue another command to the same bank until the precharge time ( tRP) is completed. This is determined as if an explicit PRECHARGE command was issued at the earliest possible time, as described for each burst type in "Burst Type" on page 13. BURST TERMINATE The BURST TERMINATE command is used to truncate fixed-length bursts. The most recently registered READ or WRITE command prior to the BURST TERMINATE command will be truncated, as shown in "Operations" on page 22. AUTO REFRESH AUTO REFRESH is used during normal operation of the SDRAM and is analogous to CAS#-BEFORE-RAS# (CBR) refresh in conventional DRAMs. This command is non persistent, so it must be issued each time a refresh is required. All active banks must be PRECHARGED prior to issuing an AUTO REFRESH command. The AUTO REFRESH command should not be issued until the minimum tRP has been met after the PRECHARGE command, as shown in "Operations" on page 22. The addressing is generated by the internal refresh controller. This makes the address bits “Don’t Care” during an AUTO REFRESH command. The 512Mb SDRAM requires 8,192 AUTO REFRESH cycles every 64ms ( tREF). Providing a distributed AUTO REFRESH command every 7.8125µs will meet the refresh requirement and ensure that each row is refreshed. Alternatively, 8,192 AUTO REFRESH commands can be issued in a burst at the minimum cycle rate ( tRFC), once every 64ms. SELF REFRESH The SELF REFRESH command can be used to retain data in the SDRAM, even if the rest of the system is powered down. When in the self refresh mode, the SDRAM retains data without external clocking. The SELF REFRESH command is initiated like an AUTO REFRESH command, except CKE is disabled (LOW). Once the SELF REFRESH command is registered, all the inputs to the SDRAM become “Don’t Care” with the exception of CKE, which must remain LOW . Once self refresh mode is engaged, the SDRAM provides its own internal clocking, causing it to perform its own AUTO REFRESH cycles. The SDRAM must remain in self refresh mode for a minimum period equal to tRAS and may remain in self refresh mode for an indefinite period beyond that. The procedure for exiting self refresh requires a sequence of commands. First, CLK must be stable (stable clock is defined as a signal cycling within timing constraints specified for the clock ball) prior to CKE going back HIGH. Once CKE is HIGH, the SDRAM must have NOP commands issued (a minimum of two clocks) for tXSR because time is required for the completion of any internal refresh in progress.

PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT48H32M16LF_1.fm - Rev. H 6/07 EN 22 ©2005 Micron Technology, Inc. All rights reserved. 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM Operations Upon exiting the self refresh mode, AUTO REFRESH commands must be issued every 7.8125µs or less as both SELF REFRESH and AUTO REFRESH utilize the row refresh counter. Deep Power-Down Deep power-down is an operating mode used to achieve maximum power reduction by eliminating the power of the whole memory array of the devices. Array data will not be retained once the device enters deep power-down mode. This mode is entered by having all banks idle then CS# and WE# held LOW with RAS# and CAS# held HIGH at the rising edge of the clock, while CKE is LOW . This mode is exited by asserting CKE HIGH. Operations Bank/Row Activation Before any READ or WRITE commands can be issued to a bank within the SDRAM, a row in that bank must be “opened.” This is accomplished via the ACTIVE command, which selects both the bank and the row to be activated (see Figure 9 on page 23). After opening a row (issuing an ACTIVE command), a READ or WRITE command may be issued to that row, subject to the tRCD specification. tRCD (MIN) should be divided by the clock period and rounded up to the next whole number to determine the earliest clock edge after the ACTIVE command on which a READ or WRITE command can be entered. For example, a tRCD specification of 20ns with a 125 MHz clock (8ns period) results in 2.5 clocks, rounded to 3. This is reflected in Figure 10 on page 23, which covers any case where 2 < tRCD (MIN)/tCK ≤ 3. (The same procedure is used to convert other specification limits from time units to clock cycles.) A subsequent ACTIVE command to a different row in the same bank can only be issued after the previous active row has been “closed” (precharged). The minimum time interval between successive ACTIVE commands to the same bank is defined by tRC. A subsequent ACTIVE command to another bank can be issued while the first bank is being accessed, which results in a reduction of total row-access overhead. The minimum time interval between successive ACTIVE commands to different banks is defined by tRRD.

PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT48H32M16LF_1.fm - Rev. H 6/07 EN 25 ©2005 Micron Technology, Inc. All rights reserved. 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM Operations Figure 12: Consecutive READ Bursts Notes: 1. Each READ command may be to any bank. DQM is LOW. CLK DQ DOUT n T2T1 T4 T3 T 6T5T0 COMMAND ADDRESS READ NOP NOP NOP NOP BANK, COL n NOP BANK, COL b DOUT n + 1 DOUT n + 2 DOUT n + 3 DOUT b READ X = 1 cycle CL = 2 CLK DQ DOUT n T2T1 T4 T3 T 6T5T0 COMMAND ADDRESS READ NOP NOP NOP NOP BANK, COL n NOP BANK, COL b DOUT n + 1 DOUT n + 2 DOUT n + 3 DOUT b READ NOP X = 2 cycles CL = 3 DON’T CARE

PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT48H32M16LF_1.fm - Rev. H 6/07 EN 27 ©2005 Micron Technology, Inc. All rights reserved. 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM Operations The DQM signal must be de-asserted prior to the WRITE command (DQM latency is zero clocks for input buffers) to ensure that the written data is not masked. Figure 13 on page 26 shows the case where the clock frequency allows for bus contention to be avoided without adding a NOP cycle, and Figure 15 on page 28 shows the case where the additional NOP is needed. A fixed-length READ burst may be followed by, or truncated with, a PRECHARGE command to the same bank (provided that auto precharge was not activated). The PRECHARGE command should be issued x cycles before the clock edge at which the last desired data element is valid, where x = CL - 1. This is shown in Figure 16 on page 28 for each possible CL; data element n + 3 is either the last of a burst of four or the last desired of a longer burst. Following the PRECHARGE command, a subsequent command to the same bank cannot be issued until tRP is met. Note that part of the row precharge time is hidden during the access of the last data element(s). In the case of a fixed-length burst being executed to completion, a PRECHARGE command issued at the optimum time (as described above) provides the same opera- tion that would result from the same fixed-length burst with auto precharge. The disad- vantage of the PRECHARGE command is that it requires that the command and address buses be available at the appropriate time to issue the command; the advantage of the PRECHARGE command is that it can be used to truncate fixed-length bursts. Figure 14: READ-to-WRITE Notes: 1. CL = 3. The READ command may be to an y bank, and the WRITE command may be to any bank. If a burst of one is used, then DQM is not required. DON’T CARE READ NOP NOP WRITENOP CLK T2T1 T4 T3T0 DQM DQ DOUT n COMMAND DIN b ADDRESS BANK, COL n BANK, COL b DS tHZ t tCK

PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT48H32M16LF_1.fm - Rev. H 6/07 EN 29 ©2005 Micron Technology, Inc. All rights reserved. 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM Operations Fixed-length READ bursts may be truncated with a BURST TERMINATE command, provided that auto precharge was not activated. The BURST TERMINATE command should be issued x cycles before the clock edge at which the last desired data element is valid, where x = CL - 1. This is shown in Figure 17 on page 29 for each possible CL; data element n + 3 is the last desired data element of a longer burst. Figure 17: Terminating a READ Burst Notes: 1. DQM is LOW. DON’T CARE CLK DQ DOUT n T2T1 T4 T3 T6 T5T0 COMMAND ADDRESS READ NOP NOP NOP NOP BANK, COL n NOP DOUT n + 1 DOUT n + 2 DOUT n + 3 BURST TERMINATE NOP CLK DQ DOUT n T2T1 T4 T3 T6 T5T0 COMMAND ADDRESS READ NOP NOP NOP BANK, COL n NOP DOUT n + 1 DOUT n + 2 DOUT n + 3 BURST TERMINATE NOP X = 1 cycle CL = 2 CL = 3 X = 2 cycles

PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT48H32M16LF_1.fm - Rev. H 6/07 EN 30 ©2005 Micron Technology, Inc. All rights reserved. 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM Operations WRITEs WRITE bursts are initiated with a WRITE command, as shown in Figure 18. The starting column and bank addresses are provided with the WRITE command, and auto precharge is either enabled or disabled for that access. If auto precharge is enabled, the row being accessed is precharged at the completion of the burst. For the generic WRITE commands used in the following illustrations, auto precharge is disabled. During WRITE bursts, the first valid data-in element will be registered coincident with the WRITE command. Subsequent data elements will be registered on each successive positive clock edge. Upon completion of a fixed-length burst, assuming no other commands have been initiated, the DQs will remain High-Z and any additional input data will be ignored (see Figure 19 on page 31). Figure 18: WRITE Command Notes: 1. EN AP = enable auto precharge DIS AP = disable auto precharge Data for any WRITE burst may be truncated with a subsequent WRITE command, and data for a fixed-length WRITE burst may be immediately followed by data for a WRITE command. The new WRITE command can be issued on any clock following the previous WRITE command, and the data provided coincident with the new command applies to the new command. An example is shown in Figure 20 on page 31. Data n + 1 is either the last of a burst of two or the last desired of a longer burst. The 512Mb SDRAM uses a pipe- lined architecture and therefore does not require the 2n rule associated with a prefetch architecture. A WRITE command can be initiated on any clock cycle following a previous CS# WE# CAS# RAS# CKE CLK COLUMN ADDRESS DON’T CARE HIGH BANK ADDRESS A0–A8 BA0, BA1 VALID ADDRESS A101 EN AP DIS AP A9, A11, A12

PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT48H32M16LF_1.fm - Rev. H 6/07 EN 34 ©2005 Micron Technology, Inc. All rights reserved. 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM Operations Fixed-length WRITE bursts can be truncated with the BURST TERMINATE command. When truncating a WRITE burst, the input data applied coincident with the BURST TERMINATE command will be ignored. The last data written (provided that DQM is LOW at that time) will be the input data applied one clock previous to the BURST TERMINATE command. This is shown in Figure 24 on page 33, where data n is the last desired data element of a longer burst. PRECHARGE The PRECHARGE command (see Figure 25 on page 34) is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row access some specified time ( tRP) after the precharge command is issued. Input A10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs BA0, BA1 select the bank. When all banks are to be precharged, inputs BA0, BA1 are treated as “Don’t Care.” Once a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued to that bank. Figure 25: PRECHARGE Command Power-Down Power-down occurs if CKE is registered LOW coincident with a NOP or COMMAND INHIBIT when no accesses are in progress. If power-down occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down occurs when there is a row active in any bank, this mode is referred to as active power-down. Entering power-down deactivates the input and output buffers, excluding CKE, for maximum power savings while in standby. The device may not remain in the power-down state longer than the refresh period (64ms) since no REFRESH operations are performed in this mode. CS# WE# CAS# RAS# CKE CLK A10 DON’T CARE HIGH All Banks Bank Selected A0–A9, A11, A12 BA0,1 BANK ADDRESS VALID ADDRESS

PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT48H32M16LF_1.fm - Rev. H 6/07 EN 36 ©2005 Micron Technology, Inc. All rights reserved. 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM Operations Figure 28: Deep Power-Down Notes: 1. Clock must be stable prior to CKE going HIGH. 2. DPD = Deep power-down mode command; PRE ALL = Precharge all banks. 3. Exit of deep power-down mode must be foll owed by the sequence described in the Deep Power-Down” section on page 35. In order to exit deep power-down mode, CKE must be asserted HIGH. After exiting, the following sequence is needed in order to enter a new command: 1. Maintain NOP input conditions for a minimum of 100µs. 2. Issue PRECHARGE commands for all banks. 3. Issue two or more AUTO REFRESH commands. The values of the mode register and extended mode register will be retained upon exiting deep power-down. Clock Suspend The clock suspend mode occurs when a column access/burst is in progress and CKE is registered LOW . In the clock suspend mode, the internal clock is deactivated, “freezing” the synchronous logic. For each positive clock edge on which CKE is sampled LOW, the next internal positive clock edge is suspended. Any command or data present on the input balls at the time of a suspended internal clock edge is ignored; any data present on the DQ balls remains driven; and burst counters are not incremented, as long as the clock is suspended (see examples in Figure 29 on page 37 and Figure 30 on page 37). Clock suspend mode is exited by registering CKE HIGH; the internal clock and related operation will resume on the subsequent positive clock edge. tIS All Banks idle with no activity on the data bus Exit deep power-down mode Enter deep power-down mode CKE CK COMMAND DPD2 NOP NOP Vaild3 T0 T1 T2 Ta0 1 Ta1 Ta2 NOP DON’T CARE tCKE Ta3 T = 100µs

PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT48H32M16LF_1.fm - Rev. H 6/07 EN 38 ©2005 Micron Technology, Inc. All rights reserved. 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM Operations Concurrent Auto Precharge An access command (READ or WRITE) to a second bank while an access command with auto precharge enabled on a first bank is executing is not allowed by SDRAMs, unless the SDRAM supports concurrent auto precharge. Micron SDRAMs support concurrent auto precharge. Four cases where concurrent auto precharge occurs are defined below. READ with Auto Precharge 1. Interrupted by a READ (with or without auto precharge): A READ to bank m will inter- rupt a READ on bank n, CL later. The precharge to bank n will begin when the READ to bank m is registered (Figure 31). 2. Interrupted by a WRITE (with or without auto precharge): A WRITE to bank m will interrupt a READ on bank n when registered. DQM should be used two clocks prior to the WRITE command to prevent bus contention. The precharge to bank n will begin when the WRITE to bank m is registered (Figure 32 on page 39). Figure 31: READ With Auto Precharge Interrupted by a READ Notes: 1. DQM is LOW. DON’T CARE CLK DQ DOUT a T2T1 T4 T3 T6 T5T0 COMMAND READ - AP BANK n NOP NOPNOPNOP DOUT a + 1 DOUT d DOUT d + 1 NOP BANK n CL = 3 (bank m) BANK m ADDRESS Idle NOP BANK n, COL a BANK m, COL d READ - AP BANK m Internal States t Page Active READ with Burst of 4 Interrupt Burst, Precharge Page Active READ with Burst of 4 Precharge RP - BANK n tRP - BANK m CL = 3 (bank n)

PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT48H32M16LF_1.fm - Rev. H 6/07 EN 39 ©2005 Micron Technology, Inc. All rights reserved. 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM Operations Figure 32: READ With Auto Precharge Interrupted by a WRITE Notes: 1. DQM is HIGH at T2 to prevent D OUT a + 1 from contending with DIN d at T4. CLK DQ DOUT a T2T1 T4 T3 T6 T5T0 COMMAND NOPNOPNOPNOP DIN d + 1 DIN d DIN d + 2 DIN d + 3 NOP BANK n BANK m ADDRESS Idle NOP DQM BANK n, COL a BANK m, COL d WRITE - AP BANK m Internal States t Page Active READ with Burst of 4 Interrupt Burst, Precharge Page Active WRITE with Burst of 4 Write-Back RP - BANK n t WR - BANK m CL = 3 (bank n) READ - AP BANK n DON’T CARE

PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT48H32M16LF_1.fm - Rev. H 6/07 EN 41 ©2005 Micron Technology, Inc. All rights reserved. 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM Truth Tables Truth Tables Notes: 1. CKE n is the logic state of CKE at clock edge n; CKEn-1 was the state of CKE at the previous clock edge. 2. Current state is the state of the SD RAM immediately prior to clock edge n. 3. COMMAND n is the command registered at clock edge n, and ACTIONn is a result of COMMANDn. 4. All states and sequences not sh own are illegal or reserved. 5. Deep power-down is power savings feature of this Mobile SDRAM device. This command is BURST TERMINATE when CKE is HIGH and deep power-down when CKE is LOW. 6. Exiting power-down at clock edge n will put the device in the all banks idle state in time for clock edge n + 1 (provided that tCKS is met). 7. Exiting self refresh at clock edge n will put the device in the all banks idle state once tXSR is met. COMMAND INHIBIT or NOP commands should be issued on any clock edges occurring during the tXSR period. A minimum of two NOP commands must be provided during the tXSR period. 8. After exiting clock suspend at clock edge n, the device will resume operation and recognize the next command at clock edge n + 1. Table 6: Truth Table – CKE Notes: 1–4 CKEn-1 CKEn Current State Commandn Actionn Notes L L Power-Down X Maintain power-down Self refresh X Maintain self refresh Clock suspend X Mainta in clock suspend Deep power-down X Maintain deep power-down 5 L H Power-Down COMMAND INHIBIT or NOP E xit power-down 6 Deep power-down X Exi t deep power-down 5 Self refresh COMMAND INHIBIT or NOP Exit self refresh 7 Clock suspend X Exit clock suspend 8 H L All banks idle COMMAND INHI BIT or NOP Power-Down entry All banks idle BURST TERMINATE Deep power-down entry 5 All banks idle AUTO REFRESH Self refresh entry Reading or writing VALID Clock suspend entry H H Table 8 on page 44

PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT48H32M16LF_1.fm - Rev. H 6/07 EN 42 ©2005 Micron Technology, Inc. All rights reserved. 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM Truth Tables Notes: 1. This table applies when CKE n-1 was HIGH and CKEn is HIGH (see Table 6 on page 41) and after tXSR has been met (if the previous state was self refresh). 2. This table is bank-specific, except where noted; i.e., the current state is for a specific bank and the commands shown are those allowed to be issued to that bank when in that state. Exceptions are covered in the notes below. 3. Current state definitions: 4. The following states must not be interrupted by a command issued to the same bank. COM- MAND INHIBIT or NOP commands, or allowable commands to the other bank should be issued on any clock edge occurring during these states. Allowable commands to the other bank are determined by its current state and Table 7, and according to Table 8 on page 44. Table 7: Truth Table – Current State Bank n, Command to Bank n Notes: 1–6; notes appear below table Current State CS# RAS# CAS# WE# Command (Action) Notes A n y HXXX COMMAND INHIBIT (NOP/Continue previous operation) LHHH NO OPERATION (NOP/Continue previous operation) Idle L L H H ACTIVE (Select and activate row) LLLH AUTO REFRESH 7 LLLL LOAD MODE REGISTER 7 LLHL PRECHARGE 8 R o w a c t i v e LHLH READ (Select column and start READ burst) 9 LHLL WRITE (Select column and start WRITE burst) 9 LLHL PRECHARGE (Deactivate row in bank or banks) 10 Read (auto precharge disabled) LHLH READ (Select column and start new READ burst) 9 LHLL WRITE (Select column and start WRITE burst) 9 LLHL PRECHARGE (Truncate READ burst, start PRECHARGE) 10 LHHL BURST TERMINATE 11 Write (auto precharge disabled) LHLH READ (Select column and start READ burst) 9 LHLL WRITE (Select column and start new WRITE burst) 9 LLHL PRECHARGE (Truncate WRITE burst, start PRECHARGE) 10 LHHL BURST TERMINATE 11 Idle: The bank has been precharged, and tRP has been met. Row active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses are in progress. Read: A READ burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. Precharging: Starts with registration of a PRECHARGE command and ends when tRP is met. Once tRP is met, the bank will be in the idle state. Row activating: Starts with registration of an ACTIVE command and ends when tRCD is met. Once tRCD is met, the bank will be in the row active state. Read w/auto- precharge enabled: Starts with registration of a READ command with auto precharge enabled and ends when tRP has been met. Once tRP is met, the bank will be in the idle state. Write w/auto- precharge enabled: Starts with registration of a WRITE command with auto precharge enabled and ends whentRP has been met. Once tRP is met, the bank will be in the idle state.

PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT48H32M16LF_1.fm - Rev. H 6/07 EN 43 ©2005 Micron Technology, Inc. All rights reserved. 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM Truth Tables 5. The following states must not be inte rrupted by any executable command; COMMAND INHIBIT or NOP commands must be applied on each positive clock edge during these states. 6. All states and sequences not sh own are illegal or reserved. 7. Not bank-specific; require s that all banks are idle. 8. Does not affect the state of the ba nk and acts as a NOP to that bank. 9. READs or WRITEs listed in the Command (Action) column include READs or WRITEs with auto precharge enabled and READs or WRITEs with auto precharge disabled. 10. May or may not be bank-specific; if all banks are to be precharged, all must be in a valid state for precharging. 11. This command is BURST TERMINATE when CKE is HIGH. Refreshing: Starts with registration of an AUTO REFRESH command and ends when tRFC is met. Once tRFC is met, the SDRAM will be in the all banks idle state. Accessing mode register: Starts with registration of a LOAD MODE REGISTER command and ends when tMRD has been met. Once tMRD is met, the Mobile SDRAM will be in the all banks idle state. Precharging all: Starts with registrati on of a PRECHARGE ALL command and ends when tRP is met. Once tRP is met, all banks will be in the idle state.

PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT48H32M16LF_1.fm - Rev. H 6/07 EN 44 ©2005 Micron Technology, Inc. All rights reserved. 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM Truth Tables Notes: 1. This table applies when CKE n-1 was HIGH and CKEn is HIGH (Table 6 on page 41) and after tXSR has been met (if the previous state was self refresh). 2. This table describes alternate bank operation, except where noted; i.e., the current state is for bank n and the commands shown are those allowed to be issued to bank m (assuming that bank m is in such a state that the given command is allowable). Exceptions are covered in the notes below. 3. Current state definitions: 4. AUTO REFRESH, SELF REFRESH and LOAD MODE REGISTER commands may only be issued when all banks are idle. Table 8: Truth Table – Current State Bank n, Command to Bank m Notes: 1–6; notes appear below and on next page Current State CS# RAS# CAS# WE# Command (Action) Notes A n y HXXX COMMAND INHIBIT (NOP/Continue previous operation) LHHH NO OPERATION (NOP/Continue previous operation) I d l e XXXX Any command otherwise allowed to bank m Row activating, active, or precharging LLH H ACTIVE (Select and activate row) LHLH READ (Select column and start READ burst) 7 LHLL WRITE (Select column and start WRITE burst) 7 LLHL PRECHARGE Read (auto precharge disabled) LLH H ACTIVE (Select and activate row) LHLH READ (Select column and start new READ burst) 7, 8 LHLL WRITE (Select column and start WRITE burst) 7, 9 LLHL PRECHARGE 10 Write (auto precharge disabled) LLH H ACTIVE (Select and activate row) LHLH READ (Select column and start READ burst) 7, 11 LHLL WRITE (Select column and start new WRITE burst) 7, 12 LLHL PRECHARGE 10 Read (with auto precharge) LLH H ACTIVE (Select and activate row) LHLH READ (Select column and start new READ burst) 7, 13, 14 LHLL WRITE (Select column and start WRITE burst) 7, 13, 15 LLHL PRECHARGE 10 Write (with auto precharge) LLH H ACTIVE (Select and activate row) LHLH READ (Select column and start READ burst) 7, 13, 16 LHLL WRITE (Select column and start new WRITE burst) 7, 13, 17 LLHL PRECHARGE 10 Idle: The bank has been precharged, and tRP has been met. Row active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses are in progress. Read: A READ burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. Read w/auto- precharge enabled: Starts with registration of a READ command with auto precharge enabled and ends when tRP has been met. Once tRP is met, the bank will be in the idle state. Write w/auto- precharge enabled: Starts with registration of a WRITE command with auto precharge enabled and ends whentRP has been met. Once tRP is met, the bank will be in the idle state.

PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT48H32M16LF_1.fm - Rev. H 6/07 EN 45 ©2005 Micron Technology, Inc. All rights reserved. 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM Truth Tables 5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current state only. 6. All states and sequences not sh own are illegal or reserved. 7. READs or WRITEs to bank m listed in the Command (Action) column include READs or WRITEs with auto precharge enabled and READs or WRITEs with auto precharge disabled. 8. For a READ without auto precharge interrup ted by a READ (with or without auto pre- charge), the READ to bank m will interrupt the READ on bank n, CL later (Figure 11 on page 24). 9. For a READ without auto precharge interrup ted by a WRITE (with or without auto pre- charge), the WRITE to bank m will interrupt the READ on bank n when registered. DQM should be used one clock prior to the WRITE command to prevent bus contention. 10. Burst in bank n continues as initiated. 11. For a WRITE without auto precharge interru pted by a READ (with or without auto pre- charge), the READ to bank m will interrupt the WRITE on bank n when registered, with the data-out appearing CL later. The last valid WRITE to bank n will be data-in registered one clock prior to the READ to bank m. 12. For a WRITE without auto precharge interrupt ed by a WRITE (with or without auto pre- charge), the WRITE to bank will interrupt the WRITE on bank n when registered. The last valid WRITE to bank n will be data-in registered one clock prior to the READ to bank m. 13. Concurrent auto precharge: Bank n will initiate the auto precharge command when its burst has been interrupted by bank m burst. 14. For a READ with auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt the READ on bank n, CL later. The PRECHARGE to bank n will begin when the READ to bank m is registered. 15. For a READ with auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will interrupt the READ on bank n when registered. DQM should be used two clocks prior to the WRITE command to prevent bus contention. The PRECHARGE to bank n will begin when the WRITE to bank m is registered. 16. For a WRITE with auto precha rge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt the WRITE on bank n when registered, with the data-out appearing CL later. The PRECHARGE to bank n will begin after tWR is met, where tWR begins when the READ to bank m is registered. The last valid WRITE bank n will be data-in registered one clock prior to the READ to bank m. 17. For a WRITE with auto precha rge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m interrupt the WRITE on bank n when registered. The PRECHARGE to bank n will begin after tWR is met, where tWR begins when the WRITE to bank m is regis- tered. The last valid WRITE to bank n will be data registered one clock to the WRITE to bank m.

PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT48H32M16LF_1.fm - Rev. H 6/07 EN 46 ©2005 Micron Technology, Inc. All rights reserved. 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM Electrical Specifications Electrical Specifications Absolute Maximum Ratings Stresses greater than those listed in Table 9 may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Table 9: Absolute Maximum Ratings Voltage/Temperature Min Max Units Voltage on VDD/VDDQ supply relative to VSS –0.3 +2.7 V Voltage on inputs, NC or I/O balls relative to VSS –0.3 +2.7 Storage temperature plastic –55 +150 °C Table 10: DC Electrical Characteristics and Operating Conditions Notes: 1, 5, 6; notes appear on pages 51–52 Parameter/Condition Symbol Min Max Units Notes Supply voltage VDD 1.7 1.95 V I/O supply voltage VDDQ 1.7 1.95 V Input high voltage: Logic 1; All inputs VIH 0.8 × VDDQV DDQ + 0.3 V 22 Input low voltage: Logic 0; All inputs VIL –0.3 +0.3 V 22 Output high voltage: VOH 0.9 × VDDQ– V 2 8 Output low voltage: VOL –0 . 2 V 2 8 Input leakage current: Any input 0V ≤ VIN ≤ VDD (All other balls not under test = 0V) II –1.0 1.0 µA Operating temperature Commercial Industrial TA TA –40 +70 +85

PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT48H32M16LF_1.fm - Rev. H 6/07 EN 47 ©2005 Micron Technology, Inc. All rights reserved. 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM Electrical Specifications Table 11: Electrical Characteristics and Recommended AC Operating Conditions Notes: 5, 6, 8, 9, 11; notes appear on pages 51–52 AC Characteristics Symbol -75 -8 Units NotesParameter Min Max Min Max Access time from CLK (pos. edge) CL = 3 tAC (3) 6 7 ns CL = 2 tAC (2) 9 9 ns Address hold time tAH 1 1 ns Address setup time tAS 1.5 2.5 ns CLK high-level width tCH 3 3 ns CLK low-level width tCL 3 3 ns Clock cycle time CL = 3 tCK (3) 7.5 8 ns 23 CL = 2 tCK (2) 9.6 10 ns 23 CKE hold time tCKH 1 1 ns CKE setup time tCKS 2.5 2.5 ns CS#, RAS#, CAS#, WE#, DQM hold time tCMH 1 1 ns CS#, RAS#, CAS#, WE#, DQM setup time tCMS 1.5 2.5 ns Data-in hold time tDH 1 1 ns Data-in setup time tDS 1.5 2.5 ns Data-out High-Z time CL = 3 tHZ (3) 6 7 ns 10 CL = 2 tHZ (2) 9 9 ns 10 Data-out Low-Z time tLZ 1 1 ns Data-out hold time (load) tOH 2.5 2.5 ns ACTIVE-to-PRECHARGE command tRAS 44 120,000 48 120,000 ns ACTIVE-to-ACTIVE command period tRC 67.5 72 ns ACTIVE-to-READ or WRITE delay tRCD 19 20 ns Refresh period (8,192 rows) tREF 64 64 ms AUTO REFRESH period tRFC 80 80 ns PRECHARGE command period tRP 19 19 ns ACTIVE bank a to ACTIVE bank b command tRRD 2 2 tCK Transition time tT 0.3 1.2 0.5 1.2 ns 7 WRITE recovery time tWR 15 15 ns 31 Exit SELF REFRESH-to-ACTIVE command tXSR 80 80 ns 20

PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT48H32M16LF_1.fm - Rev. H 6/07 EN 48 ©2005 Micron Technology, Inc. All rights reserved. 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM Electrical Specifications Table 12: AC Functional Characteristics Notes: 5, 6, 8, 9,11; notes appear on pages 51–52 Parameter Symbol -75 -8 Units Notes READ/WRITE command to READ/WRITE command tCCD 1 1 tCK 17 CKE to clock disable or power-down entry mode tCKED 1 1 tCK 14 CKE to clock enable or power-down exit mode tPED 1 1 tCK 14 DQM to input data delay tDQD 0 0 tCK 17 DQM to data mask during WRITEs tDQM 0 0 tCK 17 DQM to data High-Z during READs tDQZ 2 2 tCK 17 WRITE command to input data delay tDWD 0 0 tCK 17 Data-in to ACTIVE command tDAL 5 5 tCK 15, 21 Data-in to PRECHARGE command tDPL 2 2 tCK 16, 21 Last data-in to burst STOP command tBDL 1 1 tCK 17 Last data-in to new READ/WRITE command tCDL 1 1 tCK 17 Last data-in to PRECHARGE command tRDL 2 2 tCK 16, 21 LOAD MODE REGISTER command to ACTIVE or REFRESH command tMRD 2 2 tCK 25 Data-out High-Z from PRECHARGE command CL = 3 tROH(3) 3 3 tCK 17 CL = 2 tROH(2) 2 2 tCK 17

PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT48H32M16LF_1.fm - Rev. H 6/07 EN 49 ©2005 Micron Technology, Inc. All rights reserved. 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM Electrical Specifications Table 13: I DD Specifications and Conditions (x16) Notes: 1, 5, 6, 11, 13; notes appear on pages 51–52; VDD = 1.7V to 1.95V, VDDQ = 1.7V to 1.95V Parameter/Condition Symbol Max Units Notes-75 -8 Operating current: Active mode; Burst = 1; READ or WRITE; tRC = tRC (MIN) IDD1 95 90 mA 18, 19 Standby current: Power-down mode; All banks idle; CKE = LOW IDD2P Standard 500 500 µA 29 IDD2P Low Power 300 300 Standby current: Non-power-down mode; All banks idle; CKE = HIGH IDD2N 20 20 mA Standby current: Active mode; CKE = LOW; CS# = HIGH; All banks active; No accesses in progress IDD3P 20 20 mA 12, 19 Standby current: Active mode; CKE = HIGH; CS# = HIGH; All banks active after tRCD met; No accesses in progress IDD3N 30 30 mA 12, 19 Operating current: Burst mode; READ or WRITE; All banks active, half DQs toggling every cycle IDD4 90 85 mA 18, 19 Auto refresh current CKE = HIGH; CS# = HIGH tRFC = tRFC (MIN) IDD5 85 80 mA 12, 18, 19, 26tRFC = 7.8125µs IDD65 5 m A Deep power-down IZZ 10 10 µA 29, 30 Table 14: I DD Specifications and Conditions (x32) Notes: 1, 5, 6, 11, 13; notes appear on pages 51–52; VDD = 1.7V to 1.95V, VDDQ = 1.7V to 1.95V Parameter/Condition Symbol Max Units Notes-75 -8 Operating current: Active mode; Burst = 1; READ or WRITE; tRC = tRC (MIN) IDD1 115 110 mA 18, 19 Standby current: Power-down mode; All banks idle; CKE = LOW IDD2P Standard 500 500 µA 29 IDD2P Low Power 300 300 Standby current: Non-power-down mode; All banks idle; CKE = HIGH IDD2N 20 20 mA Standby current: Active mode; CKE = LOW; CS# = HIGH; All banks active; No accesses in progress IDD3P 20 20 mA 12, 19 Standby current: Active mode; CKE = HIGH; CS# = HIGH; All banks active after tRCD met; No accesses in progress IDD3N 30 30 mA 12, 19 Operating current: Burst mode; READ or WRITE; All banks active, half DQs toggling every cycle IDD4 120 115 mA 18, 19 Auto refresh current CKE = HIGH; CS# = HIGH tRFC = tRFC (MIN) IDD5 85 80 mA 12, 18, 19, 26tRFC = 7.8125µs IDD65 5 m A Deep power-down IZZ 10 10 µA 29, 30

PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT48H32M16LF_1.fm - Rev. H 6/07 EN 50 ©2005 Micron Technology, Inc. All rights reserved. 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM Electrical Specifications Figure 35: Typical Self Refresh Current vs. Temperature Table 15: I DD7 Specifications and Conditions (x16 and x32) Notes:1–6, 8, 11, 13, 15, 27; notes appear on pages 51–52; VDD/VDDQ = 1.70–1.95V Parameter/Condition Symbol Low IDD7 Option “L” Standard IDD7 Option Units Notes Self refresh CKE = LOW; tCK = tCK (MIN); Address and control inputs are stable; Data bus inputs are stable. Full array, 85°C IDD7a 300 500 µA 17, 29 Full array, 70°C IDD7b 230 430 µA Full array, 45°C IDD7c 180 380 µA Full array, 15°C IDD7d 160 360 µA Half array, 85°C IDD7a 250 440 µA Half array, 70°C IDD7b 200 380 µA Half array, 45°C IDD7c 170 350 µA Half array, 15°C IDD7d 150 330 µA 1/4 array, 85°C IDD7a 210 410 µA 1/4 array, 70°C IDD7b 175 365 µA 1/4 array, 45°C IDD7c 155 335 µA 1/4 array, 15°C IDD7d 140 305 µA 1/8 array, 85°C IDD7a 180 390 µA 1/8 array, 70°C IDD7b 155 350 µA 1/8 array, 45°C IDD7c 145 315 µA 1/8 array, 15°C IDD7d 135 300 µA 1/16 array, 85°C IDD7a 170 380 µA 1/16 array, 70°C IDD7b 145 340 µA 1/16 array, 45°C IDD7c 135 320 µA 1/16 array, 15°C IDD7d 130 290 µA 100 150 200 250 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature (°C) Current (µA) Full array Half array 1/4 array 1/8 array 1/16 array

PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT48H32M16LF_1.fm - Rev. H 6/07 EN 51 ©2005 Micron Technology, Inc. All rights reserved. 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM Notes Notes 1. All voltages referenced to V SS. 2. This parameter is sampled. V DD, VDDQ = +1.8V; TA = 25°C; ball under test biased at 0.9V , 1.25V , and 1.4V , respectively; f = 1 MHz. 3. IDD is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time and the outputs open. 4. Enables on-chip refresh and address counters. 5. The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range (–40°C ≤ T A ≤ +85°C for TA on IT parts) is ensured. 6. An initial pause of 100µs is required after power-up, followed by two AUTO REFRESH commands, before proper device operation is ensured. (VDD and VDDQ must be pow- ered up simultaneously. VSS and VSSQ must be at same potential.) The two AUTO REFRESH command wake-ups should be repeated any time the tREF refresh require- ment is exceeded. 7. AC characteristics assume tT = 1ns. 8. In addition to meeting the transition rate specification, the clock and CKE must tran- sit between VIH and VIL (or between VIL and VIH) in a monotonic manner. 9. Outputs measured for 1.8V at 0.9V with equivalent load: Test loads with full DQ driver strength. Performance will vary with actual system DQ bus capacitive loading, termination, and programmed drive strength. 10. tHZ defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL. The last valid data element will meet tOH before going High-Z. 11. AC timing and I DD tests have VIL and VIH, with timing referenced to VIH/2 = crossover point. If the input transition time is longer than tT (MAX), then the timing is refer- enced at VIL (MAX) and VIH (MIN) and no longer at the VIH/2 crossover point. Table 16: Capacitance (x16) Note: 2; notes appear on pages 51–52 Parameter Symbol Min Max Units Input capacitance: CLK CI1 2.0 5.0 pF Input capacitance: All other input-only balls CI2 2.0 5.0 pF Input/Output capacitance: DQs CIO 2.5 6.0 pF Table 17: Capacitance (x32) Note: 2; notes appear on pages 51–52 Parameter Symbol Min Max Units Input capacitance: CLK CI1 2.0 5.0 pF Input capacitance: All other input-only balls CI2 2.0 5.0 pF Input/Output capacitance: DQs CIO 2.5 6.0 pF Q 20pF

PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT48H32M16LF_1.fm - Rev. H 6/07 EN 52 ©2005 Micron Technology, Inc. All rights reserved. 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM Notes 12. Other input signals are allowed to transiti on no more than once every two clocks and are otherwise at valid VIH or VIL levels. 13. I DD specifications are tested after the device is properly initialized. 14. Timing actually specified by tCKS; clock(s) specified as a reference only at minimum cycle rate. 15. Timing actually specified by tWR plus tRP; clock(s) specified as a reference only at minimum cycle rate. 16. Timing actually specified by tWR. 17. Required clocks are specified by JEDEC functionality and are not dependent on any timing parameter. 18. The I DD current will increase or decrease proportionally according to the amount of frequency alteration for the test condition. 19. Address transitions average on e transition every two clocks. 20. CLK must be toggled a minimum of two times during this period. 21. Based on tCK = 7.5ns for -75, and tCK = 8ns for -8, CL = 3. 22. V IH overshoot: VIH (MAX) = VDDQ + 2V for a pulse width ≤ 3ns, and the pulse width cannot be greater than one third of the cycle rate. VIL undershoot: VIL (MIN) = –2V for a pulse width ≤ 3ns. 23. The only time that the clock frequency is allowed to change is during clock stop, power down, or self-refresh modes. 24. Auto precharge mode only. The precharge timing budget ( tRP) begins at 7ns for -8 after the first clock delay, after the last WRITE is executed. May not exceed limit set for precharge mode. 25. Parameter guaranteed by design. 26. CKE is HIGH during refresh command period tRFC (MIN), else CKE is LOW. The IDD7 limit is actually a nominal value and does not result in a fail value. 27. Values for I DD7 for 85°C are 100 percent tested. Values for 70°C, 45°C, and 15°C are sampled only. 28. I OUT = 4mA for full-drive strength. Other drive strengths require appropriate scale. 29. Current is taken 500ms after entering into this operating mode to allow tester mea- suring unit settling time. 30. Deep power-down current is a nominal valu e at 25°C. This parameter is not tested. 31. There must be one tCK during the tWR time for WRITE auto precharge.

PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT48H32M16LF_1.fm - Rev. H 6/07 EN 53 ©2005 Micron Technology, Inc. All rights reserved. 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM Timing Diagrams Timing Diagrams Figure 36: Initialize and Load Mode Register Notes: 1. PRE = PRECHARGE comman d, AR = AUTO REFRESH command, LMR = LOAD MODE REGISTER command. 2. Only NOPs or COMMAND INHIBITs may be issued during tRFC time. 3. At least one NOP or COMMAND INHIBIT is required during tMRD time. CKE BA0, BA1 Load Extended Mode Register Load Mode Register tCKS Power-up: VDD and CLK stable T = 100µs tCKH DQM DQ High-Z A0-A9, A11 VALID A10 VALID CLK tCK COMMAND1 ARNOP LMRAR LMR VALID tCMS tCMH tAS tAH BA0 = L, BA1 = L CODE CODE tAS tAH CODE CODE PRE ALL BANKS tAS tAH T0 T1 DON’T CARE ) ()() tRP tMRD3tMRD3tRFC2 tRFC2 VALID BA0 = L, BA1 = L BA0 = L, BA1 = H Precharge all banks Tn + 1 To + 1 Tp + 1 T q + 1 Tr + 1

PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT48H32M16LF_1.fm - Rev. H 6/07 EN 54 ©2005 Micron Technology, Inc. All rights reserved. 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM Timing Diagrams Figure 37: Power-Down Mode Notes: 1. Violating refresh requirements during power-down may result in a loss of data. See Table 11 on page 47. t CH t CL t CK Two clock cycles CKE CLK DQ All banks idle, enter power-down mode Precharge all active banks Input buffers gated off while in power-down mode Exit power-down mode DON’T CARE t CKS t CKS COMMAND t CMH t CMS PRECHARGE NOP NOP ACTIVE NOP All banks idle BA0, BA1 BANK BANK(S) High-Z t AH t AS t CKH t CKS DQM A0–A9, A11, A12 ROW ALL BANKS SINGLE BANK A10 ROW T0 T1 T2 Tn + 1 Tn + 2

PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT48H32M16LF_1.fm - Rev. H 6/07 EN 55 ©2005 Micron Technology, Inc. All rights reserved. 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM Timing Diagrams Figure 38: Clock Suspend Mode Notes: 1. For this example, BL = 2, CL = 3, and auto precharge is disabled. 2. A9 and A11 = “Don’t Care.” See Table 11 on page 47. t CH t CL t CK t AC t LZ DQM CLK DQ A10 t OH DOUT m t AH t AS t AH t AS t AH t AS BANK t DH DOUT e t AC t HZ DOUT m + 1 COMMAND t CMH t CMS NOP NOP NOP NOP NOP READ WRITE DON’T CARE UNDEFINED CKE t CKS t CKH BANK COLUMN m t DS DOUT e + 1 NOP t CKH t CKS t CMH t CMS

2 COLUMN e

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 BA0, BA1 A0–A9, A11, A12

PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT48H32M16LF_1.fm - Rev. H 6/07 EN 56 ©2005 Micron Technology, Inc. All rights reserved. 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM Timing Diagrams Figure 39: Auto Refresh Mode Notes: 1. Each AUTO REFRESH command performs a REFR ESH cycle. Back-to-back commands are not required. See Table 11 on page 47. UNDEFINED DON’T CARE t CH t CL t CK CKE CLK DQ t RFC t RP COMMAND t CMH t CMS NOP NOP BANK ACTIVE AUTO REFRESH NOP NOP PRECHARGE Precharge all active banks AUTO REFRESH t RFC High-Z BANK(S) t AH t AS t CKH t CKS NOP ROW ALL BANKS SINGLE BANK A10 ROW T0 T1 T2 Tn + 1 To + 1 BA0, BA1 A0–A9, A11, A12 DQM

PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT48H32M16LF_1.fm - Rev. H 6/07 EN 57 ©2005 Micron Technology, Inc. All rights reserved. 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM Timing Diagrams Figure 40: Self Refresh Mode Notes: 1. Each AUTO REFRESH command performs a REFR ESH cycle. Back-to-back commands are not required. See Table 11 on page 47. t CH t CL t CK t RP CKE CLK DQ Enter self refresh mode Precharge all active banks t XSR CLK stable prior to exiting self refresh mode Exit self refresh mode (Restart refresh time base) DON’T CARE COMMAND t CMH t CMS AUTO REFRESH PRECHARGE NOP NOP BANK(S) High-Z t CKS AH AS AUTO REFRESH > t RAS t CKH t CKS t t ALL BANKS SINGLE BANK A10 T0 T1 T2 Tn + 1 To + 1 To + 2 BA0, BA1 DQM A0–A9, A11, A12

PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT48H32M16LF_1.fm - Rev. H 6/07 EN 58 ©2005 Micron Technology, Inc. All rights reserved. 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM Timing Diagrams Figure 41: READ – Without Auto Precharge Notes: 1. For this example, BL = 4, CL = 2, and th e READ burst is followed by a manual PRECHARGE. ALL BANKS t CH t CL t CK t AC t LZ t RP t RAS t RCD CL t RC CKE CLK DQ A10 t OH DOUT m t CMH t CMS t AH t AS t AH t AS t AH t AS ROW ROW BANK BANK(S) BANK ROW ROW BANK t HZ t OH DOUT m + 3 t AC t OH t AC t OH t AC DOUT m + 2 DOUT m + 1 COMMAND t CMH t CMS PRECHARGE NOP NOP NOP ACTIVE NOP READ NOP ACTIVE DISABLE AUTO PRECHARGE SINGLE BANK DON’T CARE UNDEFINED tCKH t CKS COLUMN m T0 T1 T2 T4 T3 T5 T6 T7 T8 BA0, BA1 DQM ADDR

PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT48H32M16LF_1.fm - Rev. H 6/07 EN 59 ©2005 Micron Technology, Inc. All rights reserved. 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM Timing Diagrams Figure 42: READ – With Auto Precharge Notes: 1. For this example, BL = 4, CL = 2. t CH t CL t CK t AC t LZ t RP t RAS t RCD CL t RC CKE CLK DQ A10 t OH DOUT m t CMH t CMS t AH t AS t AH t AS t AH t AS ROW ROW BANK BANK ROW ROW BANK t HZ t OH DOUT m + 3 t AC t OH t AC t OH t AC DOUT m + 2 DOUT m + 1 COMMAND t CMH t CMS NOP NOP NOP NOP ACTIVE NOP READ NOP ACTIVE ENABLE AUTO PRECHARGE DON’T CARE UNDEFINED tCKH t CKS COLUMN m T0 T1 T2 T4 T3 T5 T6 T7 T8 BA0, BA1 DQM ADDR

PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT48H32M16LF_1.fm - Rev. H 6/07 EN 60 ©2005 Micron Technology, Inc. All rights reserved. 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM Timing Diagrams Figure 43: Single READ – Without Auto Precharge Notes: 1. For this example, BL = 1, CL = 2, and th e READ burst is followed by a manual PRECHARGE. ALL BANKS t CH t CL t CK t AC t LZ t RP t RAS t RCD CL t RC CKE CLK DQ A10 t OH DOUT m t CMH t CMS t AH t AS t AH t AS t AH t AS ROW ROW BANK BANK(S) BANK ROW ROW BANK t HZ COMMAND t CMH t CMS NOP NOP3 NOP3 PRECHARGE ACTIVE NOP READ ACTIVE NOP DISABLE AUTO PRECHARGE SINGLE BANK DON’T CARE UNDEFINED tCKH t CKS COLUMN m T0 T1 T 2 T4 T3 T5 T 6 T7 T 8 BA0, BA1 DQM ADDR

PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT48H32M16LF_1.fm - Rev. H 6/07 EN 61 ©2005 Micron Technology, Inc. All rights reserved. 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM Timing Diagrams Figure 44: Single READ – With Auto Precharge Notes: 1. For this example, BL = 1, CL = 2, and th e READ burst is followed by an auto precharge. t CH t CL t CK t AC t RP t RAS t RCD CL t RC CKE CLK DQ A10 t OH DOUT m t CMH t CMS t AH t AS t AH t AS t AH t AS ROW ROW BANK BANK ROW ROW BANK tHZ COMMAND t CMH t CMS NOP NOP NOP3 NOP3 READ ACTIVE NOP ACTIVE NOP ENABLE AUTO PRECHARGE DON’T CARE UNDEFINED tCKH t CKS COLUMN m T0 T1 T2 T4 T3 T5 T6 T7 T8 BA0, BA1 DQM ADDR

PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT48H32M16LF_1.fm - Rev. H 6/07 EN 62 ©2005 Micron Technology, Inc. All rights reserved. 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM Timing Diagrams Figure 45: Alternating Bank Read Accesses Notes: 1. For this example, BL = 4, CL = 2. DON’T CARE UNDEFINED ENABLE AUTO PRECHARGE t CH t CL t CK t AC t LZ CLK DQ A10 t OH DOUT m t CMH t CMS t AH t AS t AH t AS t AH t AS ROW ROW ROW ROW t OH DOUT m + 3 t AC t OH t AC t OH t AC DOUT m + 2 DOUT m + 1 COMMAND t CMH t CMS NOP NOP ACTIVE NOP READ NOP ACTIVE t OH DOUT b t AC t AC READ ENABLE AUTO PRECHARGE ROW ACTIVE ROW BANK 0 BANK 0 BANK 3 BANK 3 BANK 0 CKE t CKH t CKS COLUMN m COLUMN b T0 T1 T2 T4 T3 T5 T6 T7 T8 t RP - bank 0 t RAS - bank 0 t RCD - bank 0 t RCD - bank 0 CL - bank 0 t RCD - bank 4 CL - bank 4 t t RC - bank 0 RRD BA0, BA1 DQM ADDR

PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT48H32M16LF_1.fm - Rev. H 6/07 EN 63 ©2005 Micron Technology, Inc. All rights reserved. 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM Timing Diagrams Figure 46: READ – Continuous-Page Burst Notes: 1. For this example, CL = 2. t CH t CL t CK t AC t LZ t RCD CAS Latency CKE CLK DQ A10 t OH Dout m t CMH t CMS t AH t AS t AH t AS t AC t OH DOUT m+1 ROW ROW t HZ t AC t OH DOUT m+1 t AC t OH DOUT m+2 t AC t OH DOUT m-1 t AC t OH Full-page burst does not self-terminate. Can use BURST TERMINATE command. Full page completed All locations within same row DON’T CARE UNDEFINED COMMAND t CMH t CMS NOP NOP NOP ACTIVE NOP READ NOP BURST TERM NOP NOP NOP t AH t AS BANK BANK t CKH t CKS COLUMN m T0 T1 T2 T4 T3 T5 T6 Tn + 1 Tn + 2 Tn + 3 Tn + 4 BA0, BA1 DQM ADDR DOUT m

PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT48H32M16LF_1.fm - Rev. H 6/07 EN 64 ©2005 Micron Technology, Inc. All rights reserved. 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM Timing Diagrams Figure 47: READ – DQM Operation Notes: 1. For this example, CL = 2. t CH t CL t CK t AC t AC t LZ t RCD CL CKE CLK DQ A10 t OH DOUT m t CMH t CMS t AH t AS t AH t AS t AH t AS ROW BANK ROW BANK t HZ t AC t LZ t OH DOUT m + 2 t OH DOUT m + 3 t HZ COMMAND t CMH t CMS NOP NOP NOP NOP ACTIVE NOP READ NOP NOP DISABLE AUTO PRECHARGE ENABLE AUTO PRECHARGE DON’T CARE UNDEFINED tCKH t CKS COLUMN m T0 T1 T 2 T4 T3 T5 T 6 T7 T 8 BA0, BA1 DQM ADDR

PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT48H32M16LF_1.fm - Rev. H 6/07 EN 65 ©2005 Micron Technology, Inc. All rights reserved. 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM Timing Diagrams Figure 48: WRITE – Without Auto Precharge Notes: 1. For this example, BL = 1, and the WR ITE burst is followed by an auto precharge. 2. 15ns is required between <D IN m + 3> and the PRECHARGE command, regardless of fre- quency. DISABLE AUTO PRECHARGE ALL BANKs t CH t CL t CK t RP t RAS t RCD t RC CKE CLK DQ A10 t CMH t CMS t AH t AS ROW BANK BANK ROW BANK tWR2 DON’T CARE DIN m t DH t DS DIN m + 1 DIN m + 2 DIN m + 3 COMMAND t CMH t CMS NOP NOP NOP ACTIVE NOP WRITE PRECHARGE NOP NOP ROW BANK ROW t AH t AS t AH t AS t DH t DS t DH t DS t DH t DS SINGLE BANK t CKH t CKS COLUMN m T0 T1 T 2 T4 T3 T5 T 6 T7 T 8 T 9 DQM BA0, BA1 ADDR ACTIVE

PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT48H32M16LF_1.fm - Rev. H 6/07 EN 66 ©2005 Micron Technology, Inc. All rights reserved. 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM Timing Diagrams Figure 49: WRITE – With Auto Precharge Notes: 1. For this example, BL = 4. 2. There must be one tCK during the tWR time for WRITE auto precharge. ENABLE AUTO PRECHARGE t CH t CL t CK t RP t RAS t RCD t RC CKE CLK DQ A10 t CMH t CMS t AH t AS ROW BANK ROW BANK tWR2 DON’T CARE UNDEFINED DIN m t DH t DS DIN m + 1 DIN m + 2 DIN m + 3 COMMAND t CMH t CMS NOP NOP NOP ACTIVE NOP WRITE NOP NOP NOP ROW BANK ROW t AH t AS t AH t AS t DH t DS t DH t DS t DH t DS t CKH t CKS COLUMN m T0 T1 T 2 T4 T3 T5 T 6 T7 T 8 T 9 DQM BA0, BA1 ADDR ACTIVE

PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT48H32M16LF_1.fm - Rev. H 6/07 EN 67 ©2005 Micron Technology, Inc. All rights reserved. 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM Timing Diagrams Figure 50: Single WRITE – Without Auto Precharge Notes: 1. For this example, BL = 1, and the WR ITE burst is followed by a manual PRECHARGE. 2. 15ns is required between <D IN m> and the PRECHARGE command, regardless of frequency. 3. PRECHARGE comman d not allowed or tRAS would be violated. ALL BANKS t CH t CL t CK t RP t RAS t RCD tWR2 t RC CKE CLK DQ A10 t CMH t CMS t AH t AS t AH t AS t AH t AS ROW BANK BANK BANK ROW ROW BANK COMMAND t CMH t CMS NOP NOP3 NOP3 PRECHARGE ACTIVE NOP WRITE ACTIVE NOP DISABLE AUTO PRECHARGE SINGLE BANK DON’T CARE tCKH t CKS COLUMN m T0 T1 T2 T4 T3 T5 T6 T7 T8 BA0, BA1 DQM ADDR DIN m t DH t DS

PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT48H32M16LF_1.fm - Rev. H 6/07 EN 68 ©2005 Micron Technology, Inc. All rights reserved. 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM Timing Diagrams Figure 51: Single WRITE – With Auto Precharge Notes: 1. For this example, BL = 1, and the WR ITE burst is followed by a manual PRECHARGE. 2. There must be one tCK during the tWR time for WRITE auto precharge. t CH t CL t CK CKE CLK DQ A10 t CMH t CMS t AH t AS t AH t AS t AH t AS ROW ROW BANK BANK ROW ROW BANK COMMAND t CMH t CMS NOP NOP NOP NOP WRITE ACTIVE NOP NOP ACTIVE NOP ENABLE AUTO PRECHARGE DON’T CARE tCKH t CKS COLUMN m T0 T1 T2 T4 T3 T5 T6 T7 T8 T9 BA0, BA1 DQM ADDR t RP t RAS t RCD t RC tWR DIN m t DH t DS

PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT48H32M16LF_1.fm - Rev. H 6/07 EN 69 ©2005 Micron Technology, Inc. All rights reserved. 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM Timing Diagrams Figure 52: Alternating Bank Write Accesses Notes: 1. For this example, BL = 4. DON’T CARE ENABLE AUTO PRECHARGE t CH t CL t CK CLK DQ A10 t CMH t CMS t AH t AS t AH t AS t AH t AS ROW ROW ROW ROW COMMAND t CMH t CMS NOP NOP ACTIVE NOP WRITE NOP NOP ACTIVE WRITE ENABLE AUTO PRECHARGE ROW ACTIVE ROW BANK 0 BANK 0 BANK 1 BANK 1 BANK 0 CKE t CKH t CKS COLUMN m COLUMN b T0 T1 T2 T4 T3 T5 T6 T7 T8 T9 t RP - bank 0 t RAS - bank 0 t RCD - bank 0 t RCD - bank 0 t WR - bank 1 t WR - bank 0 t RCD - bank 1 t t RC - bank 0 RRD BA0, BA1 DQM ADDR DIN m t DH t DS DIN m + 1 DIN m + 2 DIN m + 3 t DH t DS t DH t DS t DH t DS DIN b t DH t DS DIN b + 1 t DH t DS DIN b + 2 t DH t DS DIN m + 3 t DH t DS

PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT48H32M16LF_1.fm - Rev. H 6/07 EN 70 ©2005 Micron Technology, Inc. All rights reserved. 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM Timing Diagrams Figure 53: WRITE – Continuous-Page Burst Notes: 1. tWR must be satisfied prior to PRECHARGE command. 2. Page left open; no tRP. t CH t CL t CK t RCD CKE CLK A10 t CMS t AH t AS t AH t AS ROW ROW Full-page burst does not self-terminate. Can use BURST TERMINATE command to stop. 1, 2 Full page completed DON’T CARE COMMAND t CMH t CMS NOP NOP NOP ACTIVE NOP WRITE BURST TERM NOP NOP DQ DIN m t DH t DS DIN m + 1 DIN m + 2 DIN m + 3 t DH t DS t DH t DS t DH t DS DIN m - 1 t DH t DS t AH t AS BANK BANK t CMH t CKH t CKS All locations within same row COLUMN m T0 T1 T2 T3 T4 T5 Tn + 1 Tn + 2 Tn + 3 BA0, BA1 DQM ADDR

PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT48H32M16LF_1.fm - Rev. H 6/07 EN 71 ©2005 Micron Technology, Inc. All rights reserved. 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM Timing Diagrams Figure 54: WRITE – DQM Operation Notes: 1. For this example, BL = 4. DON’T CARE t CH t CL t CK t RCD CKE CLK DQ A10 t CMS t AH t AS ROW BANK ROW BANK ENABLE AUTO PRECHARGE DIN m + 3 t DH t DS DIN m DIN m + 2 t CMH COMMAND NOP NOP NOP ACTIVE NOP WRITE NOP NOP t CMS t CMH t DH t DS t DH t DS t AH t AS t AH t AS DISABLE AUTO PRECHARGE t CKH t CKS COLUMN m T0 T1 T2 T3 T4 T5 T6 T7 BA0, BA1 DQM ADDR

PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT48H32M16LF_1.fm - Rev. H 6/07 EN 72 ©2005 Micron Technology, Inc. All rights reserved. 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM Package Dimensions Package Dimensions Figure 55: 54-Ball VFBGA (10mm x 11.5mm) Notes: 1. All dimensions are in millimeters. 2. Green packaging composition is available upon request. Ball A1 ID Mold compound: epoxy novolac Substrate material: plastic laminate Ball A1 ID

0.1 A A

0.65 ±0.05 54X Ø0.45 6.4 3.2 5.75 ±0.05 11.5 ±0.1

0.8 TYP

6.4 3.2 5 ±0.05 10 ±0.10

1.0 MAX

balls post reflow. Pre-reflow balls are Ø0.42 on Ø0.40 SMD ball pads. Solder ball material: SAC305 (96.5% Sn, 3% Ag, 0.5% Cu) or SAC105 (98.5% Sn, 1% Ag, 0.5% Cu) 9 8 7 3 2 1 A B C D E F G H J

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 prodmktg@micron.com www.micron.com Customer Comment Line: 800-932-4992 Micron, the M logo, the Micron logo, and Endur-IC are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. This data sheet contains minimum and maximum limits specified over the complete power supply and temperature range for production devices. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM Package Dimensions PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT48H32M16LF_1.fm - Rev. H 6/07 EN 73 ©2005 Micron Technology, Inc. All rights reserved. Figure 56: 90-Ball VFBGA (10mm x 13mm) Notes: 1. All dimensions are in millimeters. 2. Green packaging composition is available upon request. Ball A1 ID Mold compound: epoxy novolac Substrate material: plastic laminate Solder ball material: SAC305 (96.5 % Sn, 3% Ag, 0.5% Cu) or SAC105 (98.5 % Sn, 1% Ag, 0.5% Cu) 5.6 0.65 ±0.05 Seating plane A 11.2 6.4 0.1 A 90X Ø0.45 Dimensions apply to solder balls post reflow. The pre- reflow balls are Ø0.42 on Ø0.40 SMD ball pads. 13 ±0.1 Ball A1 ID 6.5 ±0.05 3.2 10 ±0.1 5 ±0.05 9 8 7 3 2 1 A B C D E F G H J K L M N P R