MT48H16M16LF

MT48H8M32LF MICRON | Alldatasheet

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PDF:09005aef8219eeeb/Source: 09005aef8219eedd Micron Technology, Inc., reserves the right to change products or specifications without notice. MT48H16M16LF__1.fm - Rev F 4/07 EN 1 ©2006 Micron Technology, Inc. All rights reserved. Mobile SDRAM MT48H16M16LF – 4 Meg x 16 x 4 banks MT48H8M32LF – 2 Meg x 32 x 4 banks

• Fully synchronous; all signals registered on positive edge of system clock V DD/VDDQ = 1.70–1.95V  Internal, pipelined operat ion; column address can be changed every clock cycle  Four internal banks for concurrent operation  Programmable burst lengths: 1, 2, 4, 8, or continuous page  Auto precharge, includes concurrent auto precharge  Auto refresh and self refresh modes  LVTTL-compatible inputs and outputs  On-chip temperature sensor to control refresh rate  Partial-array self refresh (PASR)  Deep power-down (DPD)  Selectable output drive (DS)  64ms refresh period (8,192 rows) Notes: 1. For continuous page burst, contact factory for availability. Options Marking V DD/VDDQ – 1.8V/1.8V H C o n f i g u r a t i o n – 16 Meg x 16 (4 Meg x 16 x 4 banks) 16M16 – 8 Meg x 32 (2 Meg x 32 x 4 banks) 8M32 P l a s t i c “ g r e e n ” p a c k a g e – 54-ball VFBGA (8mm x 9mm) BF – 90-ball VFBGA (8mm x 13mm) B5  Timing – cycle time – 7.5ns at CL = 3 -75 – 8ns at CL = 3 -8 P o w e r – Standard IDD2P/IDD7N o n e – Low IDD2P/IDD7L  Operating temperature range – Commercial (0° to +70°C) None – Industrial (–40°C to +85°C) IT D e s i g n r e v i s i o n : G Table 1: Addressing

16 Meg x 16 8 Meg x 32

Configuration 4 Meg x 16 x 4 banks

2 Meg x 32 x 4

Row addressing 8K (A0–A12) 4K (A0–A11) Bank addressing 4 (BA0, BA1) 4 (BA0, BA1) Column addressing 512 (A0–A8) 512 (A0–A8) Table 2: Key Timing Parameters CL = CAS (READ) latency Speed Grade Clock Rate (MHz) Access Time Data Setup Time Data Hold TimeCL = 2 CL = 3 CL = 2 CL = 3 -75 104 133 8ns 6ns 1.5ns 1ns -8 100 125 9ns 7ns 2.5ns 1ns

PDF:09005aef8219eeeb/Source: 09005aef8219eedd Micron Technology, Inc., reserves the right to change products or specifications without notice. MT48H16M16LFTOC.fm - Rev F 4/07 EN 2 ©2006 Micron Technology, Inc. All rights reserved. 256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM Table of Contents Table of Contents

PDF:09005aef8219eeeb/Source: 09005aef8219eedd Micron Technology, Inc., reserves the right to change products or specifications without notice. MT48H16M16LFLOT.fm - Rev F 4/07 EN 4 ©2006 Micron Technology, Inc. All rights reserved. 256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM List of Tables List of Tables

PDF:09005aef8219eeeb/Source: 09005aef8219eedd Micron Technology, Inc., reserves the right to change products or specifications without notice. MT48H16M16LF_2.fm - Rev F 4/07 EN 5 ©2006 Micron Technology, Inc. All rights reserved. 256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM General Description Figure 1: 256Mb Mobile SDRAM Part Numbering General Description The Micron® 256Mb Mobile SDRAM is a high-speed CMOS, dynamic random-access memory containing 268,435,456-bits. It is internally configured as a quad-bank DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the x16’ s 67,108,864-bit banks is organized as 8,192 rows by 512 columns by 16 bits. Each of the x32’ s 67,108,864-bit banks is organized as 4,096 rows by 512 columns by 32 bits. Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed. The address bits registered coincident with the READ or WRITE command are used to select the starting column location for the burst access. The SDRAM provides for programmable read or write burst lengths (BLs) of 1, 2, 4, or 8 page locations with a read burst terminate option. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. The 256Mb SDRAM uses an internal pipelined architecture to achieve high-speed opera- tion. It also allows the column address to be changed on every clock cycle to achieve a high-speed, fully random access. Precharging one bank while accessing one of the other three banks will hide the precharge cycles and provide seamless high-speed, random- access operation. Speed Grade tCK = 7.5ns tCK = 8.0ns -75 IT Operating Temp. Commercial Industrial L Power Standard IDD2P/IDD7 Low IDD2P/IDD7 Example Part Number: MT48H8M32LFB5-75LIT Mobile ConfigurationMT48 Package Speed Temp. Power Configuration

16 Meg x 16

8 Meg x 32

8 x 9 VFBGA (lead-free) 8 x 13 VFBGA (lead-free) H VDD/ VDDQ VDD/VDDQ 1.8V/1.8V BF Revision– Revision :G Design Revision

PDF:09005aef8219eeeb/Source: 09005aef8219eedd Micron Technology, Inc., reserves the right to change products or specifications without notice. MT48H16M16LF_2.fm - Rev F 4/07 EN 6 ©2006 Micron Technology, Inc. All rights reserved. 256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM Functional Block Diagrams The 256Mb SDRAM is designed to operate in 1.8V low-power memory systems. An auto refresh mode is provided, along with a power-saving deep power-down mode. All inputs and outputs are LVTTL-compatible. SDRAM offers substantial advances in DRAM operating performance, including the ability to synchronously burst data at a high data rate with automatic column-address generation, the ability to interleave between internal banks in order to hide precharge time, and the capability to randomly change column addresses on each clock cycle during a burst access. Functional Block Diagrams Figure 2: 16 Meg x 16 SDRAM RAS# CAS# ROW- ADDRESS MUX CLK CS# WE# CKE CONTROL LOGIC COLUMN- ADDRESS COUNTER/ LATCH MODE REGISTER COMMAND DECODE A0–A12, BA0, BA1 UDQM, LDQM ADDRESS REGISTER 15 256 (x16) 8,192 I/O GATING DQM MASK LOGIC READ DATA LATCH WRITE DRIVERS COLUMN DECODER BANK0 MEMORY ARRAY (8,192 x 512 x 16) BANK0 ROW- ADDRESS LATCH DECODER 8,192 Sense amplifiers BANK CONTROL LOGIC DQ0– DQ15 Bank1 Bank2 Bank3 2 2 REFRESH COUNTER EXT MODE REGISTER BA1 BA0 Bank 0 0 0 0 1 1 1 0 2 1 1 3 DATA OUTPUT REGISTER DATA INPUT REGISTER

PDF:09005aef8219eeeb/Source: 09005aef8219eedd Micron Technology, Inc., reserves the right to change products or specifications without notice. MT48H16M16LF_2.fm - Rev F 4/07 EN 7 ©2006 Micron Technology, Inc. All rights reserved. 256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM Functional Block Diagrams Figure 3: 8 Meg x 32 SDRAM RAS# CAS# ROW- ADDRESS MUX CLK CS# WE# CKE CONTROL LOGIC COLUMN- ADDRESS COUNTER/ LATCH MODE REGISTER COMMAND DECODE A0–A11, BA0, BA1 DQM0- DQM3 ADDRESS REGISTER 14 512 (x32) 4,096 COLUMN DECODER BANK0 MEMORY ARRAY (4,096 x 512 x 32) BANK0 ROW- ADDRESS LATCH DECODER 4,096 SENSE AMPLIFIERS BANK CONTROL LOGIC DQ0– DQ31 DATA INPUT REGISTER DATA OUTPUT REGISTER BANK1 BANK2 BANK3 4 4 REFRESH COUNTER BA1 BA0 Bank 0 0 0 0 1 1 1 0 2 1 1 3 EXT MODE REGISTER I/O GATING DQM MASK LOGIC READ DATA LATCH WRITE DRIVERS

PDF:09005aef8219eeeb/Source: 09005aef8219eedd Micron Technology, Inc., reserves the right to change products or specifications without notice. MT48H16M16LF_2.fm - Rev F 4/07 EN 8 ©2006 Micron Technology, Inc. All rights reserved. 256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM Ball Assignments Ball Assignments Figure 4: 54-Ball FBGA (Top View) – 8mm x 9mm A B C D E F G H J VSS DQ14 DQ12 DQ10 DQ8 UDQM A12 V SS DQ15 DQ13 DQ11 DQ9 DNU CLK A11 V SSQ VDDQ VSSQ VDDQ VSS CKE V DDQ VSSQ VDDQ VSSQ VDD CAS# BA0 DQ0 DQ2 DQ4 DQ6 LDQM RAS# BA1 V DD DQ1 DQ3 DQ5 DQ7 WE# CS# A10 V DD 1 2 3 4 5 6 7 8 9

PDF:09005aef8219eeeb/Source: 09005aef8219eedd Micron Technology, Inc., reserves the right to change products or specifications without notice. MT48H16M16LF_2.fm - Rev F 4/07 EN 9 ©2006 Micron Technology, Inc. All rights reserved. 256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM Ball Assignments Figure 5: 90-Ball VFBGA (Top View) – 8mm x 13mm 1234 6789 5 DQ26 DQ28 VSSQ VSSQ VDDQ VSS CLK DQM1 VDDQ VSSQ VSSQ DQ11 DQ13 DQ24 V DDQ DQ27 DQ29 DQ31 DQM3 CKE DQ8 DQ10 DQ12 V DDQ DQ15 VSS VSSQ DQ25 DQ30 NC NC NC VSS DQ9 DQ14 VSSQ VSS VDD VDDQ DQ22 DQ17 NC A10 NC BA0 CAS# VDD DQ6 DQ1 VDDQ VDD DQ21 DQ19 V DDQ VDDQ VSSQ VDD A11 RAS# DQM0 VSSQ VDDQ VDDQ DQ4 DQ2 DQ23 V SSQ DQ20 DQ18 DQ16 DQM2 BA1 CS# WE# DQ7 DQ5 DQ3 V SSQ DQ0 A B C D E F G H J K L M N P R DNU

PDF:09005aef8219eeeb/Source: 09005aef8219eedd Micron Technology, Inc., reserves the right to change products or specifications without notice. MT48H16M16LF_2.fm - Rev F 4/07 EN 10 ©2006 Micron Technology, Inc. All rights reserved. 256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM Ball Descriptions Ball Descriptions Table 3: VFBGA Ball Descriptions 54-Ball VFBGA 90-Ball VFBGA Symbol Type Description F2 J1 CLK Input Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the positive edge of CLK. CLK also increments the internal burst counter and controls the output registers. F3 J2 CKE Input Clock enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal. Deactivating the clock provides precharge power- down and SELF REFRESH operation (all banks idle), ACTIVE power-down (row active in any bank), Deep power-down (all banks idle), or CLOCK SUSPEND operation (burst/access in progress). CKE is synchronous except after the device enters power-down and self refresh modes, where CKE becomes asynchronous until after exiting the same mode. The input buffers, including CLK, are disabled during power-down and self refresh modes, providing low standby power. G9 J8 CS# Input Chip select: CS# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when CS# is registered HIGH. CS# provides for external bank selection on systems with multiple banks. CS# is considered part of the command code. F7, F8, F9 K7, J9, K8 CAS#, RAS#, WE# Input Command inputs: RAS#, CAS#, and WE# (along with CS#) define the command being entered. F1, E8 K9, K1, F8, F2 UDQM LDQM, DQM0– DQM3 Input Input/output mask: DQM is sampled HIGH and is an input mask signal for write accesses and an output enable signal for read accesses. Input data is masked during a WRITE cycle. The output buffers are placed in a High-Z state (two-clock latency) during a READ cycle. For the x16, LDQM corresponds to DQ0–DQ7 and UDQM corresponds to DQ8–DQ16. For the x32, DQM0 corresponds to DQ0–DQ7, DQM1 corresponds to DQ8–DQ15, DQM2 corresponds to DQ16–DQ23, and DQM3 corresponds to DQ24–DQ31. DQM0–DQM3 (or LDQM and UDQM if x16) are considered same state when referenced as DQM. DQM loading is designed to match that of DQ balls. G7, G8 J7, H8 BA0, BA1 Input Bank address input(s): BA0 and BA1 define to which bank the ACTIVE, READ, WRITE, or PRECHARGE command is being applied. These balls also provide the op-code during a LOAD MODE REGISTER (LMR) command. BA0 and BA1 become “Don’t Care” when registering an ALL BANK PRECHARGE (A10 HIGH). H7, H8, J8, J7, J3, J2, H3, H2, H1, G3, H9, G2, G8, G9, F7, F3, G1, G2, G3, H1, H2, J3, G7, H9 A0–A12 Input Address inputs: A0–A12 are sampled during the ACTIVE command (row-address A0–A12) and READ/WRITE command (column-address A0–A8 [x32]; column-address A0–A8 [x16]; with A10 defining auto precharge) to select one location out of the memory array in the respective bank. A10 is sampled during a PRECHARGE command to determine if all banks are to be precharged (A10 HIGH) or bank selected by BA0, BA1. The address inputs also provide the op-code during a LMR command.

PDF:09005aef8219eeeb/Source: 09005aef8219eedd Micron Technology, Inc., reserves the right to change products or specifications without notice. MT48H16M16LF_2.fm - Rev F 4/07 EN 11 ©2006 Micron Technology, Inc. All rights reserved. 256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM Ball Descriptions A8, B9, B8, C9, C8, D9, D8, E9, E1, D2, D1, C2, C1, B2, B1, A2 R8, N7, R9, N8, P9, M8, M7, L8, L2, M3, M2, P1, N2, R1, N3, R2, E8, D7, D8, B9, C8, A9, C7, A8, A2, C3, A1, C2, B1, D2, D3, E2 DQ0–DQ31 I/O Data input/output: Data bus. A7, B3, C7, D3 B2 , B7, C9, D9, E1, L1, M9, N9, P2, P7 VDDQ Supply DQ power: Provide isolated power to DQ for improved noise immunity. A3, B7, C3, D7 B8 , B3, C1, D1, E9, L9, M1, N1, P3, P8 VSSQ Supply DQ ground: Provide isolated ground to DQ for improved noise immunity. A9, E7, J9 A7, F9, L7, R7 V DD Supply Core power supply. A1, E3, J1 A3, F1, L3, R3 V SS Supply Ground. – E3, E7, H3, H7, NC – Internally not connected: These could be left unconnected, but it is recommended they be connected to Vss. E2 K2 DNU Input E2 is a TEST pin that must be tied to VSS or VssQ in normal operation. Table 3: VFBGA Ball Descriptions (Continued) 54-Ball VFBGA 90-Ball VFBGA Symbol Type Description

PDF:09005aef8219eeeb/Source: 09005aef8219eedd Micron Technology, Inc., reserves the right to change products or specifications without notice. MT48H16M16LF_2.fm - Rev F 4/07 EN 12 ©2006 Micron Technology, Inc. All rights reserved. 256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM Functional Description Functional Description In general, a 256Mb SDRAM is quad-bank DRAM that operates at 1.8V and includes a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA0 and BA1 select the bank, A0–A12 select the row for x16, and A0–A11 select the row for x32). The address bits (A0–A8 for x16 and A0–A8 for x32) registered coincident with the READ or WRITE command are used to select the starting column location for the burst access. Prior to normal operation, the SDRAM must be initialized. The following sections provide detailed information covering device initialization, register definition, command descriptions, and device operation. Initialization SDRAM must be powered up and initialized in a predefined manner. Operational proce- dures other than those specified may result in undefined operation. The initialization for mobile SDRAM is as follows. 1. Simultaneously apply power to V DD and VDDQ. 2. After power supplies have se ttled, apply a stable clock signal. Stable clock is defined as a signal cycling within timing constraints specified for the clock pin. 3. Wait at least 100µs. During this period NOP or COMMAND INHIBIT commands should be applied. No other command other than NOP or COMMAND INHIBIT is allowed during this period. 4. Preform a PRECHARGE ALL command to pl ace the SDRAM into an all banks idle state. 5. Wait at least tRP time. During this time NOP or COMMAND INHIBIT commands must be applied. 6. Issue an AUTO REFRESH command. 7. Wait at least tRFC time, during which only NOP or COMMAND INHIBIT commands are allowed. 8. Issue an Auto Refresh command. 9. Wait at least tRFC time, during which only NOP or COMMAND INHIBIT commands are allowed. 10. Issue a LOAD MODE REGISTER comman d with BA1=0, andBA0=0, to program the mode register with desired values. 11. Wait tMRD time. Only NOP or COMMAND INHIBIT commands may be applied dur- ing this time. 12. Issue a LOAD MODE REGISTER command with BA1=1, and BA0=0, to program the extended mode register with desired values. 13. Wait tMRD time. Only NOP or COMMAND INHIBIT commands may be applied dur- ing this time. The Mobile SDRAM is now initialized and can accept any valid command.

PDF:09005aef8219eeeb/Source: 09005aef8219eedd Micron Technology, Inc., reserves the right to change products or specifications without notice. MT48H16M16LF_2.fm - Rev F 4/07 EN 13 ©2006 Micron Technology, Inc. All rights reserved. 256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM Register Definition Register Definition Mode Register There are two MRs in the component: mode register and extended mode register (EMR). The mode register is illustrated in Figure 6 on page 14. The mode register is used to define the specific mode of operation of the SDRAM. This definition includes the selec- tion of a burst length (BL), a burst type, a CAS latency (CL), an operating mode and a write burst mode, as shown in Figure 6 on page 14. The mode register is programmed via the LMR command and will retain the stored information until it is programmed again or the device loses power. M0–M2 mode register bits specify the BL, M3 specifies the type of burst, M4–M6 specify the CL, M7 and M8 specify the operating mode, M9 specifies the write burst mode, and M10 and M11 should be set to zero. The mode register must be loaded when all banks are idle, and the controller must wait tMRD before initiating the subsequent operation. Violating either of these requirements will result in unspecified operation. Burst Length (BL) Read and write accesses to the SDRAM are burst oriented, with the BL being program- mable, as shown in Figure 6 on page 14. The BL determines the maximum number of column locations that can be accessed for a given READ or WRITE command. BL = 1, 2, 4, 8 locations are available for both the sequential and the interleaved burst types. Reserved states should not be used, as unknown operation or incompatibility with future versions may result. When a READ or WRITE command is issued, a block of columns equal to the BL is effec- tively selected. All accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached. The block is uniquely selected by A1–A8 when BL = 2, A2–A8 when BL = 4, and A3–A8 when BL = 8. The remaining (least significant) address bit(s) is (are) used to select the starting location within the block. Burst Type Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit M3. The ordering of accesses within a burst is determined by the BL, the burst type, and the starting column address, as shown in Table 4 on page 15.

PDF:09005aef8219eeeb/Source: 09005aef8219eedd Micron Technology, Inc., reserves the right to change products or specifications without notice. MT48H16M16LF_2.fm - Rev F 4/07 EN 14 ©2006 Micron Technology, Inc. All rights reserved. 256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM Register Definition Figure 6: Mode Register Definition M3 = 0 Reserved Reserved M3 = 1 Reserved Reserved Reserved Burst Type Sequential Interleaved CAS Latency Reserved Reserved Reserved Reserved Reserved Reserved Burst Length Mode Register (Mx) Address Bus Operating Mode Valid Normal operation All other states reserved Mode Register Definintion Base mode register Reserved Extended mode register Reserved M14 M13 M9 Write Burst Mode Programmed burst length Single location access Program to ensure compatibility with future devices. 9 7 6 5 4 3 8 2 1 Burst Length 0 M12 A11 M11 A10 M10 10 11 12 BA0 A12 M13 BA1 M14 13 14 0 BT CAS Latency OP Mode WB Reserved Reserved Reserved Reserved M6–M0

PDF:09005aef8219eeeb/Source: 09005aef8219eedd Micron Technology, Inc., reserves the right to change products or specifications without notice. MT48H16M16LF_2.fm - Rev F 4/07 EN 15 ©2006 Micron Technology, Inc. All rights reserved. 256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM Register Definition CAS Latency (CL) The CL is the delay, in clock cycles, between the registration of a READ command and the availability of the first piece of output data. The latency can be set to two or three clocks. If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available by clock edge n + m. The DQs will start driving as a result of the clock edge one cycle earlier (n + m - 1), and provided that the relevant access times are met, the data will be valid by clock edge n + m. For example, assuming that the clock cycle time is such that all relevant access times are met, if a READ command is registered at T0 and the latency is programmed to two clocks, the DQs will start driving after T1 and the data will be valid by T2, as shown in Figure 7 on page 16. Reserved states should not be used as unknown operation or incompatibility with future versions may result. Table 4: Burst Definition Table Burst Length Starting Column Address Order of Accesses Within a Burst Type = Sequential Type = Interleaved 2A 0 00 - 1 0 - 1 11 - 0 1 - 0 4A 1 A 0

8 A 2A 1A 0

PDF:09005aef8219eeeb/Source: 09005aef8219eedd Micron Technology, Inc., reserves the right to change products or specifications without notice. MT48H16M16LF_2.fm - Rev F 4/07 EN 16 ©2006 Micron Technology, Inc. All rights reserved. 256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM Register Definition Figure 7: CAS Latency Operating Mode The normal operating mode is selected by setting M7 and M8 to zero; the other combi- nations of values for M7 and M8 are reserved for future use. Reserved states should not be used as unknown operation or incompatibility with future versions may result. Write Burst Mode When M9 = 0, the BL programmed via M0–M2 applies to both READ and WRITE bursts; when M9 = 1, the programmed BL applies to READ bursts, but write accesses are single- location accesses. Extended Mode Register (EMR) The low-power EMR controls the functions beyond those controlled by the MR. These additional functions are special features of the mobile device. They include tempera- ture-compensated self refresh (TCSR) control, partial-array self refresh (PASR), and output drive strength. The low-power EMR is programmed via the MODE REGISTER SET command and retains the stored information until it is programmed again or the device loses power. CLK DQ T2T1 T3T0 CL = 3 LZ DOUT tOHt COMMAND NOPREAD tAC NOP DON’T CARE UNDEFINED CLK DQ T2T1 T3T0 CL = 2 LZ DOUT tOHt COMMAND NOPREAD tAC NOP NOP

PDF:09005aef8219eeeb/Source: 09005aef8219eedd Micron Technology, Inc., reserves the right to change products or specifications without notice. MT48H16M16LF_2.fm - Rev F 4/07 EN 17 ©2006 Micron Technology, Inc. All rights reserved. 256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM Register Definition Figure 8: EMR Definition Notes: 1. On-die temperature sensor is used in plac e of TCSR. Setting these bits will have no effect. The EMR must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the specified time before initiating any subsequent operation. Violating either of these requirements results in unspecified operation. Once the values are entered, the EMR settings will be retained even after exiting deep power-down mode. Temperature-Compensated Self Refresh (TCSR) On this version of the Mobile SDR SDRAM, a temperature sensor is implemented for automatic control of the self refresh oscillator on the device. Therefore, it is recom- mended not to program or use the temperature-compensated self refresh control bits in the extended mode register. Programming of the TCSR bits has no effect on the device. The self refresh oscillator will continue refresh at the factory programmed optimal rate for the device temperature. Extended Mode Register Address Bus 9 7 6 5 4 3 8 2 1 PASR TCSR1DS set to “0” 0 E12 A11 E11 A10 E10 10 11 12 Partial Array Self Refresh Coverage Full array Half array Quarter array Reserved Reserved One-eighth array One-sixteenth array Reserved Driver Strength Full strength driver Half strength driver Quarter strength driver BA0 A12 E13 BA1 E14 13 14 Mode Register Definintion Standard mode register Reserved Extended mode register Reserved E14 E13 E11 E12 E10 Valid Normal operation All other states reserved 1 1 Eighth strength driver E6–E0

PDF:09005aef8219eeeb/Source: 09005aef8219eedd Micron Technology, Inc., reserves the right to change products or specifications without notice. MT48H16M16LF_2.fm - Rev F 4/07 EN 18 ©2006 Micron Technology, Inc. All rights reserved. 256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM Register Definition Partial-Array Self Refresh (PASR) For further power savings during self refresh, the partial-array self refresh (PASR) feature allows the controller to select the amount of memory that will be refreshed during self refresh. The following refresh options are available. 1. All banks (banks 0, 1, 2, and 3). 2. Two banks (banks 0 and 1; BA1=0). 3. One bank (bank 0; BA1 = BA0 = 0). 4. Half bank (bank 0; BA1 = BA0 = row address MSB = 0). 5. Quarter bank (bank 0; BA1 = BA0; row address MSB = row address MSB -1 = 0). WRITE and READ commands occur to any bank selected during standard operation, but only the selected banks in PASR will be refreshed during self refresh. It is important to note that data in banks 2 and 3 will be lost when the two-bank option is used. Driver Strength Bits E5 and E6 of the EMR can be used to select the driver strength of the DQ outputs. This value should be set according to the application’ s requirements.

PDF:09005aef8219eeeb/Source: 09005aef8219eedd Micron Technology, Inc., reserves the right to change products or specifications without notice. MT48H16M16LF_2.fm - Rev F 4/07 EN 19 ©2006 Micron Technology, Inc. All rights reserved. 256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM Commands Commands Table 5 provides a quick reference of available commands. This is followed by a written description of each command. Three additional Truth Tables appear following “Opera- tions” on page 23. These tables provide current state/next state information. Notes: 1. CKE is HIGH for all commands shown except SELF REFRESH and deep power-down. 2. All states and sequences not show n are reserved and/or illegal. 3. The purpose of the BURST TERMINATE command is to stop a data burst, thus the command could coincide with data on the bus. However, the DQs column reads a don’t care state to illustrate that the BURST TERMINATE command can occur when there is no data present. 4. DESELECT and NOP are functionally interchangeable. 5. BA0–BA1 provide bank address and A0–A12 provide row address. 6. BA0–BA1 provide bank address; A0–A9 provide column address; A10 HIGH enables the auto precharge feature (nonpersistent), and A10 LOW disables the auto precharge feature. 7. Applies only to read bursts with auto precharge disabled; this command is undefined (and should not be used) for READ bursts with auto precharge enabled and for WRITE bursts. 8. This command is a BURST TERMINATE if CKE is HIGH, deep power-down if CKE is LOW. 9. A10 LOW: BA0–BA1 determine which bank is precharged. A10 HIGH: all banks are pre- charged and BA0–BA1 are “Don’t Care.” 10. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW. 11. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE. 12. BA0–BA1 select either the standard mode regist er or the extended mode register (BA0 = 0, BA1 = 0 select the standard mode register; BA0 = 0, BA1 = 1 select extended mode register; other combinations of BA0–BA1 are reserved.) A0–A12 provide the op-code to be written to the selected mode register. COMMAND INHIBIT The COMMAND INHIBIT function prevents new commands from being executed by the SDRAM, regardless of whether the CLK signal is enabled. The SDRAM is effectively dese- lected. Operations already in progress are not affected. Table 5: Truth Table – Commands and DQM Operation Notes 1 and 2 apply to all commands Name (Function) CS# RAS# CAS# WE# DQM ADDR DQs Notes COMMAND INHIBIT (NOP) HXXXX X X 4 NO OPERATION (NOP) LHHHX X X 4 ACTIVE (Select bank and activate row) L L H H X Bank/Row X 5 READ (Select bank and column, and start READ burst) LHLH L / H B a n k / C o l X 6 WRITE (Select bank and column, and start WRITE burst) L H L L L/H Bank/Col Valid 6 BURST TERMINATE or deep power-down (Enter deep power-down mode) L H H L X X X 3, 7, 8 PRECHARGE (Deactivate row in bank or banks) LLHLXC o d e X 9 AUTO REFRESH or SELF REFRESH (Enter self refresh mode) L L L H X X X 10, 11 LOAD MODE REGISTER LLLLX O p - C o d e X 1 2 Write enable/output enable XXXXL XA c t i v e Write inhibit/output High-Z XXXXH XH i g h - Z

PDF:09005aef8219eeeb/Source: 09005aef8219eedd Micron Technology, Inc., reserves the right to change products or specifications without notice. MT48H16M16LF_2.fm - Rev F 4/07 EN 20 ©2006 Micron Technology, Inc. All rights reserved. 256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM Commands NO OPERATION (NOP) The NO OPERATION (NOP) command is used to perform a NOP to an SDRAM which is selected (CS# is LOW). This prevents unwanted commands from being registered during idle or wait states. Operations already in progress are not affected. LOAD MODE REGISTER (LMR) The MR is loaded via inputs A0–A12, BA0, and BA1. (See “Mode Register” on page 13.) The LMR and LOAD EXTENDED MODE REGISTER (LEMR) commands can only be issued when all banks are idle, and a subsequent executable command cannot be issued until tMRD is met. ACTIVE The ACTIVE command is used to open (or activate) a row in a particular bank for a subsequent access. The value on the BA0, BA1 inputs selects the bank, and the address provided selects the row. This row remains active (or open) for accesses until a PRECHARGE command is issued to that bank. A PRECHARGE command must be issued before opening a different row in the same bank. READ The READ command is used to initiate a burst read access to an active row. The value on the BA0, BA1 inputs selects the bank, and the address provided selects the starting column location. The value on input A10 determines whether or not auto precharge is used. If auto precharge is selected, the row being accessed will be precharged at the end of the read burst; if auto precharge is not selected, the row will remain open for subse- quent accesses. Read data appears on the DQs subject to the logic level on the DQM inputs two clocks earlier. If a given DQM signal was registered HIGH, the corresponding DQs will be High-Z two clocks later; if the DQM signal was registered LOW, the DQs will provide valid data. WRITE The WRITE command is used to initiate a burst write access to an active row. The value on the BA0, BA1 inputs selects the bank, and the address provides the starting column location. The value on input A10 determines whether or not auto precharge is used. If auto precharge is selected, the row being accessed will be precharged at the end of the write burst; if auto precharge is not selected, the row will remain open for subsequent accesses. Input data appearing on the DQs is written to the memory array subject to the DQM input logic level appearing coincident with the data. If a given DQM signal is regis- tered LOW, the corresponding data will be written to memory; if the DQM signal is regis- tered HIGH, the corresponding data inputs will be ignored, and a write will not be executed to that byte/column location. PRECHARGE The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row access a specified time ( tRP) after the precharge command is issued. Input A10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs BA0, BA1 select the bank. Otherwise BA0, BA1 are treated as “Don’t Care.” Once a bank has been precharged, it is in the idle state and must be acti- vated prior to any READ or WRITE commands being issued to that bank.

PDF:09005aef8219eeeb/Source: 09005aef8219eedd Micron Technology, Inc., reserves the right to change products or specifications without notice. MT48H16M16LF_2.fm - Rev F 4/07 EN 21 ©2006 Micron Technology, Inc. All rights reserved. 256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM Commands BURST TERMINATE The BURST TERMINATE command is used to truncate fixed-length bursts. The most recently registered READ or WRITE command prior to the BURST TERMINATE command will be truncated, as shown in “Operations” on page 23. AUTO REFRESH AUTO REFRESH is used during normal operation of the SDRAM and is analogous to CAS#-BEFORE-RAS# (CBR) refresh in conventional DRAM. This command is non persis- tent, so it must be issued each time a refresh is required. All active banks must be PRECHARGED prior to issuing an AUTO REFRESH command. The AUTO REFRESH command should not be issued until the minimum tRP has been met after the PRECHARGE command, as shown in “Operations” on page 23. The addressing is generated by the internal refresh controller. This makes the address bits “Don’t Care” during an AUTO REFRESH command. The 256Mb SDRAM requires 8,192 AUTO REFRESH cycles every 64ms ( tREF). Providing a distributed AUTO REFRESH command every 7.8125µs will meet the refresh requirement and ensure that each row is refreshed. Alternatively, 8,192 AUTO REFRESH commands can be issued in a burst at the minimum cycle rate (tRFC), once every 64ms. SELF REFRESH The SELF REFRESH command can be used to retain data in the SDRAM, even if the rest of the system is powered down. When in the self refresh mode, the SDRAM retains data without external clocking. The SELF REFRESH command is initiated like an AUTO REFRESH command, except CKE is disabled (LOW). Once the SELF REFRESH command is registered, all the inputs to the SDRAM become “Don’t Care” with the exception of CKE, which must remain LOW . Once self refresh mode is engaged, the SDRAM provides its own internal clocking, causing it to perform its own auto refresh cycles. The SDRAM must remain in self refresh mode for a minimum period equal to tRAS and may remain in self refresh mode for an indefinite period beyond that. The procedure for exiting self refresh requires a sequence of commands. First, CLK must be stable (stable clock is defined as a signal cycling within timing constraints specified for the clock ball) prior to CKE going back HIGH. Once CKE is HIGH, the SDRAM must have NOP commands issued (a minimum of two clocks) for tXSR because time is required for the completion of any internal refresh in progress. Upon exiting the self refresh mode, AUTO REFRESH commands must be issued every 7.8125µs or less as both SELF REFRESH and AUTO REFRESH utilize the row refresh counter. Auto Precharge Auto precharge is a feature which performs the same individual-bank precharge func- tion described above, without requiring an explicit command. This is accomplished by using A10 to enable auto precharge in conjunction with a specific READ or WRITE command. A precharge of the bank/row that is addressed with the READ or WRITE command is automatically performed upon completion of the READ or WRITE burst. Auto precharge is non persistent in that it is either enabled or disabled for each indi- vidual READ or WRITE command.

PDF:09005aef8219eeeb/Source: 09005aef8219eedd Micron Technology, Inc., reserves the right to change products or specifications without notice. MT48H16M16LF_2.fm - Rev F 4/07 EN 22 ©2006 Micron Technology, Inc. All rights reserved. 256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM Commands Auto precharge ensures that the precharge is initiated at the earliest valid stage within a burst. The user must not issue another command to the same bank until the precharge time (tRP) is completed. This is determined as if an explicit PRECHARGE command was issued at the earliest possible time, as described for each burst type in “Operations” on page 23. Deep Power-Down Deep power-down is an operating mode used to achieve maximum power reduction by eliminating the power to the memory array. Data will not be retained once the device enters deep power-down mode.

PDF:09005aef8219eeeb/Source: 09005aef8219eedd Micron Technology, Inc., reserves the right to change products or specifications without notice. MT48H16M16LF_2.fm - Rev F 4/07 EN 23 ©2006 Micron Technology, Inc. All rights reserved. 256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM Operations Operations Bank/Row Activation Before any READ or WRITE commands can be issued to a bank within the SDRAM, a row in that bank must be “opened.” This is accomplished via the ACTIVE command, which selects both the bank and the row to be activated (see Figure 9). After opening a row (issuing an ACTIVE command), a READ or WRITE command may be issued to that row, subject to the tRCD specification. tRCD (MIN) should be divided by the clock period and rounded up to the next whole number to determine the earliest clock edge after the ACTIVE command on which a READ or WRITE command can be entered. For example, a tRCD specification of 20ns with a 125 MHz clock (8ns period) results in 2.5 clocks, rounded to 3. This is reflected in Figure 10 on page 24, which covers any case where 2 < tRCD (MIN)/tCK ≤ 3. (The same procedure is used to convert other specification limits from time units to clock cycles.) A subsequent ACTIVE command to a different row in the same bank can only be issued after the previous active row has been “closed” (precharged). The minimum time interval between successive ACTIVE commands to the same bank is defined by tRC. A subsequent ACTIVE command to another bank can be issued while the first bank is being accessed, which results in a reduction of total row-access overhead. The minimum time interval between successive ACTIVE commands to different banks is defined by tRRD. Figure 9: Activating a Specific Row in a Specific Bank CS# WE# CAS# RAS# CKE CLK A0–A11 ROW ADDRESS DON´T CARE HIGH BA0, BA1 BANK ADDRESS

PDF:09005aef8219eeeb/Source: 09005aef8219eedd Micron Technology, Inc., reserves the right to change products or specifications without notice. MT48H16M16LF_2.fm - Rev F 4/07 EN 27 ©2006 Micron Technology, Inc. All rights reserved. 256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM Operations not, the second WRITE will be an invalid WRITE. For example, if DQM was LOW during T4 (as in Figure 15 on page 28) then the WRITEs at T5 and T7 would be valid, while the WRITE at T6 would be invalid. The DQM signal must be de-asserted prior to the WRITE command (DQM latency is zero clocks for input buffers) to ensure that the written data is not masked. Figure 12 on page 25 shows the case where the clock frequency allows for bus contention to be avoided without adding a NOP cycle, and Figure 13 on page 26 shows the case where the additional NOP is needed. A fixed-length READ burst may be followed by, or truncated with, a PRECHARGE command to the same bank (provided that auto precharge was not activated). The PRECHARGE command should be issued x cycles before the clock edge at which the last desired data element is valid, where x = CL - 1. This is shown in Figure 16 on page 28 for each possible CL; data element n + 3 is either the last of a burst of four or the last desired of a longer burst. Following the PRECHARGE command, a subsequent command to the same bank cannot be issued until tRP is met. Note that part of the row precharge time is hidden during the access of the last data element(s). In the case of a fixed-length burst being executed to completion, a PRECHARGE command issued at the optimum time (as described above) provides the same operation that would result from the same fixed-length burst with auto precharge. The disadvan- tage of the PRECHARGE command is that it requires that the command and address buses be available at the appropriate time to issue the command; the advantage of the PRECHARGE command is that it can be used to truncate fixed-length page bursts. Figure 14: READ-to-WRITE Note: CL = 3. The READ command may be to any bank, and the WRITE command may be to any bank. If a burst of one is used, then DQM is not required. DON’T CARE READ NOP NOP WRITE NOP CLK T2T1 T4 T3T0 DQM DQ DOUT n COMMAND DIN b ADDRESS BANK, COL n BANK, COL b DS tHZ t tCK

PDF:09005aef8219eeeb/Source: 09005aef8219eedd Micron Technology, Inc., reserves the right to change products or specifications without notice. MT48H16M16LF_2.fm - Rev F 4/07 EN 29 ©2006 Micron Technology, Inc. All rights reserved. 256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM Operations Fixed-length READ bursts may be truncated with a BURST TERMINATE command, provided that auto precharge was not activated. The BURST TERMINATE command should be issued x cycles before the clock edge at which the last desired data element is valid, where x = CL - 1. This is shown in Figure 17 for each possible CL; data element n + 3 is the last desired data element of a longer burst. Figure 17: Terminating a READ Burst Note: DQM is LOW. DON’T CARE CLK DQ DOUT n T2T1 T4 T3 T6 T5T0 COMMAND ADDRESS READ NOP NOP NOP NOP BANK, COL n NOP DOUT n + 1 DOUT n + 2 DOUT n + 3 BURST TERMINATE NOP CLK DQ DOUT n T2T1 T4 T3 T6 T5T0 COMMAND ADDRESS READ NOP NOP NOP BANK, COL n NOP DOUT n + 1 DOUT n + 2 DOUT n + 3 BURST TERMINATE NOP X = 1 cycle CL = 2 CL = 3 X = 2 cycles

PDF:09005aef8219eeeb/Source: 09005aef8219eedd Micron Technology, Inc., reserves the right to change products or specifications without notice. MT48H16M16LF_2.fm - Rev F 4/07 EN 30 ©2006 Micron Technology, Inc. All rights reserved. 256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM Operations WRITEs WRITE bursts are initiated with a WRITE command, as shown in Figure 18 on page 30. The starting column and bank addresses are provided with the WRITE command, and auto precharge is either enabled or disabled for that access. If auto precharge is enabled, the row being accessed is precharged at the completion of the burst. For the generic WRITE commands used in the following illustrations, auto precharge is disabled. During WRITE bursts, the first valid data-in element will be registered coincident with the WRITE command. Subsequent data elements will be registered on each successive positive clock edge. Upon completion of a fixed-length burst, assuming no other commands have been initiated, the DQs will remain High-Z and any additional input data will be ignored (see Figure 19). Figure 18: WRITE Command Data for any WRITE burst may be truncated with a subsequent WRITE command, and data for a fixed-length WRITE burst may be immediately followed by data for a WRITE command. The new WRITE command can be issued on any clock following the previous WRITE command, and the data provided coincident with the new command applies to the new command. An example is shown in Figure 20 on page 31. Data n + 1 is either the last of a burst of two or the last desired of a longer burst. The 256Mb SDRAM uses a pipe- lined architecture. A WRITE command can be initiated on any clock cycle following a previous WRITE command. Full-speed random write accesses within a page can be performed to the same bank, as shown in Figure 19 on page 31, or each subsequent WRITE may be performed to a different bank. CS# WE# CAS# RAS# CKE CLK COLUMN ADDRESS DON’T CARE HIGH ENABLE AUTO PRECHARGE DISABLE AUTO PRECHARGE BANK ADDRESS A0–A8 A10 BA0, BA1 A9, A11, A12 VALID ADDRESS

PDF:09005aef8219eeeb/Source: 09005aef8219eedd Micron Technology, Inc., reserves the right to change products or specifications without notice. MT48H16M16LF_2.fm - Rev F 4/07 EN 34 ©2006 Micron Technology, Inc. All rights reserved. 256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM Operations Fixed-length or WRITE bursts can be truncated with the BURST TERMINATE command. When truncating a WRITE burst, the input data applied coincident with the BURST TERMINATE command will be ignored. The last data written (provided that DQM is LOW at that time) will be the input data applied one clock previous to the BURST TERMINATE command. This is shown in Figure 22 on page 32, where data n is the last desired data element of a longer burst. PRECHARGE The PRECHARGE command (see Figure 25) is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subse- quent row access some specified time ( tRP) after the precharge command is issued. Input A10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs BA0, BA1 select the bank. When all banks are to be precharged, inputs BA0, BA1 are treated as “Don’t Care.” Once a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued to that bank. Figure 25: PRECHARGE Command Power-Down Power-down occurs if CKE is registered LOW coincident with a NOP or COMMAND INHIBIT when no accesses are in progress. If power-down occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down occurs when there is a row active in any bank, this mode is referred to as active power-down. Entering power-down deactivates the input and output buffers, excluding CKE, for maximum power savings while in standby. The device may not remain in the power-down state longer than the refresh period (64ms) since no REFRESH operations are performed in this mode. CS# WE# CAS# RAS# CKE CLK A10 DON’T CARE HIGH All Banks Bank Selected A0–A9, A11, A12 BA0, BA1 BANK ADDRESS VALID ADDRESS

PDF:09005aef8219eeeb/Source: 09005aef8219eedd Micron Technology, Inc., reserves the right to change products or specifications without notice. MT48H16M16LF_2.fm - Rev F 4/07 EN 35 ©2006 Micron Technology, Inc. All rights reserved. 256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM Operations The power-down state is exited by registering a NOP or COMMAND INHIBIT and CKE HIGH at the desired clock edge (meeting tCKS). See Figure 24. Figure 26: Power-Down Deep Power-Down Deep power-down mode is a maximum power savings feature achieved by shutting off the power to the entire memory array of the device. Data in the memory array will not be retained once deep power-down mode is executed. Deep power-down mode is entered by having all banks idle then CS# and WE# held LOW with RAS# and CAS# HIGH at the rising edge of the clock, while CKE is LOW. CKE must be held LOW during deep power- down. To exit deep power-down mode, CKE must be asserted HIGH. Upon exit of Deep Power- Down mode, at least 200µs of valid clocks with either NOP or COMMAND INHIBIT commands are applied to the command bus, followed by a full Mobile SDRAM initializa- tion sequence, is required. Clock Suspend The clock suspend mode occurs when a column access/burst is in progress and CKE is registered LOW . In the clock suspend mode, the internal clock is deactivated, “freezing” the synchronous logic. For each positive clock edge on which CKE is sampled LOW, the next internal positive clock edge is suspended. Any command or data present on the input balls at the time of a suspended internal clock edge is ignored; any data present on the DQ balls remains driven; and burst counters are not incremented, as long as the clock is suspended. (See examples in Figure 27 and Figure 28 on page 37.) Clock suspend mode is exited by registering CKE HIGH; the internal clock and related operation will resume on the subsequent positive clock edge. Burst Read/Single Write The burst read/single write mode is entered by programming the write burst mode bit (M9) in the MR to a logic 1. In this mode, all WRITE commands result in the access of a single column location (burst of one), regardless of the programmed BL. READ commands access columns according to the programmed BL and sequence, just as in the normal mode of operation (M9 = 0). DON’T CARE tRAS tRCD tRC All banks idle Input buffers gated off Exit power-down mode tCKS > tCKS COMMAND NOP ACTIVE Enter power-down mode NOP CLK CKE

PDF:09005aef8219eeeb/Source: 09005aef8219eedd Micron Technology, Inc., reserves the right to change products or specifications without notice. MT48H16M16LF_2.fm - Rev F 4/07 EN 36 ©2006 Micron Technology, Inc. All rights reserved. 256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM Operations Concurrent Auto Precharge An access command (READ or WRITE) to a second bank while an access command with auto precharge enabled on a first bank is executing is not allowed by SDRAM, unless the SDRAM supports concurrent auto precharge. Micron SDRAM support concurrent auto precharge. Four cases where concurrent auto precharge occurs are defined in the “READ with Auto Precharge” and “WRITE with Auto Precharge” sections. READ with Auto Precharge 1. Interrupted by a READ (with or without auto precharge): A READ to bank m will inter- rupt a READ on bank n, CL later. The precharge to bank n will begin when the READ to bank m is registered (see Figure 29 on page 37). 2. Interrupted by a WRITE (with or without auto precharge): A WRITE to bank m will interrupt a READ on bank n when registered. DQM should be used two clocks prior to the WRITE command to prevent bus contention. The precharge to bank n will begin when the WRITE to bank m is registered (see Figure 30 on page 38). Figure 27: Clock Suspend During WRITE Burst Note: For this example, BL = 4 or greater, and DM is LOW. DON’T CARE DIN COMMAND ADDRESS WRITE BANK, COL n DIN n NOPNOP CLK T2T1 T4 T3 T5T0 CKE INTERNAL CLOCK NOP DIN n + 1 DIN n + 2

PDF:09005aef8219eeeb/Source: 09005aef8219eedd Micron Technology, Inc., reserves the right to change products or specifications without notice. MT48H16M16LF_2.fm - Rev F 4/07 EN 38 ©2006 Micron Technology, Inc. All rights reserved. 256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM Operations Figure 30: READ with Auto Pr echarge Interrupted by a WRITE Note: DQM is HIGH at T2 to prevent D OUT a +1 from contending with DIN d at T4. WRITE with Auto Precharge 1. Interrupted by a READ (with or without auto precharge): A READ to bank m will inter- rupt a WRITE on bank n when registered, with the data -out appearing CL later. The precharge to bank n will begin after tWR is met, where tWR begins when the READ to bank m is registered. The last valid WRITE to bank n will be data-in registered one clock prior to the READ to bank m (see Figure 31 on page 39). 2. Interrupted by a WRITE (with or without auto precharge): A WRITE to bank m will interrupt a WRITE on bank n when registered. The precharge to bank n will begin after tWR is met, where tWR begins when the WRITE to bank m is registered. The last valid data WRITE to bank n will be data registered one clock prior to a WRITE to bank m (see Figure 32 on page 39). CLK DQ DOUT a T2T1 T4 T3 T6 T5T0 COMMAND NOPNOPNOPNOP DIN d + 1 DIN d DIN d + 2 DIN d + 3 NOP BANK n BANK m ADDRESS Idle NOP DQM BANK n, COL a BANK m, COL d WRITE - AP BANK m Internal States t Page Active READ with Burst of 4 Interrupt Burst, Precharge Page Active WRITE with Burst of 4 Write-Back RP - BANK n t WR - BANK m CL = 3 (bank n) READ - AP BANK n DON’T CARE

PDF:09005aef8219eeeb/Source: 09005aef8219eedd Micron Technology, Inc., reserves the right to change products or specifications without notice. MT48H16M16LF_2.fm - Rev F 4/07 EN 40 ©2006 Micron Technology, Inc. All rights reserved. 256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM Truth Tables Truth Tables Notes: 1. CKE n is the logic state of CKE at clock edge n; CKEn-1 was the state of CKE at the previous clock edge. 2. Current state is the state of the SD RAM immediately prior to clock edge n. 3. COMMAND n is the command registered at clock edge n, and ACTIONn is a result of COM- MANDn. 4. All states and sequences not sh own are illegal or reserved. 5. Exiting power-down at clock edge n will put the device in the all banks idle state in time for clock edge n + 1 (provided that tCKS is met). 6. Exiting self refresh at clock edge n will put the device in the all banks idle state once tXSR is met. COMMAND INHIBIT or NOP commands should be issued on any clock edges occurring during the tXSR period. A minimum of two NOP commands must be provided during tXSR period. 7. After exiting clock suspend at clock edge n, the device will resume operation and recognize the next command at clock edge n + 1. 8. Deep power-down is power savings feature of this Mobile SDRAM device. This command is BURST TERMINATE when CKE is HIGH and deep power-down when CKE is LOW. Table 6: Truth Table – CKE Notes: 1–4 CKEn-1 CKEn Current State Commandn Actionn Notes L L Power-down X Maintain power-down Self refresh X Mainta in self refresh Clock suspend X Maintain clock suspend Deep power-down X Maintain deep power-down 8 L H Power-down COMMAND INHIBI T or NOP Exit power-down 5 Deep power-down X Exi t deep power-down 8 Self refresh COMMAND INHIBIT or NOP Exit self refresh 6 Clock suspend X Exit clock suspend 7 H L All banks idle COMMAND INHIBIT or NOP Power-down entry All banks idle BURST TERMIN ATE Deep power-down entry 8 All banks idle AUTO REFRESH Self refresh entry Reading or writing VALID Clock suspend entry H H See Table 8 on page 43

PDF:09005aef8219eeeb/Source: 09005aef8219eedd Micron Technology, Inc., reserves the right to change products or specifications without notice. MT48H16M16LF_2.fm - Rev F 4/07 EN 41 ©2006 Micron Technology, Inc. All rights reserved. 256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM Truth Tables Notes: 1. This table applies when CKE n-1 was HIGH and CKEn is HIGH (see Table 6 on page 40) and after tXSR has been met (if the previous state was self refresh). 2. This table is bank-specific, except where noted; i.e., the current state is for a specific bank and the commands shown are those allowed to be issued to that bank when in that state. Exceptions are covered in the notes below. 3. Current state definitions: 4. The following states must not be interrupted by a command issued to the same bank. COM- MAND INHIBIT or NOP commands, or allowable commands to the other bank should be issued on any clock edge occurring during these states. Allowable commands to the other bank are determined by its current state and Table 7, and according to Table 8 on page 43. Table 7: Truth Table – Current State Bank n, Command to Bank n Notes: 1–6; notes appear below table Current State CS# RAS# CAS# WE# Command (Action) Notes Any H X X X COMMAND INHIBIT (NOP/Continue previous operation) LHHH NO OPERATION (NOP/Continue previous operation) Idle L L H H ACTIVE (Select and activate row) LLLH AUTO REFRESH 7 LLLL LMR 7 LLHL PRECHARGE 11 R o w a c t i v e LHLH READ (Select column and start READ burst) 10 LHLL WRITE (Select column and start WRITE burst) 10 LLHL PRECHARGE (Deactivate row in bank or banks) 8 Read (auto precharge disabled) LHLH READ (Select column and start new READ burst) 10 LHLL WRITE (Select column and start WRITE burst) 10 LLHL PRECHARGE (Truncate READ burst, start PRECHARGE) 8 LHHL BURST TERMINATE 9 Write (auto precharge disabled) LHLH READ (Select column and start READ burst) 10 LHLL WRITE (Select column and start new WRITE burst) 10 LLHL PRECHARGE (Truncate WRITE burst, start PRECHARGE) 8 LHHL BURST TERMINATE 9 Idle: The bank has been precharged, and tRP has been met. Row active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses are in progress. Read: A READ burst has been initiated, wi th auto precharge disabled, and has not yet terminated or been terminated. Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. Precharging: Starts with registration of a PRECHARGE command and ends when tRP is met. Once tRP is met, the bank will be in the idle state. Row activating: Starts with registration of an ACTIVE command and ends when tRCD is met. Once tRCD is met, the bank will be in the row active state. Read w/auto- precharge enabled: Starts with registration of a READ command with auto precharge enabled and ends when tRP has been met. Once tRP is met, the bank will be in the idle state. Write w/auto- precharge enabled: Starts with registration of a WRITE command with auto precharge enabled and ends whentRP has been met. Once tRP is met, the bank will be in the idle state.

PDF:09005aef8219eeeb/Source: 09005aef8219eedd Micron Technology, Inc., reserves the right to change products or specifications without notice. MT48H16M16LF_2.fm - Rev F 4/07 EN 42 ©2006 Micron Technology, Inc. All rights reserved. 256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM Truth Tables 5. The following states must not be interrupt ed by any executable command; DESELECT or NOP commands must be applied on each positive clock edge during these states. 6. All states and sequences not shown are illegal or reserved 7. Not bank-specific; require s that all banks are idle. 8. May or may not be bank-specific; if all banks are to be precharged, all must be in a valid state for precharging. 9. Not bank-specific; BURST TERMINATE affects th e most recent READ or WRITE burst, regard- less of bank. 10. READs or WRITEs listed in the Command (Act ion) column include READs or WRITEs with auto precharge enabled and READs or WRITEs with auto precharge disabled. 11. Does not affect the state of the ba nk and acts as a NOP to that bank. Refreshing: Starts with registration of an AUTO REFRESH command and ends when tRFC is met. Once tRFC is met, the Mobile SDRAM will be in the all banks idle state. Accessing MR: Starts with registration of an LMR command and ends when tMRD has been met. Once tMRD is met, the Mobile SDRAM will be in the all banks idle state. Precharging all: Starts with registrati on of a PRECHARGE ALL command and ends when tRP is met. Once tRP is met, all banks will be in the idle state.

PDF:09005aef8219eeeb/Source: 09005aef8219eedd Micron Technology, Inc., reserves the right to change products or specifications without notice. MT48H16M16LF_2.fm - Rev F 4/07 EN 43 ©2006 Micron Technology, Inc. All rights reserved. 256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM Truth Tables Notes: 1. This table applies when CKE n-1 was HIGH and CKEn is HIGH (see Table 6 on page 40) and after tXSR has been met (if the previous state was self refresh). 2. This table describes alternate bank operation, except where noted; i.e., the current state is for bank n and the commands shown are those allowed to be issued to bank m (assuming that bank m is in such a state that the given command is allowable). Exceptions are covered in the notes below. 3. Current state definitions: 4. AUTO REFRESH, SELF REFRESH and LMR commands may only be issued when all banks are idle. Table 8: Truth Table – Current State Bank n, Command to Bank m Notes: 1–6; notes appear below and on next page Current State CS# RAS# CAS# WE# Command (Action) Notes A n y HXXX COMMAND INHIBIT (NOP/Continue previous operation) LHHH NO OPERATION (NOP/Continue previous operation) I d l e XXXX Any command otherwise allowed to bank m Row activating, active, or precharging LLH H ACTIVE (Select and activate row) LHLH READ (Select column and start READ burst) 7 LHLL WRITE (Select column and start WRITE burst) 7 LLHL PRECHARGE Read (auto precharge disabled) LLH H ACTIVE (Select and activate row) LHLH READ (Select column and start new READ burst) 7, 8 LHLL WRITE (Select column and start WRITE burst) 7, 9 LLHL PRECHARGE 10 Write (auto precharge disabled) LLH H ACTIVE (Select and activate row) LHLH READ (Select column and start READ burst) 7, 11 LHLL WRITE (Select column and start new WRITE burst) 7, 12 LLHL PRECHARGE 10 Read (with auto precharge) LLH H ACTIVE (Select and activate row) LHLH READ (Select column and start new READ burst) 7, 13, 14 LHLL WRITE (Select column and start WRITE burst) 7, 13, 15 LLHL PRECHARGE 10 Write (with auto precharge) LLH H ACTIVE (Select and activate row) LHLH READ (Select column and start READ burst) 7, 13, 16 LHLL WRITE (Select column and start new WRITE burst) 7, 13, 17 LLHL PRECHARGE 10 Idle: The bank has been precharged, and tRP has been met. Row active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses are in progress. Read: A READ burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. Read w/auto- precharge enabled: Starts with registration of a READ command with auto precharge enabled and ends when tRP has been met. Once tRP is met, the bank will be in the idle state. Write w/auto- precharge enabled: Starts with registration of a WRITE command with auto precharge enabled and ends when tRP has been met. Once tRP is met, the bank will be in the idle state.

PDF:09005aef8219eeeb/Source: 09005aef8219eedd Micron Technology, Inc., reserves the right to change products or specifications without notice. MT48H16M16LF_2.fm - Rev F 4/07 EN 45 ©2006 Micron Technology, Inc. All rights reserved. 256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM Electrical Specifications Electrical Specifications Absolute Maximum Ratings Stresses greater than those listed in Table 9 may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Table 9: Absolute Maximum Ratings Voltage/Temperature Min Max Units Voltage on VDD/VDDQ supply relative to VSS (1.8V) –0.3 +2.7 V Voltage on inputs, NC or I/O balls relative to VSS (1.8V) –0.3 +2.7 Storage temperature plastic –55 +150 Table 10: DC Electrical Characteristics and Operating Conditions Notes: 1, 5, 6; notes appear on page 51 and 52; VDD/VDDQ = 1.7–1.95V Parameter/Condition Symbol Min Max Units Notes Supply voltage VDD 1.7 1.95 V I/O supply voltage VDDQ 1.7 1.95 V Input high voltage: Logic 1; All inputs VIH 0.8 × VDDQV DDQ + 0.3 V 22 Input low voltage: Logic 0; All inputs VIL –0.3 +0.3 V 22 Output high voltage: All inputs: Iout = –4mA VOH 0.9 × VDDQ– V Output low voltage: All inputs: Iout = 4mA VOL –0 . 2 V Input leakage current: Any input 0V ≤ VIN ≤ VDD (All other balls not under test = 0V) II –1.0 1.0 µA Operating temperature TA (commercial) TA (industrial) +70 +85

PDF:09005aef8219eeeb/Source: 09005aef8219eedd Micron Technology, Inc., reserves the right to change products or specifications without notice. MT48H16M16LF_2.fm - Rev F 4/07 EN 46 ©2006 Micron Technology, Inc. All rights reserved. 256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM Electrical Specifications Table 11: Electrical Characteristics and Recommended AC Operating Conditions Notes: 5, 6, 8, 9, 11; notes appear on page 51 and 52 AC Characteristics Symbol -75 -8 Units NotesParameter Min Max Min Max Access time from CLK (pos. edge) CL = 3 tAC (3) 6 7 ns 9CL = 2 tAC (2) 8 9 ns Address hold time tAH 1 1 ns Address setup time tAS 1.5 2.5 ns CLK high-level width tCH 3 3 ns CLK low-level width tCL 3 3 ns Clock cycle time CL = 3 tCK (3) 7.5 8 ns 23 CL = 2 tCK (2) 9.6 10 ns 23 CKE hold time tCKH 1 1 ns CKE setup time tCKS 2.5 2.5 ns CS#, RAS#, CAS#, WE#, DQM hold time tCMH 1 1 ns CS#, RAS#, CAS#, WE#, DQM setup time tCMS 1.5 2.5 ns Data-in hold time tDH 1 1 ns Data-in setup time tDS 1.5 2.5 ns Data-out High-Z time CL = 3 tHZ (3) 6 7 ns 10 CL = 2 tHZ (2) 9 9 ns 10 Data-out Low-Z time tLZ 1 1 ns Data-out hold time (load) tOH 2.5 2.5 ns Data-out hold time (no load) tOHN 1.8 1.8 ns 25 ACTIVE-to-PRECHARGE command tRAS 44 120,000 48 120,000 ns ACTIVE-to-ACTIVE command period tRC 67.5 72 ns ACTIVE-to-READ or WRITE delay tRCD 19 20 ns Refresh period (8,192 rows) tREF 64 64 ms AUTO REFRESH period tRFC 80 80 ns PRECHARGE command period tRP 19 19 ns ACTIVE bank a to ACTIVE bank b command tRRD 2 2 tCK Transition time tT 0.3 1.2 0.5 1.2 ns 7 WRITE recovery time tWR 15 15 ns 31 Exit SELF REFRESH to ACTIVE command tXSR 80 80 ns 20

PDF:09005aef8219eeeb/Source: 09005aef8219eedd Micron Technology, Inc., reserves the right to change products or specifications without notice. MT48H16M16LF_2.fm - Rev F 4/07 EN 47 ©2006 Micron Technology, Inc. All rights reserved. 256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM Electrical Specifications Table 12: AC Functional Characteristics Notes: 5, 6, 8, 9,11 notes appear on page 51 and 52 Parameter Symbol -75 -8 Units Notes READ/WRITE command to READ/WRITE command tCCD 1 1 tCK 17 CKE to clock disable or power-down entry mode tCKED 1 1 tCK 14 CKE to clock enable or power-down exit setup mode tPED 1 1 tCK 14 DQM to input data delay tDQD 0 0 tCK 17 DQM to data mask during WRITEs tDQM 0 0 tCK 17 DQM to data High-Z during READs tDQZ 2 2 tCK 17 WRITE command to input data delay tDWD 0 0 tCK 17 Data-in to ACTIVE command tDAL 5 5 tCK 15, 21 Data-in to PRECHARGE command tDPL 2 2 tCK 16, 21 Last data-in to burst STOP command tBDL 1 1 tCK 17 Last data-in to new READ/WRITE command tCDL 1 1 tCK 17 Last data-in to PRECHARGE command tRDL 2 2 tCK 16, 21 LMR command to ACTIVE or REFRESH command tMRD 2 2 tCK 25 Data-out High-Z from PRECHARGE command CL = 3 tROH(3) 3 3 tCK 17 CL = 2 tROH(2) 2 2 tCK 17 Table 13: I DD Specifications and Conditions (x16) Notes: 1, 5, 6, 11, 13; notes appear on page 51 and 52; VDD/VDDQ = 1.7–1.95V Parameter/Condition Symbol Max Units Notes-75 -8 Operating current: Active mode; BL = 1; READ or WRITE; tRC = tRC (MIN) IDD1 65 60 mA 1, 18, Standby current: Power-down mode; All banks idle; CKE = LOW IDD2P 300 300 µA 30 Standby current: Non-power-down mode; All banks idle; CKE = HIGH IDD2N 20 20 mA Standby current: Active mode; CKE = LOW; CS# = HIGH; All banks active; No accesses in progress IDD3P 5 5 mA 1, 12, Standby current: Active mode; CKE = HIGH; CS# = HIGH; All banks active after tRCD met; No accesses in progress IDD3N 25 25 mA 1, 12, Operating current: Burst mode; READ or WRITE; All banks active, half DQs toggling every cycle IDD4 90 85 mA 1, 18, Auto refresh current: CKE = HIGH; CS# = HIGH tRFC = tRFC (MIN) IDD5 100 95 mA 1, 12, 18 19, tRFC = 7.8125µs IDD65 5 m A Deep power-down IZZ 10 10 µA 29, 30

PDF:09005aef8219eeeb/Source: 09005aef8219eedd Micron Technology, Inc., reserves the right to change products or specifications without notice. MT48H16M16LF_2.fm - Rev F 4/07 EN 48 ©2006 Micron Technology, Inc. All rights reserved. 256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM Electrical Specifications Table 14: I DD Specifications and Conditions (x32) Notes: 1, 5, 6, 11, 13; notes appear on page 51 and 52; VDD/VDDQ = 1.7–1.95V Parameter/Condition Symbol Max Units Notes-75 -8 Operating current: Active mode; BL = 1; READ or WRITE; tRC = tRC (MIN) IDD1 95 90 mA 1, 18, Standby current: Power-down mode; All banks idle; CKE = LOW IDD2P 300 300 µA 30 Standby current: Non-power-down mode; All banks idle; CKE = HIGH IDD2N 20 20 mA Standby current: Active mode; CKE = LOW; CS# = HIGH; All banks active; No accesses in progress IDD3P 5 5 mA 1, 12, Standby current: Active mode; CKE = HIGH; CS# = HIGH; All banks active after tRCD met; No accesses in progress IDD3N 25 25 mA 1, 12, Operating current: Burst mode; READ or WRITE; All banks active, half DQs toggling every cycle IDD4 120 115 mA 1, 18, Auto refresh current: CKE = HIGH; CS# = HIGH tRFC = tRFC (MIN) IDD5 100 95 mA 1, 12, 18, 26 tRFC = 7.8125µs IDD6 5 5 mA 19, 27 Deep power-down IZZ 10 10 µA 29, 30

PDF:09005aef8219eeeb/Source: 09005aef8219eedd Micron Technology, Inc., reserves the right to change products or specifications without notice. MT48H16M16LF_2.fm - Rev F 4/07 EN 49 ©2006 Micron Technology, Inc. All rights reserved. 256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM Electrical Specifications Figure 33: Typical Self Refresh Current vs. Temperature Table 15: I DD7 – Self Refresh Current Options Notes: 2, 28, 30; notes appear on page 51 and page 52 Temperature-Compensated Self Refresh Parameter/Condition Maximum Temperature Low IDD7 Option “L” Standard IDD7 Units Self refresh current: CKE = LOW – 4-bank refresh 85ºC 220 300 µA 70ºC 175 210 µA 45ºC 140 190 µA 15ºC 125 180 µA Self refresh current: CKE = LOW – 2-bank refresh 85ºC 200 275 µA 70ºC 150 180 µA 45ºC 130 160 µA 15ºC 115 150 µA Self refresh current: CKE = LOW – 1-bank refresh 85ºC 185 265 µA 70ºC 140 160 µA 45ºC 120 140 µA 15ºC 115 140 µA Self refresh current: CKE = LOW – Half-bank refresh 85ºC 175 255 µA 70ºC 125 150 µA 45ºC 115 130 µA 15ºC 110 125 µA Self refresh current: CKE = LOW – Quarter-bank refresh 85ºC 170 250 µA 70ºC 120 140 µA 45ºC 110 120 µA 15ºC 105 115 µA Temperature (°C) Current (µA) 100 125 150 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Full Array 1/2 Array 1/4 Array 1/8 Array 1/16 Array

PDF:09005aef8219eeeb/Source: 09005aef8219eedd Micron Technology, Inc., reserves the right to change products or specifications without notice. MT48H16M16LF_2.fm - Rev F 4/07 EN 50 ©2006 Micron Technology, Inc. All rights reserved. 256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM Electrical Specifications Table 16: Capacitance Note: 2; notes appear on page 51 and 52 Parameter Symbol Min Max Units Input capacitance: CLK CI1 1.5 4.5 pF Input capacitance: All other input-only balls CI2 2.0 4.5 pF Input/output capacitance: DQs CIO 2.0 6.0 pF

PDF:09005aef8219eeeb/Source: 09005aef8219eedd Micron Technology, Inc., reserves the right to change products or specifications without notice. MT48H16M16LF_2.fm - Rev F 4/07 EN 51 ©2006 Micron Technology, Inc. All rights reserved. 256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM Notes Notes 1. All voltages referenced to V SS. 2. This parameter is sampled. V DD, VDDQ = +1.8V; TA = 25°C; ball under test biased at 0.9V; f = 1 MHz. 3. IDD is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time and the outputs open. 4. Enables on-chip refresh and address counters. 5. The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range (–40°C ≤ T A ≤ +85°C for TA on IT parts) is ensured. 6. An initial pause of 100µs is required after power-up, followed by two AUTO REFRESH commands, before proper device operation is ensured. (VDD and VDDQ must be pow- ered up simultaneously. VSS and VSSQ must be at same potential.) The two AUTO REFRESH command wake-ups should be repeated any time the tREF refresh require- ment is exceeded. 7. AC characteristics assume tT = 1ns. 8. In addition to meeting the transition rate specification, the clock and CKE must tran- sit between VIH and VIL (or between VIL and VIH) in a monotonic manner. 9. Outputs measured for 1.8V at 0.9V with equivalent load: Test loads with full DQ driver strength. Performance will vary with actual system DQ bus capacitive loading, termination, and programmed drive strength. 10. tHZ defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL. The last valid data element will meet tOH before going High-Z. 11. AC timing and I DD tests have VIL and VIH, with timing referenced to VIH/2 = crossover point. If the input transition time is longer than tT (MAX), then the timing is refer- enced at VIL (MAX) and VIH (MIN) and no longer at the VIH/2 crossover point. 12. Other input signals are allowed to transiti on no more than once every two clocks and are otherwise at valid VIH or VIL levels. 13. I DD specifications are tested after the device is properly initialized. 14. Timing actually specified by tCKS; clock(s) specified as a reference only at minimum cycle rate. 15. Timing actually specified by tWR plus tRP; clock(s) specified as a reference only at minimum cycle rate. 16. Timing actually specified by tWR. 17. Required clocks are specified by JEDEC functionality and are not dependent on any timing parameter. 18. The I DD current will increase or decrease proportionally according to the amount of frequency alteration for the test condition. 19. Address transitions average on e transition every two clocks. 20. CLK must be toggled a minimum of two times during this period. 21. Based on tCK = 7.5ns for -75,tCK = 8ns for -8, at CL = 3. Q 20pF

PDF:09005aef8219eeeb/Source: 09005aef8219eedd Micron Technology, Inc., reserves the right to change products or specifications without notice. MT48H16M16LF_2.fm - Rev F 4/07 EN 52 ©2006 Micron Technology, Inc. All rights reserved. 256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM Notes 22. V IH overshoot: VIH (MAX) = VDDQ + 2V for a pulse width ≤ 3ns, and the pulse width cannot be greater than one third of the cycle rate. VIL undershoot: VIL (MIN) = –2V for a pulse width ≤ 3ns. 23. The clock frequency can only be changed during clock stop, power-down, or while in a self-refresh mode. 24. Auto precharge mode only. The precharge timing budget ( tRP) begins at 7ns for -8 after the first clock delay, after the last WRITE is executed. May not exceed limit set for precharge mode.The clock frequency can only be changed during 25. Parameter guaranteed by design. 26. CKE is HIGH during refresh command period tRFC (MIN) else CKE is LOW. 27. The I DD6 limit is actually a nominal value and does not result in a fail value. 28. Values for I DD7 for 70°C, 45°C, 15°C, and IDD7 1/2-bank and 1/4-bank are sampled only. Values for IDD7 4-bank, 2-bank, and 1-bank for 85°C are 100 percent tested. 29. Deep power-down current is a nominal valu e at 25°C. This parameter is not tested. 30. Test conditions include 500ms delay prior to measurement. 31. Auto precharge mode only. The precharge timing budget ( tRP) begins at 7.5ns for -75 and 7ns for -8 after the first clock delay, after the last WRITE is executed. For auto pre- charge mode, at least one clock cycle is required during tWR.

PDF:09005aef8219eeeb/Source: 09005aef8219eedd Micron Technology, Inc., reserves the right to change products or specifications without notice. MT48H16M16LF_2.fm - Rev F 4/07 EN 53 ©2006 Micron Technology, Inc. All rights reserved. 256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM Timing Diagrams Timing Diagrams Figure 34: Initialize and Load Mode Register Notes: 1. PRE = PRECHARGE comman d; AR = AUTO REFRESH command; LMR = LOAD MODE REGISTER command. 2. Only NOPs or COMMAND INHIBITs may be issued during tRFC time. 3. At least one NOP or COMMAND INHIBIT is required during tMRD time. CKE BA0, BA1 Load Extended Mode Register Load Mode Register tCKS Power-up: V DD and CLK stable T = 100µs tCKH DQM DQ High-Z ADDR VALID A10 VALID CLK tCK COMMAND1 ARNOP LMRAR LMR VALID tCMS tCMH tAS tAH BA0 = L, BA1 = L CODE CODE tAS tAH CODE CODE PRE ALL BANKS tAS tAH T0 T1 DON’T CARE ) ()() tRP tMRD3tMRD3tRFC2 tRFC2 VALID BA0 = L, BA1 = L BA0 = L, BA1 = H Precharge all banks Tn + 1 To + 1 Tp + 1 Tq + 1 Tr + 1

PDF:09005aef8219eeeb/Source: 09005aef8219eedd Micron Technology, Inc., reserves the right to change products or specifications without notice. MT48H16M16LF_2.fm - Rev F 4/07 EN 54 ©2006 Micron Technology, Inc. All rights reserved. 256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM Timing Diagrams Figure 35: Power-Down Mode Notes: 1. Violating refresh requirements during power-down may result in a loss of data. See Table 11 on page 46. t CH t CL t CK Two clock cycles CKE CLK DQ All banks idle, enter power-down mode Precharge all active banks Input buffers gated off while in power-down mode Exit power-down mode DON’T CARE t CKS t CKS COMMAND t CMH t CMS PRECHARGE NOP NOP ACTIVE NOP All banks idle BA0, BA1 BANK BANK(S) High-Z t AH t AS t CKH t CKS DQM ADDR ROW ALL BANKS SINGLE BANK A10 ROW T0 T1 T 2 Tn + 1 Tn + 2

PDF:09005aef8219eeeb/Source: 09005aef8219eedd Micron Technology, Inc., reserves the right to change products or specifications without notice. MT48H16M16LF_2.fm - Rev F 4/07 EN 55 ©2006 Micron Technology, Inc. All rights reserved. 256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM Timing Diagrams Figure 36: Clock Suspend Mode Notes: 1. For this example, BL = 2, CL = 3, and auto precharge is disabled. t CH t CL t CK t AC t LZ DQM CLK DQ A10 t OH DOUT m t AH t AS t AH t AS t AH t AS BANK t DH DOUT e t AC t HZ DOUT m + 1 COMMAND t CMH t CMS NOP NOP NOP NOP NOP READ WRITE DON’T CARE UNDEFINED CKE t CKS t CKH BANK COLUMN m t DS DOUT e + 1 NOP t CKH t CKS t CMH t CMS

2 COLUMN e

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 BA0, BA1 ADDR

PDF:09005aef8219eeeb/Source: 09005aef8219eedd Micron Technology, Inc., reserves the right to change products or specifications without notice. MT48H16M16LF_2.fm - Rev F 4/07 EN 56 ©2006 Micron Technology, Inc. All rights reserved. 256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM Timing Diagrams Figure 37: Auto Refresh Mode Notes: 1. Each AUTO REFRESH command performs a REFR ESH cycle. Back-to-back commands are not required. See Table 11 on page 46. UNDEFINED DON’T CARE t CH t CL t CK CKE CLK DQ t RFC t RP COMMAND t CMH t CMS NOP NOP BANK ACTIVE AUTO REFRESH NOP NOP PRECHARGE Precharge all active banks AUTO REFRESH t RFC High-Z BANK(S) t AH t AS t CKH t CKS NOP ROW ALL BANKS SINGLE BANK A10 ROW T0 T1 T2 Tn + 1 To + 1 BA0, BA1 ADDR DQM

PDF:09005aef8219eeeb/Source: 09005aef8219eedd Micron Technology, Inc., reserves the right to change products or specifications without notice. MT48H16M16LF_2.fm - Rev F 4/07 EN 57 ©2006 Micron Technology, Inc. All rights reserved. 256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM Timing Diagrams Figure 38: Self Refresh Mode t CH t CL t CK t RP CKE CLK DQ Enter self refresh mode Precharge all active banks t XSR CLK stable prior to exiting self refresh mode Exit self refresh mode (Restart refresh time base) DON’T CARE COMMAND t CMH t CMS AUTO REFRESH PRECHARGE NOP NOP BANK(S) High-Z t CKS AH AS AUTO REFRESH > t RAS t CKH t CKS t t ALL BANKS SINGLE BANK A10 T0 T1 T2 Tn + 1 To + 1 To + 2 BA0, BA1 DQM ADDR

PDF:09005aef8219eeeb/Source: 09005aef8219eedd Micron Technology, Inc., reserves the right to change products or specifications without notice. MT48H16M16LF_2.fm - Rev F 4/07 EN 58 ©2006 Micron Technology, Inc. All rights reserved. 256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM Timing Diagrams Figure 39: READ – without Auto Precharge Notes: 1. For this example, BL = 4, CL = 2, and th e READ burst is followed by a manual PRECHARGE. ALL BANKS t CH t CL t CK t AC t LZ t RP t RAS t RCD CL t RC CKE CLK DQ A10 t OH DOUT m t CMH t CMS t AH t AS t AH t AS t AH t AS ROW ROW BANK BANK(S) BANK ROW ROW BANK t HZ t OH DOUT m + 3 t AC t OH t AC t OH t AC DOUT m + 2 DOUT m + 1 COMMAND t CMH t CMS PRECHARGE NOP NOP NOP ACTIVE NOP READ NOP ACTIVE DISABLE AUTO PRECHARGE SINGLE BANK DON’T CARE UNDEFINED tCKH t CKS COLUMN m T0 T1 T2 T4 T3 T5 T6 T7 T8 BA0, BA1 DQM ADDR

PDF:09005aef8219eeeb/Source: 09005aef8219eedd Micron Technology, Inc., reserves the right to change products or specifications without notice. MT48H16M16LF_2.fm - Rev F 4/07 EN 59 ©2006 Micron Technology, Inc. All rights reserved. 256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM Timing Diagrams Figure 40: READ – with Auto Precharge Notes: 1. For this example, BL = 4, CL = 2. t CH t CL t CK t AC t LZ t RP t RAS t RCD CL t RC CKE CLK DQ A10 t OH DOUT m t CMH t CMS t AH t AS t AH t AS t AH t AS ROW ROW BANK BANK ROW ROW BANK t HZ t OH DOUT m + 3 t AC t OH t AC t OH t AC DOUT m + 2 DOUT m + 1 COMMAND t CMH t CMS NOP NOP NOP NOP ACTIVE NOP READ NOP ACTIVE ENABLE AUTO PRECHARGE DON’T CARE UNDEFINED tCKH t CKS COLUMN m T0 T1 T2 T4 T3 T5 T6 T7 T8 BA0, BA1 DQM ADDR

PDF:09005aef8219eeeb/Source: 09005aef8219eedd Micron Technology, Inc., reserves the right to change products or specifications without notice. MT48H16M16LF_2.fm - Rev F 4/07 EN 60 ©2006 Micron Technology, Inc. All rights reserved. 256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM Timing Diagrams Figure 41: Single READ – without Auto Precharge Notes: 1. For this example, BL = 4, CL = 2, and th e READ burst is followed by a manual PRECHARGE. 2. PRECHARGE comman d not allowed or tRAS would be violated. See Table 11 on page 46. ALL BANKS t CH t CL t CK t AC t LZ t RP t RAS t RCD CL t RC CKE CLK DQ A10 t OH DOUT m t CMH t CMS t AH t AS t AH t AS t AH t AS ROW ROW BANK BANK(S) BANK ROW ROW BANK t HZ COMMAND t CMH t CMS NOP NOP2 NOP2 PRECHARGE ACTIVE NOP READ ACTIVE NOP DISABLE AUTO PRECHARGE SINGLE BANK DON’T CARE UNDEFINED tCKH t CKS COLUMN m T0 T1 T2 T4 T3 T5 T6 T7 T8 BA0, BA1 DQM ADDR

PDF:09005aef8219eeeb/Source: 09005aef8219eedd Micron Technology, Inc., reserves the right to change products or specifications without notice. MT48H16M16LF_2.fm - Rev F 4/07 EN 61 ©2006 Micron Technology, Inc. All rights reserved. 256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM Timing Diagrams Figure 42: Single READ – with Auto Precharge Notes: 1. For this example, BL = 4, CL = 2, and th e READ burst is followed by a manual PRECHARGE. 2. PRECHARGE comman d not allowed or tRAS would be violated. See Table 11 on page 46. t CH t CL t CK t AC t RP t RAS t RCD CL t RC CKE CLK DQ A10 t OH DOUT m t CMH t CMS t AH t AS t AH t AS t AH t AS ROW ROW BANK BANK ROW ROW BANK tHZ COMMAND t CMH t CMS NOP NOP NOP2 NOP2 READ ACTIVE NOP ACTIVE NOP ENABLE AUTO PRECHARGE DON’T CARE UNDEFINED tCKH t CKS COLUMN m T0 T1 T2 T4 T3 T5 T6 T7 T8 BA0, BA1 DQM ADDR

PDF:09005aef8219eeeb/Source: 09005aef8219eedd Micron Technology, Inc., reserves the right to change products or specifications without notice. MT48H16M16LF_2.fm - Rev F 4/07 EN 62 ©2006 Micron Technology, Inc. All rights reserved. 256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM Timing Diagrams Figure 43: Alternating Bank Read Accesses Notes: 1. For this example, BL = 4, CL = 2. DON’T CARE UNDEFINED ENABLE AUTO PRECHARGE tCH tCLtCK tAC tLZ CLK DQ A10 tOH DOUT m tCMHtCMS tAHtAS tAHtAS tAHtAS ROW ROW ROW ROW tOH DOUT m + 3 tAC tOH tAC tOH tAC DOUT m + 2DOUT m + 1 COMMAND tCMHtCMS NOP NOPACTIVE NOP READ NOP ACTIVE tOH DOUT b tAC tAC READ ENABLE AUTO PRECHARGE ROW ACTIVE ROW BANK 0 BANK 0 BANK 3 BANK 3 BANK 0 CKE tCKHtCKS COLUMN m COLUMN b2 T0 T1 T2 T4 T3 T5 T6 T7 T8 tRP - bank 0 tRAS - bank 0 tRCD - bank 0 tRCD - bank 0CL - bank 0 tRCD - bank 4 CL - bank 4 t t RC - bank 0 RRD BA0, BA1 DQM ADDR

PDF:09005aef8219eeeb/Source: 09005aef8219eedd Micron Technology, Inc., reserves the right to change products or specifications without notice. MT48H16M16LF_2.fm - Rev F 4/07 EN 63 ©2006 Micron Technology, Inc. All rights reserved. 256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM Timing Diagrams Figure 44: READ – DQM Operation Notes: 1. For this example, CL = 2. tCH tCLtCK tAC tAC tLZ tRCD CL CKE CLK DQ A10 tOH DOUT m tCMHtCMS tAHtAS tAHtAS tAHtAS ROW BANK ROW BANK tHZ tAC tLZ tOH DOUT m + 2 tOH DOUT m + 3 tHZ COMMAND tCMHtCMS NOPNOPNOP NOPACTIVE NOP READ NOP NOP DISABLE AUTO PRECHARGE ENABLE AUTO PRECHARGE DON’T CARE UNDEFINED tCKHtCKS COLUMN m T0 T1 T2 T4 T3 T5 T6 T7 T8 BA0, BA1 DQM ADDR

PDF:09005aef8219eeeb/Source: 09005aef8219eedd Micron Technology, Inc., reserves the right to change products or specifications without notice. MT48H16M16LF_2.fm - Rev F 4/07 EN 64 ©2006 Micron Technology, Inc. All rights reserved. 256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM Timing Diagrams Figure 45: WRITE – without Auto Precharge Notes: 1. For this example, BL = 4, and the WR ITE burst is followed by a manual PRECHARGE. 2. 15ns is required between <D IN m + 3> and the PRECHARGE command, regardless of fre- quency. DISABLE AUTO PRECHARGE ALL BANKS t CH t CL t CK t RP t RAS t RCD t RC CKE CLK DQ A10 t CMH t CMS t AH t AS ROW BANK BANK ROW BANK tWR2 DON’T CARE DIN m t DH t DS DIN m + 1 DIN m + 2 DIN m + 3 COMMAND t CMH t CMS NOP NOP NOP ACTIVE NOP WRITE PRECHARGE NOP NOP ROW BANK ROW t AH t AS t AH t AS t DH t DS t DH t DS t DH t DS SINGLE BANK t CKH t CKS COLUMN m T0 T1 T2 T4 T3 T5 T6 T7 T8 T9 DQM BA0, BA1 ADDR ACTIVE

PDF:09005aef8219eeeb/Source: 09005aef8219eedd Micron Technology, Inc., reserves the right to change products or specifications without notice. MT48H16M16LF_2.fm - Rev F 4/07 EN 65 ©2006 Micron Technology, Inc. All rights reserved. 256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM Timing Diagrams Figure 46: WRITE – with Auto Precharge Notes: 1. For this example, BL = 4. ENABLE AUTO PRECHARGE t CH t CL t CK t RP t RAS t RCD t RC CKE CLK DQ A10 t CMH t CMS t AH t AS ROW BANK ROW BANK tWR2 DON’T CARE UNDEFINED DIN m t DH t DS DIN m + 1 DIN m + 2 DIN m + 3 COMMAND t CMH t CMS NOP NOP NOP ACTIVE NOP WRITE NOP NOP NOP ROW BANK ROW t AH t AS t AH t AS t DH t DS t DH t DS t DH t DS t CKH t CKS COLUMN m T0 T1 T2 T4 T3 T5 T6 T7 T8 T9 DQM BA0, BA1 ADDR ACTIVE

PDF:09005aef8219eeeb/Source: 09005aef8219eedd Micron Technology, Inc., reserves the right to change products or specifications without notice. MT48H16M16LF_2.fm - Rev F 4/07 EN 66 ©2006 Micron Technology, Inc. All rights reserved. 256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM Timing Diagrams Figure 47: Single WRITE – without Auto Precharge Notes: 1. For this example, BL = 1, and the WR ITE burst is followed by a manual PRECHARGE. 2. 15ns is required between <D IN m> and the PRECHARGE command, regardless of frequency. 3. PRECHARGE comman d not allowed or tRAS would be violated. See Table 11 on page 46. ALL BANKS t CH t CL t CK t RP t RAS t RCD tWR2 t RC CKE CLK DQ A10 t CMH t CMS t AH t AS t AH t AS t AH t AS ROW BANK BANK BANK ROW ROW BANK COMMAND t CMH t CMS NOP NOP3 NOP3 PRECHARGE ACTIVE NOP WRITE ACTIVE NOP DISABLE AUTO PRECHARGE SINGLE BANK DON’T CARE tCKH t CKS COLUMN m T0 T1 T2 T4 T3 T5 T6 T7 T8 BA0, BA1 DQM ADDR DIN m t DH t DS

PDF:09005aef8219eeeb/Source: 09005aef8219eedd Micron Technology, Inc., reserves the right to change products or specifications without notice. MT48H16M16LF_2.fm - Rev F 4/07 EN 67 ©2006 Micron Technology, Inc. All rights reserved. 256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM Timing Diagrams Figure 48: Single WRITE – with Auto Precharge Notes: 1. For this example, BL = 1, and the WR ITE burst is followed by a manual PRECHARGE. 2. 15ns is required between <D IN m> and the PRECHARGE command, regardless of frequency. 3. WRITE command not allowed or tRAS would be violated. See Table 11 on page 46. t CH t CL t CK CKE CLK DQ A10 t CMH t CMS t AH t AS t AH t AS t AH t AS ROW ROW BANK BANK ROW ROW BANK COMMAND t CMH t CMS NOP NOP NOP3 NOP3 WRITE ACTIVE NOP 3 NOP ACTIVE NOP ENABLE AUTO PRECHARGE DON’T CARE tCKH t CKS COLUMN m T0 T1 T2 T4 T3 T5 T6 T7 T8 T9 BA0, BA1 DQM ADDR t RP t RAS t RCD t RC tWR DIN m t DH t DS

PDF:09005aef8219eeeb/Source: 09005aef8219eedd Micron Technology, Inc., reserves the right to change products or specifications without notice. MT48H16M16LF_2.fm - Rev F 4/07 EN 68 ©2006 Micron Technology, Inc. All rights reserved. 256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM Timing Diagrams Figure 49: Alternating Bank Write Accesses Notes: 1. For this example, BL = 4. DON’T CARE ENABLE AUTO PRECHARGE t CH t CL t CK CLK DQ A10 t CMH t CMS t AH t AS t AH t AS t AH t AS ROW ROW ROW ROW COMMAND t CMH t CMS NOP NOP ACTIVE NOP WRITE NOP NOP ACTIVE WRITE ENABLE AUTO PRECHARGE ROW ACTIVE ROW BANK 0 BANK 0 BANK 1 BANK 1 BANK 0 CKE t CKH t CKS COLUMN m COLUMN b 2 T0 T1 T2 T4 T3 T5 T6 T7 T8 T9 t RP - bank 0 t RAS - bank 0 t RCD - bank 0 t RCD - bank 0 t WR - bank 1 t WR - bank 0 t RCD - bank 1 t t RC - bank 0 RRD BA0, BA1 DQM ADDR DIN m t DH t DS DIN m + 1 DIN m + 2 DIN m + 3 t DH t DS t DH t DS t DH t DS DIN b t DH t DS DIN b + 1 t DH t DS DIN b + 2 t DH t DS DIN m + 3 t DH t DS

PDF:09005aef8219eeeb/Source: 09005aef8219eedd Micron Technology, Inc., reserves the right to change products or specifications without notice. MT48H16M16LF_2.fm - Rev F 4/07 EN 69 ©2006 Micron Technology, Inc. All rights reserved. 256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM Timing Diagrams Figure 50: WRITE – DQM Operation Notes: 1. For this example, BL = 4. DON’T CARE t CH t CL t CK t RCD CKE CLK DQ A10 t CMS t AH t AS ROW BANK ROW BANK ENABLE AUTO PRECHARGE DIN m + 3 t DH t DS DIN m DIN m + 2 t CMH COMMAND NOP NOP NOP ACTIVE NOP WRITE NOP NOP t CMS t CMH t DH t DS t DH t DS t AH t AS t AH t AS DISABLE AUTO PRECHARGE t CKH t CKS COLUMN m T0 T1 T2 T3 T4 T5 T6 T7 BA0, BA1 DQM ADDR

PDF:09005aef8219eeeb/Source: 09005aef8219eedd Micron Technology, Inc., reserves the right to change products or specifications without notice. MT48H16M16LF_2.fm - Rev F 4/07 EN 70 ©2006 Micron Technology, Inc. All rights reserved. 256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM Package Dimensions Package Dimensions Figure 51: 54-Ball VFBGA (8mm x 9mm) Notes: 1. All dimensions are in millimeters. MICRON LOGO TO BE LASED BALL A1 ID SUBSTRATE MATERIAL: PLASTIC LAMINATE MOLD COMPOUND: EPOXY NOVOLAC SOLDER BALL MATERIAL: 96.5% Sn, 3% Ag, 0.5% Cu SEATING PLANE 0.65 ±0.05 BALL A9 SOLDER BALL DIAMETER REFERS TO POST REFLOW CONDITION. THE PRE- REFLOW DIAMETER IS 0.42 ON A 0.40 SMD BALL PAD.

0.10 A A

9.00 ± 0.10

0.80 TYP

4.50 ±0.05

1.00 MAX

3.20 6.40 BALL A1 ID BALL A1 0.80 TYP 8.00 ±0.10 3.20 4.00 ±0.05 6.40 54X Ø0.45 C L C L

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 prodmktg@micron.com www.micron.com Customer Comment Line: 800-932-4992 Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. This data sheet contains minimum and maximum limits specified over the complete power supply and temperature range for production devices. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. 256Mb: 16 Meg x 16, 8 Meg x 32 Mobile SDRAM Package Dimensions PDF:09005aef8219eeeb/Source: 09005aef8219eedd Micron Technology, Inc., reserves the right to change products or specifications without notice. MT48H16M16LF_2.fm - Rev F 4/07 EN 71 ©2006 Micron Technology, Inc. All rights reserved. Figure 52: 90-Ball VFBGA (8mm x 13mm) Notes: 1. All dimensions are in millimeters. BALL A1 ID MOLD COMPOUND: EPOXY NOVOLAC SUBSTRATE MATERIAL: PLASTIC LAMINATE SOLDER BALL MATERIAL: 96.5% Sn, 3%Ag, 0.5% Cu 13.00 ±0.10 BALL A1 BALL A9 BALL A1 ID 6.50 ±0.05 8.00 ±0.10 4.00 ±0.05 3.20 5.60 ±0.05 0.65 ±0.05 SEATING PLANE A 11.20 ±0.10 6.40 0.10 A 90X Ø0.45 DIMENSIONS APPLY TO SOLDER BALLS POST REFLOW. THE PRE- REFLOW DIAMETER IS 0.42 ON A 0.40 SMD BALL PAD C L C L