MT41J128M16

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Document overview

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• PDF pages: 211

Technical content

Datasheet sections

• 34 Ohm Output Driver Impedance
• 34 Ohm Driver
• 34 Ohm Output Driver Sensitivity
• 40 Ohm Output Driver Sensitivity

Features

• V DD = VDDQ = 1.5V ±0.075V
• 1.5V center-terminated push/pull I/O
• Differential bidirectional data strobe
• 8 n-bit prefetch architecture
• Differential clock inputs (CK, CK#)
• 8 internal banks
• Nominal and dynamic on-die termination (ODT) for data, strobe, and mask signals
• Programmable CAS READ latency (CL)
• Posted CAS additive latency (AL)
• Programmable CAS WRITE latency (CWL) based on tCK
• Fixed burst length (BL) of 8 and burst chop (BC) of 4 (via the mode register set [MRS])
• Selectable BC4 or BL8 on-the-fly (OTF)
• Self refresh mode C of 0°C to 95°C – 64ms, 8192 cycle refresh at 0°C to 85°C – 32ms, 8192 cycle refresh at 85°C to 95°C
• Self refresh temperature (SRT)
• Write leveling
• Multipurpose register
• Output driver calibration Options1 Marking
• Configuration – 512 Meg x 4 512M4 – 256 Meg x 8 256M8 – 128 Meg x 16 128M16
• FBGA package (Pb-free) – x4, x8 – 78-ball (8mm x 10.5mm) Rev. M, K DA – 78-ball (9mm x 11.5mm) Rev. D HX
• FBGA package (Pb-free) – x16 – 96-ball (9mm x 14mm) Rev. D HA – 96-ball (8mm x 14mm) Rev. K JT
• Timing – cycle time – 938ps @ CL = 14 (DDR3-2133) -093 – 1.071ns @ CL = 13 (DDR3-1866) -107 – 1.25ns @ CL = 11 (DDR3-1600) -125 – 1.5ns @ CL = 9 (DDR3-1333) -15E – 1.87ns @ CL = 7 (DDR3-1066) -187E
• Operating temperature – Commercial (0°C ≤ T C ≤ +95°C) None – Industrial (–40°C ≤ TC ≤ +95°C) IT
• Revision :D/:M/:K Note: 1. Not all options listed can be combined to define an offered product. Use the part catalog search on http://www.micron.com for available offerings. Table 1: Key Timing Parameters Speed Grade Data Rate (MT/s) Target tRCD-tRP-CL tRCD (ns) tRP (ns) CL (ns) -0931, 2, 3, 4 2133 14-14-14 13.09 13.09 13.09 -1071, 2, 3 1866 13-13-13 13.91 13.91 13.91 -1251, 2, 1600 11-11-11 13.75 13.75 13.75 -15E1, 1333 9-9-9 13.5 13.5 13.5 -187E 1066 7-7-7 13.1 13.1 13.1 Notes: 1. Backward compatible to 1066, CL = 7 (-187E). 2. Backward compatible to 1333, CL = 9 (-15E). 3. Backward compatible to 1600, CL = 11 (-125). 4. Backward compatible to 1866, CL = 13 (-107). 2Gb: x4, x8, x16 DDR3 SDRAM

PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 1 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice.

Table 2: Addressing Parameter 512 Meg x 4 256 Meg x 8 128 Meg x 16 Configuration 64 Meg x 4 x 8 banks 32 Meg x 8 x 8 banks 16 Meg x 16 x 8 banks Refresh count 8K 8K 8K Row addressing 32K (A[14:0]) 32K (A[14:0]) 16K (A[13:0]) Bank addressing 8 (BA[2:0]) 8 (BA[2:0]) 8 (BA[2:0]) Column addressing 2K (A[11, 9:0]) 1K (A[9:0]) 1K (A[9:0]) Page size 1KB 1KB 2KB Figure 1: DDR3 Part Numbers Package 78-ball 9mm x 11.5mm FBGA 78-ball 8mm x 10.5mm FBGA 96-ball 9mm x 14mm FBGA HX DA HA Example Part Number: MT41J256M8DA-125:K 96-ball 8mm x 14mm FBGA JT Configuration

512 Meg x 4

256 Meg x 8

128 Meg x 16

tCK = 1.071ns, CL = 13 tCK = 1.25ns, CL = 11 tCK = 1.5ns, CL = 9 tCK = 1.87ns, CL = 7 -107 -125 -15E -187E ConfigurationMT41J Package Speed Revision tCK = 0.938ns, CL = 14-093 Revision:D/:M/:K Temperature Commercial Industrial temperature None IT Note: 1. Not all options listed can be combined to define an offered product. Use the part catalog search on http://www.micron.com for available offerings. FBGA Part Marking Decoder Due to space limitations, FBGA-packaged components have an abbreviated part marking that is different from the part number. For a quick conversion of an FBGA code, see the FBGA Part Marking Decoder on Micron’s Web site: http://www.micron.com. 2Gb: x4, x8, x16 DDR3 SDRAM PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 2 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

2Gb: x4, x8, x16 DDR3 SDRAM PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 4 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

2Gb: x4, x8, x16 DDR3 SDRAM PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 5 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

2Gb: x4, x8, x16 DDR3 SDRAM PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 9 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

2Gb: x4, x8, x16 DDR3 SDRAM PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 10 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Figure 2: Simplified State Diagram SRX = Self refresh exit WRITE = WR, WRS4, WRS8 WRITE AP = WRAP, WRAPS4, WRAPS8 ZQCL = ZQ LONG CALIBRATION ZQCS = ZQ SHORT CALIBRATION Bank active ReadingWriting Activating Refreshing Self refresh Idle Active power- down ZQ calibration From any state Power applied Reset procedure Power on Initial- ization MRS, MPR, write leveling Precharge power- down Writing Reading Automatic sequence Command sequence Precharging READ READ READ READ AP READ AP READ AP PRE, PREA PRE, PREA PRE, PREA WRITE WRITE CKE L CKE L CKE L WRITE WRITE AP WRITE AP WRITE AP PDE PDE PDX PDX SRX SRE REF MRS ACT RESET ZQCL ZQCL/ZQCS ACT = ACTIVATE MPR = Multipurpose register MRS = Mode register set PDE = Power-down entry PDX = Power-down exit PRE = PRECHARGE PREA = PRECHARGE ALL READ = RD, RDS4, RDS8 READ AP = RDAP, RDAPS4, RDAPS8 REF = REFRESH RESET = START RESET PROCEDURE SRE = Self refresh entry 2Gb: x4, x8, x16 DDR3 SDRAM State Diagram PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 11 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

DDR3 SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is an 8n-prefetch architecture with an interface de- signed to transfer two data words per clock cycle at the I/O pins. A single read or write operation for the DDR3 SDRAM effectively consists of a single 8n-bit-wide, four-clock- cycle data transfer at the internal DRAM core and eight corresponding n-bit-wide, one- half-clock-cycle data transfers at the I/O pins. The differential data strobe (DQS, DQS#) is transmitted externally, along with data, for use in data capture at the DDR3 SDRAM input receiver. DQS is center-aligned with data for WRITEs. The read data is transmitted by the DDR3 SDRAM and edge-aligned to the data strobes. The DDR3 SDRAM operates from a differential clock (CK and CK#). The crossing of CK going HIGH and CK# going LOW is referred to as the positive edge of CK. Control, com- mand, and address signals are registered at every positive edge of CK. Input data is reg- istered on the first rising edge of DQS after the WRITE preamble, and output data is ref- erenced on the first rising edge of DQS after the READ preamble. Read and write accesses to the DDR3 SDRAM are burst-oriented. Accesses start at a se- lected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVATE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVATE command are used to select the bank and row to be accessed. The ad- dress bits registered coincident with the READ or WRITE commands are used to select the bank and the starting column location for the burst access. The device uses a READ and WRITE BL8 and BC4. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. As with standard DDR SDRAM, the pipelined, multibank architecture of DDR3 SDRAM allows for concurrent operation, thereby providing high bandwidth by hiding row pre- charge and activation time. A self refresh mode is provided, along with a power-saving, power-down mode. Industrial Temperature The industrial temperature (IT) device requires that the case temperature not exceed –40°C or 95°C. JEDEC specifications require the refresh rate to double when TC exceeds 85°C; this also requires use of the high-temperature self refresh option. Additionally, ODT resistance and the input/output impedance must be derated when T C is < 0°C or >95°C. General Notes

• The functionality and the timing specifications discussed in this data sheet are for the DLL enable mode of operation (normal operation).
• Throughout this data sheet, various figures and text refer to DQs as “DQ.” DQ is to be interpreted as any and all DQ collectively, unless specifically stated otherwise.
• The terms “DQS” and “CK” found throughout this data sheet are to be interpreted as DQS, DQS# and CK, CK# respectively, unless specifically stated otherwise. 2Gb: x4, x8, x16 DDR3 SDRAM Functional Description PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 12 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

• Complete functionality may be described throughout the document; any page or dia- gram may have been simplified to convey a topic and may not be inclusive of all re- quirements.
• Any specific requirement takes precedence over a general statement.
• Any functionality not specifically stated is considered undefined, illegal, and not sup- ported, and can result in unknown operation.
• Row addressing is denoted as A[ n:0]. For example, 1Gb: n = 12 (x16); 1Gb: n = 13 (x4, x8); 2Gb: n = 13 (x16) and 2Gb: n = 14 (x4, x8); 4Gb: n = 14 (x16); and 4Gb: n = 15 (x4, x8).
• Dynamic ODT has a special use case: when DDR3 devices are architected for use in a single rank memory array, the ODT ball can be wired HIGH rather than routed. Refer to the Dynamic ODT Special Use Case section.
• A x16 device's DQ bus is comprised of two bytes. If only one of the bytes needs to be used, use the lower byte for data transfers and terminate the upper byte as noted: – Connect UDQS to ground via 1k Ω* resistor. – Connect UDQS# to V DD via 1kΩ* resistor. – Connect UDM to V DD via 1kΩ* resistor. – Connect DQ[15:8] individually to either V SS, VDD, or VREF via 1kΩ resistors,* or float DQ[15:8]. *If ODT is used, 1kΩ resistor should be changed to 4x that of the selected ODT . 2Gb: x4, x8, x16 DDR3 SDRAM Functional Description PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 13 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

DDR3 SDRAM is a high-speed, CMOS dynamic random access memory. It is internally configured as an 8-bank DRAM. Figure 3: 512 Meg x 4 Functional Block Diagram Bank 5 Bank 6 Bank 7 Bank 4 Bank 7 Bank 4 Bank 5 Bank 6 Row- address MUX Control logic Column- address counter/ latch Mode registers Command decode A[14:0] BA[2:0] Address register18 256 (x32) 8,192 I/O gating DM mask logic Column decoder Bank 0 memory array (32,768 x 256 x 32) Bank 0 row- address latch and decoder 32,768 Sense amplifiers Bank control logic Bank 1 Bank 2 Bank 3 Refresh counter DQS, DQS# Columns 0, 1, and 2 Columns 0, 1, and 2 ZQCL, ZQCS To pullup/pulldown networks READ drivers DQ[3:0] READ FIFO and data MUX Data Bank 1 Bank 2 Bank 3 DM DM CK,CK# DQS, DQS# ODT control ZQ CAL WE# ZQ RZQ CK, CK# RAS# CAS# CS# ODT CKE RESET# CK,CK# DLL DQ[3:0] (1 . . . 4) (1, 2) SW1 SW2 VDDQ/2 RTT,nom RTT(WR) SW1 SW2 VDDQ/2 RTT,nom RTT(WR) SW1 SW2 VDDQ/2 RTT,nom RTT(WR) BC4 BC4 (burst chop) BC4 Column 2 (select upper or lower nibble for BC4) Data interface WRITE drivers and input logic A12VSSQ OTF OTF 2Gb: x4, x8, x16 DDR3 SDRAM Functional Block Diagrams PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 14 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Ball Assignments and Descriptions Figure 6: 78-Ball FBGA – x4, x8 (Top View) 1234 6789 5 VSS VSS VDDQ VSSQ VREFDQ NC ODT NC VSS VDD VSS VDD VSS VDD VSSQ DQ2 NF, DQ6 VDDQ VSS VDD CS# BA0 RESET# NC DQ0 DQS DQS# NF, DQ4 RAS# CAS# WE# BA2 A13 NF, NF/TDQS# DM, DM/TDQS DQ1 VDD NF, DQ7 CK CK# A10/AP NC A12/BC# A11 A14 VDD VDDQ VSSQ VSSQ VDDQ NC CKE NC VSS VDD VSS VDD VSS VSS VSSQ DQ3 VSS NF, DQ5 VSS VDD ZQ VREFCA BA1 A B C D E F G H J K L M N Notes: 1. Ball descriptions listed in Table 3 (page 18) are listed as “x4, x8” if unique; otherwise, x4 and x8 are the same. 2. A comma separates the configuration; a slash defines a selectable function. Example: D7 = NF, NF/TDQS#. NF applies to the x4 configuration only. NF/TDQS# applies to the x8 configuration only—selectable between NF or TDQS# via MRS (symbols are de- fined in Table 3). 2Gb: x4, x8, x16 DDR3 SDRAM Ball Assignments and Descriptions PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 16 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Figure 7: 96-Ball FBGA – x16 (Top View) 1234 6789 5 A B C D E F G H J K L M N P R T VDDQ VSSQ VDDQ VSSQ VSS VDDQ VSSQ VREFDQ NC ODT NC VSS VDD VSS VDD VSS DQ13 VDD DQ11 VDDQ VSSQ DQ2 DQ6 V DDQ VSS VDD CS# BA0 RESET# DQ15 VSS DQ9 UDM DQ0 LDQS LDQS# DQ4 RAS# CAS# WE# BA2 A13 DQ12 UDQS# UDQS DQ8 LDM DQ1 VDD DQ7 CK CK# A10/AP NC A12/BC# A11 NC VDDQ DQ14 DQ10 VSSQ VSSQ DQ3 VSS DQ5 VSS VDD ZQ VREFCA BA1 VSS VSSQ VDDQ VDD VDDQ VSSQ VSSQ VDDQ NC CKE NC VSS VDD VSS VDD VSS Note: 1. Ball descriptions listed in Table 4 (page 20). 2Gb: x4, x8, x16 DDR3 SDRAM Ball Assignments and Descriptions PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 17 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Table 3: 78-Ball FBGA – x4, x8 Ball Descriptions Symbol Type Description A[14:13], A12/BC#, A11, A10/AP, A[9:0] Input Address inputs: Provide the row address for ACTIVATE commands, and the column address and auto precharge bit (A10) for READ/WRITE commands, to select one location out of the memory array in the respective bank. A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one bank (A10 LOW, bank selected by BA[2:0]) or all banks (A10 HIGH). The address inputs also provide the op-code during a LOAD MODE command. Address inputs are referenced to V REFCA. A12/BC#: When enabled in the mode register (MR), A12 is sampled during READ and WRITE commands to determine whether burst chop (on-the-fly) will be performed (HIGH = BL8 or no burst chop, LOW = BC4). See Table 70 (page 113). BA[2:0] Input Bank address inputs: BA[2:0] define the bank to which an ACTIVATE, READ, WRITE, or PRECHARGE command is being applied. BA[2:0] define which mode register (MR0, MR1, MR2, or MR3) is loaded during the LOAD MODE command. BA[2:0] are referenced to V REFCA. CK, CK# Input Clock: CK and CK# are differential clock inputs. All control and address input signals are sampled on the crossing of the positive edge of CK and the negative edge of CK#. Output data strobe (DQS, DQS#) is referenced to the crossings of CK and CK#. CKE Input Clock enable: CKE enables (registered HIGH) and disables (registered LOW) internal circuitry and clocks on the DRAM. The specific circuitry that is enabled/disabled is de- pendent upon the DDR3 SDRAM configuration and operating mode. Taking CKE LOW provides PRECHARGE POWER-DOWN and SELF REFRESH operations (all banks idle), or active power-down (row active in any bank). CKE is synchronous for power- down entry and exit and for self refresh entry. CKE is asynchronous for self refresh exit. Input buffers (excluding CK, CK#, CKE, RESET#, and ODT) are disabled during POWER-DOWN. Input buffers (excluding CKE and RESET#) are disabled during SELF REFRESH. CKE is referenced to V REFCA. CS# Input Chip select: CS# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when CS# is registered HIGH. CS# provides for external rank selection on systems with multiple ranks. CS# is considered part of the command code. CS# is referenced to V REFCA. DM Input Input data mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH along with the input data during a write access. Although the DM ball is input-only, the DM loading is designed to match that of the DQ and DQS balls. DM is referenced to V REFDQ. DM has an optional use as TDQS on the x8. ODT Input On-die termination: ODT enables (registered HIGH) and disables (registered LOW) termination resistance internal to the DDR3 SDRAM. When enabled in normal operation, ODT is only applied to each of the following balls: DQ[7:0], DQS, DQS#, and DM for the x8; DQ[3:0], DQS, DQS#, and DM for the x4. The ODT input is ignored if disabled via the LOAD MODE command. ODT is referenced to V REFCA. RAS#, CAS#, WE# Input Command inputs: RAS#, CAS#, and WE# (along with CS#) define the command being entered and are referenced to VREFCA. RESET# Input Reset: RESET# is an active LOW CMOS input referenced to VSS. The RESET# input re- ceiver is a CMOS input defined as a rail-to-rail signal with DC HIGH ≥ 0.8 × VDD and DC LOW ≤ 0.2 × VDDQ. RESET# assertion and de-assertion are asynchronous. 2Gb: x4, x8, x16 DDR3 SDRAM Ball Assignments and Descriptions PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 18 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Table 3: 78-Ball FBGA – x4, x8 Ball Descriptions (Continued) Symbol Type Description DQ[3:0] I/O Data input/output: Bidirectional data bus for the x4 configuration. DQ[3:0] are referenced to VREFDQ. DQ[7:0] I/O Data input/output: Bidirectional data bus for the x8 configuration. DQ[7:0] are referenced to VREFDQ. DQS, DQS# I/O Data strobe: Output with read data. Edge-aligned with read data. Input with write data. Center-aligned to write data. TDQS, TDQS# Output Termination data strobe: Applies to the x8 configuration only. When TDQS is enabled, DM is disabled, and the TDQS and TDQS# balls provide termination resistance. V DD Supply Power supply: 1.5V ±0.075V. VDDQ Supply DQ power supply: 1.5V ±0.075V. Isolated on the device for improved noise immuni- ty. VREFCA Supply Reference voltage for control, command, and address: VREFCA must be maintained at all times (including self refresh) for proper device operation. VREFDQ Supply Reference voltage for data: VREFDQ must be maintained at all times (excluding self refresh) for proper device operation. VSS Supply Ground. VSSQ Supply DQ ground: Isolated on the device for improved noise immunity. ZQ Reference External reference ball for output drive calibration: This ball is tied to external 240Ω resistor RZQ, which is tied to VSSQ. NC – No connect: These balls should be left unconnected (the ball has no connection to the DRAM or to other balls). NF – No function: When configured as a x4 device, these balls are NF. When configured as a x8 device, these balls are defined as TDQS#, DQ[7:4]. 2Gb: x4, x8, x16 DDR3 SDRAM Ball Assignments and Descriptions PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 19 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Table 4: 96-Ball FBGA – x16 Ball Descriptions Symbol Type Description A13, A12/BC#, A11, A10/AP, A[9:0] Input Address inputs: Provide the row address for ACTIVATE commands, and the column address and auto precharge bit (A10) for READ/WRITE commands, to select one location out of the memory array in the respective bank. A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one bank (A10 LOW, bank selected by BA[2:0]) or all banks (A10 HIGH). The address inputs also pro- vide the op-code during a LOAD MODE command. Address inputs are referenced to V REFCA. A12/BC#: When enabled in the mode register (MR), A12 is sampled during READ and WRITE commands to determine whether burst chop (on-the-fly) will be performed (HIGH = BL8 or no burst chop, LOW = BC4). See Table 70 (page 113). BA[2:0] Input Bank address inputs: BA[2:0] define the bank to which an ACTIVATE, READ, WRITE, or PRECHARGE command is being applied. BA[2:0] define which mode register (MR0, MR1, MR2, or MR3) is loaded during the LOAD MODE command. BA[2:0] are referenced to V REFCA. CK, CK# Input Clock: CK and CK# are differential clock inputs. All control and address input signals are sampled on the crossing of the positive edge of CK and the negative edge of CK#. Output data strobe (DQS, DQS#) is referenced to the crossings of CK and CK#. CKE Input Clock enable: CKE enables (registered HIGH) and disables (registered LOW) internal circuitry and clocks on the DRAM. The specific circuitry that is enabled/disabled is de- pendent upon the DDR3 SDRAM configuration and operating mode. Taking CKE LOW provides PRECHARGE POWER-DOWN and SELF REFRESH operations (all banks idle),or active power-down (row active in any bank). CKE is synchronous for power-down entry and exit and for self refresh entry. CKE is asynchronous for self re- fresh exit. Input buffers (excluding CK, CK#, CKE, RESET#, and ODT) are disabled during POWER-DOWN. Input buffers (excluding CKE and RESET#) are disabled during SELF RE- FRESH. CKE is referenced to V REFCA. CS# Input Chip select: CS# enables (registered LOW) and disables (registered HIGH) the com- mand decoder. All commands are masked when CS# is registered HIGH. CS# provides for external rank selection on systems with multiple ranks. CS# is considered part of the command code. CS# is referenced to V REFCA. LDM Input Input data mask: LDM is a lower-byte, input mask signal for write data. Lower-byte input data is masked when LDM is sampled HIGH along with the input data during a write access. Although the LDM ball is input-only, the LDM loading is designed to match that of the DQ and DQS balls. LDM is referenced to V REFDQ. ODT Input On-die termination: ODT enables (registered HIGH) and disables (registered LOW) termination resistance internal to the DDR3 SDRAM. When enabled in normal operation, ODT is only applied to each of the following balls: DQ[15:0], LDQS, LDQS#, UDQS, UDQS#, LDM, and UDM. The ODT input is ignored if disabled via the LOAD MODE command. ODT is referenced to V REFCA. RAS#, CAS#, WE# Input Command inputs: RAS#, CAS#, and WE# (along with CS#) define the command being entered and are referenced to VREFCA. RESET# Input Reset: RESET# is an active LOW CMOS input referenced to VSS. The RESET# input re- ceiver is a CMOS input defined as a rail-to-rail signal with DC HIGH ≥ 0.8 × VDD and DC LOW ≤ 0.2 × VDDQ. RESET# assertion and de-assertion are asynchronous. 2Gb: x4, x8, x16 DDR3 SDRAM Ball Assignments and Descriptions PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 20 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Table 4: 96-Ball FBGA – x16 Ball Descriptions (Continued) Symbol Type Description UDM Input Input data mask: UDM is an upper-byte, input mask signal for write data. Upper-byte input data is masked when UDM is sampled HIGH along with that input data during a WRITE access. Although the UDM ball is input-only, the UDM loading is designed to match that of the DQ and DQS balls. UDM is referenced to V REFDQ. DQ[7:0] I/O Data input/output: Lower byte of bidirectional data bus for the x16 configuration. DQ[7:0] are referenced to VREFDQ. DQ[15:8] I/O Data input/output: Upper byte of bidirectional data bus for the x16 configuration. DQ[15:8] are referenced to VREFDQ. LDQS, LDQS# I/O Lower byte data strobe: Output with read data. Edge-aligned with read data. Input with write data. Center-aligned to write data. UDQS, UDQS# I/O Upper byte data strobe: Output with read data. Edge-aligned with read data. Input with write data. DQS is center-aligned to write data. VDD Supply Power supply: 1.5V ±0.075V. VDDQ Supply DQ power supply: 1.5V ±0.075V. Isolated on the device for improved noise immunity. VREFCA Supply Reference voltage for control, command, and address: VREFCA must be main- tained at all times (including self refresh) for proper device operation. VREFDQ Supply Reference voltage for data: VREFDQ must be maintained at all times (excluding self refresh) for proper device operation. VSS Supply Ground. VSSQ Supply DQ ground: Isolated on the device for improved noise immunity. ZQ Reference External reference ball for output drive calibration: This ball is tied to external 240Ω resistor RZQ, which is tied to VSSQ. NC – No connect: These balls should be left unconnected (the ball has no connection to the DRAM or to other balls). 2Gb: x4, x8, x16 DDR3 SDRAM Ball Assignments and Descriptions PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 21 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Figure 8: 78-Ball FBGA – x4, x8 (DA) Ball A1 ID

1.2 MAX

0.25 MIN

8 ±0.1 Ball A1 ID 78X Ø0.45 Dimensions apply to solder balls post-reflow on Ø0.35 SMD ball pads.

0.8 TYP

9.6 CTR 10.5 ±0.1 0.8 ±0.05 0.155

1.8 CTR

Nonconductive overmold0.12 A A Seating Plane

6.4 CTR

A B C D E F G H J K L M N Notes: 1. All dimensions are in millimeters. 2. Solder ball material: SAC305 (96.5% Sn, 3% Ag, 0.5% Cu). 2Gb: x4, x8, x16 DDR3 SDRAM Package Dimensions PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 22 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Figure 9: 78-Ball FBGA – x4, x8 (HX)

9.6 CTR

11.5 ±0.1 9 ±0.1 Ball A1 IDBall A1 ID A B C D E F G H J K L M N 123789 78X Ø0.45 Dimensions apply to solder balls post-reflow on Ø0.35 SMD ball pads. A 0.12 A Seating plane 1.1 ±0.1 0.155 Notes: 1. All dimensions are in millimeters. 2. Solder ball material: SAC305 (96.5% Sn, 3% Ag, 0.5% Cu). 2Gb: x4, x8, x16 DDR3 SDRAM Package Dimensions PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 23 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Figure 10: 96-Ball FBGA – x16 (HA) Ball A1 Index Dimensions apply to solder balls post-reflow on Ø0.35 SMD ball pads. 14 ±0.1 1.1 ±0.1

12 CTR

(covered by SR) 9 ±0.1 0.25 MIN6.4 CTR 96X Ø0.45 9 8 7 3 2 1 A B C D E F G H J K L M N P R T A 0.12 A Seating plane 0.155 Notes: 1. All dimensions are in millimeters. 2. Solder ball material: SAC305 (96.5% Sn, 3% Ag, 0.5% Cu). 2Gb: x4, x8, x16 DDR3 SDRAM Package Dimensions PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 24 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Figure 11: 96-Ball FBGA – x16 (JT) Seating plane 0.12 A 123789 A B C D E F G H J K L M N Ball A1 ID Ball A1 ID A 1.1 ±0.10.8 TYP 8 ±0.1 14 ±0.1 96X Ø0.45 Dimensions apply to solder balls post- reflow on Ø0.35 SMD ball pads. 0.155 P R T Notes: 1. All dimensions are in millimeters. 2. Solder ball material: SAC305 (96.5% Sn, 3% Ag, 0.5% Cu). 2Gb: x4, x8, x16 DDR3 SDRAM Package Dimensions PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 25 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Stresses greater than those listed in Table 5 may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may adversely affect reliability. Table 5: Absolute Maximum Ratings Symbol Parameter Min Max Unit Notes VDD VDD supply voltage relative to VSS –0.4 1.975 V 1 VDDQ VDD supply voltage relative to VSSQ –0.4 1.975 V VIN, VOUT Voltage on any pin relative to VSS –0.4 1.975 V TC Operating case temperature - Commercial 0 95 °C 2, 3 Operating case temperature - Industrial –40 95 °C 2, 3 Operating case temperature - Automotive –40 105 °C 2, 3 T STG Storage temperature –55 150 °C Notes: 1. V DD and VDDQ must be within 300mV of each other at all times, and VREF must not be greater than 0.6 × VDDQ. When VDD and VDDQ are <500mV, VREF can be ≤300mV. 2. MAX operating case temperature. T C is measured in the center of the package. 3. Device functionality is not guaranteed if the DRAM device exceeds the maximum T C dur- ing operation. 2Gb: x4, x8, x16 DDR3 SDRAM Electrical Specifications PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 26 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Table 6: DDR3 Input/Output Capacitance Note 1 applies to the entire table Capacitance Parameters Symbol 800 1066 1333 1600 1866 2133 Unit NotesMin Max Min Max Min Max Min Max Min Max Min Max Single-end I/O: DQ, DM Differential I/O: DQS, DQS#, TDQS, TDQS# C ΔC: DQS to DQS#, TDQS, TDQS# C Inputs (CTRL, CMD, ADDR) ΔC: CMD_ADDR to CK CDI_CMD_ ADDR ZQ pin capaci- tance Reset pin capaci- tance VDDQ, VOUT = 0.1V (peak-to-peak). 2. DM input is grouped with I/O pins, reflecting the fact that they are matched in loading. 3. Includes TDQS, TDQS#. C DDQS is for DQS vs. DQS# and TDQS vs. TDQS# separately. 4. C DIO = CIO(DQ) - 0.5 × (CIO(DQS) + CIO(DQS#)). 5. Excludes CK, CK#; CTRL = ODT, CS#, and CKE; CMD = RAS#, CAS#, and WE#; ADDR = A[n:0], BA[2:0]. 6. C DI_CTRL = CI(CTRL) - 0.5 × (CCK(CK) + CCK(CK#)). 7. C DI_CMD_ADDR = CI(CMD_ADDR) - 0.5 × (CCK(CK) + CCK(CK#)). 2Gb: x4, x8, x16 DDR3 SDRAM Electrical Specifications PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 27 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Table 7: Thermal Characteristics Parameter/Condition Value Unit Symbol Notes Operating case temperature – Commercial 0 to +85 °C T C 1, 2, 3 0 to +95 °C T C 1, 2, 3, 4 Operating case temperature – Industrial –40 to +85 °C T C 1, 2, 3 –40 to +95 °C T C 1, 2, 3, 4 Operating case temperature – Automotive –40 to +85 °C T C 1, 2, 3 –40 to +105 °C T C 1, 2, 3, 4 Junction-to-case (TOP) 96-ball (JT) 6.5 °C/W ΘJC 5 96-ball (HA) 3.9 78-ball (DA) M, K 6.5 78-ball (HX) 3.9 Notes: 1. Maximum operating case temperature. T C is measured in the center of the package. 2. A thermal solution must be designed to ensure the DRAM device does not exceed T C MAX during operation. 3. Device functionality is not guaranteed if the DRAM device exceeds T C MAX during oper- ation. 4. If T C exceeds 85°C, the DRAM must be refreshed externally at 2x refresh, which is a 3.9μs interval refresh rate. The use of SRT or ASR (if available) must be enabled. 5. Thermal resistance data is based on a number of samples from multiple lots and should be viewed as a typical number. 2Gb: x4, x8, x16 DDR3 SDRAM Thermal Characteristics PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 28 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Figure 12: Thermal Measurement Point 7FWHVWSRLQW 2Gb: x4, x8, x16 DDR3 SDRAM Thermal Characteristics PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 29 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Electrical Specifications – IDD Specifications and Conditions Within the following IDD measurement tables, the following definitions and conditions are used, unless stated otherwise:

• LOW: V IN ≤ VIL(AC)max; HIGH: VIN ≥ VIH(AC)min.
• Midlevel: Inputs are V REF = VDD/2.
• R ON set to RZQ/7 (34Ω
• R TT ,nom set to RZQ/6 (40Ω
• R TT(WR) set to RZQ/2 (120Ω
• Q OFF is enabled in MR1.
• ODT is enabled in MR1 (R TT ,nom) and MR2 (RTT(WR)).
• TDQS is disabled in MR1.
• External DQ/DQS/DM load resistor is 25 Ω to V DDQ/2.
• Burst lengths are BL8 fixed.
• AL equals 0 (except in I DD7).
• I DD specifications are tested after the device is properly initialized.
• Input slew rate is specified by AC parametric test conditions.
• Optional ASR is disabled.
• Read burst type uses nibble sequential (MR0[3] = 0).
• Loop patterns must be executed at least once before current measurements begin. Table 8: Timing Parameters Used for I DD Measurements – Clock Units IDD Parameter DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1866 DDR3-2133 Unit -25E -25 -187E -187 -15E -15 -125E -125 -107 -093 CL IDD 56789 1 0 1 0 1 1 1 3 1 4 C K tRCD (MIN) IDD 5 6 7 8 9 10 10 11 13 14 CK tRC (MIN) IDD 20 21 27 28 33 34 38 39 45 50 CK tRAS (MIN) IDD 15 15 20 20 24 24 28 28 32 36 CK tRP (MIN) 5 6 7 8 9 10 10 11 13 14 CK tFAW x4, x8 16 16 20 20 20 20 24 24 26 27 CK x16 20 20 27 27 30 30 32 32 33 38 CK tRRD IDD x4, x8 4 4 4 4 4 4 5 5 5 6 CK x16 4 4 6 6 5 5 6 6 6 7 CK tRFC 1Gb 44 44 59 59 74 74 88 88 103 118 CK 2Gb 64 64 86 86 107 107 128 128 150 172 CK 4Gb 104 104 139 139 174 174 208 208 243 279 CK 8Gb 140 140 187 187 234 234 280 280 328 375 CK 2Gb: x4, x8, x16 DDR3 SDRAM Electrical Specifications – IDD Specifications and Conditions PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 30 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Table 9: IDD0 Measurement Loop CK, CK# CKE Sub- Loop Cycle Number Command CS# RAS# CAS# WE# ODT BA[2:0] A[15:11] A[10] A[9:7] A[6:3] A[2:0] Data Toggling Static HIGH

0 A C T 00110000000 –

1 D 10000000000 –

2 D 10000000000 –

3 D # 11110000000 –

4 D # 11110000000 –

Repeat cycles 1 through 4 until nRAS - 1; truncate if needed nR A S P R E 00100000000 – Repeat cycles 1 through 4 until nRC - 1; truncate if needed nR C A C T 001100000F0 – nR C + 1 D 100000000F0 – nR C + 2 D 100000000F0 – nR C + 3 D # 111100000F0 – nR C + 4 D # 111100000F0 – Repeat cycles nRC + 1 through nRC + 4 until nRC - 1 + nRAS -1; truncate if needed nRC + nR A S P R E 001000000F0 – Repeat cycles nRC + 1 through nRC + 4 until 2 × RC - 1; truncate if needed 1 2 × nRC Repeat sub-loop 0, use BA[2:0] = 1 2 4 × nRC Repeat sub-loop 0, use BA[2:0] = 2 3 6 × nRC Repeat sub-loop 0, use BA[2:0] = 3 4 8 × nRC Repeat sub-loop 0, use BA[2:0] = 4 5 10 × nRC Repeat sub-loop 0, use BA[2:0] = 5 6 12 × nRC Repeat sub-loop 0, use BA[2:0] = 6 7 14 × nRC Repeat sub-loop 0, use BA[2:0] = 7 Notes: 1. DQ, DQS, DQS# are midlevel. 2. DM is LOW. 3. Only selected bank (single) active. 2Gb: x4, x8, x16 DDR3 SDRAM Electrical Specifications – IDD Specifications and Conditions PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 31 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Table 10: IDD1 Measurement Loop CK, CK# CKE Sub-Loop Cycle Number Command CS# RAS# CAS# WE# ODT BA[2:0] A[15:11] A[10] A[9:7] A[6:3] A[2:0] Data2 Toggling Static HIGH Repeat cycles 1 through 4 until nRCD - 1; truncate if needed nRCD RD 0 1 0 1 0 0 0 0 0 0 0 00000000 Repeat cycles 1 through 4 until nRAS - 1; truncate if needed nR A S P R E 00100000000 – Repeat cycles 1 through 4 until nRC - 1; truncate if needed nR C A C T 001100000F0 – nR C + 1 D 100000000F0 – nR C + 2 D 100000000F0 – nR C + 3 D # 111100000F0 – nR C + 4 D # 111100000F0 – Repeat cycles nRC + 1 through nRC + 4 until nRC + nRCD - 1; truncate if needed nRC + nRCD RD 0 1 0 1 0 0 0 0 0 F 0 00110011 Repeat cycles nRC + 1 through nRC + 4 until nRC + nRAS - 1; truncate if needed nRC + nR A S P R E 001000000F0 – Repeat cycle nRC + 1 through nRC + 4 until 2 × nRC - 1; truncate if needed 1 2 × nRC Repeat sub-loop 0, use BA[2:0] = 1 2 4 × nRC Repeat sub-loop 0, use BA[2:0] = 2 3 6 × nRC Repeat sub-loop 0, use BA[2:0] = 3 4 8 × nRC Repeat sub-loop 0, use BA[2:0] = 4 5 10 × nRC Repeat sub-loop 0, use BA[2:0] = 5 6 12 × nRC Repeat sub-loop 0, use BA[2:0] = 6 7 14 × nRC Repeat sub-loop 0, use BA[2:0] = 7 Notes: 1. DQ, DQS, DQS# are midlevel unless driven as required by the RD command. 2. DM is LOW. 3. Burst sequence is driven on each DQ signal by the RD command. 4. Only selected bank (single) active. 2Gb: x4, x8, x16 DDR3 SDRAM Electrical Specifications – IDD Specifications and Conditions PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 32 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Table 11: IDD Measurement Conditions for Power-Down Currents Name IDD2P0 Precharge Power-Down Current (Slow Exit)1 IDD2P1 Precharge Power-Down Current (Fast Exit)1 IDD2Q Precharge Quiet Standby Current IDD3P Active Power-Down Current Timing pattern N/A N/A N/A N/A CKE LOW LOW HIGH LOW External clock Toggling Toggling Toggling Toggling tCK tCK (MIN) IDD tCK (MIN) IDD tCK (MIN) IDD tCK (MIN) IDD tRC N/A N/A N/A N/A tRAS N/A N/A N/A N/A tRCD N/A N/A N/A N/A tRRD N/A N/A N/A N/A tRC N/A N/A N/A N/A CL N/A N/A N/A N/A AL N/A N/A N/A N/A CS# HIGH HIGH HIGH HIGH Command inputs LOW LOW LOW LOW Row/column addr LOW LOW LOW LOW Bank addresses LOW LOW LOW LOW DM LOW LOW LOW LOW Data I/O Midlevel Midlevel Midlevel Midlevel Output buffer DQ, DQS Enabled Enabled Enabled Enabled ODT

2 Enabled, off Enabled, off Enabled, off Enabled, off

Active banks None None None All Idle banks All All All None Special notes N/A N/A N/A N/A Notes: 1. MR0[12] defines DLL on/off behavior during precharge power-down only; DLL on (fast exit, MR0[12] = 1) and DLL off (slow exit, MR0[12] = 0). 2. “Enabled, off” means the MR bits are enabled, but the signal is LOW. 2Gb: x4, x8, x16 DDR3 SDRAM Electrical Specifications – IDD Specifications and Conditions PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 33 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Table 12: IDD2N and IDD3N Measurement Loop CK, CK# CKE Sub-Loop Cycle Number Command CS# RAS# CAS# WE# ODT BA[2:0] A[15:11] A[10] A[9:7] A[6:3] A[2:0] Data Toggling Static HIGH

0 D 10000000000 –

2 D # 111100000F0 –

3 D # 111100000F0 –

1 4–7 Repeat sub-loop 0, use BA[2:0] = 1 2 8–11 Repeat sub-loop 0, use BA[2:0] = 2 3 12–15 Repeat sub-loop 0, use BA[2:0] = 3 4 16–19 Repeat sub-loop 0, use BA[2:0] = 4 5 20–23 Repeat sub-loop 0, use BA[2:0] = 5 6 24–27 Repeat sub-loop 0, use BA[2:0] = 6 7 28–31 Repeat sub-loop 0, use BA[2:0] = 7 Notes: 1. DQ, DQS, DQS# are midlevel. 2. DM is LOW. 3. All banks closed during I DD2N; all banks open during IDD3N. Table 13: IDD2NT Measurement Loop CK, CK# CKE Sub-Loop Cycle Number Command CS# RAS# CAS# WE# ODT BA[2:0] A[15:11] A[10] A[9:7] A[6:3] A[2:0] Data Toggling Static HIGH 1 4–7 Repeat sub-loop 0, use BA[2:0] = 1; ODT = 0 2 8–11 Repeat sub-loop 0, use BA[2:0] = 2; ODT = 1 3 12–15 Repeat sub-loop 0, use BA[2:0] = 3; ODT = 1 4 16–19 Repeat sub-loop 0, use BA[2:0] = 4; ODT = 0 5 20–23 Repeat sub-loop 0, use BA[2:0] = 5; ODT = 0 6 24–27 Repeat sub-loop 0, use BA[2:0] = 6; ODT = 1 7 28–31 Repeat sub-loop 0, use BA[2:0] = 7; ODT = 1 Notes: 1. DQ, DQS, DQS# are midlevel. 2. DM is LOW. 3. All banks closed. 2Gb: x4, x8, x16 DDR3 SDRAM Electrical Specifications – IDD Specifications and Conditions PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 34 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Table 14: IDD4R Measurement Loop CK, CK# CKE Sub-Loop Cycle Number Command CS# RAS# CAS# WE# ODT BA[2:0] A[15:11] A[10] A[9:7] A[6:3] A[2:0] Data3 Toggling Static HIGH

0 RD 0 1 0 1 0 0 0 0 0 0 0 00000000

2 D # 11110000000 –

4 RD 0 1 0 1 0 0 0 0 0 F 0 00110011

5 D 100000000F0 –

6 D # 111100000F0 –

7 D # 111100000F0 –

1 8–15 Repeat sub-loop 0, use BA[2:0] = 1 2 16–23 Repeat sub-loop 0, use BA[2:0] = 2 3 24–31 Repeat sub-loop 0, use BA[2:0] = 3 4 32–39 Repeat sub-loop 0, use BA[2:0] = 4 5 40–47 Repeat sub-loop 0, use BA[2:0] = 5 6 48–55 Repeat sub-loop 0, use BA[2:0] = 6 7 56–63 Repeat sub-loop 0, use BA[2:0] = 7 Notes: 1. DQ, DQS, DQS# are midlevel when not driving in burst sequence. 2. DM is LOW. 3. Burst sequence is driven on each DQ signal by the RD command. 4. All banks open. 2Gb: x4, x8, x16 DDR3 SDRAM Electrical Specifications – IDD Specifications and Conditions PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 35 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Table 15: IDD4W Measurement Loop CK, CK# CKE Sub-Loop Cycle Number Command CS# RAS# CAS# WE# ODT BA[2:0] A[15:11] A[10] A[9:7] A[6:3] A[2:0] Data3 Toggling Static HIGH

0 WR 0 1 0 0 1 0 0 0 0 0 0 00000000

1 D 10001000000 –

2 D # 11111000000 –

3 D # 11111000000 –

4 WR 0 1 0 0 1 0 0 0 0 F 0 00110011

5 D 100010000F0 –

6 D # 111110000F0 –

7 D # 111110000F0 –

1 8–15 Repeat sub-loop 0, use BA[2:0] = 1 2 16–23 Repeat sub-loop 0, use BA[2:0] = 2 3 24–31 Repeat sub-loop 0, use BA[2:0] = 3 4 32–39 Repeat sub-loop 0, use BA[2:0] = 4 5 40–47 Repeat sub-loop 0, use BA[2:0] = 5 6 48–55 Repeat sub-loop 0, use BA[2:0] = 6 7 56–63 Repeat sub-loop 0, use BA[2:0] = 7 Notes: 1. DQ, DQS, DQS# are midlevel when not driving in burst sequence. 2. DM is LOW. 3. Burst sequence is driven on each DQ signal by the WR command. 4. All banks open. 2Gb: x4, x8, x16 DDR3 SDRAM Electrical Specifications – IDD Specifications and Conditions PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 36 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Table 16: IDD5B Measurement Loop CK, CK# CKE Sub-Loop Cycle Number Command CS# RAS# CAS# WE# ODT BA[2:0] A[15:11] A[10] A[9:7] A[6:3] A[2:0] Data Toggling Static HIGH 0 0 R E F 00010000000 –

4 D # 111100000F0 –

1b 5–8 Repeat sub-loop 1a, use BA[2:0] = 1 1c 9–12 Repeat sub-loop 1a, use BA[2:0] = 2 1d 13–16 Repeat sub-loop 1a, use BA[2:0] = 3 1e 17–20 Repeat sub-loop 1a, use BA[2:0] = 4 1f 21–24 Repeat sub-loop 1a, use BA[2:0] = 5 1g 25–28 Repeat sub-loop 1a, use BA[2:0] = 6 1h 29–32 Repeat sub-loop 1a, use BA[2:0] = 7 2 33– nRFC - 1 Repeat sub-loop 1a through 1h until nRFC - 1; truncate if needed Notes: 1. DQ, DQS, DQS# are midlevel. 2. DM is LOW. 2Gb: x4, x8, x16 DDR3 SDRAM Electrical Specifications – IDD Specifications and Conditions PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 37 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Table 17: IDD Measurement Conditions for IDD6, IDD6ET, and IDD8 IDD Test IDD6: Self Refresh Current Normal Temperature Range TC = 0°C to +85°C IDD6ET: Self Refresh Current Extended Temperature Range TC = 0°C to +95°C IDD8: Reset2 CKE LOW LOW Midlevel External clock Off, CK and CK# = LOW Off, CK and CK# = LOW Midlevel tCK N/A N/A N/A tRC N/A N/A N/A tRAS N/A N/A N/A tRCD N/A N/A N/A tRRD N/A N/A N/A tRC N/A N/A N/A CL N/A N/A N/A AL N/A N/A N/A CS# Midlevel Midlevel Midlevel Command inputs Midlevel Midlevel Midlevel Row/column addresses Midlevel Midlevel Midlevel Bank addresses Midlevel Midlevel Midlevel Data I/O Midlevel Midlevel Midlevel Output buffer DQ, DQS Enabled Enabled Midlevel ODT

1 Enabled, midlevel Enabled, midlevel Midlevel

SRT Disabled (normal) Enabled (extended) N/A ASR Disabled Disabled N/A Notes: 1. “Enabled, midlevel” means the MR command is enabled, but the signal is midlevel. 2. During a cold boot RESET (initialization), current reading is valid after power is stable and RESET has been LOW for 1ms; During a warm boot RESET (while operating), current reading is valid after RESET has been LOW for 200ns + tRFC. 2Gb: x4, x8, x16 DDR3 SDRAM Electrical Specifications – IDD Specifications and Conditions PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 38 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Table 18: IDD7 Measurement Loop CK, CK# CKE Sub-Loop Cycle Number Command CS# RAS# CAS# WE# ODT BA[2:0] A[15:11] A[10] A[9:7] A[6:3] A[2:0] Data3 Toggling Static HIGH

1 R D A 01010001000 00000000

2 D10000000000 –

3 Repeat cycle 2 until nRRD - 1

nR R D A C T 001101000F0 – nRRD + 1 RDA 010101010F0 00110011 nRRD + 2 D 100001000F0 – nRRD + 3 Repeat cycle nRRD + 2 until 2 × nRRD - 1 2 2 × nRRD Repeat sub-loop 0, use BA[2:0] = 2 3 3 × nRRD Repeat sub-loop 1, use BA[2:0] = 3 4 × nR R D D100003000F0 – 4 × nRRD + 1 Repeat cycle 4 × nRRD until nFAW - 1, if needed 5 nFAW Repeat sub-loop 0, use BA[2:0] = 4 6 nFAW + nRRD Repeat sub-loop 1, use BA[2:0] = 5 7 nFAW + 2 × nRRD Repeat sub-loop 0, use BA[2:0] = 6 8 nFAW + 3 × nRRD Repeat sub-loop 1, use BA[2:0] = 7 nFAW + 4 × nR R D D100007000F0 – nFAW + 4 × nRRD + 1 Repeat cycle nFAW + 4 × nRRD until 2 × nFAW - 1, if needed 2 × nF A W A C T 001100000F0 – 2 × nF A W + 1 R D A 010100010F0 00110011 2 × nF A W + 2 D100000000F0 – 2 × nFAW + 3 Repeat cycle 2 × nFAW + 2 until 2 × nFAW + nRRD - 1 2 × nFAW + nR R D A C T 00110100000 – 2 × n FAW + nRRD + 1 RDA 0 1010101000 00000000 2 × nFAW + nRRD + 2 D 1 0 000100000 – 2 × nFAW + nRRD + 3 Repeat cycle 2 × nFAW + nRRD + 2 until 2 × nFAW + 2 × nRRD - 1 12 2 × nFAW + 2 × nRRD Repeat sub-loop 10, use BA[2:0] = 2 13 2 × nFAW + 3 × nRRD Repeat sub-loop 11, use BA[2:0] = 3 2 × nFAW + 4 × nR R D D10000300000 – 2 × nFAW + 4 × nRRD + 1 Repeat cycle 2 × nFAW + 4 × nRRD until 3 × nFAW - 1, if needed 15 3 × nFAW Repeat sub-loop 10, use BA[2:0] = 4 2Gb: x4, x8, x16 DDR3 SDRAM Electrical Specifications – IDD Specifications and Conditions PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 39 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Table 18: IDD7 Measurement Loop (Continued) CK, CK# CKE Sub-Loop Cycle Number Command CS# RAS# CAS# WE# ODT BA[2:0] A[15:11] A[10] A[9:7] A[6:3] A[2:0] Data3 Toggling Static HIGH 16 3 × nFAW + nRRD Repeat sub-loop 11, use BA[2:0] = 5 17 3 × nFAW + 2 × nRRD Repeat sub-loop 10, use BA[2:0] = 6 18 3 × nFAW + 3 × nRRD Repeat sub-loop 11, use BA[2:0] = 7 3 × nFAW + 4 × nR R D D10000700000 – 3 × nFAW + 4 × nRRD + 1 Repeat cycle 3 × nFAW + 4 × nRRD until 4 × nFAW - 1, if needed Notes: 1. DQ, DQS, DQS# are midlevel unless driven as required by the RD command. 2. DM is LOW. 3. Burst sequence is driven on each DQ signal by the RD command. 4. AL = CL-1. 2Gb: x4, x8, x16 DDR3 SDRAM Electrical Specifications – IDD Specifications and Conditions PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 40 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Electrical Characteristics – IDD Specifications IDD values are for full operating range of voltage and temperature unless otherwise no- ted. Table 19: IDD Maximum Limits – Die Rev D Speed Bin DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1866 Unit NotesIDD Width IDD0 x4 75 85 95 105 mA 1, 2 x8 75 85 95 105 mA x16 90 100 110 120 mA IDD1 x4 95 100 105 110 mA 1, 2 x8 95 100 105 110 mA x16 125 130 135 140 mA IDD2P0 (Slow) All 12 12 12 12 mA 1, 2 IDD2P1 (Fast) x4, x8 25 30 35 40 mA 1, 2 x16 30 35 40 45 mA IDD2Q All 30 35 40 45 mA 1, 2 IDD2N All 32 37 42 47 mA 1, 2 IDD2NT x4, x8 40 45 50 55 mA 1, 2 x16 55 60 65 70 mA IDD3P x4, x8 30 35 40 45 mA 1, 2 x16 35 40 45 50 mA IDD3N All 35 40 45 50 mA 1, 2 IDD4R x4 125 145 165 185 mA 1, 2 x8 140 160 180 200 mA x16 200 245 270 295 mA IDD4W x4 135 155 170 190 mA 1, 2 x8 145 165 185 205 mA x16 210 255 280 315 mA I DD5B All 190 200 215 220 mA 1, 2 IDD6 All 12 12 12 12 mA 1, 2, 3 IDD6ET All 15 15 15 15 mA 2, 4 IDD7 x4 335 385 435 485 mA 1, 2 x8 335 385 435 485 mA x16 375 425 475 525 mA I DD8 All I DD2P0 + 2mA I DD2P0 + 2mA I DD2P0 + 2mA I DD2P0 + 2mA mA 1, 2 Notes: 1. T C = 85°C; SRT and ASR are disabled. 2. Enabling ASR could increase I DDx by up to an additional 2mA. 3. Restricted to T C MAX = 85°C. 4. T C = 85°C; ASR and ODT are disabled; SRT is enabled. 2Gb: x4, x8, x16 DDR3 SDRAM Electrical Characteristics – IDD Specifications PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 41 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

1. The I DD values must be derated (increased) on IT-option devices when operated outside the range 0°C ≤ TC ≤ +85°C: 5a. When TC < 0°C: IDD2P0, IDD2P1 and IDD3P must be derated by 4%; IDD4R and IDD4W must be derated by 2%; and IDD6, IDD6ET and IDD7 must be derated by 7%. 5b. When TC > 85°C: IDD0, IDD1, IDD2N, IDD2NT, IDD2Q, IDD3N, IDD3P, IDD4R, IDD4W, and IDD5B must be derated by 2%; and IDD2Px must be derated by 30%. Table 20: IDD Maximum Limits – Die Rev M Speed Bin DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1866 Unit NotesIDD Width IDD0 All 60 65 70 75 mA 1, 2 IDD1 All 70 75 80 85 mA 1, 2 IDD2P0 (Slow) All 12 12 12 12 mA 1, 2 IDD2P1 (Fast) All 27 32 37 42 mA 1, 2 IDD2Q All 30 35 40 45 mA 1, 2 IDD2N All 33 38 43 48 mA 1, 2 IDD2NT All 35 40 45 50 mA 1, 2 IDD3P All 40 45 50 55 mA 1, 2 IDD3N All 45 50 55 60 mA 1, 2 IDD4R x4 115 126 141 156 mA 1, 2 x8 130 141 156 171 mA IDD4W x4 100 115 130 145 mA 1, 2 x8 115 130 145 160 mA I DD5B All 185 190 195 200 mA 1, 2 IDD6 All 12 12 12 12 mA 1, 2, 3 IDD6ET All 15 15 15 15 mA 2, 4 IDD7 All 210 225 240 255 mA 1, 2 IDD8 All I DD2P0 + 2mA I DD2P0 + 2mA I DD2P0 + 2mA I DD2P0 + 2mA mA 1, 2 Notes: 1. T C = 85°C; SRT and ASR are disabled. 2. Enabling ASR could increase I DDx by up to an additional 2mA. 3. Restricted to T C MAX = 85°C. 4. T C = 85°C; ASR and ODT are disabled; SRT is enabled. 5. The I DD values must be derated (increased) on IT-option devices when operated outside the range 0°C ≤ TC ≤ +85°C: 5a. When TC < 0°C: IDD2P0, IDD2P1 and IDD3P must be derated by 4%; IDD4R and IDD4W must be derated by 2%; and IDD6, IDD6ET and IDD7 must be derated by 7%. 5b. When TC > 85°C: IDD0, IDD1, IDD2N, IDD2NT, IDD2Q, IDD3N, IDD3P, IDD4R, IDD4W, and IDD5B must be derated by 2%; and IDD2Px must be derated by 30%. 2Gb: x4, x8, x16 DDR3 SDRAM Electrical Characteristics – IDD Specifications PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 42 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Table 21: IDD Maximum Limits – Die Rev K Speed Bin DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1866 DDR3-2133 Unit NotesIDD Widt h IDD0 x4, x8 39 41 42 43 46 mA 1, 2 x16 46 48 49 51 55 mA IDD1 x4 46 50 52 55 57 mA 1, 2 x8 50 54 56 58 60 mA x16 62 67 69 72 75 mA IDD2P0 (Slow) All 12 12 12 12 12 mA 1, 2 IDD2P1 (Fast) All 15 15 15 15 15 mA 1, 2 IDD2Q All 22 22 22 22 22 mA 1, 2 IDD2N All 23 23 23 23 23 mA 1, 2 IDD2NT x4,x8 29 32 34 36 40 mA 1, 2 x16 33 36 37 39 43 mA IDD3P All 22 22 22 22 22 mA 1, 2 IDD3N x4,x8 31 33 35 37 40 mA 1, 2 x16 33 36 37 39 43 mA IDD4R x4 70 84 96 106 120 mA 1, 2 x8 74 88 100 110 125 mA x16 95 115 135 155 180 mA IDD4W x4 75 87 99 110 122 mA 1, 2 x8 79 91 103 114 126 mA x16 107 127 146 164 184 mA I DD5B All 179 181 182 184 190 mA 1, 2 IDD6 All 12 12 12 12 12 mA 1, 2, 3 IDD6ET All 15 15 15 15 15 mA 2, 4 IDD7 x4, x8 128 157 163 171 190 mA 1, 2 x16 159 179 202 226 248 mA IDD8 All I DD2P0 + 2mA I DD2P0 + 2mA I DD2P0 + 2mA I DD2P0 + 2mA I DD2P0 + 2mA mA 1, 2 Notes: 1. T C = 85°C; SRT and ASR are disabled. 2. Enabling ASR could increase I DDx by up to an additional 2mA. 3. Restricted to T C MAX = 85°C. 4. T C = 85°C; ASR and ODT are disabled; SRT is enabled. 5. The I DD values must be derated (increased) on IT-option devices when operated outside the range 0°C ≤ TC ≤ +85°C: 5a. When TC < 0°C: IDD2P0, IDD2P1 and IDD3P must be derated by 4%; IDD4R and IDD4W must be derated by 2%; and IDD6, IDD6ET and IDD7 must be derated by 7%. 5b. When TC > 85°C: IDD0, IDD1, IDD2N, IDD2NT, IDD2Q, IDD3N, IDD3P, IDD4R, IDD4W, and IDD5B must be derated by 2%; and IDD2Px must be derated by 30%. 2Gb: x4, x8, x16 DDR3 SDRAM Electrical Characteristics – IDD Specifications PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 43 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Electrical Specifications – DC and AC DC Operating Conditions Table 22: DC Electrical Characteristics and Operating Conditions All voltages are referenced to VSS Parameter/Condition Symbol Min Nom Max Unit Notes Supply voltage V DD 1.425 1.5 1.575 V 1, 2 I/O supply voltage V DDQ 1.425 1.5 1.575 V 1, 2 Input leakage current Any input 0V ≤ VIN ≤ VDD, VREF pin 0V ≤ VIN ≤ 1.1V (All other pins not under test = 0V) II –2 – 2 μA VREF supply leakage current VREFDQ = VDD/2 or VREFCA = VDD/2 (All other pins not under test = 0V) IVREF –1 – 1 μA 4 Notes: 1. V DD and VDDQ must track one another. VDDQ must be ≤ VDD. VSS = VSSQ. 2. V DD and VDDQ may include AC noise of ±50mV (250 kHz to 20 MHz) in addition to the DC (0 Hz to 250 kHz) specifications. VDD and VDDQ must be at same level for valid AC timing parameters. 3. V REF (see Table 23). 4. The minimum limit requirement is for testing purposes. The leakage current on the V REF pin should be minimal. Input Operating Conditions Table 23: DC Electrical Characteristics and Input Conditions All voltages are referenced to VSS Parameter/Condition Symbol Min Nom Max Unit Notes VIN low; DC/commands/address busses V IL VSS n/a See Table 24 V VIN high; DC/commands/address busses V IH See Table 24 n/a V DD V Input reference voltage command/address bus V REFCA(DC) 0.49 × VDD 0.5 × VDD 0.51 × VDD V 1, 2 I/O reference voltage DQ bus V REFDQ(DC) 0.49 × VDD 0.5 × VDD 0.51 × VDD V 2, 3 I/O reference voltage DQ bus in SELF REFRESH V REFDQ(SR) VSS 0.5 × VDD VDD V4 Command/address termination voltage (system level, not direct DRAM input) VTT – 0.5 × V DDQ –V 5 Notes: 1. V REFCA(DC) is expected to be approximately 0.5 × VDD and to track variations in the DC level. Externally generated peak noise (noncommon mode) on VREFCA may not exceed ±1% × VDD around the VREFCA(DC) value. Peak-to-peak AC noise on VREFCA should not ex- ceed ±2% of VREFCA(DC). 2. DC values are determined to be less than 20 MHz in frequency. DRAM must meet specifi- cations if the DRAM induces additional AC noise greater than 20 MHz in frequency. 3. V REFDQ(DC) is expected to be approximately 0.5 × VDD and to track variations in the DC level. Externally generated peak noise (noncommon mode) on VREFDQ may not exceed ±1% × VDD around the VREFDQ(DC) value. Peak-to-peak AC noise on VREFDQ should not ex- ceed ±2% of VREFDQ(DC). 2Gb: x4, x8, x16 DDR3 SDRAM Electrical Specifications – DC and AC PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 44 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

1. V REFDQ(DC) may transition to VREFDQ(SR) and back to VREFDQ(DC) when in SELF REFRESH, within restrictions outlined in the SELF REFRESH section. 5. V TT is not applied directly to the device. VTT is a system supply for signal termination re- sistors. Minimum and maximum values are system-dependent. Table 24: Input Switching Conditions Parameter/Condition Symbol DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1866 DDR3-2133 Unit Command and Address Input high AC voltage: Logic 1 @ 175mV V IH(AC175)min 175 175 – mV Input high AC voltage: Logic 1 @ 150mV V IH(AC150)min 150 150 – mV Input high AC voltage: Logic 1 @ 135 mV V IH(AC135)min – – 135 mV Input high AC voltage: Logic 1 @ 125 mV V IH(AC125)min – – 125 mV Input high DC voltage: Logic 1 @ 100 mV V IH(DC100)min 100 100 100 mV Input low DC voltage: Logic 0 @ –100mV V IL(DC100)max –100 –100 –100 mV Input low AC voltage: Logic 0 @ –125mV V IL(AC125)max – – –125 mV Input low AC voltage: Logic 0 @ –135mV V IL(AC135)max – – –135 mV Input low AC voltage: Logic 0 @ –150mV V IL(AC150)max –150 –150 – mV Input low AC voltage: Logic 0 @ –175mV V IL(AC175)max –175 –175 – mV DQ and DM Input high AC voltage: Logic 1 V IH(AC175)min 175 – – mV Input high AC voltage: Logic 1 V IH(AC150)min 150 150 – mV Input high AC voltage: Logic 1 V IH(AC135)min – – 135 mV Input high DC voltage: Logic 1 V IH(DC100)min 100 100 100 mV Input low DC voltage: Logic 0 V IL(DC100)max –100 –100 –100 mV Input low AC voltage: Logic 0 V IL(AC135)max – – –135 mV Input low AC voltage: Logic 0 V IL(AC150)max –150 –150 – mV Input low AC voltage: Logic 0 V IL(AC175)max –175 – – mV Notes: 1. All voltages are referenced to V REF. VREF is VREFCA for control, command, and address. All slew rates and setup/hold times are specified at the DRAM ball. VREF is VREFDQ for DQ and DM inputs. 2. Input setup timing parameters ( tIS and tDS) are referenced at VIL(AC)/VIH(AC), not VREF(DC). 3. Input hold timing parameters ( tIH and tDH) are referenced at VIL(DC)/VIH(DC), not VREF(DC). 4. Single-ended input slew rate = 1 V/ns; maximum input voltage swing under test is 900mV (peak-to-peak). 5. When two V IH(AC) values (and two corresponding VIL(AC) values) are listed for a specific speed bin, the user may choose either value for the input AC level. Whichever value is used, the associated setup time for that AC level must also be used. Additionally, one V IH(AC) value may be used for address/command inputs and the other VIH(AC) value may be used for data inputs. For example, for DDR3-800, two input AC levels are defined: VIH(AC175),min and VIH(AC150),min (corresponding VIL(AC175),min and VIL(AC150),min). For DDR3-800, the address/ command inputs must use either VIH(AC175),min with tIS(AC175) of 200ps or VIH(AC150),min with tIS(AC150) of 350ps; independently, the data inputs must use either VIH(AC175),min with tDS(AC175) of 75ps or VIH(AC150),min with tDS(AC150) of 125ps. 2Gb: x4, x8, x16 DDR3 SDRAM Electrical Specifications – DC and AC PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 45 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Figure 13: Input Signal 0.575V 0.0V 0.650V 0.720V 0.735V 0.750V 0.765V 0.780V 0.850V 0.925V V IL(AC) VIL(DC) VREF - AC noise VREF - DC error VREF + DC error VREF + AC noise VIH(DC) VIH(AC) 1.50V 1.90V –0.40V VDDQ VDDQ + 0.4V narrow pulse width VSS - 0.4V narrow pulse width VSS 0.575V 0.650V 0.720V 0.735V 0.750V 0.765V 0.780V 0.850V 0.925V Minimum VIL and VIH levels VIH(DC) VIH(AC) VIL(AC) VIL(DC) VIL and VIH levels with ringback Note: 1. Numbers in diagrams reflect nominal values. 2Gb: x4, x8, x16 DDR3 SDRAM Electrical Specifications – DC and AC PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 46 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Table 27: Differential Input Operating Conditions (CK, CK# and DQS, DQS#) Parameter/Condition Symbol Min Max Unit Notes Differential input voltage logic high - slew V IH,diff 200 n/a mV 4 Differential input voltage logic low - slew V IL,diff n/a –200 mV 4 Differential input voltage logic high V IH,diff(AC) 2 × (VIH(AC) - VREF)V DD/VDDQ mV 5 Differential input voltage logic low V IL,diff(AC) VSS/VSSQ 2 × (VIL(AC)-VREF)m V 6 Differential input crossing voltage relative to VDD/2 for DQS, DQS#; CK, CK# VIX VREF(DC) - 150 V REF(DC) + 150 mV 4, 7 Differential input crossing voltage relative to VDD/2 for CK, CK# VIX (175) V REF(DC) - 175 V REF(DC) + 175 mV 4, 7, 8 Single-ended high level for strobes V SEH VDDQ/2 + 175 V DDQ mV 5 Single-ended high level for CK, CK# V DD/2 + 175 V DD mV 5 Single-ended low level for strobes V SEL VSSQ VDDQ/2 - 175 mV 6 Single-ended low level for CK, CK# V SS VDD/2 - 175 mV 6 Notes: 1. Clock is referenced to V DD and VSS. Data strobe is referenced to VDDQ and VSSQ. 2. Reference is V REFCA(DC) for clock and VREFDQ(DC) for strobe. 3. Differential input slew rate = 2 V/ns 4. Defines slew rate reference points, relative to input crossing voltages. 5. Minimum DC limit is relative to single-ended signals; overshoot specifications are appli- cable. 6. Maximum DC limit is relative to single-ended signals; undershoot specifications are ap- plicable. 7. The typical value of V IX(AC) is expected to be about 0.5 × VDD of the transmitting device, and VIX(AC) is expected to track variations in VDD. VIX(AC) indicates the voltage at which differential input signals must cross. 8. The V IX extended range (±175mV) is allowed only for the clock; this VIX extended range is only allowed when the following conditions are met: The single-ended input signals are monotonic, have the single-ended swing V SEL, VSEH of at least VDD/2 ±250mV, and the differential slew rate of CK, CK# is greater than 3 V/ns. 9. V IX must provide 25mV (single-ended) of the voltages separation. 2Gb: x4, x8, x16 DDR3 SDRAM Electrical Specifications – DC and AC PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 48 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Figure 18: Definition of Differential AC-Swing and tDVAC VIH,diff(AC)min 0.0 VIL,diff,max tDVAC VIH,diff,min VIL,diff(AC)max Half cycle tDVAC CK - CK# DQS - DQS# Table 28: Allowed Time Before Ringback (tDVAC) for CK - CK# and DQS - DQS# Slew Rate (V/ns) tDVAC (ps) at |VIH,diff(AC) to VIL,diff(AC)| 350mV 300mV >4.0 75 175 4.0 57 170 3.0 50 167 2.0 38 163 1.9 34 162 1.6 29 161 1.4 22 159 1.2 13 155 1.0 0 150 <1.0 0 150 Note: 1. Below V IL(AC) 2Gb: x4, x8, x16 DDR3 SDRAM Electrical Specifications – DC and AC PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 50 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Slew Rate Definitions for Single-Ended Input Signals Setup (tIS and tDS) nominal slew rate for a rising signal is defined as the slew rate be- tween the last crossing of VREF and the first crossing of VIH(AC)min. Setup (tIS and tDS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of V REF and the first crossing of VIL(AC)max. Hold (tIH and tDH) nominal slew rate for a rising signal is defined as the slew rate be- tween the last crossing of VIL(DC)max and the first crossing of VREF. Hold (tIH and tDH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of V IH(DC)min and the first crossing of VREF (see Figure 19 (page 52)). Table 29: Single-Ended Input Slew Rate Definition Input Slew Rates (Linear Signals) Measured CalculationInput Edge From To Setup Rising V REF VIH(AC)min VIH(AC)min - VREF ǻTRSse Falling V REF VIL(AC)max VREF - VIL(AC)max ǻTFSse Hold Rising V IL(DC)max VREF VREF - VIL(DC)max ǻTFHse Falling V IH(DC)min VREF VIH(DC)min - VREF ǻTRSHse 2Gb: x4, x8, x16 DDR3 SDRAM Electrical Specifications – DC and AC PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 51 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Figure 19: Nominal Slew Rate Definition for Single-Ended Input Signals ǻTRSse ǻTFSse ǻTRHse ǻTFHse VREFDQ or VREFCA VIH(AC)min VIH(DC)min VIL(AC)max VIL(DC)max VREFDQ or VREFCA VIH(AC)min VIH(DC)min VIL(AC)max VIL(DC)max Setup Hold Single-ended input voltage (DQ, CMD, ADDR)Single-ended input voltage (DQ, CMD, ADDR) 2Gb: x4, x8, x16 DDR3 SDRAM Electrical Specifications – DC and AC PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 52 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Slew Rate Definitions for Differential Input Signals Input slew rate for differential signals (CK, CK# and DQS, DQS#) are defined and meas- ured, as shown in Table 30 and Figure 20. The nominal slew rate for a rising signal is defined as the slew rate between V IL,diff,max and VIH,diff,min. The nominal slew rate for a falling signal is defined as the slew rate between VIH,diff,min and VIL,diff,max. Table 30: Differential Input Slew Rate Definition Differential Input Slew Rates (Linear Signals) Measured CalculationInput Edge From To CK and DQS reference Rising V IL,diff,max VIH,diff,min VIH,diff,min - VIL,diff,max ǻTRdiff Falling V IH,diff,min VIL,diff,max VIH,diff,min - VIL,diff,max ǻTFdiff Figure 20: Nominal Differential Input Slew Rate Definition for DQS, DQS# and CK, CK# ǻTRdiff ǻTFdiff VIH,diff,min VIL,diff,max Differential input voltage (DQS, DQS#; CK, CK#) 2Gb: x4, x8, x16 DDR3 SDRAM Electrical Specifications – DC and AC PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 53 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

The ODT effective resistance RTT is defined by MR1[9, 6, and 2]. ODT is applied to the DQ, DM, DQS, DQS#, and TDQS, TDQS# balls (x8 devices only). The ODT target values and a functional representation are listed in Table 31 and Table 32 (page 55). The indi- vidual pull-up and pull-down resistors (RTT(PU) and RTT(PD)) are defined as follows:

• RTT(PU) = (VDDQ - VOUT)/|IOUT|, under the condition that RTT(PD) is turned off
• RTT(PD) = (VOUT)/|IOUT|, under the condition that RTT(PU) is turned off Figure 21: ODT Levels and I-V Characteristics RTT(PU) RTT(PD) ODT Chip in termination mode VDDQ DQ VSSQ IOUT = IPD - IPU IPU IPD IOUT VOUT To other circuitry such as RCV, . . . Table 31: On-Die Termination DC Electrical Characteristics Parameter/Condition Symbol Min Nom Max Unit Notes RTT effective impedance R TT(EFF) See Table 32 (page 55) 1, 2 Deviation of VM with respect to VDDQ/2 ΔVM –5 5 % 1, 2, 3 Notes: 1. Tolerance limits are applicable after proper ZQ calibration has been performed at a stable temperature and voltage (VDDQ = VDD, VSSQ = VSS). Refer to ODT Sensitivity (page 56) if either the temperature or voltage changes after calibration. 2. Measurement definition for R TT: Apply VIH(AC) to pin under test and measure current I[VIH(AC)], then apply VIL(AC) to pin under test and measure current I[VIL(AC)]: RTT = VIH(AC) - VIL(AC) I(VIH(AC)) - I(VIL(AC)) 3. Measure voltage (VM) at the tested pin with no load: ǻVM = – 12 × VM VDDQ × 100 4. For IT and AT devices, the minimum values are derated by 6% when the device operates between –40°C and 0°C (TC). 2Gb: x4, x8, x16 DDR3 SDRAM ODT Characteristics PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 54 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Table 32 (page 55) provides an overview of the ODT DC electrical characteristics. The values provided are not specification requirements; however, they can be used as design guidelines to indicate what R TT is targeted to provide:

• R TT Ω is made up of RTT120(PD240) and RTT120(PU240)
• R TT Ω is made up of RTT60(PD120) and RTT60(PU120)
• R TT Ω is made up of RTT40(PD80) and RTT40(PU80)
• R TT Ω is made up of RTT30(PD60) and RTT30(PU60)
• R TT Ω is made up of RTT20(PD40) and RTT20(PU40) Table 32: RTT Effective Impedances MR1 [9, 6, 2] RTT Resistor VOUT Min Nom Max Unit 0, 1, 0 Ω RTT120(PD240) 0.2 × VDDQ 0.6 1.0 1.1 RZQ/1 0.5 × VDDQ 0.9 1.0 1.1 RZQ/1 0.8 × VDDQ 0.9 1.0 1.4 RZQ/1 RTT120(PU240) 0.2 × VDDQ 0.9 1.0 1.4 RZQ/1 0.5 × VDDQ 0.9 1.0 1.1 RZQ/1 0.8 × VDDQ 0.6 1.0 1.1 RZQ/1 Ω VIL(AC) to VIH(AC) 0.9 1.0 1.6 RZQ/2 0, 0, 1 Ω RTT60(PD120) 0.2 × VDDQ 0.6 1.0 1.1 RZQ/2 0.5 × VDDQ 0.9 1.0 1.1 RZQ/2 0.8 × VDDQ 0.9 1.0 1.4 RZQ/2 RTT60(PU120) 0.2 × VDDQ 0.9 1.0 1.4 RZQ/2 0.5 × VDDQ 0.9 1.0 1.1 RZQ/2 0.8 × VDDQ 0.6 1.0 1.1 RZQ/2 Ω VIL(AC) to VIH(AC) 0.9 1.0 1.6 RZQ/4 0, 1, 1 Ω RTT40(PD80) 0.2 × VDDQ 0.6 1.0 1.1 RZQ/3 0.5 × VDDQ 0.9 1.0 1.1 RZQ/3 0.8 × VDDQ 0.9 1.0 1.4 RZQ/3 RTT40(PU80) 0.2 × VDDQ 0.9 1.0 1.4 RZQ/3 0.5 × VDDQ 0.9 1.0 1.1 RZQ/3 0.8 × VDDQ 0.6 1.0 1.1 RZQ/3 Ω VIL(AC) to VIH(AC) 0.9 1.0 1.6 RZQ/6 1, 0, 1 Ω RTT30(PD60) 0.2 × VDDQ 0.6 1.0 1.1 RZQ/4 0.5 × VDDQ 0.9 1.0 1.1 RZQ/4 0.8 × VDDQ 0.9 1.0 1.4 RZQ/4 RTT30(PU60) 0.2 × VDDQ 0.9 1.0 1.4 RZQ/4 0.5 × VDDQ 0.9 1.0 1.1 RZQ/4 0.8 × VDDQ 0.6 1.0 1.1 RZQ/4 Ω VIL(AC) to VIH(AC) 0.9 1.0 1.6 RZQ/8 2Gb: x4, x8, x16 DDR3 SDRAM ODT Characteristics PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 55 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Table 32: RTT Effective Impedances (Continued) MR1 [9, 6, 2] RTT Resistor VOUT Min Nom Max Unit 1, 0, 0 Ω RTT20(PD40) 0.2 × VDDQ 0.6 1.0 1.1 RZQ/6 0.5 × VDDQ 0.9 1.0 1.1 RZQ/6 0.8 × VDDQ 0.9 1.0 1.4 RZQ/6 RTT20(PU40) 0.2 × VDDQ 0.9 1.0 1.4 RZQ/6 0.5 × VDDQ 0.9 1.0 1.1 RZQ/6 0.8 × VDDQ 0.6 1.0 1.1 RZQ/6 Ω VIL(AC) to VIH(AC) 0.9 1.0 1.6 RZQ/12 Note: 1. Values assume an RZQ of 240 Ω r ODT Sensitivity If either the temperature or voltage changes after I/O calibration, then the tolerance limits listed in Table 31 (page 54) and Table 32 can be expected to widen according to Table 33 and Table 34 (page 56). Table 33: ODT Sensitivity Definition Symbol Min Max Unit RTT 0.9 - dRTTdT × |DT| - dRTTdV × |DV| 1.6 + dR TTdT × |DT| + dRTTdV × |DV| RZQ/(2, 4, 6, 8, 12) Note: 1. ΔT = T - T(@ calibration), ΔV = VDDQ - VDDQ(@ calibration) and VDD = VDDQ. Table 34: ODT Temperature and Voltage Sensitivity Change Min Max Unit dRTTdT 0 1.5 %/°C dRTTdV 0 0.15 %/mV Note: 1. ΔT = T - T(@ calibration), ΔV = VDDQ - VDDQ(@ calibration) and VDD = VDDQ. ODT Timing Definitions ODT loading differs from that used in AC timing measurements. The reference load for ODT timings is shown in Figure 22. Two parameters define when ODT turns on or off synchronously, two define when ODT turns on or off asynchronously, and another de- fines when ODT turns on or off dynamically. Table 35 outlines and provides definition and measurement references settings for each parameter (see Table 36 (page 57)). ODT turn-on time begins when the output leaves High-Z and ODT resistance begins to turn on. ODT turn-off time begins when the output leaves Low-Z and ODT resistance begins to turn off. 2Gb: x4, x8, x16 DDR3 SDRAM ODT Characteristics PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 56 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Figure 25: tADC Definition CK CK# tADC DQ, DM DQS, DQS# TDQS, TDQS# End point: Extrapolated point at VRTT,nom TSW21 tADC End point: Extrapolated point at VRTT(WR) VDDQ/2 VSSQ VRTT,nom VRTT(WR) VRTT,nom Begin point: Rising edge of CK - CK# defined by the end point of ODTLcnw Begin point: Rising edge of CK - CK# defined by the end point of ODTLcwn4 or ODTLcwn8 TSW11 VSW1 VSW2 TSW12 TSW22 2Gb: x4, x8, x16 DDR3 SDRAM ODT Characteristics PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 59 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

The output driver impedance is selected by MR1[5,1] during initialization. The selected value is able to maintain the tight tolerances specified if proper ZQ calibration is per- formed. Output specifications refer to the default output driver unless specifically sta- ted otherwise. A functional representation of the output buffer is shown below. The out- put driver impedance R ON is defined by the value of the external reference resistor RZQ as follows:

• RON,x = RZQ/y (with RZQ = 240Ω r x Ω or 40Ω with y = 7 or 6, respectively) The individual pull-up and pull-down resistors RON(PU) and RON(PD) are defined as fol- lows:
• RON(PU) = (VDDQ - VOUT)/|IOUT|, when RON(PD) is turned off
• RON(PD) = (VOUT)/|IOUT|, when RON(PU) is turned off Figure 26: Output Driver RON(PU) RON(PD) Output driver To other circuitry such as RCV, . . . Chip in drive mode V DDQ VSSQ IPU IPD IOUT VOUT DQ 2Gb: x4, x8, x16 DDR3 SDRAM Output Driver Impedance PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 60 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

34 Ohm Output Driver Impedance

The 34Ω driver (MR1[5, 1] = 01) is the default driver. Unless otherwise stated, all timings and specifications listed herein apply to the 34Ω driver only. Its impedance RON is de- fined by the value of the external reference resistor RZQ as follows: RON34 = RZQ/7 (with nominal RZQ = 240Ω ±1%) and is actually 34.3Ω r Table 37: 34 Ohm Driver Impedance Characteristics MR1[5,1] RON Resistor VOUT Min Nom Max Unit Notes 0,1 Ω RON34(PD) 0.2/VDDQ 0.6 1.0 1.1 RZQ/7 0.5/VDDQ 0.9 1.0 1.1 RZQ/7 0.8/VDDQ 0.9 1.0 1.4 RZQ/7 RON34(PU) 0.2/VDDQ 0.9 1.0 1.4 RZQ/7 0.5/VDDQ 0.9 1.0 1.1 RZQ/7 0.8/VDDQ 0.6 1.0 1.1 RZQ/7 Pull-up/pull-down mismatch (MMPUPD) 0.5/V DDQ –10% n/a 10 % 2 Notes: 1. Tolerance limits assume RZQ of 240 Ω ±1% and are applicable after proper ZQ calibra- tion has been performed at a stable temperature and voltage: VDDQ = VDD; VSSQ = VSS). Refer to 34 Ohm Output Driver Sensitivity (page 63) if either the temperature or the voltage changes after calibration. 2. Measurement definition for mismatch between pull-up and pull-down (MM PUPD). Meas- ure both RON(PU) and RON(PD) at 0.5 × VDDQ: MMPUPD = × 100 RON(PU) - RON(PD) RON,nom 3. For IT and AT (1Gb only) devices, the minimum values are derated by 6% when the de- vice operates between –40°C and 0°C (TC). 2Gb: x4, x8, x16 DDR3 SDRAM Output Driver Impedance PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 61 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

34 Ohm Driver

The 34Ω driver’s current range has been calculated and summarized in Table 39 (page 62) VDD = 1.5V , Table 40 (page 62) for VDD = 1.57V , and Table 41 (page 63) for VDD = 1.42V . The individual pull-up and pull-down resistors RON34(PD) and RON34(PU) are defined as follows:

• RON34(PD) = (VOUT)/|IOUT|; RON34(PU) is turned off
• RON34(PU) = (VDDQ - VOUT)/|IOUT|; RON34(PD) is turned off Table 38: 34 Ohm Driver Pull-Up and Pull-Down Impedance Calculations RON Min Nom Max Unit RZQ = 240Ω r 237.6 240 242.4 Ω RZQ/7 = (240Ω r 33.9 34.3 34.6 Ω MR1[5,1] R ON Resistor V OUT Min Nom Max Unit 0, 1 Ω RON34(PD) 0.2 × VDDQ 20.4 34.3 38.1 Ω 0.5 × VDDQ 30.5 34.3 38.1 Ω 0.8 × VDDQ 30.5 34.3 48.5 Ω RON34(PU) 0.2 × VDDQ 30.5 34.3 48.5 Ω 0.5 × VDDQ 30.5 34.3 38.1 Ω 0.8 × VDDQ 20.4 34.3 38.1 Ω Table 39: 34 Ohm Driver IOH/IOL Characteristics: VDD = VDDQ = 1.5V MR1[5,1] RON Resistor VOUT Max Nom Min Unit 0, 1 Ω RON34(PD) IOL @ 0.2 × VDDQ 14.7 8.8 7.9 mA IOL @ 0.5 × VDDQ 24.6 21.9 19.7 mA IOL @ 0.8 × VDDQ 39.3 35.0 24.8 mA RON34(PU) IOH @ 0.2 × VDDQ 39.3 35.0 24.8 mA IOH @ 0.5 × VDDQ 24.6 21.9 19.7 mA IOH @ 0.8 × VDDQ 14.7 8.8 7.9 mA Table 40: 34 Ohm Driver IOH/IOL Characteristics: VDD = VDDQ = 1.575V MR1[5,1] RON Resistor VOUT Max Nom Min Unit 0, 1 Ω RON34(PD) IOL @ 0.2 × VDDQ 15.5 9.2 8.3 mA IOL @ 0.5 × VDDQ 25.8 23 20.7 mA IOL @ 0.8 × VDDQ 41.2 36.8 26 mA RON34(PU) IOH @ 0.2 × VDDQ 41.2 36.8 26 mA IOH @ 0.5 × VDDQ 25.8 23 20.7 mA IOH @ 0.8 × VDDQ 15.5 9.2 8.3 mA 2Gb: x4, x8, x16 DDR3 SDRAM Output Driver Impedance PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 62 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Table 41: 34 Ohm Driver IOH/IOL Characteristics: VDD = VDDQ = 1.425V MR1[5,1] RON Resistor VOUT Max Nom Min Unit 0, 1 Ω RON34(PD) IOL @ 0.2 × VDDQ 14.0 8.3 7.5 mA IOL @ 0.5 × VDDQ 23.3 20.8 18.7 mA IOL @ 0.8 × VDDQ 37.3 33.3 23.5 mA RON34(PU) IOH @ 0.2 × VDDQ 37.3 33.3 23.5 mA IOH @ 0.5 × VDDQ 23.3 20.8 18.7 mA IOH @ 0.8 × VDDQ 14.0 8.3 7.5 mA

34 Ohm Output Driver Sensitivity

If either the temperature or the voltage changes after ZQ calibration, then the tolerance limits listed in Table 37 (page 61) can be expected to widen according to Table 42 and Table 43 (page 63). Table 42: 34 Ohm Output Driver Sensitivity Definition Symbol Min Max Unit RON(PD) @ 0.2 × VDDQ 0.6 - dRONdTL × |ΔT| - dRONdVL × |ΔV| 1.1 + dR ONdTL × |ΔT| + dRONdVL × |ΔV| RZQ/7 RON(PD) @ 0.5 × VDDQ 0.9 - dRONdTM × |ΔT| - dRONdVM × |ΔV| 1.1 + dR ONdTM × |ΔT| + dRONdVM × |ΔV| RZQ/7 RON(PD) @ 0.8 × VDDQ 0.9 - dRONdTH × |ΔT| - dRONdVH × |ΔV| 1.4 + dR ONdTH × |ΔT| + dRONdVH × |ΔV| RZQ/7 RON(PU) @ 0.2 × VDDQ 0.9 - dRONdTL × |ΔT| - dRONdVL × |ΔV| 1.4 + dR ONdTL × |ΔT| + dRONdVL × |ΔV| RZQ/7 RON(PU) @ 0.5 × VDDQ 0.9 - dRONdTM × |ΔT| - dRONdVM × |ΔV| 1.1 + dR ONdTM × |ΔT| + dRONdVM × |ΔV| RZQ/7 RON(PU) @ 0.8 × VDDQ 0.6 - dRONdTH × |ΔT| - dRONdVH × |ΔV| 1.1 + dR ONdTH × |ΔT| + dRONdVH × |ΔV| RZQ/7 Note: 1. ΔT = T - T(@CALIBRATION) ΔV = VDDQ - VDDQ(@CALIBRATION); and VDD = VDDQ. Table 43: 34 Ohm Output Driver Voltage and Temperature Sensitivity Change Min Max Unit dRONdTM 0 1.5 %/°C dRONdVM 0 0.13 %/mV dRONdTL 0 1.5 %/°C dRONdVL 0 0.13 %/mV dRONdTH 0 1.5 %/°C dRONdVH 0 0.13 %/mV 2Gb: x4, x8, x16 DDR3 SDRAM Output Driver Impedance PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 63 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Table 44: 40 Ohm Driver Impedance Characteristics MR1[5,1] RON Resistor VOUT Min Nom Max Unit 0,0 Ω RON40(PD) 0.2 × VDDQ 0.6 1.0 1.1 RZQ/6 0.5 × VDDQ 0.9 1.0 1.1 RZQ/6 0.8 × VDDQ 0.9 1.0 1.4 RZQ/6 RON40(PU) 0.2 × VDDQ 0.9 1.0 1.4 RZQ/6 0.5 × VDDQ 0.9 1.0 1.1 RZQ/6 0.8 × VDDQ 0.6 1.0 1.1 RZQ/6 Pull-up/pull-down mismatch (MMPUPD) 0.5 × V DDQ –10% n/a 10 % Notes: 1. Tolerance limits assume RZQ of 240 Ω ±1% and are applicable after proper ZQ calibra- tion has been performed at a stable temperature and voltage (VDDQ = VDD; VSSQ = VSS). Refer to 40 Ohm Output Driver Sensitivity (page 64) if either the temperature or the voltage changes after calibration. 2. Measurement definition for mismatch between pull-up and pull-down (MM PUPD). Meas- ure both RON(PU) and RON(PD) at 0.5 × VDDQ: MMPUPD = × 100 RON(PU) - RON(PD) RON,nom 3. For IT and AT (1Gb only) devices, the minimum values are derated by 6% when the de- vice operates between –40°C and 0°C (TC).

40 Ohm Output Driver Sensitivity

If either the temperature or the voltage changes after I/O calibration, then the tolerance limits listed in Table 44 can be expected to widen according to Table 45 and Table 46 (page 65). Table 45: 40 Ohm Output Driver Sensitivity Definition Symbol Min Max Unit RON(PD) @ 0.2 × VDDQ 0.6 - dRONdTL × |ΔT| - dRONdVL × |ΔV| 1.1 + dR ONdTL × |ΔT| + dRONdVL × |ΔV| RZQ/6 RON(PD) @ 0.5 × VDDQ 0.9 - dRONdTM × |ΔT| - dRONdVM × |ΔV| 1.1 + dR ONdTM × |ΔT| + dRONdVM × |ΔV| RZQ/6 RON(PD) @ 0.8 × VDDQ 0.9 - dRONdTH × |ΔT| - dRONdVH × |ΔV| 1.4 + dR ONdTH × |ΔT| + dRONdVH × |ΔV| RZQ/6 RON(PU) @ 0.2 × VDDQ 0.9 - dRONdTL × |ΔT| - dRONdVL × |ΔV| 1.4 + dR ONdTL × |ΔT| + dRONdVL × |ΔV| RZQ/6 RON(PU) @ 0.5 × VDDQ 0.9 - dRONdTM × |ΔT| - dRONdVM × |ΔV| 1.1 + dR ONdTM × |ΔT| + dRONdVM × |ΔV| RZQ/6 RON(PU) @ 0.8 × VDDQ 0.6 - dRONdTH × |ΔT| - dRONdVH × |ΔV| 1.1 + dR ONdTH × |ΔT| + dRONdVH × |ΔV| RZQ/6 Note: 1. ΔT = T - T(@CALIBRATION)ΔV = VDDQ - VDDQ(@CALIBRATION); and VDD = VDDQ. 2Gb: x4, x8, x16 DDR3 SDRAM Output Driver Impedance PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 64 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Table 46: 40 Ohm Output Driver Voltage and Temperature Sensitivity Change Min Max Unit dRONdTM 0 1.5 %/°C dRONdVM 0 0.15 %/mV dRONdTL 0 1.5 %/°C dRONdVL 0 0.15 %/mV dRONdTH 0 1.5 %/°C dRONdVH 0 0.15 %/mV 2Gb: x4, x8, x16 DDR3 SDRAM Output Driver Impedance PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 65 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Output Characteristics and Operating Conditions The DRAM uses both single-ended and differential output drivers. The single-ended output driver is summarized below, while the differential output driver is summarized in Table 48 (page 67). Table 47: Single-Ended Output Driver Characteristics All voltages are referenced to VSS Parameter/Condition Symbol Min Max Unit Notes Output leakage current: DQ are disabled; 0V ≤ VOUT ≤ VDDQ; ODT is disabled; ODT is HIGH IOZ –5 5 μA 1 Output slew rate: Single-ended; For rising and falling edges, measure between VOL(AC) = VREF - 0.1 × VDDQ and VOH(AC) = VREF + 0.1 × VDDQ SRQse 2.5 6 V/ns 1, 2, 3, 4 Single-ended DC high-level output voltage V OH(DC) 0.8 × VDDQ V 1, 2, 5 Single-ended DC mid-point level output voltage V OM(DC) 0.5 × VDDQ V 1, 2, 5 Single-ended DC low-level output voltage V OL(DC) 0.2 × VDDQ V 1, 2, 5 Single-ended AC high-level output voltage V OH(AC) VTT + 0.1 × VDDQ V 1, 2, 3, 6 Single-ended AC low-level output voltage V OL(AC) VTT - 0.1 × VDDQ V 1, 2, 3, 6 Delta RON between pull-up and pull-down for DQ/DQS MM PUPD –10 10 % 1, 7 Test load for AC timing and output slew rates Output to V TT (VDDQ/2) via 25Ω resistor 3 Notes: 1. RZQ of 240 Ω ±1% with RZQ/7 enabled (default 34Ω driver) and is applicable after prop- er ZQ calibration has been performed at a stable temperature and voltage (VDDQ = VDD; VSSQ = VSS). 2. VTT = VDDQ/2. 3. See Figure 29 (page 68) for the test load configuration. 4. The 6 V/ns maximum is applicable for a single DQ signal when it is switching either from HIGH to LOW or LOW to HIGH while the remaining DQ signals in the same byte lane are either all static or all switching in the opposite direction. For all other DQ signal switch- ing combinations, the maximum limit of 6 V/ns is reduced to 5 V/ns. 5. See Table 37 (page 61) for IV curve linearity. Do not use AC test load. 6. See Table 49 (page 69) for output slew rate. 7. See Table 37 (page 61) for additional information. 8. See Figure 27 (page 67) for an example of a single-ended output signal. 2Gb: x4, x8, x16 DDR3 SDRAM Output Characteristics and Operating Conditions PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 66 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Table 48: Differential Output Driver Characteristics All voltages are referenced to VSS Parameter/Condition Symbol Min Max Unit Notes Output leakage current: DQ are disabled; 0V ≤ VOUT ≤ VDDQ; ODT is disabled; ODT is HIGH IOZ –5 5 μA 1 Output slew rate: Differential; For rising and falling edges, measure between VOL,diff(AC) = –0.2 × VDDQ and VOH,diff(AC) = +0.2 × VDDQ SRQdiff 5 12 V/ns 1 Output differential cross-point voltage V OX(AC) VREF - 150 V REF + 150 mV 1, 2, 3 Differential high-level output voltage V OH,diff(AC) +0.2 × VDDQ V 1, 4 Differential low-level output voltage V OL,diff(AC) –0.2 × VDDQ V 1, 4 Delta Ron between pull-up and pull-down for DQ/DQS MM PUPD –10 10 % 1, 5 Test load for AC timing and output slew rates Output to V TT (VDDQ/2) via 25Ω resistor 3 Notes: 1. RZQ of 240 Ω ±1% with RZQ/7 enabled (default 34Ω driver) and is applicable after prop- er ZQ calibration has been performed at a stable temperature and voltage (VDDQ = VDD; VSSQ = VSS). 2. VREF = VDDQ/2; slew rate @ 5 V/ns, interpolate for faster slew rate. 3. See Figure 29 (page 68) for the test load configuration. 4. See Table 50 (page 70) for the output slew rate. 5. See Table 37 (page 61) for additional information. 6. See Figure 28 (page 68) for an example of a differential output signal. Figure 27: DQ Output Signal VOH(AC) MIN output MAX output VOL(AC) 2Gb: x4, x8, x16 DDR3 SDRAM Output Characteristics and Operating Conditions PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 67 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Slew Rate Definitions for Single-Ended Output Signals The single-ended output driver is summarized in Table 47 (page 66). With the reference load for timing measurements, the output slew rate for falling and rising edges is de- fined and measured between V OL(AC) and VOH(AC) for single-ended signals. Table 49: Single-Ended Output Slew Rate Definition Single-Ended Output Slew Rates (Linear Signals) Measured CalculationOutput Edge From To DQ Rising V OL(AC) VOH(AC) VOH(AC) - VOL(AC) ǻTRse Falling V OH(AC) VOL(AC) VOH(AC) - VOL(AC) ǻTFse Figure 30: Nominal Slew Rate Definition for Single-Ended Output Signals VOH(AC) VOL(AC) VTT ǻTFse ǻTRse 2Gb: x4, x8, x16 DDR3 SDRAM Output Characteristics and Operating Conditions PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 69 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Slew Rate Definitions for Differential Output Signals The differential output driver is summarized in Table 48 (page 67). With the reference load for timing measurements, the output slew rate for falling and rising edges is de- fined and measured between V OL(AC) and VOH(AC) for differential signals. Table 50: Differential Output Slew Rate Definition Differential Output Slew Rates (Linear Signals) Measured CalculationOutput Edge From To DQS, DQS# Rising V OL,diff(AC) VOH,diff(AC) VOH,diff(AC) - VOL,diff(AC) ǻTRdiff Falling V OH,diff(AC) VOL,diff(AC) VOH,diff(AC) - VOL,diff(AC) ǻTFdiff Figure 31: Nominal Differential Output Slew Rate Definition for DQS, DQS# ǻTRdiff ǻTFdiff VOH,diff(AC) VOL,diff(AC) 2Gb: x4, x8, x16 DDR3 SDRAM Output Characteristics and Operating Conditions PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 70 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Table 51: DDR3-1066 Speed Bins DDR3-1066 Speed Bin -187E -187 Unit Notes CL-tRCD-tRP 7-7-7 8-8-8 Parameter Symbol Min Max Min Max Internal READ command to first data tAA 13.125 – 15 – ns ACTIVATE to internal READ or WRITE delay time tRCD 13.125 – 15 – ns PRECHARGE command period tRP 13.125 – 15 – ns ACTIVATE-to-ACTIVATE or REFRESH command period tRC 50.625 – 52.5 – ns ACTIVATE-to-PRECHARGE command period tRAS 37.5 9 x tREFI 37.5 9 x tREFI ns 1 CL = 5 CWL = 5 tCK (AVG) 3.0 3.3 3.0 3.3 ns 2 CWL = 6 tCK (AVG) Reserved Reserved ns 3 CL = 6 CWL = 5 tCK (AVG) 2.5 3.3 2.5 3.3 ns 2 CWL = 6 tCK (AVG) Reserved Reserved ns 3 CL = 7 CWL = 5 tCK (AVG) Reserved Reserved ns 3 CWL = 6 tCK (AVG) 1.875 <2.5 Reserved ns 2, 3 CL = 8 CWL = 5 tCK (AVG) Reserved Reserved ns 3 CWL = 6 tCK (AVG) 1.875 <2.5 1.875 <2.5 ns 2 Supported CL settings 5, 6, 7, 8 5, 6, 8 CK Supported CWL settings 5, 6 5, 6 CK Notes: 1. tREFI depends on TOPER. 2. The CL and CWL settings result in tCK requirements. When making a selection of tCK, both CL and CWL requirement settings need to be fulfilled. 3. Reserved settings are not allowed. 2Gb: x4, x8, x16 DDR3 SDRAM Speed Bin Tables PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 71 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Table 52: DDR3-1333 Speed Bins DDR3-1333 Speed Bin -15E1 -152 Unit Notes CL-tRCD-tRP 9-9-9 10-10-10 Parameter Symbol Min Max Min Max Internal READ command to first data tAA 13.5 – 15 – ns ACTIVATE to internal READ or WRITE delay time tRCD 13.5 – 15 – ns PRECHARGE command period tRP 13.5 – 15 – ns ACTIVATE-to-ACTIVATE or REFRESH command period tRC 49.5 – 51 – ns ACTIVATE-to-PRECHARGE command period tRAS 36 9 x tREFI 36 9 x tREFI ns 3 CL = 5 CWL = 5 tCK (AVG) 3.0 3.3 3.0 3.3 ns 4 CWL = 6, 7 tCK (AVG) Reserved Reserved ns 5 CL = 6 CWL = 5 tCK (AVG) 2.5 3.3 2.5 3.3 ns 4 CWL = 6 tCK (AVG) Reserved Reserved ns 5 CWL = 7 tCK (AVG) Reserved Reserved ns 5 CL = 7 CWL = 5 tCK (AVG) Reserved Reserved ns 5 CWL = 6 tCK (AVG) 1.875 <2.5 Reserved ns 4, 5 CWL = 7 tCK (AVG) Reserved Reserved ns 5 CL = 8 CWL = 5 tCK (AVG) Reserved Reserved ns 5 CWL = 6 tCK (AVG) 1.875 <2.5 1.875 <2.5 ns 4 CWL = 7 tCK (AVG) Reserved Reserved ns 5 CL = 9 CWL = 5, 6 tCK (AVG) Reserved Reserved ns 5 CWL = 7 tCK (AVG) 1.5 <1.875 Reserved ns 4, 5 CL = 10 CWL = 5, 6 tCK (AVG) Reserved Reserved ns 5 CWL = 7 tCK (AVG) 1.5 <1.875 1.5 <1.875 ns 4 Supported CL settings 5, 6, 7, 8, 9, 10 5, 6, 8, 10 CK Supported CWL settings 5, 6, 7 5, 6, 7 CK Notes: 1. The -15E speed grade is backward compatible with 1066, CL = 7 (-187E). 2. The -15 speed grade is backward compatible with 1066, CL = 8 (-187). tREFI depends on TOPER. 4. The CL and CWL settings result in tCK requirements. When making a selection of tCK, both CL and CWL requirement settings need to be fulfilled. 5. Reserved settings are not allowed. 2Gb: x4, x8, x16 DDR3 SDRAM Speed Bin Tables PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 72 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Table 53: DDR3-1600 Speed Bins DDR3-1600 Speed Bin -1251 Unit Notes CL-tRCD-tRP 11-11-11 Parameter Symbol Min Max Internal READ command to first data tAA 13.75 – ns ACTIVATE to internal READ or WRITE delay time tRCD 13.75 – ns PRECHARGE command period tRP 13.75 – ns ACTIVATE-to-ACTIVATE or REFRESH command period tRC 48.75 – ns ACTIVATE-to-PRECHARGE command period tRAS 35 9 x tREFI ns 2 CL = 5 CWL = 5 tCK (AVG) 3.0 3.3 ns 3 CWL = 6, 7, 8 tCK (AVG) Reserved ns 4 CL = 6 CWL = 5 tCK (AVG) 2.5 3.3 ns 3 CWL = 6 tCK (AVG) Reserved ns 4 CWL = 7, 8 tCK (AVG) Reserved ns 4 CL = 7 CWL = 5 tCK (AVG) Reserved ns 4 CWL = 6 tCK (AVG) 1.875 <2.5 ns 3 CWL = 7 tCK (AVG) Reserved ns 4 CWL = 8 tCK (AVG) Reserved ns 4 CL = 8 CWL = 5 tCK (AVG) Reserved ns 4 CWL = 6 tCK (AVG) 1.875 <2.5 ns 3 CWL = 7 tCK (AVG) Reserved ns 4 CWL = 8 tCK (AVG) Reserved ns 4 CL = 9 CWL = 5, 6 tCK (AVG) Reserved ns 4 CWL = 7 tCK (AVG) 1.5 <1.875 ns 3 CWL = 8 tCK (AVG) Reserved ns 4 CL = 10 CWL = 5, 6 tCK (AVG) Reserved ns 4 CWL = 7 tCK (AVG) 1.5 <1.875 ns 3 CWL = 8 tCK (AVG) Reserved ns 4 CL = 11 CWL = 5, 6, 7 tCK (AVG) Reserved ns 4 CWL = 8 tCK (AVG) 1.25 <1.5 ns 3 Supported CL settings 5, 6, 7, 8, 9, 10, 11 CK Supported CWL settings 5, 6, 7, 8 CK Notes: 1. The -125 speed grade is backward compatible with 1333, CL = 9 (-15E) and 1066, CL = 7 (-187E). 2. tREFI depends on TOPER. 3. The CL and CWL settings result in tCK requirements. When making a selection of tCK, both CL and CWL requirement settings need to be fulfilled. 4. Reserved settings are not allowed. 2Gb: x4, x8, x16 DDR3 SDRAM Speed Bin Tables PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 73 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Table 54: DDR3-1866 Speed Bins DDR3-1866 Speed Bin -1071 Unit Notes CL-tRCD-tRP 13-13-13 Parameter Symbol Min Max Internal READ command to first data tAA 13.91 20 ACTIVATE to internal READ or WRITE delay time tRCD 13.91 – ns PRECHARGE command period tRP 13.91 – ns ACTIVATE-to-ACTIVATE or REFRESH command period tRC 47.91 – ns ACTIVATE-to-PRECHARGE command period tRAS 34 9 x tREFI ns 2 CL = 5 CWL = 5 tCK (AVG) 3.0 3.3 ns 3 CWL = 6, 7, 8, 9 tCK (AVG) Reserved ns 4 CL = 6 CWL = 5 tCK (AVG) 2.5 3.3 ns 3 CWL = 6, 7, 8, 9 tCK (AVG) Reserved ns 4 CL = 7 CWL = 5, 7, 8, 9 tCK (AVG) Reserved ns 4 CWL = 6 tCK (AVG) 1.875 <2.5 ns 3 CL = 8 CWL = 5, 8, 9 tCK (AVG) Reserved ns 4 CWL = 6 tCK (AVG) 1.875 <2.5 ns 3 CWL = 7 tCK (AVG) Reserved ns 4 CL = 9 CWL = 5, 6, 8, 9 tCK (AVG) Reserved ns 4 CWL = 7 tCK (AVG) 1.5 <1.875 ns 3 CL = 10 CWL = 5, 6, 9 tCK (AVG) Reserved ns 4 CWL = 7 tCK (AVG) 1.5 <1.875 ns 3 CWL = 8 tCK (AVG) Reserved ns 4 CL = 11 CWL = 5, 6, 7 tCK (AVG) Reserved ns 4 CWL = 8 tCK (AVG) 1.25 <1.5 ns 3 CWL = 9 tCK (AVG) Reserved ns 4 CL = 12 CWL = 5, 6, 7, 8 tCK (AVG) Reserved ns 4 CWL = 9 tCK (AVG) Reserved ns 4 CL = 13 CWL = 5, 6, 7, 8 tCK (AVG) Reserved ns 4 CWL = 9 tCK (AVG) 1.071 <1.25 ns 3 Supported CL settings 5, 6, 7, 8, 9, 10, 11, 13 CK Supported CWL settings 5, 6, 7, 8, 9 CK Notes: 1. The -107 speed grade is backward compatible with 1600, CL = 11 (-125) , 1333, CL = 9 2. tREFI depends on TOPER. 3. The CL and CWL settings result in tCK requirements. When making a selection of tCK, both CL and CWL requirement settings need to be fulfilled. 4. Reserved settings are not allowed. 2Gb: x4, x8, x16 DDR3 SDRAM Speed Bin Tables PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 74 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Table 55: DDR3-2133 Speed Bins DDR3-2133 Speed Bin -0931 Unit Notes CL-tRCD-tRP 14-14-14 Parameter Symbol Min Max Internal READ command to first data tAA 13.09 20 ACTIVATE to internal READ or WRITE delay time tRCD 13.09 – ns PRECHARGE command period tRP 13.09 – ns ACTIVATE-to-ACTIVATE or REFRESH command period tRC 46.13 – ns ACTIVATE-to-PRECHARGE command period tRAS 33 9 x tREFI ns 2 CL = 5 CWL = 5 tCK (AVG) 3.0 3.3 ns 3 CWL = 6, 7, 8, 9 tCK (AVG) Reserved ns 4 CL = 6 CWL = 5 tCK (AVG) 2.5 3.3 ns 3 CWL = 6, 7, 8, 9 tCK (AVG) Reserved ns 4 CL = 7 CWL = 5, 7, 8, 9 tCK (AVG) Reserved ns 4 CWL = 6 tCK (AVG) 1.875 <2.5 ns 3 CL = 8 CWL = 5, 8, 9 tCK (AVG) Reserved ns 4 CWL = 6 tCK (AVG) 1.875 <2.5 ns 3 CWL = 7 tCK (AVG) Reserved ns 4 CL = 9 CWL = 5, 6, 8, 9 tCK (AVG) Reserved ns 4 CWL = 7 tCK (AVG) 1.5 <1.875 ns 3 CL = 10 CWL = 5, 6, 9 tCK (AVG) Reserved ns 4 CWL = 7 tCK (AVG) 1.5 <1.875 ns 3 CWL = 8 tCK (AVG) Reserved ns 4 CL = 11 CWL = 5, 6, 7 tCK (AVG) Reserved ns 4 CWL = 8 tCK (AVG) 1.25 <1.5 ns 3 CWL = 9 tCK (AVG) Reserved ns 4 CL = 12 CWL = 5, 6, 7, 8 tCK (AVG) Reserved ns 4 CWL = 9 tCK (AVG) Reserved ns 4 CL = 13 CWL = 5, 6, 7, 8 tCK (AVG) Reserved ns 4 CWL = 9 tCK (AVG) 1.071 <1.25 ns 3 CL = 14 CWL = 5, 6, 7, 8, 9 tCK (AVG) Reserved Reserved ns 4 CWL = 10 tCK (AVG) 0.938 <1.071 ns 3 Supported CL settings 5, 6, 7, 8, 9, 10, 11, 13, 14 CK Supported CWL settings 5, 6, 7, 8, 9 CK Notes: 1. The -093 speed grade is backward compatible with 1866, CL = 13 (-107) , 1600, CL = 11 2. tREFI depends on TOPER. 3. The CL and CWL settings result in tCK requirements. When making a selection of tCK, both CL and CWL requirement settings need to be fulfilled. 4. Reserved settings are not allowed. 2Gb: x4, x8, x16 DDR3 SDRAM Speed Bin Tables PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 75 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Electrical Characteristics and AC Operating Conditions Table 56: Electrical Characteristics and AC Operating Conditions Notes 1–8 apply to the entire table Parameter Symbol DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 Unit NotesMin Max Min Max Min Max Min Max Clock Timing Clock period average: DLL disable mode TC ≤ 85°C tCK (DLL_DIS) 8 7800 8 7800 8 7800 8 7800 ns 9, 42 TC = >85°C to 95°C 8 3900 8 3900 8 3900 8 3900 ns 42 Clock period average: DLL enable mode tCK (AVG) See Speed Bin Tables (page 71) for tCK range allowed ns 10, 11 Clock period jitter DLL locked tJITper –100 100 –90 90 –80 80 –70 70 ps 13 DLL locking tJITper,lck –90 90 –80 80 –70 70 –60 60 ps 13 Clock absolute period tCK (ABS) MIN = tCK (AVG) MIN + tJITper MIN; MAX = tCK (AVG) MAX + tJITper MAX ps Clock absolute high pulse width tCH (ABS) 0.43 – 0.43 – 0.43 – 0.43 – tCK (AVG) Clock absolute low pulse width tCL (ABS) 0.43 – 0.43 – 0.43 – 0.43 – tCK (AVG) Cycle-to-cycle jitter DLL locked tJITcc 200 180 160 140 ps 16 DLL locking tJITcc,lck 180 160 140 120 ps 16 Cumulative error across 2 cycles tERR2per –147 147 –132 132 –118 118 –103 103 ps 17 3 cycles tERR3per –175 175 –157 157 –140 140 –122 122 ps 17 4 cycles tERR4per –194 194 –175 175 –155 155 –136 136 ps 17 5 cycles tERR5per –209 209 –188 188 –168 168 –147 147 ps 17 6 cycles tERR6per –222 222 –200 200 –177 177 –155 155 ps 17 7 cycles tERR7per –232 232 –209 209 –186 186 –163 163 ps 17 8 cycles tERR8per –241 241 –217 217 –193 193 –169 169 ps 17 9 cycles tERR9per –249 249 –224 224 –200 200 –175 175 ps 17 10 cycles tERR10per –257 257 –231 231 –205 205 –180 180 ps 17 11 cycles tERR11per –263 263 –237 237 –210 210 –184 184 ps 17 12 cycles tERR12per –269 269 –242 242 –215 215 –188 188 ps 17 cycles tERRnper tERRnper MIN = (1 + 0.68ln[n]) × tJITper MIN tERRnper MAX = (1 + 0.68ln[n]) × tJITper MAX ps 17 2Gb: x4, x8, x16 DDR3 SDRAM Electrical Characteristics and AC Operating Conditions PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 76 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Table 56: Electrical Characteristics and AC Operating Conditions (Continued) Notes 1–8 apply to the entire table Parameter Symbol DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 Unit NotesMin Max Min Max Min Max Min Max DQ Input Timing Data setup time to DQS, DQS# Base (specification) tDS (AC175) VREF @ 1 V/ns 250 – 200 – – – – – ps 19, 20 Data setup time to DQS, DQS# Base (specification) tDS (AC150) 125 – 75 – 30 – 10 – ps 18, 19, VREF @ 1 V/ns 275 – 250 – 180 – 160 – ps 19, 20 Data setup time to DQS, DQS# Base (specification) tDS (AC135) Data hold time from DQS, DQS# Base (specification) tDH (DC100) 150 – 100 – 65 – 45 – ps 18, 19 VREF @ 1 V/ns 250 – 200 – 165 – 145 – ps 19, 20 Minimum data pulse width tDIPW 600 – 490 – 400 – 360 – ps 41 DQ Output Timing DQS, DQS# to DQ skew, per access tDQSQ – 200 – 150 – 125 – 100 ps DQ output hold time from DQS, DQS# tQH 0.38 – 0.38 – 0.38 – 0.38 – tCK (AVG) DQ Low-Z time from CK, CK# tLZDQ –800 400 –600 300 –500 250 –450 225 ps 22, 23 DQ High-Z time from CK, CK# tHZDQ – 400 – 300 – 250 – 225 ps 22, 23 DQ Strobe Input Timing DQS, DQS# differential input high pulse width DQS, DQS# falling setup to CK, CK# rising tDSS 0.2 – 0.2 – 0.2 – 0.18 – CK 25 DQS, DQS# falling hold from CK, CK# rising tDSH 0.2 – 0.2 – 0.2 – 0.18 – CK 25 DQS, DQS# differential WRITE preamble tWPRE 0.9 – 0.9 – 0.9 – 0.9 – CK DQS, DQS# differential WRITE postamble tWPST 0.3 – 0.3 – 0.3 – 0.3 – CK DQ Strobe Output Timing DQS, DQS# rising to/from rising CK, CK# tDQSCK –400 400 –300 300 –255 255 –225 225 ps 23 DQS, DQS# rising to/from rising CK, CK# when DLL is disabled tDQSCK (DLL_DIS) 11 011 011 011 0 n s 2 6 2Gb: x4, x8, x16 DDR3 SDRAM Electrical Characteristics and AC Operating Conditions PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 77 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Table 56: Electrical Characteristics and AC Operating Conditions (Continued) Notes 1–8 apply to the entire table Parameter Symbol DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 Unit NotesMin Max Min Max Min Max Min Max DQS, DQS# differential output high time tQSH 0.38 – 0.38 – 0.40 – 0.40 – CK 21 DQS, DQS# differential output low time tQSL 0.38 – 0.38 – 0.40 – 0.40 – CK 21 DQS, DQS# Low-Z time (RL - 1) tLZDQS –800 400 –600 300 –500 250 –450 225 ps 22, 23 DQS, DQS# High-Z time (RL + BL/2) tHZDQS – 400 – 300 – 250 – 225 ps 22, 23 DQS, DQS# differential READ preamble tRPRE 0.9 Note 24 0.9 Note 24 0.9 Note 24 0.9 Note 24 CK 23, 24 DQS, DQS# differential READ postamble tRPST 0.3 Note 27 0.3 Note 27 0.3 Note 27 0.3 Note 27 CK 23, 27 Command and Address Timing DLL locking time tDLLK 512 – 512 – 512 – 512 – CK 28 CTRL, CMD, ADDR setup to CK,CK# Base (specification) tIS (AC175) 200 – 125 – 65 – 45 – ps 29, 30, VREF @ 1 V/ns 375 – 300 – 240 – 220 – ps 20, 30 CTRL, CMD, ADDR setup to CK,CK# Base (specification) tIS (AC150) 350 – 275 – 190 – 170 – ps 29, 30, VREF @ 1 V/ns 500 – 425 – 340 – 320 – ps 20, 30 CTRL, CMD, ADDR hold from CK,CK# Base (specification) tIH (DC100) 275 – 200 – 140 – 120 – ps 29, 30 VREF @ 1 V/ns 375 – 300 – 240 – 220 – ps 20, 30 Minimum CTRL, CMD, ADDR pulse width tIPW 900 – 780 – 620 – 560 – ps 41 ACTIVATE to internal READ or WRITE delay tRCD See Speed Bin Tables (page 71) for tRCD ns 31 PRECHARGE command period tRP See Speed Bin Tables (page 71) for tRP ns 31 ACTIVATE-to-PRECHARGE command period tRAS See Speed Bin Tables (page 71) for tRAS ns 31, 32 ACTIVATE-to-ACTIVATE command period tRC See Speed Bin Tables (page 71) for tRC ns 31, 43 ACTIVATE-to-ACTIVATE minimum command period x4/x8 (1KB page size) tRRD MIN = greater of 4CK or 10ns MIN = greater of 4CK or 7.5ns MIN = greater of 4CK or 6ns MIN = greater of 4CK or 6ns CK 31 x16 (2KB page size) MIN = greater of 4CK or 10ns MIN = greater of 4CK or 7.5ns CK 31 Four ACTIVATE windows x4/x8 (1KB page size) tFAW 40 – 37.5 – 30 – 30 – ns 31 x16 (2KB page size) 50 – 50 – 45 – 40 – ns 31 Write recovery time tWR MIN = 15ns; MAX = n/a ns 31, 32, 33,34 Delay from start of internal WRITE transaction to internal READ command tWTR MIN = greater of 4CK or 7.5ns; MAX = n/a CK 31, 34 2Gb: x4, x8, x16 DDR3 SDRAM Electrical Characteristics and AC Operating Conditions PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 78 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Table 56: Electrical Characteristics and AC Operating Conditions (Continued) Notes 1–8 apply to the entire table Parameter Symbol DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 Unit NotesMin Max Min Max Min Max Min Max READ-to-PRECHARGE time tRTP MIN = greater of 4CK or 7.5ns; MAX = n/a CK 31, 32 CAS#-to-CAS# command delay tCCD MIN = 4CK; MAX = n/a CK Auto precharge write recovery + precharge time tDAL MIN = WR + tRP/tCK (AVG); MAX = n/a CK MODE REGISTER SET command cycle time tMRD MIN = 4CK; MAX = n/a CK MODE REGISTER SET command update delay tMOD MIN = greater of 12CK or 15ns; MAX = n/a CK MULTIPURPOSE REGISTER READ burst end to mode register set for multipurpose register exit tMPRR MIN = 1CK; MAX = n/a CK Calibration Timing ZQCL command: Long calibration time POWER-UP and RE- SET operation tZQinit 512 – 512 – 512 – 512 – CK Normal operation tZQoper 256 – 256 – 256 – 256 – CK ZQCS command: Short calibration time tZQCS 64 – 64 – 64 – 64 – CK Initialization and Reset Timing Exit reset from CKE HIGH to a valid command tXPR MIN = greater of 5CK or tRFC + 10ns; MAX = n/a CK Begin power supply ramp to power supplies stable tVDDPR MIN = n/a; MAX = 200 ms RESET# LOW to power supplies stable tRPS MIN = 0; MAX = 200 ms RESET# LOW to I/O and RTT High-Z tIOZ MIN = n/a; MAX = 20 ns 35 Refresh Timing REFRESH-to-ACTIVATE or REFRESH command period tRFC – 1Gb MIN = 110; MAX = 70,200 ns tRFC – 2Gb MIN = 160; MAX = 70,200 ns tRFC – 4Gb MIN = 260; MAX = 70,200 ns tRFC – 8Gb MIN = 350; MAX = 70,200 ns Maximum refresh period TC ≤ 85°C – 64 (1X) ms 36 TC > 85°C 32 (2X) ms 36 Maximum average periodic refresh TC ≤ 85°C tREFI 7.8 (64ms/8192) μs 36 TC > 85°C 3.9 (32ms/8192) μs 36 Self Refresh Timing 2Gb: x4, x8, x16 DDR3 SDRAM Electrical Characteristics and AC Operating Conditions PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 79 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Table 56: Electrical Characteristics and AC Operating Conditions (Continued) Notes 1–8 apply to the entire table Parameter Symbol DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 Unit NotesMin Max Min Max Min Max Min Max Exit self refresh to commands not requiring a locked DLL tXS MIN = greater of 5CK or tRFC + 10ns; MAX = n/a CK Exit self refresh to commands requiring a locked DLL tXSDLL MIN = tDLLK (MIN); MAX = n/a CK 28 Minimum CKE low pulse width for self re- fresh entry to self refresh exit timing tCKESR MIN = tCKE (MIN) + CK; MAX = n/a CK Valid clocks after self refresh entry or power- down entry tCKSRE MIN = greater of 5CK or 10ns; MAX = n/a CK Valid clocks before self refresh exit, power-down exit, or reset exit tCKSRX MIN = greater of 5CK or 10ns; MAX = n/a CK Power-Down Timing CKE MIN pulse width tCKE (MIN) Greater of 3CK or 7.5ns Greater of 3CK or 5.625ns Greater of 3CK or 5.625ns Greater of 3CK or 5ns CK Command pass disable delay tCPDED MIN = 1; MAX = n/a CK Power-down entry to power-down exit tim- ing tPD MIN = tCKE (MIN); MAX = 9 * tREFI CK Begin power-down period prior to CKE registered HIGH tANPD WL - 1CK CK Power-down entry period: ODT either synchronous or asynchronous PDE Greater of tANPD or tRFC - REFRESH command to CKE LOW time CK Power-down exit period: ODT either synchronous or asynchronous PDX tANPD + tXPDLL CK Power-Down Entry Minimum Timing ACTIVATE command to power-down entry tACTPDEN MIN = 1 CK PRECHARGE/PRECHARGE ALL command to power-down entry tPRPDEN MIN = 1 CK REFRESH command to power-down entry tREFPDEN MIN = 1 CK 37 MRS command to power-down entry tMRSPDEN MIN = tMOD (MIN) CK READ/READ with auto precharge command to power-down entry tRDPDEN MIN = RL + 4 + 1 CK WRITE command to power-down entry BL8 (OTF, MRS) BC4OTF tWRPDEN MIN = WL + 4 + tWR/tCK (AVG) CK BC4MRS tWRPDEN MIN = WL + 2 + tWR/tCK (AVG) CK 2Gb: x4, x8, x16 DDR3 SDRAM Electrical Characteristics and AC Operating Conditions PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 80 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Table 56: Electrical Characteristics and AC Operating Conditions (Continued) Notes 1–8 apply to the entire table Parameter Symbol DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 Unit NotesMin Max Min Max Min Max Min Max WRITE with auto precharge command to power-down entry BL8 (OTF, MRS) BC4OTF tWRAP- DEN MIN = WL + 4 + WR + 1 CK BC4MRS tWRAP- DEN MIN = WL + 2 + WR + 1 CK Power-Down Exit Timing DLL on, any valid command, or DLL off to commands not requiring locked DLL tXP MIN = greater of 3CK or 7.5ns; MAX = n/a MIN = greater of 3CK or 6ns; MAX = n/a CK Precharge power-down with DLL off to commands requiring a locked DLL tXPDLL MIN = greater of 10CK or 24ns; MAX = n/a CK 28 ODT Timing RTT synchronous turn-on delay ODTLon CWL + AL - 2CK CK 38 RTT synchronous turn-off delay ODTLoff CWL + AL - 2CK CK 40 RTT turn-on from ODTL on reference tAON –400 400 –300 300 –250 250 –225 225 ps 23, 38 Asynchronous RTT turn-on delay (power-down with DLL off) tAONPD MIN = 2; MAX = 8.5 ns 38 Asynchronous RTT turn-off delay (power-down with DLL off) tAOFPD MIN = 2; MAX = 8.5 ns 40 ODT HIGH time with WRITE command and BL8 ODTH8 MIN = 6; MAX = n/a CK ODT HIGH time without WRITE command or with WRITE command and BC4 ODTH4 MIN = 4; MAX = n/a CK Dynamic ODT Timing RTT,nom-to-RTT(WR) change skew ODTLcnw WL - 2CK CK RTT(WR)-to-RTT,nom change skew - BC4 ODTLcwn4 4CK + ODTLoff CK RTT(WR)-to-RTT,nom change skew - BL8 ODTLcwn8 6CK + ODTLoff CK Write Leveling Timing First DQS, DQS# rising edge tWLMRD 40 – 40 – 40 – 40 – CK DQS, DQS# delay tWLDQSEN 25 – 25 – 25 – 25 – CK Write leveling setup from rising CK, CK# crossing to rising DQS, DQS# crossing tWLS 325 – 245 – 195 – 165 – ps 2Gb: x4, x8, x16 DDR3 SDRAM Electrical Characteristics and AC Operating Conditions PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 81 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Table 56: Electrical Characteristics and AC Operating Conditions (Continued) Notes 1–8 apply to the entire table Parameter Symbol DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 Unit NotesMin Max Min Max Min Max Min Max Write leveling hold from rising DQS, DQS# crossing to rising CK, CK# crossing tWLH 325 – 245 – 195 – 165 – ps Write leveling output delay tW L O 0909090 7 . 5 n s Write leveling output error tWLOE 02020202 n s 2Gb: x4, x8, x16 DDR3 SDRAM Electrical Characteristics and AC Operating Conditions PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 82 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Notes: 1. AC timing parameters are valid from specified T C MIN to TC MAX values. 2. All voltages are referenced to V SS. 3. Output timings are only valid for R ON34 output buffer selection. 4. The unit tCK (AVG) represents the actual tCK (AVG) of the input clock under operation. The unit CK represents one clock cycle of the input clock, counting the actual clock edges. 5. AC timing and I DD tests may use a VIL-to-VIH swing of up to 900mV in the test environ- ment, but input timing is still referenced to VREF (except tIS, tIH, tDS, and tDH use the AC/DC trip points and CK, CK# and DQS, DQS# use their crossing points). The minimum slew rate for the input signals used to test the device is 1 V/ns for single-ended inputs and 2 V/ns for differential inputs in the range between V IL(AC) and VIH(AC). 6. All timings that use time-based values (ns, μs, ms) should use tCK (AVG) to determine the correct number of clocks (Table 56 (page 76) uses CK or tCK [AVG] interchangeably). In the case of noninteger results, all minimum limits are to be rounded up to the nearest whole integer, and all maximum limits are to be rounded down to the nearest whole integer. 7. Strobe or DQS diff refers to the DQS and DQS# differential crossing point when DQS is the rising edge. Clock or CK refers to the CK and CK# differential crossing point when CK is the rising edge. 8. This output load is used for all AC timing (except ODT reference timing) and slew rates. The actual test load may be different. The output signal voltage reference point is V DDQ/2 for single-ended signals and the crossing point for differential signals (see Fig- ure 29 (page 68)). 9. When operating in DLL disable mode, Micron does not warrant compliance with normal mode timings or functionality. 10. The clock’s tCK (AVG) is the average clock over any 200 consecutive clocks and tCK (AVG) MIN is the smallest clock rate allowed, with the exception of a deviation due to clock jitter. Input clock jitter is allowed provided it does not exceed values specified and must be of a random Gaussian distribution in nature. 11. Spread spectrum is not included in the jitter specification values. However, the input clock can accommodate spread-spectrum at a sweep rate in the range of 20–60 kHz with an additional 1% of tCK (AVG) as a long-term jitter component; however, the spread spectrum may not use a clock rate below tCK (AVG) MIN. 12. The clock’s tCH (AVG) and tCL (AVG) are the average half clock period over any 200 con- secutive clocks and is the smallest clock half period allowed, with the exception of a de- viation due to clock jitter. Input clock jitter is allowed provided it does not exceed values specified and must be of a random Gaussian distribution in nature. 13. The period jitter ( tJITper) is the maximum deviation in the clock period from the average or nominal clock. It is allowed in either the positive or negative direction. 14. tCH (ABS) is the absolute instantaneous clock high pulse width as measured from one rising edge to the following falling edge. 15. tCL (ABS) is the absolute instantaneous clock low pulse width as measured from one fall- ing edge to the following rising edge. 16. The cycle-to-cycle jitter tJITcc is the amount the clock period can deviate from one cycle to the next. It is important to keep cycle-to-cycle jitter at a minimum during the DLL locking time. 17. The cumulative jitter error tERRnper, where n is the number of clocks between 2 and 50, is the amount of clock time allowed to accumulate consecutively away from the average clock over n number of clock cycles. 18. tDS (base) and tDH (base) values are for a single-ended 1 V/ns slew rate DQs and 2 V/ns slew rate differential DQS, DQS#. 19. These parameters are measured from a data signal (DM, DQ0, DQ1, and so forth) transi- tion edge to its respective data strobe signal (DQS, DQS#) crossing. 2Gb: x4, x8, x16 DDR3 SDRAM Electrical Characteristics and AC Operating Conditions PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 83 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

1. The setup and hold times are listed converting the base specification values (to which derating tables apply) to VREF when the slew rate is 1 V/ns. These values, with a slew rate of 1 V/ns, are for reference only. 21. When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJITper (larger of tJITper (MIN) or tJITper (MAX) of the input clock (output deratings are relative to the SDRAM input clock). 22. Single-ended signal parameter. 23. The DRAM output timing is aligned to the nominal or average clock. Most output pa- rameters must be derated by the actual jitter error when input clock jitter is present, even when within specification. This results in each parameter becoming larger. The fol- lowing parameters are required to be derated by subtracting tERR10per (MAX): tDQSCK (MIN), tLZDQS (MIN), tLZDQ (MIN), and tAON (MIN). The following parameters are re- quired to be derated by subtracting tERR10per (MIN): tDQSCK (MAX), tHZ (MAX), tLZDQS (MAX), tLZDQ MAX, and tAON (MAX). The parameter tRPRE (MIN) is derated by subtract- ing tJITper (MAX), while tRPRE (MAX) is derated by subtracting tJITper (MIN). 24. The maximum preamble is bound by tLZDQS (MAX). 25. These parameters are measured from a data strobe signal (DQS, DQS#) crossing to its re- spective clock signal (CK, CK#) crossing. The specification values are not affected by the amount of clock jitter applied, as these are relative to the clock signal crossing. These parameters should be met whether clock jitter is present. 26. The tDQSCK (DLL_DIS) parameter begins CL + AL - 1 cycles after the READ command. 27. The maximum postamble is bound by tHZDQS (MAX). 28. Commands requiring a locked DLL are: READ (and RDAP) and synchronous ODT com- mands. In addition, after any change of latency tXPDLL, timing must be met. 29. tIS (base) and tIH (base) values are for a single-ended 1 V/ns control/command/address slew rate and 2 V/ns CK, CK# differential slew rate. 30. These parameters are measured from a command/address signal transition edge to its respective clock (CK, CK#) signal crossing. The specification values are not affected by the amount of clock jitter applied as the setup and hold times are relative to the clock signal crossing that latches the command/address. These parameters should be met whether clock jitter is present. 31. For these parameters, the DDR3 SDRAM device supports tnPARAM (nCK) = RU(tPARAM [ns]/tCK[AVG] [ns]), assuming all input clock jitter specifications are satisfied. For exam- ple, the device will support tnRP (nCK) = RU(tRP/tCK[AVG]) if all input clock jitter specifi- cations are met. This means that for DDR3-800 6-6-6, of which tRP = 5ns, the device will support tnRP = RU(tRP/tCK[AVG]) = 6 as long as the input clock jitter specifications are met. That is, the PRECHARGE command at T0 and the ACTIVATE command at T0 + 6 are valid even if six clocks are less than 15ns due to input clock jitter. 32. During READs and WRITEs with auto precharge, the DDR3 SDRAM will hold off the in- ternal PRECHARGE command until tRAS (MIN) has been satisfied. 33. When operating in DLL disable mode, the greater of 4CK or 15ns is satisfied for tWR. 34. The start of the write recovery time is defined as follows:

• For BL8 (fixed by MRS or OTF): Rising clock edge four clock cycles after WL
• For BC4 (OTF): Rising clock edge four clock cycles after WL
• For BC4 (fixed by MRS): Rising clock edge two clock cycles after WL 35. RESET# should be LOW as soon as power starts to ramp to ensure the outputs are in High-Z. Until RESET# is LOW, the outputs are at risk of driving and could result in exces- sive current, depending on bus activity. 36. The refresh period is 64ms when T C is less than or equal to 85°C. This equates to an aver- age refresh rate of 7.8125μs. However, nine REFRESH commands should be asserted at least once every 70.3μs. When T C is greater than 85°C, the refresh period is 32ms. 37. Although CKE is allowed to be registered LOW after a REFRESH command when 2Gb: x4, x8, x16 DDR3 SDRAM Electrical Characteristics and AC Operating Conditions PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 84 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

tREFPDEN (MIN) is satisfied, there are cases where additional time such as tXPDLL (MIN) is required. 38. ODT turn-on time MIN is when the device leaves High-Z and ODT resistance begins to turn on. ODT turn-on time maximum is when the ODT resistance is fully on. The ODT reference load is shown in Figure 21 (page 54). Designs that were created prior to JEDEC tightening the maximum limit from 9ns to 8.5ns will be allowed to have a 9ns maxi- mum. 39. Half-clock output parameters must be derated by the actual tERR10per and tJITdty when input clock jitter is present. This results in each parameter becoming larger. The parame- ters tADC (MIN) and tAOF (MIN) are each required to be derated by subtracting both tERR10per (MAX) and tJITdty (MAX). The parameters tADC (MAX) and tAOF (MAX) are required to be derated by subtracting both tERR10per (MAX) and tJITdty (MAX). 40. ODT turn-off time minimum is when the device starts to turn off ODT resistance. ODT turn-off time maximum is when the DRAM buffer is in High-Z. The ODT reference load is shown in Figure 22 (page 57). This output load is used for ODT timings (see Figure 29 (page 68)). 41. Pulse width of a input signal is defined as the width between the first crossing of V REF(DC) and the consecutive crossing of VREF(DC). 42. Should the clock rate be larger than tRFC (MIN), an AUTO REFRESH command should have at least one NOP command between it and another AUTO REFRESH command. Ad- ditionally, if the clock rate is slower than 40ns (25 MHz), all REFRESH commands should be followed by a PRECHARGE ALL command. 43. DRAM devices should be evenly addressed when being accessed. Disproportionate ac- cesses to a particular row address may result in a reduction of REFRESH characteristics or product lifetime. 44. When two V IH(AC) values (and two corresponding VIL(AC) values) are listed for a specific speed bin, the user may choose either value for the input AC level. Whichever value is used, the associated setup time for that AC level must also be used. Additionally, one V IH(AC) value may be used for address/command inputs and the other VIH(AC) value may be used for data inputs. For example, for DDR3-800, two input AC levels are defined: VIH(AC175),min and VIH(AC150),min (corresponding VIL(AC175),min and VIL(AC150),min). For DDR3-800, the address/ command inputs must use either VIH(AC175),min with tIS(AC175) of 200ps or VIH(AC150),min with tIS(AC150) of 350ps; independently, the data inputs must use either VIH(AC175),min with tDS(AC175) of 75ps or VIH(AC150),min with tDS(AC150) of 125ps. 2Gb: x4, x8, x16 DDR3 SDRAM Electrical Characteristics and AC Operating Conditions PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 85 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Electrical Characteristics and AC Operating Conditions Table 57: Electrical Characteristics and AC Operating Conditions for Speed Extensions Notes 1–8 apply to the entire table Parameter Symbol DDR3-1866 DDR3-2133 Unit NotesMin Max Min Max Clock Timing Clock period average: DLL disable mode TC = 0°C to 85°C tCK (DLL_DIS) 8 7800 8 7800 ns 9, 42 TC = >85°C to 95°C 8 3900 8 3900 ns 42 Clock period average: DLL enable mode tCK (AVG) See Speed Bin Tables (page 71) for tCK range allowed ns 10, 11 High pulse width average tCH (AVG) 0.47 0.53 0.47 0.53 CK 12 Low pulse width average tCL (AVG) 0.47 0.53 0.47 0.53 CK 12 Clock period jitter DLL locked tJITper –60 60 –50 50 ps 13 DLL locking tJITper,lck –50 50 –40 40 ps 13 Clock absolute period tCK (ABS) MIN = tCK (AVG) MIN + tJITper MIN; MAX = tCK (AVG) MAX + tJITper MAX ps Clock absolute high pulse width tCH (ABS) 0.43 – 0.43 – tCK (AVG) Clock absolute low pulse width tCL (ABS) 0.43 – 0.43 – tCK (AVG) Cycle-to-cycle jitter DLL locked tJITcc 120 120 ps 16 DLL locking tJITcc,lck 100 100 ps 16 2Gb: x4, x8, x16 DDR3 SDRAM Electrical Characteristics and AC Operating Conditions PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 86 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Table 57: Electrical Characteristics and AC Operating Conditions for Speed Extensions (Continued) Notes 1–8 apply to the entire table Parameter Symbol DDR3-1866 DDR3-2133 Unit NotesMin Max Min Max Cumulative error across 2 cycles tERR2per –88 88 -74 74 ps 17 3 cycles tERR3per –105 105 -87 87 ps 17 4 cycles tERR4per –117 117 -97 97 ps 17 5 cycles tERR5per –126 126 -105 105 ps 17 6 cycles tERR6per –133 133 -111 111 ps 17 7 cycles tERR7per –139 139 -116 116 ps 17 8 cycles tERR8per –145 145 -121 121 ps 17 9 cycles tERR9per –150 150 -125 125 ps 17 10 cycles tERR10per –154 154 -128 128 ps 17 11 cycles tERR11per –158 158 -132 132 ps 17 12 cycles tERR12per –161 161 -134 134 ps 17 cycles tERRnper tERRnper MIN = (1 + 0.68ln[n]) × tJITper MIN tERRnper MAX = (1 + 0.68ln[n]) × tJITper MAX ps DQ Input Timing Data setup time to DQS, DQS# Base (specification) @ 2 V/ns tDS (AC135) 68 – 53 – ps 18, 19 VREF @ 2 V/ns 135 – 120.5 – ps 19, 20 Data hold time from DQS, DQS# Base (specification) @ 2 V/ns tDH (DC100) 70 – 55 – ps 18, 19 VREF @ 2 V/ns 120 – 105 – ps 19, 20 Minimum data pulse width tDIPW 320 – 280 – ps 41 DQ Output Timing DQS, DQS# to DQ skew, per access tDQSQ – 85 – 75 ps DQ output hold time from DQS, DQS# tQH 0.38 – 0.38 – tCK (AVG) DQ Low-Z time from CK, CK# tLZDQ –390 195 –360 180 ps 22, 23 DQ High-Z time from CK, CK# tHZDQ – 195 – 180 ps 22, 23 DQ Strobe Input Timing DQS, DQS# rising to CK, CK# rising tDQSS –0.27 0.27 –0.27 0.27 CK 25 2Gb: x4, x8, x16 DDR3 SDRAM Electrical Characteristics and AC Operating Conditions PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 87 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Table 57: Electrical Characteristics and AC Operating Conditions for Speed Extensions (Continued) Notes 1–8 apply to the entire table Parameter Symbol DDR3-1866 DDR3-2133 Unit NotesMin Max Min Max DQS, DQS# differential input low pulse width tDQSL 0.45 0.55 0.45 0.55 CK DQS, DQS# differential input high pulse width tDQSH 0.45 0.55 0.45 0.55 CK DQS, DQS# falling setup to CK, CK# rising tDSS 0.18 – 0.18 – CK 25 DQS, DQS# falling hold from CK, CK# rising tDSH 0.18 – 0.18 – CK 25 DQS, DQS# differential WRITE preamble tWPRE 0.9 – 0.9 – CK DQS, DQS# differential WRITE postamble tWPST 0.3 – 0.3 – CK DQ Strobe Output Timing DQS, DQS# rising to/from rising CK, CK# tDQSCK –195 195 –180 180 ps 23 DQS, DQS# rising to/from rising CK, CK# when DLL is disabled tDQSCK (DLL_DIS) 1 10 1 10 ns 26 DQS, DQS# differential output high time tQSH 0.40 – 0.40 – CK 21 DQS, DQS# differential output low time tQSL 0.40 – 0.40 – CK 21 DQS, DQS# Low-Z time (RL - 1) tLZDQS –390 195 –360 180 ps 22, 23 DQS, DQS# High-Z time (RL + BL/2) tHZDQS – 195 – 180 ps 22, 23 DQS, DQS# differential READ preamble tRPRE 0.9 Note 24 0.9 Note 24 CK 23, 24 DQS, DQS# differential READ postamble tRPST 0.3 Note 27 0.3 Note 27 CK 23, 27 Command and Address Timing DLL locking time tDLLK 512 – 512 – CK 28 CTRL, CMD, ADDR setup to CK,CK# Base (specification) tIS (AC135) 65 – 60 – ps 29, 30, VREF @ 1 V/ns 200 – 195 – ps 20, 30 CTRL, CMD, ADDR setup to CK,CK# Base (specification) tIS (AC125) 150 – 135 – ps 29, 30, VREF @ 1 V/ns 275 – 260 – ps 20, 30 CTRL, CMD, ADDR hold from CK,CK# Base (specification) tIH (DC100) 100 – 95 – ps 29, 30 VREF @ 1 V/ns 200 – 195 – ps 20, 30 Minimum CTRL, CMD, ADDR pulse width tIPW 535 – 470 – ps 41 ACTIVATE to internal READ or WRITE delay tRCD See Speed Bin Tables (page 71) for tRCD ns 31 PRECHARGE command period tRP See Speed Bin Tables (page 71) for tRP ns 31 ACTIVATE-to-PRECHARGE command period tRAS See Speed Bin Tables (page 71) for tRAS ns 31, 32 2Gb: x4, x8, x16 DDR3 SDRAM Electrical Characteristics and AC Operating Conditions PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 88 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Table 57: Electrical Characteristics and AC Operating Conditions for Speed Extensions (Continued) Notes 1–8 apply to the entire table Parameter Symbol DDR3-1866 DDR3-2133 Unit NotesMin Max Min Max ACTIVATE-to-ACTIVATE command period tRC See Speed Bin Tables (page 71) for tRC ns 31, 43 ACTIVATE-to-ACTIVATE minimum command pe- riod 1KB page size tRRD MIN = greater of 4CK or 5ns CK 31 2KB page size MIN = greater of 4CK or 6ns CK 31 Four ACTIVATE windows 1KB page size tFAW 27 – 25 – ns 31 2KB page size 35 – 35 – ns 31 Write recovery time tWR MIN = 15ns; MAX = n/a ns 31, 32, Delay from start of internal WRITE transac- tion to internal READ command tWTR MIN = greater of 4CK or 7.5ns; MAX = n/a CK 31, 34 READ-to-PRECHARGE time tRTP MIN = greater of 4CK or 7.5ns; MAX = n/a CK 31, 32 CAS#-to-CAS# command delay tCCD MIN = 4CK; MAX = n/a CK Auto precharge write recovery + precharge time tDAL MIN = WR + tRP/tCK (AVG); MAX = n/a CK MODE REGISTER SET command cycle time tMRD MIN = 4CK; MAX = n/a CK MODE REGISTER SET command update delay tMOD MIN = greater of 12CK or 15ns; MAX = n/a CK MULTIPURPOSE REGISTER READ burst end to mode register set for multipurpose register exit tMPRR MIN = 1CK; MAX = n/a CK Calibration Timing ZQCL command: Long calibration time POWER-UP and RE- SET operation tZQinit MIN = n/a MAX = max(512nCK, 640ns) CK Normal operation tZQoper MIN = n/a MAX = max(256nCK, 320ns) CK ZQCS command: Short calibration time MIN = n/a MAX = max(64nCK, 80ns) tZQCS CK Initialization and Reset Timing Exit reset from CKE HIGH to a valid command tXPR MIN = greater of 5CK or tRFC + 10ns; MAX = n/a CK Begin power supply ramp to power supplies stable tVDDPR MIN = n/a; MAX = 200 ms RESET# LOW to power supplies stable tRPS MIN = 0; MAX = 200 ms RESET# LOW to I/O and RTT High-Z tIOZ MIN = n/a; MAX = 20 ns 35 2Gb: x4, x8, x16 DDR3 SDRAM Electrical Characteristics and AC Operating Conditions PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 89 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Table 57: Electrical Characteristics and AC Operating Conditions for Speed Extensions (Continued) Notes 1–8 apply to the entire table Parameter Symbol DDR3-1866 DDR3-2133 Unit NotesMin Max Min Max Refresh Timing REFRESH-to-ACTIVATE or REFRESH command period tRFC – 1Gb MIN = 110; MAX = 70,200 ns tRFC – 2Gb MIN = 160; MAX = 70,200 ns tRFC – 4Gb MIN = 260; MAX = 70,200 ns tRFC – 8Gb MIN = 350; MAX = 70,200 ns Maximum refresh period TC ≤ 85°C – 64 (1X) ms 36 TC > 85°C 32 (2X) ms 36 Maximum average periodic refresh TC ≤ 85°C tREFI 7.8 (64ms/8192) μs 36 TC > 85°C 3.9 (32ms/8192) μs 36 Self Refresh Timing Exit self refresh to commands not requiring a locked DLL tXS MIN = greater of 5CK or tRFC + 10ns; MAX = n/a CK Exit self refresh to commands requiring a locked DLL tXSDLL MIN = tDLLK (MIN); MAX = n/a CK 28 Minimum CKE low pulse width for self re- fresh entry to self refresh exit timing tCKESR MIN = tCKE (MIN) + CK; MAX = n/a CK Valid clocks after self refresh entry or power- down entry tCKSRE MIN = greater of 5CK or 10ns; MAX = n/a CK Valid clocks before self refresh exit, power-down exit, or reset exit tCKSRX MIN = greater of 5CK or 10ns; MAX = n/a CK Power-Down Timing CKE MIN pulse width tCKE (MIN) Greater of 3CK or 5ns CK Command pass disable delay tCPDED MIN = 2; MAX = n/a CK Power-down entry to power-down exit tim- ing tPD MIN = tCKE (MIN); MAX = 9 * tREFI CK Begin power-down period prior to CKE registered HIGH tANPD WL - 1CK CK Power-down entry period: ODT either synchronous or asynchronous PDE Greater of tANPD or tRFC - REFRESH command to CKE LOW time CK Power-down exit period: ODT either synchronous or asynchronous PDX tANPD + tXPDLL CK 2Gb: x4, x8, x16 DDR3 SDRAM Electrical Characteristics and AC Operating Conditions PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 90 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Table 57: Electrical Characteristics and AC Operating Conditions for Speed Extensions (Continued) Notes 1–8 apply to the entire table Parameter Symbol DDR3-1866 DDR3-2133 Unit NotesMin Max Min Max Power-Down Entry Minimum Timing ACTIVATE command to power-down entry tACTPDEN MIN = 2 CK PRECHARGE/PRECHARGE ALL command to power-down entry tPRPDEN MIN = 2 CK REFRESH command to power-down entry tREFPDEN MIN = 2 CK 37 MRS command to power-down entry tMRSPDEN MIN = tMOD (MIN) CK READ/READ with auto precharge command to power-down entry tRDPDEN MIN = RL + 4 + 1 CK WRITE command to power-down entry BL8 (OTF, MRS) BC4OTF tWRPDEN MIN = WL + 4 + tWR/tCK (AVG) CK BC4MRS tWRPDEN MIN = WL + 2 + tWR/tCK (AVG) CK WRITE with auto pre- charge command to power-down entry BL8 (OTF, MRS) BC4OTF tWRAP- DEN MIN = WL + 4 + WR + 1 CK BC4MRS tWRAP- DEN MIN = WL + 2 + WR + 1 CK Power-Down Exit Timing DLL on, any valid command, or DLL off to commands not requiring locked DLL tXP MIN = greater of 3CK or 6ns; MAX = n/a CK Precharge power-down with DLL off to commands requiring a locked DLL tXPDLL MIN = greater of 10CK or 24ns; MAX = n/a CK 28 ODT Timing RTT synchronous turn-on delay ODTL on CWL + AL - 2CK CK 38 RTT synchronous turn-off delay ODTL off CWL + AL - 2CK CK 40 RTT turn-on from ODTL on reference tAON –195 195 –180 180 ps 23, 38 RTT turn-off from ODTL off reference tAOF 0.3 0.7 0.3 0.7 CK 39, 40 Asynchronous RTT turn-on delay (power-down with DLL off) tAONPD MIN = 2; MAX = 8.5 ns 38 Asynchronous RTT turn-off delay (power-down with DLL off) tAOFPD MIN = 2; MAX = 8.5 ns 40 ODT HIGH time with WRITE command and BL8 ODTH8 MIN = 6; MAX = n/a CK 2Gb: x4, x8, x16 DDR3 SDRAM Electrical Characteristics and AC Operating Conditions PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 91 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Table 57: Electrical Characteristics and AC Operating Conditions for Speed Extensions (Continued) Notes 1–8 apply to the entire table Parameter Symbol DDR3-1866 DDR3-2133 Unit NotesMin Max Min Max ODT HIGH time without WRITE command or with WRITE command and BC4 ODTH4 MIN = 4; MAX = n/a CK Dynamic ODT Timing RTT,nom-to-RTT(WR) change skew ODTLcnw WL - 2CK CK RTT(WR)-to-RTT,nom change skew - BC4 ODTLcwn4 4CK + ODTLoff CK RTT(WR)-to-RTT,nom change skew - BL8 ODTLcwn8 6CK + ODTLoff CK RTT dynamic change skew tADC 0.3 0.7 0.3 0.7 CK 39 Write Leveling Timing First DQS, DQS# rising edge tWLMRD 40 – 40 – CK DQS, DQS# delay tWLDQSEN 25 – 25 – CK Write leveling setup from rising CK, CK# crossing to rising DQS, DQS# crossing tWLS 140 – 125 – ps Write leveling hold from rising DQS, DQS# crossing to rising CK, CK# crossing tWLH 140 – 125 – ps Write leveling output delay tWLO 0 7.5 0 7 ns Write leveling output error tWLOE 0 2 0 2 ns 2Gb: x4, x8, x16 DDR3 SDRAM Electrical Characteristics and AC Operating Conditions PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 92 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Notes: 1. AC timing parameters are valid from specified T C MIN to TC MAX values. 2. All voltages are referenced to V SS. 3. Output timings are only valid for R ON34 output buffer selection. 4. The unit tCK (AVG) represents the actual tCK (AVG) of the input clock under operation. The unit CK represents one clock cycle of the input clock, counting the actual clock edges. 5. AC timing and I DD tests may use a VIL-to-VIH swing of up to 900mV in the test environ- ment, but input timing is still referenced to VREF (except tIS, tIH, tDS, and tDH use the AC/DC trip points and CK, CK# and DQS, DQS# use their crossing points). The minimum slew rate for the input signals used to test the device is 1 V/ns for single-ended inputs (DQs are at 2V/ns for DDR3-1866 and DDR3-2133) and 2 V/ns for differential inputs in the range between V IL(AC) and VIH(AC). 6. All timings that use time-based values (ns, μs, ms) should use tCK (AVG) to determine the correct number of clocks (Table 57 (page 86) uses CK or tCK [AVG] interchangeably). In the case of noninteger results, all minimum limits are to be rounded up to the nearest whole integer, and all maximum limits are to be rounded down to the nearest whole integer. 7. Strobe or DQSdiff refers to the DQS and DQS# differential crossing point when DQS is the rising edge. Clock or CK refers to the CK and CK# differential crossing point when CK is the rising edge. 8. This output load is used for all AC timing (except ODT reference timing) and slew rates. The actual test load may be different. The output signal voltage reference point is V DDQ/2 for single-ended signals and the crossing point for differential signals (see Fig- ure 29 (page 68)). 9. When operating in DLL disable mode, Micron does not warrant compliance with normal mode timings or functionality. 10. The clock’s tCK (AVG) is the average clock over any 200 consecutive clocks and tCK (AVG) MIN is the smallest clock rate allowed, with the exception of a deviation due to clock jitter. Input clock jitter is allowed provided it does not exceed values specified and must be of a random Gaussian distribution in nature. 11. Spread spectrum is not included in the jitter specification values. However, the input clock can accommodate spread-spectrum at a sweep rate in the range of 20–60 kHz with an additional 1% of tCK (AVG) as a long-term jitter component; however, the spread spectrum may not use a clock rate below tCK (AVG) MIN. 12. The clock’s tCH (AVG) and tCL (AVG) are the average half clock period over any 200 con- secutive clocks and is the smallest clock half period allowed, with the exception of a de- viation due to clock jitter. Input clock jitter is allowed provided it does not exceed values specified and must be of a random Gaussian distribution in nature. 13. The period jitter ( tJITper) is the maximum deviation in the clock period from the average or nominal clock. It is allowed in either the positive or negative direction. 14. tCH (ABS) is the absolute instantaneous clock high pulse width as measured from one rising edge to the following falling edge. 15. tCL (ABS) is the absolute instantaneous clock low pulse width as measured from one fall- ing edge to the following rising edge. 16. The cycle-to-cycle jitter tJITcc is the amount the clock period can deviate from one cycle to the next. It is important to keep cycle-to-cycle jitter at a minimum during the DLL locking time. 17. The cumulative jitter error tERRnper, where n is the number of clocks between 2 and 50, is the amount of clock time allowed to accumulate consecutively away from the average clock over n number of clock cycles. 18. tDS (base) and tDH (base) values are for a single-ended 1 V/ns slew rate DQs (DQs are at 2V/ns for DDR3-1866 and DDR3-2133) and 2 V/ns slew rate differential DQS, DQS#. 2Gb: x4, x8, x16 DDR3 SDRAM Electrical Characteristics and AC Operating Conditions PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 93 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

1. These parameters are measured from a data signal (DM, DQ0, DQ1, and so forth) transi- tion edge to its respective data strobe signal (DQS, DQS#) crossing. 20. The setup and hold times are listed converting the base specification values (to which derating tables apply) to VREF when the slew rate is 1 V/ns (DQs are at 2V/ns for DDR3-1866 and DDR3-2133). These values, with a slew rate of 1 V/ns (DQs are at 2V/ns for DDR3-1866 and DDR3-2133), are for reference only. 21. When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJITper (larger of tJITper (MIN) or tJITper (MAX) of the input clock (output deratings are relative to the SDRAM input clock). 22. Single-ended signal parameter. 23. The DRAM output timing is aligned to the nominal or average clock. Most output pa- rameters must be derated by the actual jitter error when input clock jitter is present, even when within specification. This results in each parameter becoming larger. The fol- lowing parameters are required to be derated by subtracting tERR10per (MAX): tDQSCK (MIN), tLZDQS (MIN), tLZDQ (MIN), and tAON (MIN). The following parameters are re- quired to be derated by subtracting tERR10per (MIN): tDQSCK (MAX), tHZ (MAX), tLZDQS (MAX), tLZDQ (MAX), and tAON (MAX). The parameter tRPRE (MIN) is derated by sub- tracting tJITper (MAX), while tRPRE (MAX) is derated by subtracting tJITper (MIN). 24. The maximum preamble is bound by tLZDQS (MAX). 25. These parameters are measured from a data strobe signal (DQS, DQS#) crossing to its re- spective clock signal (CK, CK#) crossing. The specification values are not affected by the amount of clock jitter applied, as these are relative to the clock signal crossing. These parameters should be met whether clock jitter is present. 26. The tDQSCK (DLL_DIS) parameter begins CL + AL - 1 cycles after the READ command. 27. The maximum postamble is bound by tHZDQS (MAX). 28. Commands requiring a locked DLL are: READ (and RDAP) and synchronous ODT com- mands. In addition, after any change of latency tXPDLL, timing must be met. 29. tIS (base) and tIH (base) values are for a single-ended 1 V/ns control/command/address slew rate and 2 V/ns CK, CK# differential slew rate. 30. These parameters are measured from a command/address signal transition edge to its respective clock (CK, CK#) signal crossing. The specification values are not affected by the amount of clock jitter applied as the setup and hold times are relative to the clock signal crossing that latches the command/address. These parameters should be met whether clock jitter is present. 31. For these parameters, the DDR3 SDRAM device supports tnPARAM (nCK) = RU(tPARAM [ns]/tCK[AVG] [ns]), assuming all input clock jitter specifications are satisfied. For exam- ple, the device will support tnRP (nCK) = RU(tRP/tCK[AVG]) if all input clock jitter specifi- cations are met. This means that for DDR3-800 6-6-6, of which tRP = 5ns, the device will support tnRP = RU(tRP/tCK[AVG]) = 6 as long as the input clock jitter specifications are met. That is, the PRECHARGE command at T0 and the ACTIVATE command at T0 + 6 are valid even if six clocks are less than 15ns due to input clock jitter. 32. During READs and WRITEs with auto precharge, the DDR3 SDRAM will hold off the in- ternal PRECHARGE command until tRAS (MIN) has been satisfied. 33. When operating in DLL disable mode, the greater of 4CK or 15ns is satisfied for tWR. 34. The start of the write recovery time is defined as follows:

• For BL8 (fixed by MRS or OTF): Rising clock edge four clock cycles after WL
• For BC4 (OTF): Rising clock edge four clock cycles after WL
• For BC4 (fixed by MRS): Rising clock edge two clock cycles after WL 35. RESET# should be LOW as soon as power starts to ramp to ensure the outputs are in High-Z. Until RESET# is LOW, the outputs are at risk of driving and could result in exces- sive current, depending on bus activity. 2Gb: x4, x8, x16 DDR3 SDRAM Electrical Characteristics and AC Operating Conditions PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 94 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

1. The refresh period is 64ms when T C is less than or equal to 85°C. This equates to an aver- age refresh rate of 7.8125μs. However, nine REFRESH commands should be asserted at least once every 70.3μs. When T C is greater than 85°C, the refresh period is 32ms. 37. Although CKE is allowed to be registered LOW after a REFRESH command when tREFPDEN (MIN) is satisfied, there are cases where additional time such as tXPDLL (MIN) is required. 38. ODT turn-on time MIN is when the device leaves High-Z and ODT resistance begins to turn on. ODT turn-on time maximum is when the ODT resistance is fully on. The ODT reference load is shown in Figure 21 (page 54). Designs that were created prior to JEDEC tightening the maximum limit from 9ns to 8.5ns will be allowed to have a 9ns maxi- mum. 39. Half-clock output parameters must be derated by the actual tERR10per and tJITdty when input clock jitter is present. This results in each parameter becoming larger. The parame- ters tADC (MIN) and tAOF (MIN) are each required to be derated by subtracting both tERR10per (MAX) and tJITdty (MAX). The parameters tADC (MAX) and tAOF (MAX) are required to be derated by subtracting both tERR10per (MAX) and tJITdty (MAX). 40. ODT turn-off time minimum is when the device starts to turn off ODT resistance. ODT turn-off time maximum is when the DRAM buffer is in High-Z. The ODT reference load is shown in Figure 22 (page 57). This output load is used for ODT timings (see Figure 29 (page 68)). 41. Pulse width of a input signal is defined as the width between the first crossing of V REF(DC) and the consecutive crossing of VREF(DC). 42. Should the clock rate be larger than tRFC (MIN), an AUTO REFRESH command should have at least one NOP command between it and another AUTO REFRESH command. Ad- ditionally, if the clock rate is slower than 40ns (25 MHz), all REFRESH commands should be followed by a PRECHARGE ALL command. 43. DRAM devices should be evenly addressed when being accessed. Disproportionate ac- cesses to a particular row address may result in a reduction of REFRESH characteristics or product lifetime. 44. When two V IH(AC) values (and two corresponding VIL(AC) values) are listed for a specific speed bin, the user may choose either value for the input AC level. Whichever value is used, the associated setup time for that AC level must also be used. Additionally, one V IH(AC) value may be used for address/command inputs and the other VIH(AC) value may be used for data inputs. For example, for DDR3-800, two input AC levels are defined: VIH(AC175),min and VIH(AC150),min (corresponding VIL(AC175),min and VIL(AC150),min). For DDR3-800, the address/ command inputs must use either VIH(AC175),min with tIS(AC175) of 200ps or VIH(AC150),min with tIS(AC150) of 350ps; independently, the data inputs must use either VIH(AC175),min with tDS(AC175) of 75ps or VIH(AC150),min with tDS(AC150) of 125ps. 2Gb: x4, x8, x16 DDR3 SDRAM Electrical Characteristics and AC Operating Conditions PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 95 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Command and Address Setup, Hold, and Derating The total tIS (setup time) and tIH (hold time) required is calculated by adding the data sheet tIS (base) and tIH (base) values (see Table 58; values come from Table 56 (page 76)) to the ΔtIS and ΔtIH derating values (see Table 59 (page 97) and Table 60 (page 97)), respectively. Example: tIS (total setup time) = tIS (base) + ΔtIS. For a valid transition, the input signal has to remain above/below VIH(AC)/VIL(AC) for some time tVAC (see Table 60 (page 97)). Although the total setup time for slow slew rates might be negative (for example, a valid input signal will not have reached VIH(AC)/VIL(AC) at the time of the rising clock transi- tion), a valid input signal is still required to complete the transition and to reach V IH(AC)/VIL(AC) (see Figure 13 (page 46) for input signal requirements). For slew rates that fall between the values listed in Table 60 (page 97) and Table 63 (page 99), the derat- ing values may be obtained by linear interpolation. Setup ( tIS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VREF(DC) and the first crossing of VIH(AC)min. Setup (tIS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VREF(DC) and the first crossing of VIL(AC)max. If the actual signal is always earlier than the nominal slew rate line between the shaded VREF(DC)-to-AC region, use the nominal slew rate for derat- ing value (see Figure 32 (page 100)). If the actual signal is later than the nominal slew rate line anywhere between the shaded V REF(DC)-to-AC region, the slew rate of a tangent line to the actual signal from the AC level to the DC level is used for derating value (see Figure 34 (page 102)). Hold ( tIH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(DC)max and the first crossing of VREF(DC). Hold (tIH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VIH(DC)min and the first crossing of VREF(DC). If the actual signal is always later than the nominal slew rate line between the shaded DC-to-VREF(DC) region, use the nominal slew rate for derat- ing value (see Figure 33 (page 101)). If the actual signal is earlier than the nominal slew rate line anywhere between the shaded DC-to-V REF(DC) region, the slew rate of a tangent line to the actual signal from the DC level to the VREF(DC) level is used for derating value (see Figure 35 (page 103)). Table 58: Command and Address Setup and Hold Values Referenced – AC/DC-Based Symbol 800 1066 1333 1600 1866 2133 Unit Reference tIS(base, AC175) 200 125 65 45 – – ps V IH(AC)/VIL(AC) tIS(base, AC150) 350 275 190 170 – – ps V IH(AC)/VIL(AC) tIS(base, AC135) – – – – 65 60 ps V IH(AC)/VIL(AC) tIS(base, AC125) – – – – 150 135 ps V IH(AC)/VIL(AC) tIH(base, DC100) 275 200 140 120 100 95 ps V IH(DC)/VIL(DC) 2Gb: x4, x8, x16 DDR3 SDRAM Command and Address Setup, Hold, and Derating PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 96 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Table 59: Derating Values for tIS/tIH – AC175/DC100-Based ΔΔtIS, ΔtIH Derating (ps) – AC/DC-Based AC175 Threshold: VIH(AC) = VREF(DC) + 175mV, VIL(AC) = VREF(DC) - 175mV CMD/ ADDR Slew Rate V/ns CK, CK# Differential Slew Rate ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIH ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH 2.0 88 50 88 50 88 50 96 58 104 66 112 74 120 84 128 100 1.5 59 34 59 34 59 34 67 42 75 50 83 58 91 68 99 84 1.0 0 0 0 0 00 8 8 16 16 24 24 32 34 40 50 0.9 –2 –4 –2 –4 –2 –4 6 4 14 12 22 20 30 30 38 46 0.8 –6 –10 –6 –10 –6 –10 2 –2 10 6 18 14 26 24 34 40 0.7 –11 –16 –11 –16 –11 –16 –3 –8 5 0 13 8 21 18 29 34 0.6 –17 –26 –17 –26 –17 –26 –9 –18 –1 –10 7 –2 15 8 23 24 Table 60: Derating Values for tIS/tIH – AC150/DC100-Based ΔtIS, ΔtIH Derating (ps) – AC/DC-Based AC150 Threshold: VIH(AC) = VREF(DC) + 150mV, VIL(AC) = VREF(DC) - 150mV CMD/ ADDR Slew Rate V/ns CK, CK# Differential Slew Rate ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIH ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH 2.0 75 50 75 50 75 50 83 58 91 66 99 74 107 84 115 100 1.5 50 34 50 34 50 34 58 42 66 50 74 58 82 68 90 84 1.0 0 0 0 0 00 8 8 16 16 24 24 32 34 40 50 0.9 0 –4 0 –4 0– 4 8 4 16 12 24 20 32 30 40 46 0.8 0 –10 0 –10 0 –10 8 –2 16 6 24 14 32 24 40 40 0.7 0 –16 0 –16 0 –16 8 –8 16 0 24 8 32 18 40 34 0.6 –1 –26 –1 –26 –1 –26 7 –18 15 –10 23 –2 31 8 39 24 0.5 –10 –40 –10 –40 –10 –40 –2 –32 6 –24 14 –16 22 –6 30 10 2Gb: x4, x8, x16 DDR3 SDRAM Command and Address Setup, Hold, and Derating PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 97 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Table 61: Derating Values for tIS/tIH – AC135/DC100-Based ΔΔtIS, ΔtIH Derating (ps) – AC/DC-Based AC135 Threshold: VIH(AC) = VREF(DC) + 135mV, VIL(AC) = VREF(DC) - 135mV CMD/ ADDR Slew Rate V/ns CK, CK# Differential Slew Rate ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIH ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH 2.0 68 50 68 50 68 50 76 58 84 66 92 74 100 84 108 100 1.5 45 34 45 34 45 34 53 42 61 50 69 58 77 68 85 84 1.0 0 0 0 0 00 8 8 16 16 24 24 32 34 40 50 0.9 2 –4 2 –4 2– 4 1 0 4 1 81 22 62 03 43 04 24 6 0.8 3 –10 3 –10 3 –10 11 –2 19 6 27 14 35 24 43 40 0.7 6 –16 6 –16 6 –16 14 –8 22 0 30 8 38 18 46 34 0.6 9 –26 9 –26 9 –26 17 –18 25 –10 33 –2 41 8 49 24 0.5 5 –40 5 –40 5 –40 13 –32 21 –24 29 –16 37 –6 45 10 0.4 –3 –60 –3 –60 –3 –60 6 –52 14 –44 22 –36 30 –26 38 –10 Table 62: Derating Values for tIS/tIH – AC125/DC100-Based ΔtIS, ΔtIH Derating (ps) – AC/DC-Based AC125 Threshold: VIH(AC) = VREF(DC) + 125mV, VIL(AC) = VREF(DC) - 125mV CMD/ ADDR Slew Rate V/ns CK, CK# Differential Slew Rate ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH ΔtIH ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH 2.0 63 50 63 50 63 50 71 58 79 66 87 74 95 84 103 100 1.5 42 34 42 34 42 34 50 42 58 50 66 58 74 68 82 84 1.0 0 0 0 0 00 8 8 16 16 24 24 32 34 40 50 0.9 4 –4 4 –4 4– 4 1 2 4 2 01 22 82 03 63 04 44 6 0.8 6 –10 6 –10 6 –10 14 –2 22 6 30 14 38 24 45 40 0.7 11 –16 11 –16 11 –16 19 –8 27 0 35 8 43 18 51 34 0.6 16 –26 16 –26 16 –26 24 –18 32 –10 40 –2 48 8 56 24 0.5 15 –40 15 –40 15 –40 23 –32 31 –24 39 –16 47 –6 55 10 0.4 13 –60 13 –60 13 –60 21 –52 29 –44 37 –36 45 –26 53 –10 2Gb: x4, x8, x16 DDR3 SDRAM Command and Address Setup, Hold, and Derating PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 98 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Table 63: Minimum Required Time tVAC Above VIH(AC) or Below VIL(AC)for Valid Transition Slew Rate (V/ns) tVAC at 175mV (ps) tVAC at 150mV (ps) tVAC at 135mV (ps) tVAC at 125mV (ps) >2.0 75 175 168 173 2.0 57 170 168 173 1.5 50 167 145 152 1.0 38 130 100 110 0.9 34 113 85 96 0.8 29 93 66 79 0.7 22 66 42 56

0.6 Note 1 30 10 27

0.5 Note 1 Note 1 Note 1 Note 1

<0.5 Note 1 Note 1 Note 1 Note 1 Note: 1. Rising input signal shall become equal to or greater than VIH(ac) level and Falling input signal shall become equal to or less than VIL(ac) level. 2Gb: x4, x8, x16 DDR3 SDRAM Command and Address Setup, Hold, and Derating PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 99 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Figure 32: Nominal Slew Rate and tVAC for tIS (Command and Address – Clock) VSS Setup slew rate rising signal Setup slew rate falling signal ǻTF ǻTR VDDQ VIH(AC)min VIH(DC)min VREF(DC) VIL(DC)max VIL(DC)max Nominal slew rate VREF to AC region tVAC tVAC DQS DQS# CK# CK tIS tIH tIS tIH Nominal slew rate VREF to AC region VREF(DC) - VIL(AC)max ǻTF VIH(AC)min - VREF(DC) ǻTR Note: 1. The clock and the strobe are drawn on different time scales. 2Gb: x4, x8, x16 DDR3 SDRAM Command and Address Setup, Hold, and Derating PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 100 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Figure 33: Nominal Slew Rate for tIH (Command and Address – Clock) VSS Hold slew rate falling signal Hold slew rate rising signal ǻTR ǻTF = = VDDQ VIH(AC)min VIH(DC)min VREF(DC) VIL(DC)max VIL(AC)max Nominal slew rate DC to VREF region DQS DQS# CK# CK tIS tIH tIS tIH DC to VREF region Nominal slew rate VREF(DC) - VIL(DC)max ǻTR VIH(DC)min - VREF(DC) ǻTF Note: 1. The clock and the strobe are drawn on different time scales. 2Gb: x4, x8, x16 DDR3 SDRAM Command and Address Setup, Hold, and Derating PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 101 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Figure 34: Tangent Line for tIS (Command and Address – Clock) VSS Setup slew rate rising signal Setup slew rate falling signal = VDDQ VIH(AC)min VIH(DC)min VREF(DC) VIL(DC)max VIL(DC)max Tangent line VREF to AC region Nominal line tVAC tVAC DQS DQS# CK# CK tIS tIH tIS tIH VREF to AC region Tangent line Nominal line Tangent line (VIH(DC)min - VREF(DC)) Tangent line (VREF(DC) - VIL(AC)max) ǻTR ǻTR ǻTF ǻTF Note: 1. The clock and the strobe are drawn on different time scales. 2Gb: x4, x8, x16 DDR3 SDRAM Command and Address Setup, Hold, and Derating PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 102 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Figure 35: Tangent Line for tIH (Command and Address – Clock) VSS Hold slew rate falling signal = VDDQ VIH(AC)min VIH(DC)min VREF(DC) VIL(DC)max VIL(AC)max Tangen t line DC to VREF region Hold slew rate rising signal = DQS DQS# CK# CK tIS tIH tIS tIH DC to VREF region Tangen t line Nominal line Nominal line Tangent line (VREF(DC) - VIL(DC)max) Tangent line (VIH(DC)min - VREF(DC)) ǻTR ǻTR ǻTR ǻTF Note: 1. The clock and the strobe are drawn on different time scales. 2Gb: x4, x8, x16 DDR3 SDRAM Command and Address Setup, Hold, and Derating PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 103 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Data Setup, Hold, and Derating The total tDS (setup time) and tDH (hold time) required is calculated by adding the data sheet tDS (base) and tDH (base) values (see Table 64 (page 104); values come from Ta- ble 56 (page 76)) to the ΔtDS and ΔtDH derating values (see Table 65 (page 105)), re- spectively. Example: tDS (total setup time) = tDS (base) + ΔtDS. For a valid transition, the input signal has to remain above/below VIH(AC)/VIL(AC) for some time tVAC (see Table 69 (page 108)). Although the total setup time for slow slew rates might be negative (for example, a valid input signal will not have reached VIH(AC)/VIL(AC)) at the time of the rising clock transi- tion), a valid input signal is still required to complete the transition and to reach V IH/VIL(AC). For slew rates that fall between the values listed in Table 66 (page 105), the derating values may obtained by linear interpolation. Setup (tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VREF(DC) and the first crossing of VIH(AC)min. Setup (tDS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VREF(DC) and the first crossing of VIL(AC)max. If the actual signal is always earlier than the nominal slew rate line between the shaded VREF(DC)-to-AC region, use the nominal slew rate for derating value (see Figure 36 (page 109)). If the actual signal is later than the nominal slew rate line anywhere between the shaded V REF(DC)-to-AC region, the slew rate of a tangent line to the actual signal from the AC level to the DC level is used for derating value (see Figure 38 (page 111)). Hold ( tDH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(DC)max and the first crossing of VREF(DC). Hold (tDH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VIH(DC)min and the first crossing of VREF(DC). If the actual signal is always later than the nominal slew rate line between the shaded DC-to-VREF(DC) region, use the nominal slew rate for derating value (see Figure 37 (page 110)). If the actual signal is earlier than the nominal slew rate line anywhere between the shaded DC-to-V REF(DC) region, the slew rate of a tangent line to the actual signal from the DC-to-VREF(DC) region is used for derating val- ue (see Figure 39 (page 112)). Table 64: DDR3 Data Setup and Hold Values at 1 V/ns (DQS, DQS# at 2 V/ns) – AC/DC-Based Symbol 800 1066 1333 1600 1866 2133 Unit Reference tDS (base) AC175 75 25 – – – – ps V IH(AC)/VIL(AC) tDS (base) AC150 125 75 30 10 – – ps V IH(AC)/VIL(AC) tDS (base) AC135 165 115 60 40 68 53 ps V IH(AC)/VIL(AC) tDH (base) DC100 150 100 65 45 70 55 ps V IH(DC)/VIL(DC) Slew Rate Referenced 1 1 1 1 2 2 V/ns 2Gb: x4, x8, x16 DDR3 SDRAM Data Setup, Hold, and Derating PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 104 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Table 65: Derating Values for tDS/tDH – AC175/DC100-Based Shaded cells indicate slew rate combinations not supported ΔΔtDS, ΔtDH Derating (ps) – AC/DC-Based DQ Slew Rate V/ns DQS, DQS# Differential Slew Rate ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH 2.0 88 50 88 50 88 50 1.5 59 34 59 34 59 34 67 42 1 . 0 00000088 1 6 1 6 0.9 –2 –4 –2 –4 6 4 14 12 22 20 0.8 –6 –10 2 –2 10 6 18 14 26 24 0.7 –3 –8 5 0 13 8 21 18 29 34 0.6 –1 –10 7 –2 15 8 23 24 0.5 –11 –16 –2 –6 5 10 Table 66: Derating Values for tDS/tDH – AC150/DC100-Based Shaded cells indicate slew rate combinations not supported ΔtDS, ΔtDH Derating (ps) – AC/DC-Based DQ Slew Rate V/ns DQS, DQS# Differential Slew Rate ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH 2.0 75 50 75 50 75 50 1.5 50 34 50 34 50 34 58 42 1 . 0 00000088 1 6 1 6 0.9 0 –4 0 –4 8 4 16 12 24 20 0.8 0 –10 8 –2 16 6 24 14 32 24 0.7 8 –8 16 0 24 8 32 18 40 34 0.6 15 –10 23 –2 31 8 39 24 0.5 14 –16 22 –6 30 10 0.4 7 –26 15 –10 2Gb: x4, x8, x16 DDR3 SDRAM Data Setup, Hold, and Derating PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 105 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Table 67: Derating Values for tDS/tDH – AC135/DC100-Based at 1V/ns Shaded cells indicate slew rate combinations not supported ΔΔtDS, ΔtDH Derating (ps) – AC/DC-Based DQ Slew Rate V/ns DQS, DQS# Differential Slew Rate ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH 2.0 68 50 68 50 68 50 1.5 45 34 45 34 45 34 53 42 1 . 0 00000088 1 6 1 6 0.9 2 –4 2 –4 10 4 18 12 26 20 0.8 3 –10 11 –2 19 6 27 14 35 24 0.7 14 –8 22 0 30 8 38 18 46 34 0.6 25 –19 33 –2 41 8 49 24 0.5 29 –16 37 –6 45 –10 0.4 30 26 38 –10 2Gb: x4, x8, x16 DDR3 SDRAM Data Setup, Hold, and Derating PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 106 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Table 68: Derating Values for tDS/tDH – AC135/DC100-Based at 2V/ns Shaded cells indicate slew rate combinations not supported ΔΔtDS, ΔtDH Derating (ps) – AC/DC-Based DQ Slew Rate V/ns DQS, DQS# Differential Slew Rate Δ tDS Δ tDH Δ tDS Δ tDH Δ tDS Δ tDH Δ tDS Δ tDH Δ tDS Δ tDH Δ tDS Δ tDH Δ tDS Δ tDH Δ tDS Δ tDH Δ tDS Δ tDH Δ tDS Δ tDH Δ tDS Δ tDH Δ tDS Δ tDH 4.0 34 25 34 25 34 25 3.5 29 21 29 21 29 21 29 21 3.0 23 17 23 17 23 17 23 17 23 17 2.5 14 10 14 10 14 10 14 10 14 10 2.0 0000000000 2Gb: x4, x8, x16 DDR3 SDRAM Data Setup, Hold, and Derating PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 107 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Table 69: Required Minimum Time tVAC Above VIH(AC) (Below VIL(AC)) for Valid DQ Transition Slew Rate (V/ns) tVAC at 175mV (ps) tVAC at 150mV (ps) tVAC at 135mV (ps) DDR3-800/1066 DDR3-800/1066/1333/1600 DDR3-800/1066/1333/1600 DDR3-1866 DDR3-2133 >2.0 75 105 113 93 73 2.0 57 105 113 93 73 1.5 50 80 90 70 50 1.0 38 30 45 25 5 0.9 34 13 30 Note 1 Note 1 0.8 29 Note 1 11 Note 1 Note 1

0.7 Note 1 Note 1 Note 1 Note 1 Note 1

0.6 Note 1 Note 1 Note 1 Note 1 Note 1

0.5 Note 1 Note 1 Note 1 Note 1 Note 1

<0.5 Note 1 Note 1 Note 1 Note 1 Note 1 Note: 1. Rising input signal shall become equal to or greater than VIH(ac) level and Falling input signal shall become equal to or less than VIL(ac) level. 2Gb: x4, x8, x16 DDR3 SDRAM Data Setup, Hold, and Derating PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 108 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Figure 36: Nominal Slew Rate and tVAC for tDS (DQ – Strobe) VSS Setup slew rate rising signal Setup slew rate falling signal ǻTF ǻTR = = VDDQ VIH(AC)min VIH(DC)min VREF(DC) VIL(DC)max VIL(AC)max Nominal slew rate VREF to AC region tVAC tVAC tDHtDS DQS DQS# tDHtDS CK# CK VREF to AC region Nominal slew rate VIH(AC)min - VREF(DC) ǻTR VREF(DC) - VIL(AC)max ǻTF Note: 1. The clock and the strobe are drawn on different time scales. 2Gb: x4, x8, x16 DDR3 SDRAM Data Setup, Hold, and Derating PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 109 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Figure 37: Nominal Slew Rate for tDH (DQ – Strobe) VSS Hold slew rate falling signal Hold slew rate rising signal == VDDQ VIH(AC)min VIH(DC)min VREF(DC) VIL(DC)max VIL(AC)max Nominal slew rateDC to VREF region tDHtDS DQS DQS# tDHtDS CK# CK DC to VREF region Nominal slew rate VREF(DC) - VIL(DC)max VIL(DC)min - VREF(DC) ǻTR ǻTF ǻTFǻTR Note: 1. The clock and the strobe are drawn on different time scales. 2Gb: x4, x8, x16 DDR3 SDRAM Data Setup, Hold, and Derating PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 110 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Figure 38: Tangent Line for tDS (DQ – Strobe) VSS Setup slew rate rising signal Setup slew rate falling signal = VDDQ VIH(AC)min VIH(DC)min VREF(DC) VIL(DC)max VIL(AC)max Tangent line VREF to AC region Nominal line tVAC tVAC tDHtDS DQS DQS# tDHtDS CK# CK VREF to AC region Tangent line Nominal line Tangent line (VREF(DC) - VIL(AC)max) Tangent line (VIH(AC)min - VREF(DC)) ǻTR ǻTR ǻTF ǻTF Note: 1. The clock and the strobe are drawn on different time scales. 2Gb: x4, x8, x16 DDR3 SDRAM Data Setup, Hold, and Derating PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 111 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Figure 39: Tangent Line for tDH (DQ – Strobe) VSS Hold slew rate falling signal ǻTFǻTR VDDQ VIH(AC)min VIH(DC)min VREF(DC) VIL(DC)max VIL(AC)max Tangent line DC to VREF region Hold slew rate rising signal = DQS DQS# CK# CK DC to VREF region Tangent line Nominal line Nominal line Tangent line (VIH(DC)min - VREF(DC)) ǻTF Tangent line (VREF(DC) - VIL(DC)max) ǻTR tDS tDH tDS tDH Note: 1. The clock and the strobe are drawn on different time scales. 2Gb: x4, x8, x16 DDR3 SDRAM Data Setup, Hold, and Derating PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 112 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Commands – Truth Tables Table 70: Truth Table – Command Notes 1–5 apply to the entire table Function Symbol CKE CS# RAS# CAS# WE# BA [2:0] An A12 A10 A[11, 9:0] Notes Prev. Cycle Next Cycle MODE REGISTER SET MRS H H L L L L BA OP code REFRESH REF H H L L L H V V V V V Self refresh entry SRE H L L L L H V V V V V 6 Self refresh exit SRX L H H V V V V V V V V 6, 7 LH HH Single-bank PRECHARGE PRE H H L L H L BA V V L V PRECHARGE all banks PREA H H L L H L V V H V Bank ACTIVATE ACT H H L L H H BA Row address (RA) WRITE BL8MRS, BC4MRS WR H H L H L L BA RFU V L CA 8 BC4OTF WRS4 H H L H L L BA RFU L L CA 8 BL8OTF WRS8 H H L H L L BA RFU H L CA 8 WRITE with auto precharge BL8MRS, BC4MRS WRAP H H L H L L BA RFU V H CA 8 BC4OTF WRAPS4 H H L H L L BA RFU L H CA 8 BL8OTF WRAPS8 H H L H L L BA RFU H H CA 8 READ BL8MRS, BC4MRS RD H H L H L H BA RFU V L CA 8 BC4OTF RDS4 H H L H L H BA RFU L L CA 8 BL8OTF RDS8 H H L H L H BA RFU H L CA 8 READ with auto precharge BL8MRS, BC4MRS RDAP H H L H L H BA RFU V H CA 8 BC4OTF RDAPS4 H H L H L H BA RFU L H CA 8 BL8OTF RDAPS8 H H L H L H BA RFU H H CA 8 NO OPERATION NOP H H H H H V V V V V 9 Device DESELECTED DES H H H X X X X X X X X 10 Power-down entry PDE H L L H H H V V V V V 6 HV V V Power-down exit PDX L H L H H H V V V V V 6, 11 HV V V ZQ CALIBRATION LONG ZQCL H H L H H L X X X H X 12 ZQ CALIBRATION SHORT ZQCS H H L H H L X X X L X Notes: 1. Commands are defined by the states of CS#, RAS#, CAS#, WE#, and CKE at the rising edge of the clock. The MSB of BA, RA, and CA are device-, density-, and configuration- dependent. 2Gb: x4, x8, x16 DDR3 SDRAM Commands – Truth Tables PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 113 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

1. RESET# is enabled LOW and used only for asynchronous reset. Thus, RESET# must be held HIGH during any normal operation. 3. The state of ODT does not affect the states described in this table. 4. Operations apply to the bank defined by the bank address. For MRS, BA selects one of four mode registers. 5. “V” means “H” or “L” (a defined logic level), and “X” means “Don’t Care.” 6. See Table 71 (page 115) for additional information on CKE transition. 7. Self refresh exit is asynchronous. 8. Burst READs or WRITEs cannot be terminated or interrupted. MRS (fixed) and OTF BL/BC are defined in MR0. 9. The purpose of the NOP command is to prevent the DRAM from registering any unwan- ted commands. A NOP will not terminate an operation that is executing. 10. The DES and NOP commands perform similarly. 11. The power-down mode does not perform any REFRESH operations. 12. ZQ CALIBRATION LONG is used for either ZQinit (first ZQCL command during initializa- tion) or ZQoper (ZQCL command after initialization). 2Gb: x4, x8, x16 DDR3 SDRAM Commands – Truth Tables PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 114 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Table 71: Truth Table – CKE Notes 1–2 apply to the entire table; see Table 70 (page 113) for additional command details Current State3 CKE Command5 (RAS#, CAS#, WE#, CS#) Action5 Notes Previous Cycle4 (n - 1) Present Cycle4 (n) Power-down L L “Don’t Care” Maintain power-down L H DES or NOP Power-down exit Self refresh L L “Don’t Care” Maintain self refresh L H DES or NOP Self refresh exit Bank(s) active H L DES or NOP Active power-down entry Reading H L DES or NOP Power-down entry Writing H L DES or NOP Power-down entry Precharging H L DES or NOP Power-down entry Refreshing H L DES or NOP Precharge power-down entry All banks idle H L DES or NOP Precharge power-down entry 6 H L REFRESH Self refresh Notes: 1. All states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document. 2. tCKE (MIN) means CKE must be registered at multiple consecutive positive clock edges. CKE must remain at the valid input level the entire time it takes to achieve the required number of registration clocks. Thus, after any CKE transition, CKE may not transition from its valid level during the time period of tIS + tCKE (MIN) + tIH. 3. Current state = The state of the DRAM immediately prior to clock edge n. 4. CKE ( n) is the logic state of CKE at clock edge n; CKE (n - 1) was the state of CKE at the previous clock edge. 5. COMMAND is the command registered at the clock edge (must be a legal command as defined in Table 70 (page 113)). Action is a result of COMMAND. ODT does not affect the states described in this table and is not listed. 6. Idle state = All banks are closed, no data bursts are in progress, CKE is HIGH, and all tim- ings from previous operations are satisfied. All self refresh exit and power-down exit pa- rameters are also satisfied. 2Gb: x4, x8, x16 DDR3 SDRAM Commands – Truth Tables PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 115 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

The DESELT (DES) command (CS# HIGH) prevents new commands from being execu- ted by the DRAM. Operations already in progress are not affected. NO OPERATION The NO OPERATION (NOP) command (CS# LOW) prevents unwanted commands from being registered during idle or wait states. Operations already in progress are not affec- ted. ZQ CALIBRATION LONG The ZQ CALIBRATION LONG (ZQCL) command is used to perform the initial calibra- tion during a power-up initialization and reset sequence (see Figure 48 (page 132)). This command may be issued at any time by the controller, depending on the system environment. The ZQCL command triggers the calibration engine inside the DRAM. Af- ter calibration is achieved, the calibrated values are transferred from the calibration en- gine to the DRAM I/O, which are reflected as updated R ON and ODT values. The DRAM is allowed a timing window defined by either tZQinit or tZQoper to perform a full calibration and transfer of values. When ZQCL is issued during the initialization sequence, the timing parameter tZQinit must be satisfied. When initialization is com- plete, subsequent ZQCL commands require the timing parameter tZQoper to be satis- fied. ZQ CALIBRATION SHORT The ZQ CALIBRATION SHORT (ZQCS) command is used to perform periodic calibra- tions to account for small voltage and temperature variations. A shorter timing window is provided to perform the reduced calibration and transfer of values as defined by tim- ing parameter tZQCS. A ZQCS command can effectively correct a minimum of 0.5% RON and RTT impedance error within 64 clock cycles, assuming the maximum sensitivities specified in Table 42 (page 63) and Table 43 (page 63). ACTIVATE The ACTIVATE command is used to open (or activate) a row in a particular bank for a subsequent access. The value on the BA[2:0] inputs selects the bank, and the address provided on inputs A[n:0] selects the row. This row remains open (or active) for accesses until a PRECHARGE command is issued to that bank. A PRECHARGE command must be issued before opening a different row in the same bank. READ The READ command is used to initiate a burst read access to an active row. The address provided on inputs A[2:0] selects the starting column address, depending on the burst length and burst type selected (see Burst Order table for additional information). The value on input A10 determines whether auto precharge is used. If auto precharge is se- lected, the row being accessed will be precharged at the end of the READ burst. If auto 2Gb: x4, x8, x16 DDR3 SDRAM Commands PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 116 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

precharge is not selected, the row will remain open for subsequent accesses. The value on input A12 (if enabled in the mode register) when the READ command is issued de- termines whether BC4 (chop) or BL8 is used. After a READ command is issued, the READ burst may not be interrupted. Table 72: READ Command Summary Function Symbol CKE CS# RAS# CAS# WE# BA [3:0] An A12 A10 A[11, 9:0] Prev. Cycle Next Cycle READ BL8MRS, BC4MRS RD H L H L H BA RFU V L CA BC4OTF RDS4 H L H L H BA RFU L L CA BL8OTF RDS8 H L H L H BA RFU H L CA READ with auto precharge BL8MRS, BC4MRS RDAP H L H L H BA RFU V H CA BC4OTF RDAPS4 H L H L H BA RFU L H CA BL8OTF RDAPS8 H L H L H BA RFU H H CA WRITE The WRITE command is used to initiate a burst write access to an active row. The value on the BA[2:0] inputs selects the bank. The value on input A10 determines whether auto precharge is used. The value on input A12 (if enabled in the MR) when the WRITE com- mand is issued determines whether BC4 (chop) or BL8 is used. Input data appearing on the DQ is written to the memory array subject to the DM input logic level appearing coincident with the data. If a given DM signal is registered LOW, the corresponding data will be written to memory. If the DM signal is registered HIGH, the corresponding data inputs will be ignored and a WRITE will not be executed to that byte/column location. Table 73: WRITE Command Summary Function Symbol CKE CS# RAS# CAS# WE# BA [3:0] An A12 A10 A[11, 9:0] Prev. Cycle Next Cycle WRITE BL8MRS, BC4MRS WR H L H L L BA RFU V L CA BC4OTF WRS4 H L H L L BA RFU L L CA BL8OTF WRS8 H L H L L BA RFU H L CA WRITE with auto precharge BL8MRS, BC4MRS WRAP H L H L L BA RFU V H CA BC4OTF WRAPS4 H L H L L BA RFU L H CA BL8OTF WRAPS8 H L H L L BA RFU H H CA 2Gb: x4, x8, x16 DDR3 SDRAM Commands PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 117 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

The PRECHARGE command is used to de-activate the open row in a particular bank or in all banks. The bank(s) are available for a subsequent row access a specified time (tRP) after the PRECHARGE command is issued, except in the case of concurrent auto pre- charge. A READ or WRITE command to a different bank is allowed during a concurrent auto precharge as long as it does not interrupt the data transfer in the current bank and does not violate any other timing parameters. Input A10 determines whether one or all banks are precharged. In the case where only one bank is precharged, inputs BA[2:0] se- lect the bank; otherwise, BA[2:0] are treated as “Don’t Care.” After a bank is precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued to that bank. A PRECHARGE command is treated as a NOP if there is no open row in that bank (idle state) or if the previously open row is already in the process of precharging. However, the precharge period is determined by the last PRECHARGE command issued to the bank. REFRESH The REFRESH command is used during normal operation of the DRAM and is analo- gous to CAS#-before-RAS# (CBR) refresh or auto refresh. This command is nonpersis- tent, so it must be issued each time a refresh is required. The addressing is generated by the internal refresh controller. This makes the address bits a “Don’t Care” during a RE- FRESH command. The DRAM requires REFRESH cycles at an average interval of 7.8μs (maximum when T C ≤ 85°C or 3.9μs maximum when TC ≤ 95°C). The REFRESH period begins when the REFRESH command is registered and ends tRFC (MIN) later. To allow for improved efficiency in scheduling and switching between tasks, some flexi- bility in the absolute refresh interval is provided. A maximum of eight REFRESH com- mands can be posted to any given DRAM, meaning that the maximum absolute interval between any REFRESH command and the next REFRESH command is nine times the maximum average interval refresh rate. Self refresh may be entered with up to eight RE- FRESH commands being posted. After exiting self refresh (when entered with posted REFRESH commands), additional posting of REFRESH commands is allowed to the ex- tent that the maximum number of cumulative posted REFRESH commands (both pre- and post-self refresh) does not exceed eight REFRESH commands. At any given time, a maximum of 16 REFRESH commands can be issued within 2 x tREFI. 2Gb: x4, x8, x16 DDR3 SDRAM Commands PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 118 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Figure 40: Refresh Mode NOP1NOP1 NOP1PRE RA Bank(s)3 BA REF NOP 5 REF2 NOP5 ACTNOP5 One bank All banks tCK tCH tCL RA tRFC2tRP tRFC (MIN) T0 T1 T2 T3 T4 Ta0 Tb0Ta1 Tb1 Tb2 Don’t CareIndicates break in time scale Valid5 Valid5 Valid5 CK CK# Command CKE Address A10 BA[2:0] DQ4 DM4 DQS, DQS#4 Notes: 1. NOP commands are shown for ease of illustration; other valid commands may be possi- ble at these times. CKE must be active during the PRECHARGE, ACTIVATE, and REFRESH commands, but may be inactive at other times (see Power-Down Mode (page 180)). 2. The second REFRESH is not required, but two back-to-back REFRESH commands are shown. 3. “Don’t Care” if A10 is HIGH at this point; however, A10 must be HIGH if more than one bank is active (must precharge all active banks). 4. For operations shown, DM, DQ, and DQS signals are all “Don’t Care”/High-Z. 5. Only NOP and DES commands are allowed after a REFRESH command and until tRFC (MIN) is satisfied. SELF REFRESH The SELF REFRESH command is used to retain data in the DRAM, even if the rest of the system is powered down. When in self refresh mode, the DRAM retains data without ex- ternal clocking. Self refresh mode is also a convenient method used to enable/disable the DLL as well as to change the clock frequency within the allowed synchronous oper- ating range (see Input Clock Frequency Change (page 124)). All power supply inputs (including V REFCA and VREFDQ) must be maintained at valid levels upon entry/exit and during self refresh mode operation. VREFDQ may float or not drive VDDQ/2 while in self refresh mode under the following conditions:

• V SS < VREFDQ < VDD is maintained
• V REFDQ is valid and stable prior to CKE going back HIGH
• The first WRITE operation may not occur earlier than 512 clocks after V REFDQ is valid
• All other self refresh mode exit timing requirements are met 2Gb: x4, x8, x16 DDR3 SDRAM Commands PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 119 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

If the DLL is disabled by the mode register (MR1[0] can be switched during initialization or later), the DRAM is targeted, but not guaranteed, to operate similarly to the normal mode, with a few notable exceptions:

• The DRAM supports only one value of CAS latency (CL = 6) and one value of CAS WRITE latency (CWL = 6).
• DLL disable mode affects the read data clock-to-data strobe relationship ( tDQSCK), but not the read data-to-data strobe relationship (tDQSQ, tQH). Special attention is required to line up the read data with the controller time domain when the DLL is dis- abled.
• In normal operation (DLL on), tDQSCK starts from the rising clock edge AL + CL cycles after the READ command. In DLL disable mode, tDQSCK starts AL + CL - 1 cy- cles after the READ command. Additionally, with the DLL disabled, the value of tDQSCK could be larger than tCK. The ODT feature (including dynamic ODT) is not supported during DLL disable mode. The ODT resistors must be disabled by continuously registering the ODT ball LOW by programming R TT ,nom MR1[9, 6, 2] and RTT(WR) MR2[10, 9] to 0 while in the DLL disable mode. Specific steps must be followed to switch between the DLL enable and DLL disable modes due to a gap in the allowed clock rates between the two modes (tCK [AVG] MAX and tCK [DLL_DIS] MIN, respectively). The only time the clock is allowed to cross this clock rate gap is during self refresh mode. Thus, the required procedure for switching from the DLL enable mode to the DLL disable mode is to change frequency during self refresh: 1. Starting from the idle state (all banks are precharged, all timings are fulfilled, ODT is turned off, and R TT ,nom and RTT(WR) are High-Z), set MR1[0] to 1 to disable the DLL. 2. Enter self refresh mode after tMOD has been satisfied. 3. After tCKSRE is satisfied, change the frequency to the desired clock rate. 4. Self refresh may be exited when the clock is stable with the new frequency for tCKSRX. After tXS is satisfied, update the mode registers with appropriate values. 5. The DRAM will be ready for its next command in the DLL disable mode after the greater of tMRD or tMOD has been satisfied. A ZQCL command should be issued with appropriate timings met. 2Gb: x4, x8, x16 DDR3 SDRAM Commands PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 120 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Figure 41: DLL Enable Mode to DLL Disable Mode Command T0 T1 Ta0 Ta1 Tb0 Tc0 Td0 Td1 Te0 Te1 Tf0 CK CK# ODT9 Valid1 Don’t Care Valid1 SRE3 NOPMRS2 NOP SRX4 MRS5 Valid1NOP NOP Indicates break in time scale tMOD tCKSRE tMODtXS tCKESR CKE tCKSRX876 Notes: 1. Any valid command. 2. Disable DLL by setting MR1[0] to 1. 3. Enter SELF REFRESH. 4. Exit SELF REFRESH. 5. Update the mode registers with the DLL disable parameters setting. 6. Starting with the idle state, R TT is in the High-Z state. 7. Change frequency. 8. Clock must be stable tCKSRX. 9. Static LOW in the case that R TT,nom or RTT(WR) is enabled; otherwise, static LOW or HIGH. A similar procedure is required for switching from the DLL disable mode back to the DLL enable mode. This also requires changing the frequency during self refresh mode (see Figure 42 (page 122)). 1. Starting from the idle state (all banks are precharged, all timings are fulfilled, ODT is turned off, and R TT ,nom and RTT(WR) are High-Z), enter self refresh mode. 2. After tCKSRE is satisfied, change the frequency to the new clock rate. 3. Self refresh may be exited when the clock is stable with the new frequency for tCKSRX. After tXS is satisfied, update the mode registers with the appropriate val- ues. At a minimum, set MR1[0] to 0 to enable the DLL. Wait tMRD, then set MR0[8] to 1 to enable DLL RESET . 4. After another tMRD delay is satisfied, update the remaining mode registers with the appropriate values. 5. The DRAM will be ready for its next command in the DLL enable mode after the greater of tMRD or tMOD has been satisfied. However, before applying any com- mand or function requiring a locked DLL, a delay of tDLLK after DLL RESET must be satisfied. A ZQCL command should be issued with the appropriate timings met. 2Gb: x4, x8, x16 DDR3 SDRAM Commands PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 121 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Figure 42: DLL Disable Mode to DLL Enable Mode CKE T0 Ta0 Ta1 Tb0 Tc0 Tc1 Td0 Te0 Tf0 Tg0 CK CK# ODT10 SRE1 NOPCommand NOP SRX2 MRS3 MRS4 MRS5 Valid6 Valid Don’t CareIndicates break in time scale tCKSRE tCKSRX987 tXS tMRD tMRD tCKESR ODTLoff + 1 × tCK Th0 tDLLK Notes: 1. Enter SELF REFRESH. 2. Exit SELF REFRESH. 3. Wait tXS, then set MR1[0] to 0 to enable DLL. 4. Wait tMRD, then set MR0[8] to 1 to begin DLL RESET. 5. Wait tMRD, update registers (CL, CWL, and write recovery may be necessary). 6. Wait tMOD, any valid command. 7. Starting with the idle state. 8. Change frequency. 9. Clock must be stable at least tCKSRX. 10. Static LOW in the case that R TT,nom or RTT(WR) is enabled; otherwise, static LOW or HIGH. The clock frequency range for the DLL disable mode is specified by the parameter tCK (DLL_DIS). Due to latency counter and timing restrictions, only CL = 6 and CWL = 6 are supported. DLL disable mode will affect the read data clock to data strobe relationship ( tDQSCK) but not the data strobe to data relationship (tDQSQ, tQH). Special attention is needed to line up read data to the controller time domain. Compared to the DLL on mode where tDQSCK starts from the rising clock edge AL + CL cycles after the READ command, the DLL disable mode tDQSCK starts AL + CL - 1 cycles after the READ command. WRITE operations function similarly between the DLL enable and DLL disable modes; however, ODT functionality is not allowed with DLL disable mode. 2Gb: x4, x8, x16 DDR3 SDRAM Commands PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 122 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Figure 43: DLL Disable tDQSCK T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 Don’t CareTransitioning Data Valid NOPREAD NOP NOP NOP NOP NOP NOP NOP NOP NOP CK CK# Command Address DIb + 3DIb + 2DIb + 1DIb DIb + 7DIb + 6DIb + 5DIb + 4 DQ BL8 DLL on DQS, DQS# DLL on DQ BL8 DLL disable DQS, DQS# DLL off DQ BL8 DLL disable DQS, DQS# DLL off RL = AL + CL = 6 (CL = 6, AL = 0) CL = 6 DIb + 3DIb + 2DIb + 1DIb DIb + 7DIb + 6DIb + 5DIb + 4 DIb + 3DIb + 2DIb + 1DIb DIb + 7DIb + 6DIb + 5DIb + 4 tDQSCK (DLL_DIS) MIN tDQSCK (DLL_DIS) MAX RL (DLL_DIS) = AL + (CL - 1) = 5 Table 74: READ Electrical Characteristics, DLL Disable Mode Parameter Symbol Min Max Unit Access window of DQS from CK, CK# tDQSCK (DLL_DIS) 1 10 ns 2Gb: x4, x8, x16 DDR3 SDRAM Commands PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 123 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Input Clock Frequency Change When the DDR3 SDRAM is initialized, the clock must be stable during most normal states of operation. This means that after the clock frequency has been set to the stable state, the clock period is not allowed to deviate, except for what is allowed by the clock jitter and spread spectrum clocking (SSC) specifications. The input clock frequency can be changed from one stable clock rate to another under two conditions: self refresh mode and precharge power-down mode. It is illegal to change the clock frequency outside of those two modes. For the self refresh mode con- dition, when the DDR3 SDRAM has been successfully placed into self refresh mode and tCKSRE has been satisfied, the state of the clock becomes a “Don’t Care.” When the clock becomes a “Don’t Care,” changing the clock frequency is permissible if the new clock frequency is stable prior to tCKSRX. When entering and exiting self refresh mode for the sole purpose of changing the clock frequency, the self refresh entry and exit specifications must still be met. The precharge power-down mode condition is when the DDR3 SDRAM is in precharge power-down mode (either fast exit mode or slow exit mode). Either ODT must be at a logic LOW or R TT ,nom and RTT(WR) must be disabled via MR1 and MR2. This ensures RTT ,nom and RTT(WR) are in an off state prior to entering precharge power-down mode, and CKE must be at a logic LOW . A minimum of tCKSRE must occur after CKE goes LOW before the clock frequency can change. The DDR3 SDRAM input clock frequency is al- lowed to change only within the minimum and maximum operating frequency speci- fied for the particular speed grade ( tCK [AVG] MIN to tCK [AVG] MAX). During the input clock frequency change, CKE must be held at a stable LOW level. When the input clock frequency is changed, a stable clock must be provided to the DRAM tCKSRX before pre- charge power-down may be exited. After precharge power-down is exited and tXP has been satisfied, the DLL must be reset via the MRS. Depending on the new clock fre- quency, additional MRS commands may need to be issued. During the DLL lock time, R TT ,nom and RTT(WR) must remain in an off state. After the DLL lock time, the DRAM is ready to operate with a new clock frequency. 2Gb: x4, x8, x16 DDR3 SDRAM Input Clock Frequency Change PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 124 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Figure 44: Change Frequency During Precharge Power-Down CK CK# Command NOPNOPNOP Address CKE DQ DM DQS, DQS# NOP tCK Enter precharge power-down mode Exit precharge power-down mode T0 T1 Ta0 Tc0 Tb0T2 Don’t Care tCKE tXP MRS DLL RESET Valid Valid NOP tCH tIH tIS tCL Tc1 Td0 Te1 Td1 tCKSRE tCHb tCLb tCKb tCHb tCLb tCKb tCHb tCLb tCKb tCPDED ODT NOP Te0 Previous clock frequency New clock frequency Frequency change Indicates break in time scale tIH tIS tIH tIS tDLLK tAOFPD/tAOF tCKSRX High-Z High-Z Notes: 1. Applicable for both SLOW-EXIT and FAST-EXIT precharge power-down modes. 2. tAOFPD and tAOF must be satisfied and outputs High-Z prior to T1 (see On-Die Termina- tion (ODT) (page 190) for exact requirements). 3. If the R TT,nom feature was enabled in the mode register prior to entering precharge power-down mode, the ODT signal must be continuously registered LOW, ensuring RTT is in an off state. If the RTT,nom feature was disabled in the mode register prior to enter- ing precharge power-down mode, RTT will remain in the off state. The ODT signal can be registered LOW or HIGH in this case. 2Gb: x4, x8, x16 DDR3 SDRAM Input Clock Frequency Change PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 125 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

For better signal integrity, DDR3 SDRAM memory modules have adopted fly-by topolo- gy for the commands, addresses, control signals, and clocks. Write leveling is a scheme for the memory controller to adjust or de-skew the DQS strobe (DQS, DQS#) to CK rela- tionship at the DRAM with a simple feedback feature provided by the DRAM. Write lev- eling is generally used as part of the initialization process, if required. For normal DRAM operation, this feature must be disabled. This is the only DRAM operation where the DQS functions as an input (to capture the incoming clock) and the DQ function as outputs (to report the state of the clock). Note that nonstandard ODT schemes are re- quired. The memory controller using the write leveling procedure must have adjustable delay settings on its DQS strobe to align the rising edge of DQS to the clock at the DRAM pins. This is accomplished when the DRAM asynchronously feeds back the CK status via the DQ bus and samples with the rising edge of DQS. The controller repeatedly delays the DQS strobe until a CK transition from 0 to 1 is detected. The DQS delay established by this procedure helps ensure tDQSS, tDSS, and tDSH specifications in systems that use fly-by topology by de-skewing the trace length mismatch. A conceptual timing of this procedure is shown in Figure 45. Figure 45: Write Leveling Concept CK CK# Source Differential DQS Differential DQS Differential DQS DQ DQ CK CK# Destination Destination Push DQS to capture 0–1 transition T0 T1 T2 T3 T4 T5 T6 T7 T0 T1 T2 T3 T4 T5 T6Tn CK CK# T0 T1 T2 T3 T4 T5 T6Tn Don’t Care 2Gb: x4, x8, x16 DDR3 SDRAM Write Leveling PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 126 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

When write leveling is enabled, the rising edge of DQS samples CK, and the prime DQ outputs the sampled CK’s status. The prime DQ for a x4 or x8 configuration is DQ0 with all other DQ (DQ[7:1]) driving LOW . The prime DQ for a x16 configuration is DQ0 for the lower byte and DQ8 for the upper byte. It outputs the status of CK sampled by LDQS and UDQS. All other DQ (DQ[7:1], DQ[15:9]) continue to drive LOW . Two prime DQ on a x16 enable each byte lane to be leveled independently. The write leveling mode register interacts with other mode registers to correctly config- ure the write leveling functionality. Besides using MR1[7] to disable/enable write level- ing, MR1[12] must be used to enable/disable the output buffers. The ODT value, burst length, and so forth need to be selected as well. This interaction is shown in Table 75. It should also be noted that when the outputs are enabled during write leveling mode, the DQS buffers are set as inputs, and the DQ are set as outputs. Additionally, during write leveling mode, only the DQS strobe terminations are activated and deactivated via the ODT ball. The DQ remain disabled and are not affected by the ODT ball. Table 75: Write Leveling Matrix Note 1 applies to the entire table DRAM ODT Ball DRAM RTT,nom DRAM State Case Notes Write Leveling Output Buffers RTT,nom Value DQS DQ Disabled See normal operations Write leveling not enabled 0 Enabled (1) Disabled (1) n/a Low Off Off DQS not receiving: not terminated Prime DQ High-Z: not terminated Other DQ High-Z: not terminated ΩΩ ΩΩ, or 120Ω High On DQS not receiving: terminated by R TT Prime DQ High-Z: not terminated Other DQ High-Z: not terminated Enabled (0) n/a Low Off DQS receiving: not terminated Prime DQ driving CK state: not terminated Other DQ driving LOW: not terminated ΩΩ, or 120Ω High On DQS receiving: terminated by R TT Prime DQ driving CK state: not terminated Other DQ driving LOW: not terminated Notes: 1. Expected usage if used during write leveling: Case 1 may be used when DRAM are on a dual-rank module and on the rank not being leveled or on any rank of a module not being leveled on a multislot system. Case 2 may be used when DRAM are on any rank of a module not being leveled on a multislot system. Case 3 is generally not used. Case 4 is generally used when DRAM are on the rank that is being leveled. 2. Since the DRAM DQS is not being driven (MR1[12] = 1), DQS ignores the input strobe, and all R TT,nom values are allowed. This simulates a normal standby state to DQS. 3. Since the DRAM DQS is being driven (MR1[12] = 0), DQS captures the input strobe, and only some RTT,nom values are allowed. This simulates a normal write state to DQS. 2Gb: x4, x8, x16 DDR3 SDRAM Write Leveling PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 127 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

A memory controller initiates the DRAM write leveling mode by setting MR1[7] to 1, as- suming the other programable features (MR0, MR1, MR2, and MR3) are first set and the DLL is fully reset and locked. The DQ balls enter the write leveling mode going from a High-Z state to an undefined driving state, so the DQ bus should not be driven. During write leveling mode, only the NOP or DES commands are allowed. The memory con- troller should attempt to level only one rank at a time; thus, the outputs of other ranks should be disabled by setting MR1[12] to 1 in the other ranks. The memory controller may assert ODT after a tMOD delay, as the DRAM will be ready to process the ODT tran- sition. ODT should be turned on prior to DQS being driven LOW by at least ODTLon delay (WL - 2 tCK), provided it does not violate the aforementioned tMOD delay require- ment. The memory controller may drive DQS LOW and DQS# HIGH after tWLDQSEN has been satisfied. The controller may begin to toggle DQS after tWLMRD (one DQS toggle is DQS transitioning from a LOW state to a HIGH state with DQS# transitioning from a HIGH state to a LOW state, then both transition back to their original states). At a mini- mum, ODTLon and tAON must be satisfied at least one clock prior to DQS toggling. After tWLMRD and a DQS LOW preamble (tWPRE) have been satisfied, the memory controller may provide either a single DQS toggle or multiple DQS toggles to sample CK for a given DQS-to-CK skew. Each DQS toggle must not violate tDQSL (MIN) and tDQSH (MIN) specifications. tDQSL (MAX) and tDQSH (MAX) specifications are not applicable during write leveling mode. The DQS must be able to distinguish the CK’s rising edge within tWLS and tWLH. The prime DQ will output the CK’s status asynchronously from the associated DQS rising edge CK capture within tWLO. The remaining DQ that always drive LOW when DQS is toggling must be LOW within tWLOE after the first tWLO is sat- isfied (the prime DQ going LOW). As previously noted, DQS is an input and not an out- put during this process. Figure 46 (page 129) depicts the basic timing parameters for the overall write leveling procedure. The memory controller will most likely sample each applicable prime DQ state and de- termine whether to increment or decrement its DQS delay setting. After the memory controller performs enough DQS toggles to detect the CK’s 0-to-1 transition, the memo- ry controller should lock the DQS delay setting for that DRAM. After locking the DQS setting is locked, leveling for the rank will have been achieved, and the write leveling mode for the rank should be disabled or reprogrammed (if write leveling of another rank follows). 2Gb: x4, x8, x16 DDR3 SDRAM Write Leveling PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 128 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Figure 46: Write Leveling Sequence CK CK# Command T1 T2 Early remaining DQ Late remaining DQ tWLOE NOP2 NOPMRS1 NOP NOP NOP NOP NOP NOP NOP NOP NOP tWLStWLH Don’t CareUndefined Driving ModeIndicates break in time scale Prime DQ5 Differential DQS4 ODT tMOD tDQSL3 tDQSL3tDQSH3 tDQSH3 tWLOtWLMRD tWLDQSEN tWLO tWLO tWLO Notes: 1. MRS: Load MR1 to enter write leveling mode. 2. NOP: NOP or DES. 3. DQS, DQS# needs to fulfill minimum pulse width requirements tDQSH (MIN) and tDQSL (MIN) as defined for regular writes. The maximum pulse width is system-dependent. 4. Differential DQS is the differential data strobe (DQS, DQS#). Timing reference points are the zero crossings. The solid line represents DQS; the dotted line represents DQS#. 5. DRAM drives leveling feedback on a prime DQ (DQ0 for x4 and x8). The remaining DQ are driven LOW and remain in this state throughout the leveling procedure. 2Gb: x4, x8, x16 DDR3 SDRAM Write Leveling PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 129 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Write Leveling Mode Exit Procedure After the DRAM are leveled, they must exit from write leveling mode before the normal mode can be used. Figure 47 depicts a general procedure for exiting write leveling mode. After the last rising DQS (capturing a 1 at T0), the memory controller should stop driving the DQS signals after tWLO (MAX) delay plus enough delay to enable the memo- ry controller to capture the applicable prime DQ state (at ~Tb0). The DQ balls become undefined when DQS no longer remains LOW, and they remain undefined until tMOD after the MRS command (at Te1). The ODT input should be de-asserted LOW such that ODTLoff (MIN) expires after the DQS is no longer driving LOW . When ODT LOW satisfies tIS, ODT must be kept LOW (at ~Tb0) until the DRAM is ready for either another rank to be leveled or until the normal mode can be used. After DQS termination is switched off, write level mode should be disabled via the MRS command (at Tc2). After tMOD is satisfied (at Te1), any valid com- mand may be registered by the DRAM. Some MRS commands may be issued after tMRD (at Td1). Figure 47: Write Leveling Exit Procedure NOP CK T0 T1 T2 Ta0 Tb0 Tc0 Tc1 Tc2 Td0 Td1 Te0 Te1 CK# Command ODT RTT(DQ) NOPNOP NOP NOP NOP NOP MRS NOP NOP Address MR1 Valid Valid Valid Valid Don’t CareTransitioning RTT DQS, RTT DQS# RTT,nom Undefined Driving Mode tAOF (MAX) tMRD Indicates break in time scale DQS, DQS# CK = 1DQ tIS tAOF (MIN) tMOD tWLO + tWLOE ODTLoff Note: 1. The DQ result, = 1, between Ta0 and Tc0, is a result of the DQS, DQS# signals capturing CK HIGH just after the T0 state. 2Gb: x4, x8, x16 DDR3 SDRAM Write Leveling PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 130 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

The following sequence is required for power-up and initialization, as shown in Fig- ure 48 (page 132): 1. Apply power. RESET# is recommended to be below 0.2 × V DDQ during power ramp to ensure the outputs remain disabled (High-Z) and ODT off (RTT is also High-Z). All other inputs, including ODT , may be undefined. During power-up, either of the following conditions may exist and must be met:

• Condition A: DD and VDDQ are driven from a single-power converter output and are ramped with a maximum delta voltage between them of ΔV ≤ 300mV . Slope re- versal of any power supply signal is allowed. The voltage levels on all balls oth- er than V DD, VDDQ, VSS, VSSQ must be less than or equal to VDDQ and VDD on one side, and must be greater than or equal to VSSQ and VSS on the other side. – Both V DD and VDDQ power supplies ramp to VDD,min and VDDQ,min within tVDDPR = 200ms. –V REFDQ tracks VDD × 0.5, VREFCA tracks VDD × 0.5. –V TT is limited to 0.95V when the power ramp is complete and is not applied directly to the device; however, tVTD should be greater than or equal to 0 to avoid device latchup.
• Condition B: –V DD may be applied before or at the same time as VDDQ. –V DDQ may be applied before or at the same time as VTT, VREFDQ, and VREFCA. – No slope reversals are allowed in the power supply ramp for this condition. 2. Until stable power, maintain RESET# LOW to ensure the outputs remain disabled (High-Z). After the power is stable, RESET# must be LOW for at least 200μs to be- gin the initialization process. ODT will remain in the High-Z state while RESET# is LOW and until CKE is registered HIGH. 3. CKE must be LOW 10ns prior to RESET# transitioning HIGH. 4. After RESET# transitions HIGH, wait 500μs (minus one clock) with CKE LOW . 5. After the CKE LOW time, CKE may be brought HIGH (synchronously) and only NOP or DES commands may be issued. The clock must be present and valid for at least 10ns (and a minimum of five clocks) and ODT must be driven LOW at least tIS prior to CKE being registered HIGH. When CKE is registered HIGH, it must be continuously registered HIGH until the full initialization process is complete. 6. After CKE is registered HIGH and after tXPR has been satisfied, MRS commands may be issued. Issue an MRS (LOAD MODE) command to MR2 with the applicable settings (provide LOW to BA2 and BA0 and HIGH to BA1). 7. Issue an MRS command to MR3 with the applicable settings. 8. Issue an MRS command to MR1 with the applicable settings, including enabling the DLL and configuring ODT . 9. Issue an MRS command to MR0 with the applicable settings, including a DLL RE- SET command. tDLLK (512) cycles of clock input are required to lock the DLL. 10. Issue a ZQCL command to calibrate R TT and RON values for the process voltage temperature (PVT). Prior to normal operation, tZQinit must be satisfied. 11. When tDLLK and tZQinit have been satisfied, the DDR3 SDRAM will be ready for normal operation. 2Gb: x4, x8, x16 DDR3 SDRAM Initialization PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 131 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Figure 48: Initialization Sequence CKE RTT BA[2:0] All voltage supplies valid and stable T = 200μs (MIN) DM DQS Address A10 CK CK# tCL Command NOP T0 Ta0 Don’t Care tCL tIS tCK ODT DQ Tb0 tDLLK MR1 with DLL enable MR0 with DLL reset tMRD tMOD MRSMRS BA0 = H BA1 = L BA2 = L BA0 = L BA1 = L BA2 = L Code Code Code Code Valid Valid Valid Valid Normal operation MR2 MR3 tMRD tMRD MRSMRS BA0 = L BA1 = H BA2 = L BA0 = H BA1 = H BA2 = L Code Code Code Code Tc0 Td0 VTT VREF VDDQ VDD RESET# T = 500μs (MIN) tCKSRX Stable and valid clock Valid Power-up ramp T (MAX) = 200ms DRAM ready for external commands tZQinit ZQ calibration A10 = H ZQCL tIS See power-up conditions in the initialization sequence text, set up 1 tXPR Valid tIOZ = 20ns Indicates break in time scale T (MIN) = 10ns tVTD 2Gb: x4, x8, x16 DDR3 SDRAM Initialization PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 132 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Mode registers (MR0–MR3) are used to define various modes of programmable opera- tions of the DDR3 SDRAM. A mode register is programmed via the mode register set (MRS) command during initialization, and it retains the stored information (except for MR0[8], which is self-clearing) until it is reprogrammed, RESET# goes LOW, the device loses power. Contents of a mode register can be altered by re-executing the MRS command. Even if the user wants to modify only a subset of the mode register’s variables, all variables must be programmed when the MRS command is issued. Reprogramming the mode register will not alter the contents of the memory array, provided it is performed cor- rectly. The MRS command can only be issued (or re-issued) when all banks are idle and in the precharged state ( tRP is satisfied and no data bursts are in progress). After an MRS com- mand has been issued, two parameters must be satisfied: tMRD and tMOD. The control- ler must wait tMRD before initiating any subsequent MRS commands. Figure 49: MRS to MRS Command Timing (tMRD) Valid Valid MRS1 MRS2NOP NOP NOP NOP T0 T1 T2 Ta0 Ta1 Ta2 CK# CK Command Address CKE3 Don’t CareIndicates break in time scale tMRD Notes: 1. Prior to issuing the MRS command, all banks must be idle and precharged, tRP (MIN) must be satisfied, and no data bursts can be in progress. 2. tMRD specifies the MRS to MRS command minimum cycle time. 3. CKE must be registered HIGH from the MRS command until tMRSPDEN (MIN) (see Pow- er-Down Mode (page 180)). 4. For a CAS latency change, tXPDLL timing must be met before any non-MRS command. The controller must also wait tMOD before initiating any non-MRS commands (exclud- ing NOP and DES). The DRAM requires tMOD in order to update the requested features, with the exception of DLL RESET , which requires additional time. Until tMOD has been satisfied, the updated features are to be assumed unavailable. 2Gb: x4, x8, x16 DDR3 SDRAM Mode Registers PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 133 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Figure 50: MRS to nonMRS Command Timing (tMOD) Valid Valid MRS non MRSNOP NOP NOP NOP T0 T1 T2 Ta0 Ta1 Ta2 CK# CK Command Address CKE Valid Old setting New setting Don’t CareIndicates break in time scale tMOD Updating setting Notes: 1. Prior to issuing the MRS command, all banks must be idle (they must be precharged, tRP must be satisfied, and no data bursts can be in progress). 2. Prior to Ta2 when tMOD (MIN) is being satisfied, no commands (except NOP/DES) may be issued. 3. If R TT was previously enabled, ODT must be registered LOW at T0 so that ODTL is satis- fied prior to Ta1. ODT must also be registered LOW at each rising CK edge from T0 until tMODmin is satisfied at Ta2. 4. CKE must be registered HIGH from the MRS command until tMRSPDEN (MIN), at which time power-down may occur (see Power-Down Mode (page 180)). Mode Register 0 (MR0) The base register, mode register 0 (MR0), is used to define various DDR3 SDRAM modes of operation. These definitions include the selection of a burst length, burst type, CAS latency, operating mode, DLL RESET , write recovery, and precharge power-down mode (see Figure 51 (page 135)). Burst Length Burst length is defined by MR0[1:0]. Read and write accesses to the DDR3 SDRAM are burst-oriented, with the burst length being programmable to 4 (chop mode), 8 (fixed mode), or selectable using A12 during a READ/WRITE command (on-the-fly). The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE command. When MR0[1:0] is set to 01 during a READ/WRITE command, if A12 = 0, then BC4 (chop) mode is selected. If A12 = 1, then BL8 mode is selected. Specific timing diagrams, and turnaround between READ/WRITE, are shown in the READ/WRITE sections of this document. When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached. The block is uniquely selected by A[i:2] when the burst length is set to 4 and by A[i:3] when the burst length is set to 8 (where Ai is the most significant column address bit for a given config- uration). The remaining (least significant) address bit(s) is (are) used to select the start- 2Gb: x4, x8, x16 DDR3 SDRAM Mode Register 0 (MR0) PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 134 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

ing location within the block. The programmed burst length applies to both READ and WRITE bursts. Figure 51: Mode Register 0 (MR0) Definitions CL BLCAS# latency BTPD A9 A7 A6 A5 A4 A3A8 A2 A1 A0 Mode register 0 (MR0) Address bus 97 6 5 4 382 1 0 A10A12 A11A14BA0 10111213 READ Burst Type Sequential (nibble) Interleaved CAS Latency Reserved DLL Write Recovery WR010 M12 Precharge PD DLL off (slow exit) DLL on (fast exit) BA1 BA2 Burst Length Fixed BL8 4 or 8 (on-the-fly via A12) Fixed BC4 (chop) Reserved M10 M11 M15 M16 Mode Register Mode register 0 (MR0) Mode register 1 (MR1) Mode register 2 (MR2) Mode register 3 (MR3) A13 01 01 DLL Reset No Yes 01101 4 Note: 1. MR0[17, 14, 13, 7] are reserved for future use and must be programmed to 0. Burst Type Accesses within a given burst may be programmed to either a sequential or an inter- leaved order. The burst type is selected via MR0[3] (see Figure 51 (page 135)). The order- ing of accesses within a burst is determined by the burst length, the burst type, and the starting column address. DDR3 only supports 4-bit burst chop and 8-bit burst access modes. Full interleave address ordering is supported for READs, while WRITEs are re- stricted to nibble (BC4) or word (BL8) boundaries. 2Gb: x4, x8, x16 DDR3 SDRAM Mode Register 0 (MR0) PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 135 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Table 76: Burst Order Burst Length READ/ WRITE Starting Column Address (A[2, 1, 0]) Burst Type = Sequential (Decimal) Burst Type = Interleaved (Decimal) Notes

4 READ 0 0 0 0, 1, 2, 3, Z, Z, Z, Z 0, 1, 2, 3, Z, Z, Z, Z 1, 2

WRITE 0 V V 0, 1, 2, 3, X, X, X, X 0, 1, 2, 3, X, X, X, X 1, 3, 4

8 READ 0 0 0 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 1

WRITE V V V 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 1, 3 Notes: 1. Internal READ and WRITE operations start at the same point in time for BC4 as they do for BL8. 2. Z = Data and strobe output drivers are in tri-state. 3. V = A valid logic level (0 or 1), but the respective input buffer ignores level-on input pins. 4. X = “Don’t Care.” DLL RESET DLL RESET is defined by MR0[8] (see Figure 51 (page 135)). Programming MR0[8] to 1 activates the DLL RESET function. MR0[8] is self-clearing, meaning it returns to a value of 0 after the DLL RESET function has been initiated. Anytime the DLL RESET function is initiated, CKE must be HIGH and the clock held stable for 512 ( tDLLK) clock cycles before a READ command can be issued. This is to allow time for the internal clock to be synchronized with the external clock. Failing to wait for synchronization to occur may result in invalid output timing specifications, such as tDQSCK timings. Write Recovery WRITE recovery time is defined by MR0[11:9] (see Figure 51 (page 135)). Write recovery values of 5, 6, 7, 8, 10, 12, or 14 may be used by programming MR0[11:9]. The user is 2Gb: x4, x8, x16 DDR3 SDRAM Mode Register 0 (MR0) PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 136 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

required to program the correct value of write recovery, which is calculated by dividing tWR (ns) by tCK (ns) and rounding up a noninteger value to the next integer: WR (cycles) = roundup (tWR [ns]/tCK [ns]). Precharge Power-Down (Precharge PD) The precharge power-down (PD) bit applies only when precharge power-down mode is being used. When MR0[12] is set to 0, the DLL is off during precharge power-down, pro- viding a lower standby current mode; however, tXPDLL must be satisfied when exiting. When MR0[12] is set to 1, the DLL continues to run during precharge power-down mode to enable a faster exit of precharge power-down mode; however, tXP must be sat- isfied when exiting (see Power-Down Mode (page 180)). CAS Latency (CL) The CL is defined by MR0[6:4], as shown in Figure 51 (page 135). CAS latency is the de- lay, in clock cycles, between the internal READ command and the availability of the first bit of output data. The CL can be set to 5, 6, 7, 8, 9, 10, 11, 12, 13 or 14. DDR3 SDRAM do not support half-clock latencies. Examples of CL = 6 and CL = 8 are shown below. If an internal READ command is regis- tered at clock edge n, and the CAS latency is m clocks, the data will be available nomi- nally coincident with clock edge n + m.Table 51 (page 71) through Table 54 (page 74) indicate the CLs supported at various operating frequencies. Figure 52: READ Latency READ NOP NOP NOP NOP NOP NOPNOP CK CK# Command DQ DQS, DQS# DQS, DQS# T0 T1 T2 T3 T4 T5 T6 T7 T8 Don’t Care CK CK# Command DQ READ NOP NOP NOP NOP NOP NOPNOP T0 T1 T2 T3 T4 T5 T6 T7 T8 DI n + 3 DI n + 1 DI n + 2 DI n + 4 DI n DI n NOP NOP AL = 0, CL = 8 AL = 0, CL = 6 Transitioning Data Notes: 1. For illustration purposes, only CL = 6 and CL = 8 are shown. Other CL values are possible. 2. Shown with nominal tDQSCK and nominal tDSDQ. 2Gb: x4, x8, x16 DDR3 SDRAM Mode Register 0 (MR0) PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 137 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Mode Register 1 (MR1) The mode register 1 (MR1) controls additional features and functions not available in the other mode registers: DLL ENABLE/DISABLE, output drive strength, OUTPUT ENA- BLE/DISABLE (Q OFF), TDQS ENABLE/DISABLE (x8 configuration only), on-die termi- nation (ODT) resistance value R TT ,nom, WRITE LEVELING, and posted CAS additive la- tency (AL). These features and functions are controlled via the bits shown in the figure below. The MR1 register is programmed via the MRS command and retains the stored information until it is reprogrammed, RESET# goes LOW, or the device loses power. Re- programming the MR1 register will not alter the contents of the memory array, provided it is reprogrammed correctly. The MR1 register must be loaded when all banks are idle and no bursts are in progress. The controller must satisfy the specified timing parameters tMRD and tMOD before ini- tiating a subsequent operation. Figure 53: Mode Register 1 (MR1) Definition AL RTTQ Off A9 A7 A6 A5 A4 A3A8 A2 A1 A0 Mode register 1 (MR1) Address bus 97 6 5 4 382 1 0 A10A12 A11BA0BA1 10111213 DLL Enable Enable (normal) Disable Output Drive Strength RZQ/6 (40ȍ NOM) RZQ/7 (34ȍ NOM) Reserved Reserved WL

011 ODS DLLRTTTDQS

Disable (normal) Enable Additive Latency (AL) Disabled (AL = 0) AL = CL - 1 AL = CL - 2 Reserved RTT ODS A13A14 1617 001 M11 TDQS Disabled Enabled 01 01 RTT,nom (ODT) 2 Non-Writes RTT,nom disabled RZQ/4 (60ȍ NOM) RZQ/2 (120ȍ NOM) RZQ/6 (40ȍ NOM) RZQ/12 (20ȍ NOM) RZQ/8 (30ȍ NOM) Reserved Reserved RTT,nom (ODT) 3 Writes RTT,nom disabled RZQ/4 (60ȍ NOM) RZQ/2 (120ȍ NOM) RZQ/6 (40ȍ NOM) n/a n/a Reserved Reserved Mode Register Mode register set 0 (MR0) Mode register set 1 (MR1) Mode register set 2 (MR2) Mode register set 3 (MR3) M15 M16 Notes: 1. MR1[17, 14, 13, 10, 8] are reserved for future use and must be programmed to 0. 2. During write leveling, if MR1[7] and MR1[12] are 1, then all R TT,nom values are available for use. 3. During write leveling, if MR1[7] is 1, but MR1[12] is 0, then only R TT,nom write values are available for use. DLL ENABLE/DISABLE The DLL may be enabled or disabled by programming MR1[0] during the LOAD MODE command (see Figure 53 (page 138)). The DLL must be enabled for normal operation. DLL enable is required during power-up initialization and upon returning to normal operation, after having disabled the DLL for the purpose of debugging or evaluation. Enabling the DLL should always be followed by resetting the DLL using the appropriate LOAD MODE command. 2Gb: x4, x8, x16 DDR3 SDRAM Mode Register 1 (MR1) PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 138 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

If the DLL is enabled prior to entering self refresh mode, the DLL is automatically disa- bled when entering the SELF REFRESH operation and is automatically re-enabled and reset upon exit of the SELF REFRESH operation. If the DLL is disabled prior to entering self refresh mode, the DLL remains disabled, even upon exit of the SELF REFRESH oper- ation until it is re-enabled and reset. The DRAM is not tested to check—nor does Micron warrant compliance with—normal mode timings or functionality when the DLL is disabled. An attempt has been made to have the DRAM operate in the normal mode where reasonably possible when the DLL has been disabled; however, by industry standard, a few known exceptions are defined:

• ODT is not allowed to be used.
• The output data is no longer edge-aligned to the clock.
• CL and CWL can only be six clocks. When the DLL is disabled, timing and functionality can vary from the normal operation specifications when the DLL is enabled (see DLL Disable Mode (page 120)). Disabling the DLL also implies the need to change the clock frequency (see Input Clock Frequen- cy Change (page 124)). Output Drive Strength The DDR3 SDRAM uses a programmable impedance output buffer. The drive strength mode register setting is defined by MR1[5, 1]. RZQ/7 (34Ω [NOM]) is the primary output driver impedance setting for DDR3 SDRAM devices. To calibrate the output driver im- pedance, an external precision resistor (RZQ) is connected between the ZQ ball and V SSQ. The value of the resistor must be 240Ω r The output impedance is set during initialization. Additional impedance calibration up- dates do not affect device operation, and all data sheet timings and current specifica- tions are met during an update. To meet the 34Ω specification, the output drive strength must be set to 34Ω during initi- alization. To obtain a calibrated output driver impedance after power-up, the DDR3 SDRAM needs a calibration command that is part of the initialization and reset proce- dure. OUTPUT ENABLE/DISABLE The OUTPUT ENABLE/DISABLE function is defined by MR1[12] (see Figure 53 (page 138)). When enabled (MR1[12] = 0), all outputs (DQ, DQS, DQS#) function when in the normal mode of operation. When disabled (MR1[12] = 1), all DDR3 SDRAM out- puts (DQ and DQS, DQS#) are High-Z. The output disable feature is intended to be used during I DD characterization of the READ current and during tDQSS margining (write leveling) only. TDQS ENABLE Termination data strobe (TDQS) is a function of the x8 DDR3 SDRAM configuration that provides termination resistance R TT, and can be useful in some system configura- tions. TDQS is not supported in x4 or x16 configurations. When enabled via the mode register (MR1[11]), R TT applied to DQS and DQS# is also applied to TDQS and TDQS#. In contrast to the RDQS function of DDR2 SDRAM, DDR3’s TDQS provides the termina- tion resistance R TT only. The OUTPUT DATA STROBE function of RDQS is not provided by TDQS; thus, RON does not apply to TDQS and TDQS#. The TDQS and DM functions 2Gb: x4, x8, x16 DDR3 SDRAM Mode Register 1 (MR1) PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 139 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

share the same ball. When the TDQS function is enabled via the mode register, the DM function is not supported. When the TDQS function is disabled, the DM function is pro- vided, and the TDQS# ball is not used. The TDQS function is available in the x8 DDR3 SDRAM configuration only and must be disabled via the mode register for the x4 and x16 configurations. On-Die Termination (ODT) On-die termination (ODT) resistance RTT ,nom is defined by MR1[9, 6, 2] (see Figure 53 (page 138)). The RTT termination resistance value applies to the DQ, DM, DQS, DQS#, and TDQS, TDQS# balls. DDR3 supports multiple RTT termination resistance values based on RZQ/n where n can be 2, 4, 6, 8, or 12 and RZQ is 240Ω Unlike DDR2, DDR3 ODT must be turned off prior to reading data out and must remain off during a READ burst. RTT ,nom termination is allowed any time after the DRAM is ini- tialized, calibrated, and not performing read accesses, or when it is not in self refresh mode. Additionally, write accesses with dynamic ODT (R TT(WR)) enabled temporarily re- places RTT ,nom with RTT(WR). The effective termination, RTT(EFF), may be different from RTT targeted due to nonlinear- ity of the termination. For RTT(EFF) values and calculations, see On-Die Termination (ODT) (page 190). The ODT feature is designed to improve signal integrity of the memory channel by ena- bling the DDR3 SDRAM controller to independently turn on/off ODT for any or all devi- ces. The ODT input control pin is used to determine when R TT is turned on (ODTLon) and off (ODTLoff), assuming ODT has been enabled via MR1[9, 6, 2]. Timings for ODT are detailed in On-Die Termination (ODT) (page 190). WRITE LEVELING The WRITE LEVELING function is enabled by MR1[7] (see Figure 53 (page 138)). Write leveling is used (during initialization) to de-skew the DQS strobe to clock offset as a re- sult of fly-by topology designs. For better signal integrity, DDR3 SDRAM memory mod- ules adopted fly-by topology for the commands, addresses, control signals, and clocks. The fly-by topology benefits from a reduced number of stubs and their lengths. Howev- er, fly-by topology induces flight time skews between the clock and DQS strobe (and DQ) at each DRAM on the DIMM. Controllers will have a difficult time maintaining tDQSS, tDSS, and tDSH specifications without supporting write leveling in systems that use fly-by topology-based modules. Write leveling timing and detailed operation infor- mation is provided in Write Leveling (page 126). Posted CAS Additive Latency (AL) Posted CAS additive latency (AL) is supported to make the command and data bus effi- cient for sustainable bandwidths in DDR3 SDRAM. MR1[4, 3] define the value of AL (see Figure 54 (page 141)). MR1[4, 3] enable the user to program the DDR3 SDRAM with AL = 0, CL - 1, or CL - 2. With this feature, the DDR3 SDRAM enables a READ or WRITE command to be issued after the ACTIVATE command for that bank prior to tRCD (MIN). The only restriction is ACTIVATE to READ or WRITE + AL ≥ tRCD (MIN) must be satisfied. Assuming tRCD (MIN) = CL, a typical application using this feature sets AL = CL - 1tCK = tRCD (MIN) - 1 tCK. The READ or WRITE command is held for the time of the AL before it is released 2Gb: x4, x8, x16 DDR3 SDRAM Mode Register 1 (MR1) PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 140 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

internally to the DDR3 SDRAM device. READ latency (RL) is controlled by the sum of the AL and CAS latency (CL), RL = AL + CL. WRITE latency (WL) is the sum of CAS WRITE latency and AL, WL = AL + CWL (see Mode Register 2 (MR2) (page 142)). Exam- ples of READ and WRITE latencies are shown in Figure 54 (page 141) and Figure 55 (page 142). Figure 54: READ Latency (AL = 5, CL = 6) CK CK# Command DQ DQS, DQS# ACTIVE n T0 T1 Don’t Care NOP NOP T6 T12 NOPREAD n T13 NOP DO n + 3 DO n + 2 DO n + 1 RL = AL + CL = 11 T14 NOP DO n tRCD (MIN) AL = 5 CL = 6 T11 BC4 Indicates break in time scale Transitioning Data NOP 2Gb: x4, x8, x16 DDR3 SDRAM Mode Register 1 (MR1) PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 141 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Mode Register 2 (MR2) The mode register 2 (MR2) controls additional features and functions not available in the other mode registers. These addional functions are CAS WRITE latency (CWL), AU- TO SELF REFRESH (ASR), SELF REFRESH TEMPERATURE (SRT), and DYNAMIC ODT TT(WR)). These functions are controlled via the bits shown in the figure below. MR2 is programmed via the MRS command and will retain the stored information until it is programmed again or the device loses power. Reprogramming the MR2 register will not alter the contents of the memory array, provided it is reprogrammed correctly. The MR2 register must be loaded when all banks are idle and no data bursts are in progress, and the controller must wait the specified time tMRD and tMOD before initiating a subse- quent operation. Figure 55: Mode Register 2 (MR2) Definition M15 M16 Mode Register Mode register set 0 (MR0) Mode register set 1 (MR1) Mode register set 2 (MR2) Mode register set 3 (MR3) A9 A7 A6 A5 A4 A3A8 A2 A1 A0 Mode register 2 (MR2) Address bus 97 6 5 4 382 1 0 A10A12 A11BA0BA1 101112131415

0 CWL0101

01 01 01 01 0101 SRTRTT(WR) Auto Self Refresh (Optional) Disabled: Manual Enabled: Automatic Self Refresh Temperature Normal (0°C to 85°C) Extended (0°C to 95°C) CAS Write Latency (CWL) 5 CK (tCK • 2.5ns) 6 CK (2.5ns > tCK • 1.875ns) 7 CK (1.875ns > tCK • 1.5ns) 8 CK (1.5ns > tCK • 1.25ns) 9 CK (1.25ns > tCK • 1.07ns) 10 CK (1.071ns > tCK • 0.938ns) Reserved Reserved M10 Dynamic ODT TT(WR) ) RTT(WR) disabled RZQ/4 (60ȍ NOM) RZQ/2 (120ȍ NOM) Reserved Notes: 1. MR2[17, 14:11, 8, and 2:0] are reserved for future use and must all be programmed to 0. 2. On die revision A, ASR is not available; MR2[6] must be programmed to 0 and, if operat- ing in self refresh mode above 85°C, MR2[7] (SRT) must be used. CAS WRITE Latency (CWL) CAS write latency (CWL) is defined by MR2[5:3] and is the delay, in clock cycles, from the releasing of the internal write to the latching of the first data in. CWL must be cor- rectly set to the corresponding operating clock frequency (see Figure 55). The overall WRITE latency (WL) is equal to CWL + AL (Figure 53 (page 138)). 2Gb: x4, x8, x16 DDR3 SDRAM Mode Register 2 (MR2) PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 142 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Figure 56: CAS WRITE Latency CK CK# Command DQ DQS, DQS# ACTIVE n T0 T1 Don’t Care NOP NOP T6 T12 NOPWRITE n T13 NOP DI n + 3 DI n + 2 DI n + 1 T14 NOP DI n tRCD (MIN) NOP AL = 5 T11 Indicates break in time scale WL = AL + CWL = 11 Transitioning Data CWL = 6 AUTO SELF REFRESH (ASR) Mode register MR2[6] is used to disable/enable the ASR function. When ASR is disabled, the self refresh mode’s refresh rate is assumed to be at the normal 85°C limit (some- times referred to as 1x refresh rate). In the disabled mode, ASR requires the user to en- sure the DRAM never exceeds a case temperature ( T C) of 85°C while in self refresh, un- less the user enables the SRT function when TC is between 85°C and 95°C. Enabling ASR assumes the DRAM self refresh rate is changed automatically from 1x to 2x when TC exceeds 85°C. This enables the user to operate the DRAM beyond the stand- ard 85°C limit up to the optional extended temperature range of 95°C while in self re- fresh mode. The standard self refresh current test specifies test conditions for normal T C (85°C) only, meaning that if ASR is enabled, the standard self refresh current specifications do not apply (see Extended Temperature Usage (page 179)). SELF REFRESH TEMPERATURE (SRT) Mode register MR2[7] is used to disable/enable the SRT function. When SRT is disabled, the self refresh mode’s refresh rate is assumed to be at the normal 85°C limit (some- times referred to as 1x refresh rate). In the disabled mode, SRT requires the user to en- sure the DRAM never exceeds a T C of 85°C while in self refresh mode, unless the user enables ASR. When SRT is enabled, the DRAM self refresh is changed internally from 1x to 2x, regard- less of TC. This enables the user to operate the DRAM beyond the standard 85°C limit up to the optional extended temperature range of 95°C while in self refresh mode. The standard self refresh current test specifies test conditions for normal T C (85°C) only, meaning that if SRT is enabled, the standard self refresh current specifications do not apply (see Extended Temperature Usage (page 179)). 2Gb: x4, x8, x16 DDR3 SDRAM Mode Register 2 (MR2) PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 143 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

If the normal TC limit of 85°C is not exceeded, then neither SRT nor ASR is required, and both can be disabled throughout operation. However, if the extended temperature op- tion of 95°C is needed, the user is required to provide a 2x refresh rate during manual refresh and to enable either the SRT or the ASR to ensure self refresh is performed at the 2x rate. SRT forces the DRAM to switch the internal self refresh rate from 1x to 2x. Self refresh is performed at the 2x refresh rate regardless of the case temperature. ASR automatically switches the DRAM’s internal self refresh rate from 1x to 2x. Howev- er, while in self refresh mode, ASR enables the refresh rate to automatically adjust be- tween 1x and 2x over the supported temperature range. One other disadvantage of ASR is the DRAM cannot always switch from a 1x to 2x refresh rate at an exact T C of 85°C. Although the DRAM will support data integrity when it switches from a 1x to 2x refresh rate, it may switch at a temperature lower than 85°C. Since only one mode is necessary, SRT and ASR cannot be enabled at the same time. Dynamic On-Die Termination (ODT) The dynamic ODT (RTT(WR)) feature is defined by MR2[10, 9]. Dynamic ODT is enabled when a value is selected for the dynamic ODT resistance RTT(WR). This new DDR3 SDRAM feature enables the ODT termination resistance value to change without issu- ing an MRS command, essentially changing the ODT termination on-the-fly. With dynamic ODT (R TT(WR)) enabled, the DRAM switches from nominal ODT (RTT ,nom) to dynamic ODT (RTT(WR)) when beginning a WRITE burst, and subsequently switches back to normal ODT (RTT ,nom) at the completion of the WRITE burst. If RTT ,nom is disa- bled, the RTT ,nom value will be High-Z. Special timing parameters must be adhered to when dynamic ODT (RTT(WR)) is enabled: ODTLcnw, ODTLcwn4, ODTLcwn8, ODTH4, ODTH8, and tADC. Dynamic ODT is only applicable during WRITE cycles. If normal ODT (RTT ,nom) is disa- bled, dynamic ODT (RTT(WR)) is still permitted. RTT ,nom and RTT(WR) can be used inde- pendent of one another. Dynamic ODT is not available during write leveling mode, re- gardless of the state of ODT (R TT ,nom). For details on dynamic ODT operation, refer to On-Die Termination (ODT) (page 190). 2Gb: x4, x8, x16 DDR3 SDRAM Mode Register 2 (MR2) PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 144 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Mode Register 3 (MR3) The mode register 3 (MR3) controls additional features and functions not available in the other mode registers. Currently defined is the MULTIPURPOSE REGISTER (MPR). This function is controlled via the bits shown in the figure below. The MR3 is program- med via the LOAD MODE command and retains the stored information until it is pro- grammed again or until the device loses power. Reprogramming the MR3 register will not alter the contents of the memory array, provided it is reprogrammed correctly. The MR3 register must be loaded when all banks are idle and no data bursts are in progress, and the controller must wait the specified time tMRD and tMOD before initiating a sub- sequent operation. Figure 57: Mode Register 3 (MR3) Definition A9 A7 A6 A5 A4 A3A8 A2 A1 A0 Mode register 3 (MR3) Address bus 97 6 5 4 382 1 0 A10A12 A11BA0BA1 101112131415 A13A14 0101 01 01 01 01 01 01 MPR 11 BA2 1617 01 01 01 01 01 MPR Enable Normal DRAM operations2 Dataflow from MPR MPR_RF M15 M16 Mode Register Mode register set (MR0) Mode register set 1 (MR1) Mode register set 2 (MR2) Mode register set 3 (MR3) MPR READ Function Predefined pattern3 Reserved Reserved Reserved Notes: 1. MR3[17 and 14:3] are reserved for future use and must all be programmed to 0. 2. When MPR control is set for normal DRAM operation, MR3[1, 0] will be ignored. 3. Intended to be used for READ synchronization. MULTIPURPOSE REGISTER (MPR) The MULTIPURPOSE REGISTER (MPR) function is used to output a predefined system timing calibration bit sequence. Bit 2 is the master bit that enables or disables access to the MPR register, and bits 1 and 0 determine which mode the MPR is placed in. The ba- sic concept of the multipurpose register is shown in Figure 58 (page 146). If MR3[2] = 0, then MPR access is disabled, and the DRAM operates in normal mode. However, if MR3[2] = 1, then the DRAM no longer outputs normal read data but outputs MPR data as defined by MR3[0, 1]. If MR3[0, 1] = 00, then a predefined read pattern for system calibration is selected. To enable the MPR, the MRS command is issued to MR3, and MR3[2] = 1. Prior to issu- ing the MRS command, all banks must be in the idle state (all banks are precharged, and tRP is met). When the MPR is enabled, any subsequent READ or RDAP commands are redirected to the multipurpose register. The resulting operation when a READ or RDAP command is issued, is defined by MR3[1:0] when the MPR is enabled (see Ta- ble 78 (page 147)). When the MPR is enabled, only READ or RDAP commands are al- lowed until a subsequent MRS command is issued with the MPR disabled (MR3[2] = 0). Power-down mode, self refresh, and any other non-READ/RDAP commands are not al- lowed during MPR enable mode. The RESET function is supported during MPR enable mode. 2Gb: x4, x8, x16 DDR3 SDRAM Mode Register 3 (MR3) PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 145 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Figure 58: MPR Block Diagram Memory core MR3[2] = 0 (MPR off) DQ, DM, DQS, DQS# Multipurpose register predefined data for READs MR3[2] = 1 (MPR on) Notes: 1. A predefined data pattern can be read out of the MPR with an external READ com- mand. 2. MR3[2] defines whether the data flow comes from the memory core or the MPR. When the data flow is defined, the MPR contents can be read out continuously with a regular READ or RDAP command. Table 77: MPR Functional Description of MR3 Bits MR3[2] MR3[1:0] FunctionMPR MPR READ Function 0 “Don’t Care” Normal operation, no MPR transaction All subsequent READs come from the DRAM memory array All subsequent WRITEs go to the DRAM memory array

1 A[1:0]

(see Table 78 (page 147)) Enable MPR mode, subsequent READ/RDAP commands defined by bits 1 and MPR Functional Description The JEDEC MPR definition enables either a prime DQ (DQ0 on x4 and x8; on x16, DQ0 = lower byte and DQ8 = upper byte) to output the MPR data with the remaining DQ driv- en LOW, or all DQ to output the MPR data. The MPR readout supports fixed READ burst and READ burst chop (MRS and OTF via A12/BC#) with regular READ latencies and AC timings applicable, provided the DLL is locked as required. MPR addressing for a valid MPR read is as follows:

• A[1:0] must be set to 00 as the burst order is fixed per nibble.
• A2 selects the burst order: BL8, A2 is set to 0, and the burst order is fixed to 0, 1, 2, 3, 4, 5, 6, 7.
• For burst chop 4 cases, the burst order is switched on the nibble base along with the following: – A2 = 0; burst order = 0, 1, 2, 3 – A2 = 1; burst order = 4, 5, 6, 7 2Gb: x4, x8, x16 DDR3 SDRAM Mode Register 3 (MR3) PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 146 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

• Burst order bit 0 (the first bit) is assigned to LSB, and burst order bit 7 (the last bit) is assigned to MSB.
• A[9:3] are “Don’t Care.”
• A10 is “Don’t Care.”
• A11 is “Don’t Care.”
• A12: Selects burst chop mode on-the-fly, if enabled within MR0.
• A13 is a “Don’t Care”
• BA[2:0] are “Don’t Care.” MPR Address Definitions and Bursting Order The MPR currently supports a single data format. This data format is a predefined read pattern for system calibration. The predefined pattern is always a repeating 01 bit pat- tern. Examples of the different types of predefined READ pattern bursts are shown in the fol- lowing figures. Table 78: MPR Readouts and Burst Order Bit Mapping MR3[2] MR3[1:0] Function Burst Length Read A[2:0] Burst Order and Data Pattern 1 00 READ predefined pattern for system calibration BL8 000 Burst order: 0, 1, 2, 3, 4, 5, 6, 7 Predefined pattern: 01010101 BC4 000 Burst order: 0, 1, 2, 3 Predefined pattern: 0101 BC4 100 Burst order: 4, 5, 6, 7 Predefined pattern: 0101 1 01 RFU n/a n/a n/a n/a n/a n/a n/a n/a n/a 1 10 RFU n/a n/a n/a n/a n/a n/a n/a n/a n/a 1 11 RFU n/a n/a n/a n/a n/a n/a n/a n/a n/a Note: 1. Burst order bit 0 is assigned to LSB and burst order bit 7 is assigned to MSB of the selec- ted MPR agent. 2Gb: x4, x8, x16 DDR3 SDRAM Mode Register 3 (MR3) PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 147 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Figure 59: MPR System Read Calibration with BL8: Fixed Burst Order Single Readout T0 Ta0 Tb0 Tb1 Tc0 Tc1 Tc2 Tc3 Tc4 Tc5 Tc6 Tc7 Tc8 Tc9 Tc10 CK CK# MRSPREA READ1 NOPNOP NOP NOP NOP NOP NOP NOP MRS NOP NOP ValidCommand tMPRR Don’t CareIndicates break in time scale DQS, DQS# Bank address 3 Valid 3 0A[1:0] Valid02 1A2 02 0 00A[9:3] Valid 00 01A10/AP Valid 0 0A11 Valid 0 0A12/BC# Valid1 0 0A[15:13] Valid 0 DQ tMODtRP tMOD RL Notes: 1. READ with BL8 either by MRS or OTF. 2. Memory controller must drive 0 on A[2:0]. 2Gb: x4, x8, x16 DDR3 SDRAM Mode Register 3 (MR3) PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 148 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Figure 60: MPR System Read Calibration with BL8: Fixed Burst Order, Back-to-Back Readout T0 Ta Tb Tc0 Tc1 Tc2 Tc3 Tc4 Tc5 Tc6 Tc7 Tc8 Tc9 Tc10 Td CK CK# tMPRR Don’t CareIndicates break in time scale RL

3 Valid 3Bank address Valid

A[1:0] Valid02020 A2 12021 0 0A[15:13] Valid Valid 0 A[9:3] Valid Valid 0000 A11 Valid Valid 00 A12/BC# Valid1 00 A10/AP Valid Valid 001 RL PREA READ1 NOP NOP NOP NOP NOP NOP NOP NOP NOP MRS ValidCommand READ1MRS DQ Valid DQS, DQS# tRP tMOD tCCD tMOD Notes: 1. READ with BL8 either by MRS or OTF. 2. Memory controller must drive 0 on A[2:0]. 2Gb: x4, x8, x16 DDR3 SDRAM Mode Register 3 (MR3) PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 149 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Figure 61: MPR System Read Calibration with BC4: Lower Nibble, Then Upper Nibble T0 Ta Tb CK CK# DQ DQS, DQS# tMODtMPRR Don’t Care Tc0 Tc1 Tc2 Tc3 Tc4 Tc5 Tc6 Tc7 Tc8 Tc9 Tc10 Td NOP NOP NOP NOP NOP MRS NOP NOP ValidCommand MRSPREA READ1 READ1 NOP NOP Indicates break in time scale Bank address 3 Valid 3Valid 0A[1:0] Valid0202 1A2 1403 0 00A[9:3] Valid Valid 00 01A10/AP Valid Valid 0 0A11 Valid Valid 0 0A12/BC# Valid1 Valid1 0 0A[15:13] Valid Valid 0 RL RL tRF tMOD tCCD Notes: 1. READ with BC4 either by MRS or OTF. 2. Memory controller must drive 0 on A[1:0]. 2Gb: x4, x8, x16 DDR3 SDRAM Mode Register 3 (MR3) PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 150 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Figure 62: MPR System Read Calibration with BC4: Upper Nibble, Then Lower Nibble T0 Ta Tb 01A10/AP Valid Valid 0 CK CK# MRSPREA READ1 READ1 NOP NOP NOP NOP NOP NOP NOP MRS NOP NOP ValidCommand 004131A2 tMODtMPRR 02020A[1:0] Valid 00A[15:13] Valid Valid 00A11 Valid Valid 0000A[9:3] Valid Valid Don’t Care Tc0 Tc1 Tc2 Tc3 Tc4 Tc5 Tc6 Tc7 Tc8 Tc9 Tc10 Td Indicates break in time scale RL DQ DQS, DQS# 0A12/BC# Valid1 Valid1 0 RL tRF tMOD tCCD Notes: 1. READ with BC4 either by MRS or OTF. 2. Memory controller must drive 0 on A[1:0]. 2Gb: x4, x8, x16 DDR3 SDRAM Mode Register 3 (MR3) PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 151 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

MPR Read Predefined Pattern The predefined read calibration pattern is a fixed pattern of 01010101. The following is an example of using the predetermined read calibration pattern. The example is to per- form multiple reads from the MPR to do system-level read timing calibration based on the predefined standard pattern. The following protocol outlines the steps used to perform the read calibration: 1. Precharge all banks. 2. After tRP is satisfied, set MRS, MR3[2] = 1 and MR3[1:0] = 00. This redirects all sub- sequent reads and loads the predefined pattern into the MPR. As soon as tMRD and tMOD are satisfied, the MPR is available. 3. Data WRITE operations are not allowed until the MPR returns to the normal DRAM state. 4. Issue a READ with burst order information (all other address pins are “Don’t Care”):

• A[1:0] = 00 (data burst order is fixed starting at nibble)
• A2 = 0 (for BL8, burst order is fixed as 0, 1, 2, 3, 4, 5, 6, 7)
• A12 = 1 (use BL8) 5. After RL = AL + CL, the DRAM bursts out the predefined read calibration pattern (01010101). 6. The memory controller repeats the calibration reads until read data capture at memory controller is optimized. 7. After the last MPR read burst and after tMPRR has been satisfied, issue MRS, MR3[2] = 0, and MR3[1:0] = “Don’t Care” to the normal DRAM state. All subse- quent read and write accesses will be regular reads and writes from/to the DRAM array. 8. When tMRD and tMOD are satisfied from the last MRS, the regular DRAM com- mands (such as activating a memory bank for regular read or write access) are per- mitted. MODE REGISTER SET (MRS) Command The mode registers are loaded via inputs BA[2:0], A[13:0]. BA[2:0] determine which mode register is programmed:
• BA2 = 0, BA1 = 0, BA0 = 0 for MR0
• BA2 = 0, BA1 = 0, BA0 = 1 for MR1
• BA2 = 0, BA1 = 1, BA0 = 0 for MR2
• BA2 = 0, BA1 = 1, BA0 = 1 for MR3 The MRS command can only be issued (or re-issued) when all banks are idle and in the precharged state ( tRP is satisfied and no data bursts are in progress). The controller must wait the specified time tMRD before initiating a subsequent operation such as an ACTIVATE command (see Figure 49 (page 133)). There is also a restriction after issuing an MRS command with regard to when the updated functions become available. This parameter is specified by tMOD. Both tMRD and tMOD parameters are shown in Fig- ure 49 (page 133) and Figure 50 (page 134). Violating either of these requirements will result in unspecified operation. 2Gb: x4, x8, x16 DDR3 SDRAM MODE REGISTER SET (MRS) Command PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 152 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

The ZQ CALIBRATION command is used to calibrate the DRAM output drivers (RON) and ODT values (RTT) over process, voltage, and temperature, provided a dedicated 240Ω (±1%) external resistor is connected from the DRAM’s ZQ ball to VSSQ. DDR3 SDRAM require a longer time to calibrate RON and ODT at power-up initialization and self refresh exit, and a relatively shorter time to perform periodic calibrations. DDR3 SDRAM defines two ZQ CALIBRATION commands: ZQCL and ZQCS. An example of ZQ calibration timing is shown below. All banks must be precharged and tRP must be met before ZQCL or ZQCS commands can be issued to the DRAM. No other activities (other than issuing another ZQCL or ZQCS command) can be performed on the DRAM channel by the controller for the du- ration of tZQinit or tZQoper. The quiet time on the DRAM channel helps accurately cali- brate RON and ODT . After DRAM calibration is achieved, the DRAM should disable the ZQ ball’s current consumption path to reduce power. ZQ CALIBRATION commands can be issued in parallel to DLL RESET and locking time. Upon self refresh exit, an explicit ZQCL is required if ZQ calibration is desired. In dual-rank systems that share the ZQ resistor between devices, the controller must not enable overlap of tZQinit, tZQoper, or tZQCS between ranks. Figure 63: ZQ CALIBRATION Timing (ZQCL and ZQCS) NOPZQCL NOP NOP Valid Valid ZQCS NOP NOP NOP ValidCommand Indicates break in time scale T0 T1 Ta0 Ta1 Ta2 Ta3 Tb0 Tb1 Tc0 Tc1 Tc2 Address Valid Valid Valid A10 Valid Valid Valid CK CK# Don’t Care DQ High-Z High-Z 33 Activities Activ- ities Valid ValidODT 2 2 Valid 1CKE 1 Valid Valid Valid tZQCStZQinit or tZQoper Notes: 1. CKE must be continuously registered HIGH during the calibration procedure. 2. ODT must be disabled via the ODT signal or the MRS during the calibration procedure. 3. All devices connected to the DQ bus should be High-Z during calibration. 2Gb: x4, x8, x16 DDR3 SDRAM ZQ CALIBRATION Operation PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 153 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Before any READ or WRITE commands can be issued to a bank within the DRAM, a row in that bank must be opened (activated). This is accomplished via the ACTIVATE com- mand, which selects both the bank and the row to be activated. After a row is opened with an ACTIVATE command, a READ or WRITE command may be issued to that row, subject to the tRCD specification. However, if the additive latency is programmed correctly, a READ or WRITE command may be issued prior to tRCD (MIN). In this operation, the DRAM enables a READ or WRITE command to be issued after the ACTIVATE command for that bank, but prior to tRCD (MIN) with the require- ment that (ACTIVATE-to-READ/WRITE) + AL ≥ tRCD (MIN) (see Posted CAS Additive Latency). tRCD (MIN) should be divided by the clock period and rounded up to the next whole number to determine the earliest clock edge after the ACTIVATE command on which a READ or WRITE command can be entered. The same procedure is used to con- vert other specification limits from time units to clock cycles. When at least one bank is open, any READ-to-READ command delay or WRITE-to- WRITE command delay is restricted to tCCD (MIN). A subsequent ACTIVATE command to a different row in the same bank can only be is- sued after the previous active row has been closed (precharged). The minimum time in- terval between successive ACTIVATE commands to the same bank is defined by tRC. A subsequent ACTIVATE command to another bank can be issued while the first bank is being accessed, which results in a reduction of total row-access overhead. The mini- mum time interval between successive ACTIVATE commands to different banks is de- fined by tRRD. No more than four bank ACTIVATE commands may be issued in a given tFAW (MIN) period, and the tRRD (MIN) restriction still applies. The tFAW (MIN) param- eter applies, regardless of the number of banks already opened or closed. Figure 64: Example: Meeting tRRD (MIN) and tRCD (MIN) Command Don’t Care T1T0 T2 T3 T4 T5 T8 T9 tRRD Row Row Col Bank x Bank y Bank y NOPACT NOP NOPACT NOP NOP RD/WR tRCD BA[2:0] CK# Address CK T10 T11 NOP NOP Indicates break in time scale 2Gb: x4, x8, x16 DDR3 SDRAM ACTIVATE Operation PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 154 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Figure 65: Example: tFAW Command Don’t Care T1T0 T4 T5 T8 T9 T10 T11 tRRD Row Row Bank a Bank b Row Bank c Row Bank d Bank y Row Bank y NOPACT NOPACT ACT NOP NOP tFAW BA[2:0] CK# Address CK T19 T20 NOPACT ACT Bank e Indicates break in time scale 2Gb: x4, x8, x16 DDR3 SDRAM ACTIVATE Operation PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 155 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

READ bursts are initiated with a READ command. The starting column and bank ad- dresses are provided with the READ command and auto precharge is either enabled or disabled for that burst access. If auto precharge is enabled, the row being accessed is automatically precharged at the completion of the burst. If auto precharge is disabled, the row will be left open after the completion of the burst. During READ bursts, the valid data-out element from the starting column address is available READ latency (RL) clocks later. RL is defined as the sum of posted CAS additive latency (AL) and CAS latency (CL) (RL = AL + CL). The value of AL and CL is programma- ble in the mode register via the MRS command. Each subsequent data-out element is valid nominally at the next positive or negative clock edge (that is, at the next crossing of CK and CK#). Figure 66 shows an example of RL based on a CL setting of 8 and an AL setting of 0. Figure 66: READ Latency CK CK# Command READ NOP NOP NOP NOP NOP NOP NOP Address Bank a, Col n CL = 8, AL = 0 DQ DQS, DQS# DO n T0 T7 T8 T9 T10 T11 Don’t CareTransitioning Data T12 T12 Indicates break in time scale Notes: 1. DO n = data-out from column n. 2. Subsequent elements of data-out appear in the programmed order following DO n. DQS, DQS# is driven by the DRAM along with the output data. The initial LOW state on DQS and HIGH state on DQS# is known as the READ preamble (tRPRE). The LOW state on DQS and the HIGH state on DQS#, coincident with the last data-out element, is known as the READ postamble ( tRPST). Upon completion of a burst, assuming no other commands have been initiated, the DQ goes High-Z. A detailed explanation of tDQSQ (valid data-out skew), tQH (data-out window hold), and the valid data window are de- picted in Figure 77 (page 164). A detailed explanation of tDQSCK (DQS transition skew to CK) is also depicted in Figure 77 (page 164). Data from any READ burst may be concatenated with data from a subsequent READ command to provide a continuous flow of data. The first data element from the new burst follows the last element of a completed burst. The new READ command should be issued tCCD cycles after the first READ command. This is shown for BL8 in Figure 67 (page 158). If BC4 is enabled, tCCD must still be met, which will cause a gap in the data output, as shown in Figure 68 (page 158). Nonconsecutive READ data is reflected in 2Gb: x4, x8, x16 DDR3 SDRAM READ Operation PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 156 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Figure 76: Data Output Timing – tDQSQ and Data Valid Window T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 Bank,Col n tRPST NOPREAD NOPNOP NOP NOP NOP NOP NOP NOP NOP CK CK# Command1 Address2 tDQSQ (MAX) DQS, DQS# DQ3 (last data valid) DQ3 (first data no longer valid) All DQ collectively DOn DOn + 3DOn + 2DOn + 1 DOn + 7DOn + 6DOn + 5DOn + 4 DOn + 2DOn + 1 DOn + 7DOn + 6DOn + 5DOn + 4 DO n + 3 DO n + 2 DO n + 1 DO n DO n + 7 DO n + 6 DO n + 5 DO n DOn + 3 tRPRE Don’t Care Data valid Data valid tQHtQH tHZDQ (MAX) DO n + 4 RL = AL + CL tDQSQ (MAX) tLZDQ (MIN) Notes: 1. NOP commands are shown for ease of illustration; other commands may be valid at these times. 2. The BL8 setting is activated by either MR0[1, 0] = 0, 0 or MR0[0, 1] = 0, 1 and A12 = 1 during READ command at T0. 3. DO n = data-out from column n. 4. BL8, RL = 5 (AL = 0, CL = 5). 5. Output timings are referenced to V DDQ/2 and DLL on and locked. 6. tDQSQ defines the skew between DQS, DQS# to data and does not define DQS, DQS# to CK. 7. Early data transitions may not always happen at the same DQ. Data transitions of a DQ can be early or late within a burst. 2Gb: x4, x8, x16 DDR3 SDRAM READ Operation PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 163 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

tHZ and tLZ transitions occur in the same access time as valid data transitions. These parameters are referenced to a specific voltage level that specifies when the device out- put is no longer driving tHZDQS and tHZDQ, or begins driving tLZDQS, tLZDQ. Fig- ure 78 (page 165) shows a method of calculating the point when the device is no longer driving tHZDQS and tHZDQ, or begins driving tLZDQS, tLZDQ, by measuring the signal at two different voltages. The actual voltage measurement points are not critical as long as the calculation is consistent. The parameters tLZDQS, tLZDQ, tHZDQS, and tHZDQ are defined as single-ended. Figure 77: Data Strobe Timing – READs RL measured to this point DQS, DQS# early strobe CK tLZDQS (MIN) tHZDQS (MIN) DQS, DQS# late strobe tLZDQS (MAX) tHZDQS (MAX)tDQSCK (MAX) tDQSCK (MAX) tDQSCK (MAX) tDQSCK (MAX) tDQSCK (MIN) tDQSCK (MIN) tDQSCK (MIN) tDQSCK (MIN) CK# tRPRE tQSH tQSHtQSL tQSL tQSL tQSLtQSH tQSH Bit 0 Bit 1 Bit 2 Bit 7 tRPRE Bit 0 Bit 1 Bit 2 Bit 7 Bit 6Bit 3 Bit 4 Bit 5 Bit 6Bit 4Bit 3 Bit 5 tRPST tRPST T0 T1 T2 T3 T4 T5 T6 2Gb: x4, x8, x16 DDR3 SDRAM READ Operation PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 164 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Figure 80: tRPST Timing tRPST DQS - DQS# DQS DQS# tRPST begins T2 tRPST ends Resulting differential signal relevant for tRPST specification CK CK# VTT tC tA tB tD Single-ended signal, provided as background information Single-ended signal, provided as background information VTT VTT 2Gb: x4, x8, x16 DDR3 SDRAM READ Operation PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 166 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

WRITE bursts are initiated with a WRITE command. The starting column and bank ad- dresses are provided with the WRITE command, and auto precharge is either enabled or disabled for that access. If auto precharge is selected, the row being accessed is pre- charged at the end of the WRITE burst. If auto precharge is not selected, the row will remain open for subsequent accesses. After a WRITE command has been issued, the WRITE burst may not be interrupted. For the generic WRITE commands used in Fig- ure 83 (page 169) through Figure 91 (page 174), auto precharge is disabled. During WRITE bursts, the first valid data-in element is registered on a rising edge of DQS following the WRITE latency (WL) clocks later and subsequent data elements will be registered on successive edges of DQS. WRITE latency (WL) is defined as the sum of posted CAS additive latency (AL) and CAS WRITE latency (CWL): WL = AL + CWL. The values of AL and CWL are programmed in the MR0 and MR2 registers, respectively. Prior to the first valid DQS edge, a full cycle is needed (including a dummy crossover of DQS, DQS#) and specified as the WRITE preamble shown in Figure 83 (page 169). The half cycle on DQS following the last data-in element is known as the WRITE postamble. The time between the WRITE command and the first valid edge of DQS is WL clocks tDQSS. Figure 84 (page 170) through Figure 91 (page 174) show the nominal case where tDQSS = 0ns; however, Figure 83 (page 169) includes tDQSS (MIN) and tDQSS (MAX) cases. Data may be masked from completing a WRITE using data mask. The data mask occurs on the DM ball aligned to the WRITE data. If DM is LOW, the WRITE completes normal- ly. If DM is HIGH, that bit of data is masked. Upon completion of a burst, assuming no other commands have been initiated, the DQ will remain High-Z, and any additional input data will be ignored. Data for any WRITE burst may be concatenated with a subsequent WRITE command to provide a continuous flow of input data. The new WRITE command can be tCCD clocks following the previous WRITE command. The first data element from the new burst is applied after the last element of a completed burst. Figure 84 (page 170) and Figure 85 (page 170) show concatenated bursts. An example of nonconsecutive WRITEs is shown in Figure 86 (page 171). Data for any WRITE burst may be followed by a subsequent READ command after tWTR has been met (see Figure 87 (page 171), Figure 88 (page 172), and Figure 89 (page 173)). Data for any WRITE burst may be followed by a subsequent PRECHARGE command, providing tWR has been met, as shown in Figure 90 (page 174) and Figure 91 (page 174). Both tWTR and tWR starting time may vary, depending on the mode register settings (fixed BC4, BL8 versus OTF). 2Gb: x4, x8, x16 DDR3 SDRAM WRITE Operation PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 167 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Figure 83: WRITE Burst DIn + 3DI n + 2DIn + 1DIn T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 Don’t CareTransitioning Data DIn + 7DI n + 6DIn + 5DIn + 4 Bank,Col n NOPWRITE NOPNOP NOP NOP NOP NOP NOP NOP NOP CK CK# Command1 DQ3 DQS, DQS# Address2 tWPST tWPRE tWPST tDQSL DQ3 DQ3 tWPST DQS, DQS# DQS, DQS# tDQSL tWPRE tDQSS tDQSS tDSH tDSH tDSH tDSH tDSS tDSS tDSS tDSS tDSS tDSS tDSS tDSS tDSS tDSS tDSH tDSH tDSH tDSH tDQSLtDQSH tDQSLtDQSH tDQSLtDQSH tDQSH tDQSL tDQSL tDQSL tDQSLtDQSHtDQSH tDQSH tDQSH tDQSLtDQSH tDQSLtDQSH tDQSH tDQSLtDQSH tDQSLtDQSH tDQSLtDQSH tDQSH WL = AL + CWL tDQSS (MIN) tDQSS (NOM) tDQSS (MAX) tDQSL tWPRE DI n + 3DI n + 2DI n + 1DI n DIn + 7DI n + 6DI n + 5DIn + 4 DIn + 3DIn + 2DIn + 1DI n DIn + 7DIn + 6DIn + 5DIn + 4 Notes: 1. NOP commands are shown for ease of illustration; other commands may be valid at these times. 2. The BL8 setting is activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during the WRITE command at T0. 3. DI n = data-in for column n. 4. BL8, WL = 5 (AL = 0, CWL = 5). tDQSS must be met at each rising clock edge. 6. tWPST is usually depicted as ending at the crossing of DQS, DQS#; however, tWPST ac- tually ends when DQS no longer drives LOW and DQS# no longer drives HIGH. 2Gb: x4, x8, x16 DDR3 SDRAM WRITE Operation PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 169 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Figure 88: WRITE to READ (BC4 Mode Register Setting) WL = 5 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 Ta0 Don’t CareTransitioning Data NOPWRITE Valid READ Valid NOP NOP NOP NOP NOP NOP NOPNOP CK CK# Command1 DQ4 DQS, DQS# Address3 tWPST tWTR2 tWPRE Indicates break in time scale DIn + 3DIn + 2DIn + 1DIn Notes: 1. NOP commands are shown for ease of illustration; other commands may be valid at these times. 2. tWTR controls the WRITE-to-READ delay to the same device and starts with the first rising clock edge after the last write data shown at T7. 3. The fixed BC4 setting is activated by MR0[1:0] = 10 during the WRITE command at T0 and the READ command at Ta0. 4. DI n = data-in for column n. 5. BC4 (fixed), WL = 5 (AL = 0, CWL = 5), RL = 5 (AL = 0, CL = 5). 2Gb: x4, x8, x16 DDR3 SDRAM WRITE Operation PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 172 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Figure 89: WRITE (BC4 OTF) to READ (BC4 OTF) WL = 5 RL = 5 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 tWPRE T10 T11 Don’t CareTransitioning Data Tn NOPWRITE READ ValidValid NOP NOP NOP NOP NOP NOP NOP NOPNOP CK CK# Command1 DQ4 DQS, DQS# Address3 tWPST tBL = 4 clocks NOP tWTR2 Indicates break in time scale DIn + 3DIn + 2DIn + 1DIn Notes: 1. NOP commands are shown for ease of illustration; other commands may be valid at these times. 2. tWTR controls the WRITE-to-READ delay to the same device and starts after tBL. 3. The BC4 OTF setting is activated by MR0[1:0] = 01 and A12 = 0 during the WRITE command at T0 and the READ command at Tn. 4. DI n = data-in for column n. 5. BC4, RL = 5 (AL = 0, CL = 5), WL = 5 (AL = 0, CWL = 5). 2Gb: x4, x8, x16 DDR3 SDRAM WRITE Operation PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 173 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Figure 93: Data Input Timing tDH tDHtDS tDS DM DQ DI b DQS, DQS# Don’t CareTransitioning Data tDQSH tDQSLtWPRE tWPST 2Gb: x4, x8, x16 DDR3 SDRAM WRITE Operation PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 176 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Input A10 determines whether one bank or all banks are to be precharged and, in the case where only one bank is to be precharged, inputs BA[2:0] select the bank. When all banks are to be precharged, inputs BA[2:0] are treated as “Don’t Care.” After a bank is precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued. SELF REFRESH Operation The SELF REFRESH operation is initiated like a REFRESH command except CKE is LOW . The DLL is automatically disabled upon entering SELF REFRESH and is automatically enabled and reset upon exiting SELF REFRESH. All power supply inputs (including V REFCA and VREFDQ) must be maintained at valid lev- els upon entry/exit and during self refresh mode operation. VREFDQ may float or not drive VDDQ/2 while in self refresh mode under certain conditions:

• V SS < VREFDQ < VDD is maintained.
• V REFDQ is valid and stable prior to CKE going back HIGH.
• The first WRITE operation may not occur earlier than 512 clocks after V REFDQ is valid.
• All other self refresh mode exit timing requirements are met. The DRAM must be idle with all banks in the precharge state (tRP is satisfied and no bursts are in progress) before a self refresh entry command can be issued. ODT must also be turned off before self refresh entry by registering the ODT ball LOW prior to the self refresh entry command (see On-Die Termination (ODT) (page 190) for timing re- quirements). If R TT ,nom and RTT(WR) are disabled in the mode registers, ODT can be a “Don’t Care.” After the self refresh entry command is registered, CKE must be held LOW to keep the DRAM in self refresh mode. After the DRAM has entered self refresh mode, all external control signals, except CKE and RESET#, are “Don’t Care.” The DRAM initiates a minimum of one REFRESH com- mand internally within the tCKE period when it enters self refresh mode. The requirements for entering and exiting self refresh mode depend on the state of the clock during self refresh mode. First and foremost, the clock must be stable (meeting tCK specifications) when self refresh mode is entered. If the clock remains stable and the frequency is not altered while in self refresh mode, then the DRAM is allowed to exit self refresh mode after tCKESR is satisfied (CKE is allowed to transition HIGH tCKESR later than when CKE was registered LOW). Since the clock remains stable in self refresh mode (no frequency change), tCKSRE and tCKSRX are not required. However, if the clock is altered during self refresh mode (if it is turned-off or its frequency changes), then tCKSRE and tCKSRX must be satisfied. When entering self refresh mode, tCKSRE must be satisfied prior to altering the clock's frequency. Prior to exiting self refresh mode, tCKSRX must be satisfied prior to registering CKE HIGH. When CKE is HIGH during self refresh exit, NOP or DES must be issued for tXS time. tXS is required for the completion of any internal refresh already in progress and must be satisfied before a valid command not requiring a locked DLL can be issued to the de- vice. tXS is also the earliest time self refresh re-entry may occur. Before a command re- quiring a locked DLL can be applied, a ZQCL command must be issued, tZQOPER tim- ing must be met, and tXSDLL must be satisfied. ODT must be off during tXSDLL. 2Gb: x4, x8, x16 DDR3 SDRAM PRECHARGE Operation PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 177 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Figure 94: Self Refresh Entry/Exit Timing CK CK# Command NOP NOP4SRE (REF)3 Address CKE ODT2 RESET#2 Valid Valid6SRX (NOP) NOP5 tRP8 tXSDLL7, 9 ODTL tIStCPDEDtIS tIS Enter self refresh mode (synchronous) Exit self refresh mode (asynchronous) T0 T1 T2 Tc0 Tc1 Td0 Tb0 Don’t Care Te0 Valid Valid7 Valid Valid Valid tIH Ta0 Tf0 Indicates break in time scale tCKSRX1tCKSRE1 tXS6, 9 tCKESR (MIN)1 Notes: 1. The clock must be valid and stable, meeting tCK specifications at least tCKSRE after en- tering self refresh mode, and at least tCKSRX prior to exiting self refresh mode, if the clock is stopped or altered between states Ta0 and Tb0. If the clock remains valid and unchanged from entry and during self refresh mode, then tCKSRE and tCKSRX do not apply; however, tCKESR must be satisfied prior to exiting at SRX. 2. ODT must be disabled and R TT off prior to entering self refresh at state T1. If both RTT,nom and RTT(WR) are disabled in the mode registers, ODT can be a “Don’t Care.” 3. Self refresh entry (SRE) is synchronous via a REFRESH command with CKE LOW. 4. A NOP or DES command is required at T2 after the SRE command is issued prior to the inputs becoming “Don’t Care.” 5. NOP or DES commands are required prior to exiting self refresh mode until state Te0. tXS is required before any commands not requiring a locked DLL. 7. tXSDLL is required before any commands requiring a locked DLL. 8. The device must be in the all banks idle state prior to entering self refresh mode. For example, all banks must be precharged, tRP must be met, and no data bursts can be in progress. 9. Self refresh exit is asynchronous; however, tXS and tXSDLL timings start at the first rising clock edge where CKE HIGH satisfies tISXR at Tc1. tCKSRX timing is also measured so that tISXR is satisfied at Tc1. 2Gb: x4, x8, x16 DDR3 SDRAM SELF REFRESH Operation PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 178 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Extended Temperature Usage Micron’s DDR3 SDRAM support the optional extended case temperature (TC) range of 0°C to 95°C. Thus, the SRT and ASR options must be used at a minimum. The extended temperature range DRAM must be refreshed externally at 2x (double re- fresh) anytime the case temperature is above 85°C (and does not exceed 95°C). The ex- ternal refresh requirement is accomplished by reducing the refresh period from 64ms to 32ms. However, self refresh mode requires either ASR or SRT to support the extended temperature. Thus, either ASR or SRT must be enabled when T C is above 85°C or self refresh cannot be used until TC is at or below 85°C. Table 79 summarizes the two exten- ded temperature options and Table 80 summarizes how the two extended temperature options relate to one another. Table 79: Self Refresh Temperature and Auto Self Refresh Description Field MR2 Bits Description Self Refresh Temperature (SRT) SRT 7 If ASR is disabled (MR2[6] = 0), SRT must be programmed to indicate T OPER during self refresh: *MR2[7] = 0: Normal operating temperature range (0°C to 85°C) *MR2[7] = 1: Extended operating temperature range (0°C to 95°C) If ASR is enabled (MR2[7] = 1), SRT must be set to 0, even if the extended temperature range is supported *MR2[7] = 0: SRT is disabled Auto Self Refresh (ASR) ASR 6 When ASR is enabled, the DRAM automatically provides SELF REFRESH power management func- tions, (refresh rate for all supported operating temperature values) * MR2[6] = 1: ASR is enabled (M7 must = 0) When ASR is not enabled, the SRT bit must be programmed to indicate T OPER during SELF REFRESH operation * MR2[6] = 0: ASR is disabled; must use manual self refresh temperature (SRT) Table 80: Self Refresh Mode Summary MR2[6] (ASR) MR2[7] (SRT) SELF REFRESH Operation Permitted Operating Temperature Range for Self Refresh Mode 0 0 Self refresh mode is supported in the normal temperature range Normal (0°C to 85°C) 0 1 Self refresh mode is supported in normal and extended temper- ature ranges; When SRT is enabled, it increases self refresh power consumption Normal and extended (0°C to 95°C) 1 0 Self refresh mode is supported in normal and extended temper- ature ranges; Self refresh power consumption may be tempera- ture-dependent Normal and extended (0°C to 95°C) 1 1 Illegal 2Gb: x4, x8, x16 DDR3 SDRAM Extended Temperature Usage PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 179 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Power-down is synchronously entered when CKE is registered LOW coincident with a NOP or DES command. CKE is not allowed to go LOW while an MRS, MPR, ZQCAL, READ, or WRITE operation is in progress. CKE is allowed to go LOW while any of the other legal operations (such as ROW ACTIVATION, PRECHARGE, auto precharge, or RE- FRESH) are in progress. However, the power-down I DD specifications are not applicable until such operations have completed. Depending on the previous DRAM state and the command issued prior to CKE going LOW, certain timing constraints must be satisfied (as noted in Table 81). Timing diagrams detailing the different power-down mode entry and exits are shown in Figure 95 (page 182) through Figure 104 (page 187). Table 81: Command to Power-Down Entry Parameters DRAM Status Last Command Prior to CKE LOW1 Parameter (Min) Parameter Value Figure Idle or active ACTIVATE tACTPDEN 1 tCK Figure 102 (page 186) Idle or active PRECHARGE tPRPDEN 1 tCK Figure 103 (page 186) Active READ or READAP tRDPDEN RL + 4 tCK + 1tCK Figure 98 (page 184) Active WRITE: BL8OTF, BL8MRS, BC4OTF tWRPDEN WL + 4 tCK + tWR/tCK Figure 99 (page 184) Active WRITE: BC4MRS WL + 2 tCK + tWR/tCK Figure 99 (page 184) Active WRITEAP: BL8OTF, BL8MRS, BC4OTF tWRAPDEN WL + 4 tCK + WR + 1tCK Figure 100 (page 185) Active WRITEAP: BC4MRS WL + 2 tCK + WR + 1tCK Figure 100 (page 185) Idle REFRESH tREFPDEN 1 tCK Figure 101 (page 185) Power-down REFRESH tXPDLL Greater of 10 tCK or 24ns Figure 105 (page 187) Idle MODE REGISTER SET tMRSPDEN tMOD Figure 104 (page 187) Note: 1. If slow-exit mode precharge power-down is enabled and entered, ODT becomes asyn- chronous tANPD prior to CKE going LOW and remains asynchronous until tANPD + tXPDLL after CKE goes HIGH. Entering power-down disables the input and output buffers, excluding CK, CK#, ODT , CKE, and RESET#. NOP or DES commands are required until tCPDED has been satis- fied, at which time all specified input/output buffers are disabled. The DLL should be in a locked state when power-down is entered for the fastest power-down exit timing. If the DLL is not locked during power-down entry, the DLL must be reset after exiting power-down mode for proper READ operation as well as synchronous ODT operation. During power-down entry, if any bank remains open after all in-progress commands are complete, the DRAM will be in active power-down mode. If all banks are closed after all in-progress commands are complete, the DRAM will be in precharge power-down mode. Precharge power-down mode must be programmed to exit with either a slow exit mode or a fast exit mode. When entering precharge power-down mode, the DLL is turned off in slow exit mode or kept on in fast exit mode. The DLL also remains on when entering active power-down. ODT has special timing constraints when slow exit mode precharge power-down is enabled and entered. Refer to Asynchronous ODT Mode (page 203) for detailed ODT usage requirements in slow 2Gb: x4, x8, x16 DDR3 SDRAM Power-Down Mode PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 180 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

exit mode precharge power-down. A summary of the two power-down modes is listed in Table 82 (page 181). While in either power-down state, CKE is held LOW, RESET# is held HIGH, and a stable clock signal must be maintained. ODT must be in a valid state but all other input signals are “Don’t Care.” If RESET# goes LOW during power-down, the DRAM will switch out of power-down mode and go into the reset state. After CKE is registered LOW, CKE must remain LOW until tPD (MIN) has been satisfied. The maximum time allowed for power- down duration is tPD (MAX) (9 × tREFI). The power-down states are synchronously exited when CKE is registered HIGH (with a required NOP or DES command). CKE must be maintained HIGH until tCKE has been satisfied. A valid, executable command may be applied after power-down exit latency, tXP , and tXPDLL have been satisfied. A summary of the power-down modes is listed be- low. For specific CKE-intensive operations, such as repeating a power-down-exit-to-refresh- to-power-down-entry sequence, the number of clock cycles between power-down exit and power-down entry may not be sufficient to keep the DLL properly updated. In addi- tion to meeting tPD when the REFRESH command is used between power-down exit and power-down entry, two other conditions must be met. First, tXP must be satisfied before issuing the REFRESH command. Second, tXPDLL must be satisfied before the next power-down may be entered. An example is shown in Figure 105 (page 187). Table 82: Power-Down Modes DRAM State MR0[12] DLL State Power- Down Exit Relevant Parameters Active (any bank open) “Don’t Care” On Fast tXP to any other valid command Precharged (all banks precharged)

1 On Fast tXP to any other valid command

0 Off Slow tXPDLL to commands that require the DLL to be

locked (READ, RDAP, or ODT on); tXP to any other valid command 2Gb: x4, x8, x16 DDR3 SDRAM Power-Down Mode PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 181 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Figure 95: Active Power-Down Entry and Exit CK CK# Command NOP NOP NOP NOP Address CKE tCK tCH tCL Enter power-down mode Exit power-down mode Don’t Care ValidValid Valid tCPDED Valid tIS tIH tIH tIS T0 T1 T2 Ta0 Ta1 Ta2 Ta3 Ta4 NOP tXP tCKE (MIN) Indicates break in time scale tPD 2Gb: x4, x8, x16 DDR3 SDRAM Power-Down Mode PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 182 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

The RESET signal (RESET#) is an asynchronous reset signal that triggers any time it drops LOW, and there are no restrictions about when it can go LOW . After RESET# goes LOW, it must remain LOW for 100ns. During this time, the outputs are disabled, ODT TT) turns off (High-Z), and the DRAM resets itself. CKE should be driven LOW prior to RESET# being driven HIGH. After RESET# goes HIGH, the DRAM must be re-initialized as though a normal power-up was executed. All refresh counters on the DRAM are reset, and data stored in the DRAM is assumed unknown after RESET# has gone LOW . 2Gb: x4, x8, x16 DDR3 SDRAM RESET Operation PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 188 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Figure 106: RESET Sequence T = 10ns (MIN) T = 100ns (MIN) T = 500μs (MIN) tXPR tMRD tMRD tMRD tMOD tCK tIOZ = 20ns CKE RTT BA[2:0] All voltage supplies valid and stable High-Z DM DQS High-Z Address A10 CK CK# tCL Command NOP T0 Ta0 Don’t Care tCL ODT DQ High-Z Tb0 tDLLK MR1 with DLL ENABLE MRSMRS BA0 = H BA1 = L BA2 = L BA0 = L BA1 = L BA2 = L Code Code Code Code Valid Valid Valid Valid Normal operation MR2 MR3 MRSMRS BA0 = L BA1 = H BA2 = L BA0 = H BA1 = H BA2 = L Code Code Code Code Tc0 Td0 RESET# Stable and valid clock Valid DRAM ready for external commands tZQinit A10 = H ZQCL tIS Valid System RESET (warm boot) ZQCALMR0 with DLL RESET Indicates break in time scale t CKSRX1 tIS tIS tIS Static LOW in case RTT_Nom is enabled at time Ta0, otherwise static HIGH or LOW Note: 1. The minimum time required is the longer of 10ns or 5 clocks. 2Gb: x4, x8, x16 DDR3 SDRAM RESET Operation PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 189 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

On-Die Termination (ODT) On-die termination (ODT) is a feature that enables the DRAM to enable/disable and turn on/off termination resistance for each DQ, DQS, DQS#, and DM for the x4 and x8 configurations (and TDQS, TDQS# for the x8 configuration, when enabled). ODT is ap- plied to each DQ, UDQS, UDQS#, LDQS, LDQS#, UDM, and LDM signal for the x16 con- figuration. ODT is designed to improve signal integrity of the memory channel by enabling the DRAM controller to independently turn on/off the DRAM’s internal termination resist- ance for any grouping of DRAM devices. ODT is not supported during DLL disable mode (simple functional representation shown below). The switch is enabled by the in- ternal ODT control logic, which uses the external ODT ball and other control informa- tion. Figure 107: On-Die Termination ODT VDDQ/2 RTT Switch DQ, DQS, DQS#, DM, TDQS, TDQS# To other circuitry such as RCV, . . . Functional Representation of ODT The value of RTT (ODT termination resistance value) is determined by the settings of several mode register bits (see Table 87 (page 193)). The ODT ball is ignored while in self refresh mode (must be turned off prior to self refresh entry) or if mode registers MR1 and MR2 are programmed to disable ODT . ODT is comprised of nominal ODT and dynamic ODT modes and either of these can function in synchronous or asynchronous mode (when the DLL is off during precharge power-down or when the DLL is synchro- nizing). Nominal ODT is the base termination and is used in any allowable ODT state. Dynamic ODT is applied only during writes and provides OTF switching from no R TT or RTT ,nom to RTT(WR). The actual effective termination, RTT(EFF), may be different from RTT targeted due to nonlinearity of the termination. For RTT(EFF) values and calculations, see ODT Charac- teristics (page 54). Nominal ODT ODT (NOM) is the base termination resistance for each applicable ball; it is enabled or disabled via MR1[9, 6, 2] (see Mode Register 1 (MR1) Definition), and it is turned on or off via the ODT ball. 2Gb: x4, x8, x16 DDR3 SDRAM On-Die Termination (ODT) PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 190 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Table 83: Truth Table – ODT (Nominal) Note 1 applies to the entire table MR1[9, 6, 2] ODT Pin DRAM Termination State DRAM State Notes 000 0 R TT,nom disabled, ODT off Any valid 2 000 1 R TT,nom disabled, ODT on Any valid except self refresh, read 3 000–101 0 R TT,nom enabled, ODT off Any valid 2 000–101 1 R TT,nom enabled, ODT on Any valid except self refresh, read 3 110 and 111 X R TT,nom reserved, ODT on or off Illegal Notes: 1. Assumes dynamic ODT is disabled (see Dynamic ODT (page 192) when enabled). 2. ODT is enabled and active during most writes for proper termination, but it is not illegal for it to be off during writes. 3. ODT must be disabled during reads. The R TT,nom value is restricted during writes. Dynam- ic ODT is applicable if enabled. Nominal ODT resistance RTT ,nom is defined by MR1[9, 6, 2], as shown in Mode Register 1 (MR1) Definition. The RTT ,nom termination value applies to the output pins previously mentioned. DDR3 SDRAM supports multiple RTT ,nom values based on RZQ/n where n can be 2, 4, 6, 8, or 12 and RZQ is 240Ω. RTT ,nom termination is allowed any time after the DRAM is initialized, calibrated, and not performing read access, or when it is not in self refresh mode. Write accesses use R TT ,nom if dynamic ODT (RTT(WR)) is disabled. If RTT ,nom is used dur- ing writes, only RZQ/2, RZQ/4, and RZQ/6 are allowed (see Table 87 (page 193)). ODT timings are summarized in Table 84 (page 191), as well as listed in Table 56 (page 76). Examples of nominal ODT timing are shown in conjunction with the synchronous mode of operation in Synchronous ODT Mode (page 198). Table 84: ODT Parameters Symbol Description Begins at Defined to Definition for All DDR3 Speed Bins Unit ODTLon ODT synchronous turn-on delay ODT registered HIGH R TT(ON) ±tAON CWL + AL - 2 tCK ODTLoff ODT synchronous turn-off delay ODT registered HIGH R TT(OFF) ±tAOF CWL + AL - 2 tCK tAONPD ODT asynchronous turn-on delay ODT registered HIGH R TT(ON) 2–8.5 ns tAOFPD ODT asynchronous turn-off delay ODT registered HIGH R TT(OFF) 2–8.5 ns ODTH4 ODT minimum HIGH time after ODT assertion or write (BC4) ODT registered HIGH or write registration with ODT HIGH ODT registered LOW 4tCK tCK ODTH8 ODT minimum HIGH time after write (BL8) Write registration with ODT HIGH ODT registered LOW 6tCK tCK tAON ODT turn-on relative to ODTLon completion Completion of ODTLon RTT(ON) See Table 56 (page 76) ps tAOF ODT turn-off relative to ODTLoff completion Completion of ODTLoff RTT(OFF) 0.5tCK ± 0.2tCK tCK 2Gb: x4, x8, x16 DDR3 SDRAM On-Die Termination (ODT) PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 191 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

In certain application cases, and to further enhance signal integrity on the data bus, it is desirable that the termination strength of the DDR3 SDRAM can be changed without issuing an MRS command, essentially changing the ODT termination on the fly. With dynamic ODT R TT(WR)) enabled, the DRAM switches from nominal ODT RTT ,nom) to dy- namic ODT RTT(WR)) when beginning a WRITE burst and subsequently switches back to nominal ODT RTT ,nom) at the completion of the WRITE burst. This requirement is sup- ported by the dynamic ODT feature, as described below. Dynamic ODT Special Use Case When DDR3 devices are architect as a single rank memory array, dynamic ODT offers a special use case: the ODT ball can be wired high (via a current limiting resistor prefer- red) by having R TT ,nom disabled via MR1 and RTT(WR) enabled via MR2. This will allow the ODT signal not to have to be routed yet the DRAM can provide ODT coverage dur- ing write accesses. When enabling this special use case, some standard ODT spec conditions may be viola- ted: ODT is sometimes suppose to be held low. Such ODT spec violation (ODT not LOW) is allowed under this special use case. Most notably, if Write Leveling is used, this would appear to be a problem since R TT(WR) can not be used (should be disabled) and RTT(NOM) should be used. For Write leveling during this special use case, with the DLL locked, then RTT(NOM) maybe enabled when entering Write Leveling mode and disabled when exiting Write Leveling mode. More so, RTT(NOM) must be enabled when enabling Write Leveling, via same MR1 load, and disabled when disabling Write Leveling, via same MR1 load if R TT(NOM) is to be used. ODT will turn-on within a delay of ODTLon + tAON + tMOD + 1CK (enabling via MR1) or turn-off within a delay of ODTLoff + tAOF + tMOD + 1CK. As seen in the table below, between the Load Mode of MR1 and the previously specified delay, the value of ODT is uncertain. this means the DQ ODT termination could turn-on and then turn-off again during the period of stated uncertainty. Table 85: Write Leveling with Dynamic ODT Special Case Begin RTT,nom Uncertainty End RTT,nom Uncertainty I/Os RTT,nom Final State MR1 load mode command: Enable Write Leveling and RTT(NOM) ODTLon + tAON + tMOD + 1CK DQS, DQS# Drive R TT,nom value DQs No R TT,nom MR1 load mode command: Disable Write Leveling and RTT(NOM) ODTLoff + tAOFF + tMOD + 1CK DQS, DQS# No R TT,nom DQs No R TT,nom Functional Description The dynamic ODT mode is enabled if either MR2[9] or MR2[10] is set to 1. Dynamic ODT is not supported during DLL disable mode so RTT(WR) must be disabled. The dy- namic ODT function is described below:

• Two R TT values are available—RTT ,nom and RTT(WR). – The value for R TT ,nom is preselected via MR1[9, 6, 2]. – The value for R TT(WR) is preselected via MR2[10, 9]. 2Gb: x4, x8, x16 DDR3 SDRAM Dynamic ODT PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 192 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

• During DRAM operation without READ or WRITE commands, the termination is con- trolled. – Nominal termination strength R TT ,nom is used. – Termination on/off timing is controlled via the ODT ball and latencies ODTLon and ODTLoff.
• When a WRITE command (WR, WRAP , WRS4, WRS8, WRAPS4, WRAPS8) is registered, and if dynamic ODT is enabled, the ODT termination is controlled. – A latency of ODTLcnw after the WRITE command: termination strength R TT ,nom switches to RTT(WR) – A latency of ODTLcwn8 (for BL8, fixed or OTF) or ODTLcwn4 (for BC4, fixed or OTF) after the WRITE command: termination strength RTT(WR) switches back to RTT ,nom. – On/off termination timing is controlled via the ODT ball and determined by ODT- Lon, ODTLoff, ODTH4, and ODTH8. – During the tADC transition window, the value of RTT is undefined. ODT is constrained during writes and when dynamic ODT is enabled (see Table 86 (page 193)). ODT timings listed in Table 84 (page 191) also apply to dynamic ODT mode. Table 86: Dynamic ODT Specific Parameters Symbol Description Begins at Defined to Definition for All DDR3 Speed Bins Unit ODTLcnw Change from R TT,nom to RTT(WR) Write registration R TT switched from RTT,nom to RTT(WR) WL - 2 tCK ODTLcwn4 Change from R TT(WR) to RTT,nom (BC4) Write registration R TT switched from RTT(WR) to RTT,nom 4tCK + ODTL off tCK ODTLcwn8 Change from R TT(WR) to RTT,nom (BL8) Write registration R TT switched from RTT(WR) to RTT,nom 6tCK + ODTL off tCK tADC R TT change skew ODTLcnw completed R TT transition complete 0.5 tCK ± 0.2tCK tCK Table 87: Mode Registers for RTT,nom MR1 (RTT,nom) RTT,nom (RZQ) RTT,nom (Ohm) RTT,nom Mode RestrictionM9 M6 M2 0 0 0 Off Off n/a 0 0 1 RZQ/4 60 Self refresh 0 1 0 RZQ/2 120 0 1 1 RZQ/6 40 1 0 0 RZQ/12 20 Self refresh, write 1 0 1 RZQ/8 30 1 1 0 Reserved Reserved n/a 1 1 1 Reserved Reserved n/a Note: 1. RZQ = 240 Ω. If RTT,nom is used during WRITEs, only RZQ/2, RZQ/4, RZQ/6 are allowed. 2Gb: x4, x8, x16 DDR3 SDRAM Dynamic ODT PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 193 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Figure 110: Dynamic ODT: ODT Pin Asserted Together with WRITE Command for 6 Clock Cycles, BL8 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 ODTLcwn8 ODTLon ODTLcnw WL tAOF (MAX) T10 T11 CK CK# Address RTT ODT DQ DQS, DQS# DIb + 3DIb + 2DIb + 1DIb DIb + 7DIb + 6DIb + 5DI b + 4 Valid Don’t CareTransitioning Command WRS8NOP NOPNOP NOP NOP NOP NOP NOP NOP NOP NOP RTT(WR) ODTH8 ODTLoff tADC (MAX) tAON (MIN) tAOF (MIN) Notes: 1. Via MRS or OTF; AL = 0, CWL = 5. If R TT,nom can be either enabled or disabled, ODT can be HIGH. RTT(WR) is enabled. 2. In this example, ODTH8 = 6 is satisfied exactly. 2Gb: x4, x8, x16 DDR3 SDRAM Dynamic ODT PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 196 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Synchronous ODT mode is selected whenever the DLL is turned on and locked and when either RTT ,nom or RTT(WR) is enabled. Based on the power-down definition, these modes are:

• Any bank active with CKE HIGH
• Refresh mode with CKE HIGH
• Idle mode with CKE HIGH
• Active power-down mode (regardless of MR0[12])
• Precharge power-down mode if DLL is enabled by MR0[12] during precharge power- down ODT Latency and Posted ODT In synchronous ODT mode, RTT turns on ODTLon clock cycles after ODT is sampled HIGH by a rising clock edge and turns off ODTLoff clock cycles after ODT is registered LOW by a rising clock edge. The actual on/off times varies by tAON and tAOF around each clock edge (see Table 90 (page 199)). The ODT latency is tied to the WRITE latency (WL) by ODTLon = WL - 2 and ODTLoff = WL - 2. Since write latency is made up of CAS WRITE latency (CWL) and additive latency (AL), the AL programmed into the mode register (MR1[4, 3]) also applies to the ODT signal. The device’s internal ODT signal is delayed a number of clock cycles defined by the AL relative to the external ODT signal. Thus, ODTLon = CWL + AL - 2 and ODTLoff = CWL + AL - 2. Timing Parameters Synchronous ODT mode uses the following timing parameters: ODTLon, ODTLoff, ODTH4, ODTH8, tAON, and tAOF . The minimum RTT turn-on time (tAON [MIN]) is the point at which the device leaves High-Z and ODT resistance begins to turn on. Maxi- mum R TT turn-on time (tAON [MAX]) is the point at which ODT resistance is fully on. Both are measured relative to ODTLon. The minimum RTT turn-off time (tAOF [MIN]) is the point at which the device starts to turn off ODT resistance. The maximum RTT turn off time (tAOF [MAX]) is the point at which ODT has reached High-Z. Both are measured from ODTLoff. When ODT is asserted, it must remain HIGH until ODTH4 is satisfied. If a WRITE com- mand is registered by the DRAM with ODT HIGH, then ODT must remain HIGH until ODTH4 (BC4) or ODTH8 (BL8) after the WRITE command (see Figure 114 (page 200)). ODTH4 and ODTH8 are measured from ODT registered HIGH to ODT registered LOW or from the registration of a WRITE command until ODT is registered LOW . 2Gb: x4, x8, x16 DDR3 SDRAM Synchronous ODT Mode PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 198 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Table 90: Synchronous ODT Parameters Symbol Description Begins at Defined to Definition for All DDR3 Speed Bins Unit ODTLon ODT synchronous turn-on delay ODT registered HIGH R TT(ON) ±tAON CWL + AL - 2 tCK ODTLoff ODT synchronous turn-off delay ODT registered HIGH R TT(OFF) ±tAOF CWL +AL - 2 tCK ODTH4 ODT minimum HIGH time after ODT assertion or WRITE (BC4) ODT registered HIGH or write regis- tration with ODT HIGH ODT registered LOW 4 tCK tCK ODTH8 ODT minimum HIGH time after WRITE (BL8) Write registration with ODT HIGH ODT registered LOW 6 tCK tCK tAON ODT turn-on relative to ODTLon completion Completion of ODTLon R TT(ON) See Table 56 (page 76) ps tAOF ODT turn-off relative to ODTLoff completion Completion of ODTLoff R TT(OFF) 0.5tCK ± 0.2tCK tCK Figure 113: Synchronous ODT T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 CWL - 2AL = 3AL = 3 tAON (MAX) tAOF (MAX) T10 T11 T12 T13 T14 T15 CK CK# RTT ODT Don’t CareTransitioning RTT,nom CKE tAOF (MIN) ODTLoff = CWL + AL - 2 ODTLon = CWL + AL - 2 ODTH4 (MIN) tAON (MIN) Note: 1. AL = 3; CWL = 5; ODTLon = WL = 6.0; ODTLoff = WL - 2 = 6. R TT,nom is enabled. 2Gb: x4, x8, x16 DDR3 SDRAM Synchronous ODT Mode PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 199 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Figure 114: Synchronous ODT (BC4) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 tAOF (MAX) tAOF (MIN) tAON (MAX) tAOF (MAX) T10 T11 T12 T13 T14 T15 T17T16 CK CK# RTT CKE NOP WRS4NOP NOP NOP NOP NOPNOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOPCommand Don’t CareTransitioning tAON (MIN) RTT,nom ODTLoff = WL - 2 ODTH4 (MIN) ODTH4 ODTLoff = WL - 2 ODTLon = WL - 2 tAON (MIN) tAON (MAX) ODTH4 ODTLon = WL - 2 tAOF (MIN) ODT RTT,nom Notes: 1. WL = 7. R TT,nom is enabled. RTT(WR) is disabled. 2. ODT must be held HIGH for at least ODTH4 after assertion (T1). 3. ODT must be kept HIGH ODTH4 (BC4) or ODTH8 (BL8) after the WRITE command (T7). 4. ODTH is measured from ODT first registered HIGH to ODT first registered LOW or from the registration of the WRITE command with ODT HIGH to ODT registered LOW. 5. Although ODTH4 is satisfied from ODT registered HIGH at T6, ODT must not go LOW before T11 as ODTH4 must also be satisfied from the registration of the WRITE command at T7. 2Gb: x4, x8, x16 DDR3 SDRAM Synchronous ODT Mode PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 200 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Because the device cannot terminate and drive at the same time, RTT must be disabled at least one-half clock cycle before the READ preamble by driving the ODT ball LOW (if either R TT ,nom or RTT(WR) is enabled). RTT may not be enabled until the end of the post- amble, as shown in the following example. Note: ODT may be disabled earlier and enabled later than shown in Figure 115 (page 202). 2Gb: x4, x8, x16 DDR3 SDRAM Synchronous ODT Mode PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 201 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Figure 115: ODT During READs T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T17T16 CK CK# ValidAddress DI b + 3 DI b + 2 DI b + 1 DI b DI b + 7 DI b + 6 DI b + 5 DI b + 4 DQ DQS, DQS# Don’t CareTransitioning Command NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOPNOPREAD ODTLon = CWL + AL - 2 ODT tAON (MAX) RL = AL + CL ODTLoff = CWL + AL - 2 tAOF (MIN) RTT RTT,nomRTT,nom tAOF (MAX) Note: 1. ODT must be disabled externally during READs by driving ODT LOW. For example, CL = 6; AL = CL - 1 = 5; RL = AL + CL = 11; CWL = 5; ODTLon = CWL + AL - 2 = 8; ODTLoff = CWL + AL - 2 = 8. RTT,nom is enabled. RTT(WR) is a “Don’t Care.” 2Gb: x4, x8, x16 DDR3 SDRAM Synchronous ODT Mode PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 202 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Asynchronous ODT mode is available when the DRAM runs in DLL on mode and when either RTT ,nom or RTT(WR) is enabled; however, the DLL is temporarily turned off in pre- charged power-down standby (via MR0[12]). Additionally, ODT operates asynchronous- ly when the DLL is synchronizing after being reset. See Power-Down Mode (page 180) for definition and guidance over power-down details. In asynchronous ODT timing mode, the internal ODT command is not delayed by AL relative to the external ODT command. In asynchronous ODT mode, ODT controls R TT by analog time. The timing parameters tAONPD and tAOFPD replace ODTLon/tAON and ODTLoff/tAOF , respectively, when ODT operates asynchronously. The minimum RTT turn-on time (tAONPD [MIN]) is the point at which the device termi- nation circuit leaves High-Z and ODT resistance begins to turn on. Maximum RTT turn- on time (tAONPD [MAX]) is the point at which ODT resistance is fully on. tAONPD (MIN) and tAONPD (MAX) are measured from ODT being sampled HIGH. The minimum RTT turn-off time (tAOFPD [MIN]) is the point at which the device termi- nation circuit starts to turn off ODT resistance. Maximum RTT turn-off time (tAOFPD [MAX]) is the point at which ODT has reached High-Z. tAOFPD (MIN) and tAOFPD (MAX) are measured from ODT being sampled LOW . 2Gb: x4, x8, x16 DDR3 SDRAM Asynchronous ODT Mode PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 203 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Figure 116: Asynchronous ODT Timing with Fast ODT Transition T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 tAONPD (MAX) tAOFPD (MAX) T10 T11 T12 T13 T14 T15 T17T16 CK CK# RTT ODT RTT,nom Don’t CareTransitioning CKE tIH tIS tIH tIS tAOFPD (MIN)tAONPD (MIN) Note: 1. AL is ignored. Table 91: Asynchronous ODT Timing Parameters for All Speed Bins Symbol Description Min Max Unit tAONPD Asynchronous R TT turn-on delay (power-down with DLL off) 2 8.5 ns tAOFPD Asynchronous R TT turn-off delay (power-down with DLL off) 2 8.5 ns 2Gb: x4, x8, x16 DDR3 SDRAM Asynchronous ODT Mode PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 204 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Synchronous to Asynchronous ODT Mode Transition (Power-Down Entry) There is a transition period around power-down entry (PDE) where the DRAM’s ODT may exhibit either synchronous or asynchronous behavior. This transition period oc- curs if the DLL is selected to be off when in precharge power-down mode by the setting MR0[12] = 0. Power-down entry begins tANPD prior to CKE first being registered LOW, and ends when CKE is first registered LOW . tANPD is equal to the greater of ODTLoff + 1tCK or ODTLon + 1tCK. If a REFRESH command has been issued, and it is in progress when CKE goes LOW, power-down entry ends tRFC after the REFRESH command, rath- er than when CKE is first registered LOW . Power-down entry then becomes the greater of tANPD and tRFC - REFRESH command to CKE registered LOW . ODT assertion during power-down entry results in an RTT change as early as the lesser of tAONPD (MIN) and ODTLon × tCK + tAON (MIN), or as late as the greater of tAONPD (MAX) and ODTLon × tCK + tAON (MAX). ODT de-assertion during power-down entry can result in an RTT change as early as the lesser of tAOFPD (MIN) and ODTLoff × tCK + tAOF (MIN), or as late as the greater of tAOFPD (MAX) and ODTLoff × tCK + tAOF (MAX). Table 92 (page 206) summarizes these parameters. If AL has a large value, the uncertainty of the state of RTT becomes quite large. This is because ODTLon and ODTLoff are derived from the WL; and WL is equal to CWL + AL. Figure 117 (page 206) shows three different cases:

• ODT_A: Synchronous behavior before tANPD.
• ODT_B: ODT state changes during the transition period with tAONPD (MIN) < ODTLon × tCK + tAON (MIN) and tAONPD (MAX) > ODTLon × tCK + tAON (MAX).
• ODT_C: ODT state changes after the transition period with asynchronous behavior. 2Gb: x4, x8, x16 DDR3 SDRAM Asynchronous ODT Mode PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 205 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Table 92: ODT Parameters for Power-Down (DLL Off) Entry and Exit Transition Period Description Min Max Power-down entry transition period (power-down entry) Greater of: tANPD or tRFC - refresh to CKE LOW Power-down exit transition period (power-down exit) tANPD + tXPDLL ODT to RTT turn-on delay (ODTLon = WL - 2) Lesser of: tAONPD (MIN) (2ns) or ODTLon × tCK + tAON (MIN) Greater of: tAONPD (MAX) (8.5ns) or ODTLon × tCK + tAON (MAX) ODT to RTT turn-off delay (ODTLoff = WL - 2) Lesser of: tAOFPD (MIN) (2ns) or ODTLoff × tCK + tAOF (MIN) Greater of: tAOFPD (MAX) (8.5ns) or ODTLoff × tCK + tAOF (MAX) tANPD WL - 1 (greater of ODTLoff + 1 or ODTLon + 1) Figure 117: Synchronous to Asynchronous Transition During Precharge Power-Down (DLL Off) Entry T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 tAOFPD (MAX) ODTLoff T10 T11 T12 T13 Ta0 Ta1 Ta3Ta2 CK CK# DRAM RTT B asynchronous or synchronous RTT,nom DRAM RTT C asynchronous RTT,nom Don’t CareTransitioning CKE NOP NOP NOPNOP NOPCommand NOP REF NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP PDE transition period Indicates break in time scale ODTLoff + tAOFPD (MIN) tAOFPD (MAX) tAOFPD (MIN) ODTLoff + tAOFPD (MAX) tAOFPD (MIN) tANPD tAOF (MIN) tAOF (MAX) DRAM RTT A synchronous RTT,nom ODT A synchronous ODT C asynchronous ODT B asynchronous or synchronous tRFC (MIN) Note: 1. AL = 0; CWL = 5; ODTL(off) = WL - 2 = 3. 2Gb: x4, x8, x16 DDR3 SDRAM Asynchronous ODT Mode PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 206 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Asynchronous to Synchronous ODT Mode Transition (Power-Down Exit) The DRAM’s ODT can exhibit either asynchronous or synchronous behavior during power-down exit (PDX). This transition period occurs if the DLL is selected to be off when in precharge power-down mode by setting MR0[12] to 0. Power-down exit begins tANPD prior to CKE first being registered HIGH, and ends tXPDLL after CKE is first reg- istered HIGH. tANPD is equal to the greater of ODTLoff + 1tCK or ODTLon + 1tCK. The transition period is tANPD + tXPDLL. ODT assertion during power-down exit results in an RTT change as early as the lesser of tAONPD (MIN) and ODTLon × tCK + tAON (MIN), or as late as the greater of tAONPD (MAX) and ODTLon × tCK + tAON (MAX). ODT de-assertion during power-down exit may result in an RTT change as early as the lesser of tAOFPD (MIN) and ODTLoff × tCK + tAOF (MIN), or as late as the greater of tAOFPD (MAX) and ODTLoff × tCK + tAOF (MAX). Table 92 (page 206) summarizes these parameters. If AL has a large value, the uncertainty of the RTT state becomes quite large. This is be- cause ODTLon and ODTLoff are derived from WL, and WL is equal to CWL + AL. Fig- ure 118 (page 208) shows three different cases:

• ODT C: Asynchronous behavior before tANPD.
• ODT B: ODT state changes during the transition period, with tAOFPD (MIN) < ODTL- off × tCK + tAOF (MIN), and ODTLoff × tCK + tAOF (MAX) > tAOFPD (MAX).
• ODT A: ODT state changes after the transition period with synchronous response. 2Gb: x4, x8, x16 DDR3 SDRAM Asynchronous to Synchronous ODT Mode Transition (Power- Down Exit) PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 207 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Figure 118: Asynchronous to Synchronous Transition During Precharge Power-Down (DLL Off) Exit T0 T1 T2 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 Tb0 Tb1 Tb2 Tc0 Tc1 Td0 Td1Tc2 CK CK# Don’t CareTransitioning ODT C synchronous NOP NOPNOPCOMMAND NOP NOP NOP NOP NOP NOP NOP NOP NOP RTT B asynchronous or synchronous DRAM RTT A asynchronous DRAM RTT C synchronous RTT,nom NOPNOP ODT B asynchronous or synchronous CKE tAOF (MIN) RTT,nom Indicates break in time scale ODTLoff + tAOF (MIN) tAOFPD (MAX) ODTLoff + tAOF (MAX) tXPDLL tAOF (MAX)ODTLoff ODT A asynchronous PDX transition period tAOFPD (MIN) tAOFPD (MAX) RTT,nom tANPD tAOFPD (MIN) Note: 1. CL = 6; AL = CL - 1; CWL = 5; ODTLoff = WL - 2 = 8. 2Gb: x4, x8, x16 DDR3 SDRAM Asynchronous to Synchronous ODT Mode Transition (Power- Down Exit) PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 208 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

Asynchronous to Synchronous ODT Mode Transition (Short CKE Pulse) If the time in the precharge power-down or idle states is very short (short CKE LOW pulse), the power-down entry and power-down exit transition periods overlap. When overlap occurs, the response of the DRAM’s R TT to a change in the ODT state can be synchronous or asynchronous from the start of the power-down entry transition period to the end of the power-down exit transition period, even if the entry period ends later than the exit period. If the time in the idle state is very short (short CKE HIGH pulse), the power-down exit and power-down entry transition periods overlap. When this overlap occurs, the re- sponse of the DRAM’s R TT to a change in the ODT state may be synchronous or asyn- chronous from the start of power-down exit transition period to the end of the power- down entry transition period. 2Gb: x4, x8, x16 DDR3 SDRAM Asynchronous to Synchronous ODT Mode Transition (Power- Down Exit) PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 209 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 www.micron.com/productsupport Customer Comment Line: 800-932-4992 Micron and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered final, these specifications are subject to change, as further product development and data characterization some- times occur. 2Gb: x4, x8, x16 DDR3 SDRAM Asynchronous to Synchronous ODT Mode Transition (Power- Down Exit) PDF: 09005aef826aaadc 2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN 211 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2006 Micron Technology, Inc. All rights reserved.