MT40A1G16RC-062E:E

MT40A4G4 MICRON | Alldatasheet

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Technical content

Datasheet sections

Features

• V DD = VDDQ = 1.2V ±60mV
• V PP = 2.5V , –125mV , +250mV
• On-die, internal, adjustable V REFDQ generation
• 1.2V pseudo open-drain I/O C maximum up to 95°C – 64ms, 8192-cycle refresh up to 85°C – 32ms, 8192-cycle refresh at >85°C to 95°C
• 16 internal banks (x4, x8): 4 groups of 4 banks each
• 8 internal banks (x16): 2 groups of 4 banks each
• 8 n-bit prefetch architecture
• Programmable data strobe preambles
• Data strobe preamble training
• Command/Address latency (CAL)
• Multipurpose register READ and WRITE capability
• Write leveling
• Self refresh mode
• Low-power auto self refresh (LPASR)
• Temperature controlled refresh (TCR)
• Fine granularity refresh
• Self refresh abort
• Maximum power saving
• Output driver calibration
• Nominal, park, and dynamic on-die termination (ODT)
• Data bus inversion (DBI) for data bus
• Command/Address (CA) parity
• Databus write cyclic redundancy check (CRC)
• Per-DRAM addressability
• Connectivity test
• JEDEC JESD-79-4 compliant
• sPPR and hPPR capability Options1 Marking
• Configuration – 4 Gig x 4 4G4 – 2 Gig x 8 2G8 – 1 Gig x 16 1G16
• 78-ball FBGA package (Pb-free) – x4, x8 – 10mm x 11mm – Rev. B VA – 9mm x 11mm – Rev. E JC
• 96-ball FBGA package (Pb-free) – x16 – 10mm x 13mm – Rev. B RC – 9mm x 13mm – Rev. E KD
• Timing – cycle time – 0.625ns @ CL = 22 (DDR4-3200) -062E – 0.682ns @ CL = 21 (DDR4-2933) -068
• Operating temperature – Commercial (0° ื T C ื 95°C) None – Industrial (–40° ื TC ื 95°C) IT
• Revision :B, :E Note: 1. Not all options listed can be combined to define an offered product. Use the part catalog search on http://www.micron.com for available offerings. Table 1: Key Timing Parameters Speed Grade1 Data Rate (MT/s) Target CL-nRCD-nRP tAA (ns) tRCD (ns) tRP (ns) -062E 3200 22-22-22 13.75 13.75 13.75 Note: 1. Refer to the Speed Bin Tables for additional details. 16Gb: x4, x8, x16 DDR4 SDRAM

16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 1 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice.

Table 2: Addressing Parameter 4096 Meg x 4 2048 Meg x 8 1024 Meg x 16 Number of bank groups 4 4 2 Bank group address BG[1:0] BG[1:0] BG0 Bank count per group 4 4 4 Bank address in bank group BA[1:0] BA[1:0] BA[1:0] Row addressing 256K (A[17:0]) 128K (A[16:0]) 128K (A[16:0]) Column addressing 1K (A[9:0]) 1K (A[9:0]) 1K (A[9:0]) Page size 1 512B 1KB 2KB Note: 1. Page size is per bank, calculated as follows: Page size = 2COLBITS × ORG/8, where COLBIT = the number of column address bits and ORG = the number of DQ bits. 16Gb: x4, x8, x16 DDR4 SDRAM 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 2 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Figure 1: Order Part Number Example Example Part Number: MT40A2G8VA-068:B Configuration

4 Gig x 4

2 Gig x 8

1 Gig x 16

ConfigurationMT40A Package Speed Revision :B, :E Commercial Industrial temperature None ITPackage Mark 78-ball 10.0mm x 11.0mm FBGA VA Case Temperature 96-ball 10.0mm x 13.0mm FBGA RC Revision -062E tCK = 0.682ns, CL = 21 tCK = 0.625ns, CL = 22 -068 Speed Grade Cycle Time, CAS Latency JC KD 78-ball 9.0mm x 11.0mm FBGA 96-ball 9.0mm x 13.0mm FBGA 16Gb: x4, x8, x16 DDR4 SDRAM 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 3 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

16Gb: x4, x8, x16 DDR4 SDRAM 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 5 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

16Gb: x4, x8, x16 DDR4 SDRAM 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 6 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

16Gb: x4, x8, x16 DDR4 SDRAM 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 7 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

16Gb: x4, x8, x16 DDR4 SDRAM 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 8 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

16Gb: x4, x8, x16 DDR4 SDRAM 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 9 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

16Gb: x4, x8, x16 DDR4 SDRAM 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 15 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

16Gb: x4, x8, x16 DDR4 SDRAM 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 16 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Table 107: DDR4-1600 through DDR4-2400 Differential Input Slew Rate and Input Levels for DQS_t, DQS_c ... 286 Table 108: DDR4-2666 through DDR4-3200 Differential Input Slew Rate and Input Levels for DQS_t, DQS_c ... 287 Table 135: Basic I 16Gb: x4, x8, x16 DDR4 SDRAM 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 17 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

16Gb: x4, x8, x16 DDR4 SDRAM 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 18 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Important Notes and Warnings Micron Technology, Inc. ("Micron") reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions. This document supersedes and replaces all information supplied prior to the publication hereof. You may not rely on any information set forth in this docu- ment if you obtain the product described herein from any unauthorized distributor or other source not authorized by Micron. Automotive Applications. Products are not designed or intended for use in automotive applications unless specifi- cally designated by Micron as automotive-grade by their respective data sheets. Distributor and customer/distrib- utor shall assume the sole risk and liability for and shall indemnify and hold Micron harmless against all claims, costs, damages, and expenses and reasonable attorneys' fees arising out of, directly or indirectly, any claim of product liability, personal injury, death, or property damage resulting directly or indirectly from any use of non- automotive-grade products in automotive applications. Customer/distributor shall ensure that the terms and con- ditions of sale between customer/distributor and any customer of distributor/customer (1) state that Micron products are not designed or intended for use in automotive applications unless specifically designated by Micron as automotive-grade by their respective data sheets and (2) require such customer of distributor/customer to in- demnify and hold Micron harmless against all claims, costs, damages, and expenses and reasonable attorneys' fees arising out of, directly or indirectly, any claim of product liability, personal injury, death, or property damage resulting from any use of non-automotive-grade products in automotive applications. Critical Applications. Products are not authorized for use in applications in which failure of the Micron compo- nent could result, directly or indirectly in death, personal injury, or severe property or environmental damage ("Critical Applications"). Customer must protect against death, personal injury, and severe property and environ- mental damage by incorporating safety design measures into customer's applications to ensure that failure of the Micron component will not result in such harms. Should customer or distributor purchase, use, or sell any Micron component for any critical application, customer and distributor shall indemnify and hold harmless Micron and its subsidiaries, subcontractors, and affiliates and the directors, officers, and employees of each against all claims, costs, damages, and expenses and reasonable attorneys' fees arising out of, directly or indirectly, any claim of product liability, personal injury, or death arising in any way out of such critical application, whether or not Mi- cron or its subsidiaries, subcontractors, or affiliates were negligent in the design, manufacture, or warning of the Micron product. Customer Responsibility. Customers are responsible for the design, manufacture, and operation of their systems, applications, and products using Micron products. ALL SEMICONDUCTOR PRODUCTS HAVE INHERENT FAIL- URE RATES AND LIMITED USEFUL LIVES. IT IS THE CUSTOMER'S SOLE RESPONSIBILITY TO DETERMINE WHETHER THE MICRON PRODUCT IS SUITABLE AND FIT FOR THE CUSTOMER'S SYSTEM, APPLICATION, OR PRODUCT . Customers must ensure that adequate design, manufacturing, and operating safeguards are included in customer's applications and products to eliminate the risk that personal injury, death, or severe property or en- vironmental damages will result from failure of any semiconductor component. Limited Warranty. In no event shall Micron be liable for any indirect, incidental, punitive, special or consequential damages (including without limitation lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort, warranty, breach of contract or other legal theory, unless explicitly stated in a written agreement executed by Micron's duly authorized representative. General Notes and Description

Description

The DDR4 SDRAM is a high-speed dynamic random-access memory internally config- ured as an eight-bank DRAM for the x16 configuration and as a 16-bank DRAM for the 16Gb: x4, x8, x16 DDR4 SDRAM Important Notes and Warnings CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 19 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

x4 and x8 configurations. The DDR4 SDRAM uses an 8n-prefetch architecture to ach- ieve high-speed operation. The 8n-prefetch architecture is combined with an interface designed to transfer two data words per clock cycle at the I/O pins. A single READ or WRITE operation for the DDR4 SDRAM consists of a single 8n-bit wide, four-clock data transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins. Industrial Temperature An industrial temperature (IT) device option requires that the case temperature not ex- ceed below –40°C or above 95°C. JEDEC specifications require the refresh rate to double when T C exceeds 85°C; this also requires use of the high-temperature self refresh option. Additionally, ODT resistance and the input/output impedance must be derated when operating outside of the commercial temperature range, when T C is between –40°C and 0°C. Automotive Temperature The automotive temperature (AT) device option requires that the case temperature not exceed below –40°C or above 105°C. The specifications require the refresh rate to 2X when T C exceeds 85°C; 4X when TC exceeds 95°C. Additionally, ODT resistance and the input/output impedance must be derated when operating temperature Tc <0°C. General Notes

• The functionality and the timing specifications discussed in this data sheet are for the DLL enable mode of operation (normal operation), unless specifically stated other- wise.
• Throughout the data sheet, the various figures and text refer to DQs as "DQ." The DQ term is to be interpreted as any and all DQ collectively, unless specifically stated oth- erwise.
• The terms "_t" and "_c" are used to represent the true and complement of a differen- tial signal pair. These terms replace the previously used notation of "#" and/or over- bar characters. For example, differential data strobe pair DQS, DQS# is now referred to as DQS_t, DQS_c.
• The term "_n" is used to represent a signal that is active LOW and replaces the previ- ously used "#" and/or overbar characters. For example: CS# is now referred to as CS_n.
• The terms "DQS" and "CK" found throughout the data sheet are to be interpreted as DQS_t, DQS_c and CK_t, CK_c respectively, unless specifically stated otherwise.
• Complete functionality may be described throughout the entire document; any page or diagram may have been simplified to convey a topic and may not be inclusive of all requirements.
• Any specific requirement takes precedence over a general statement.
• Any functionality not specifically stated here within is considered undefined, illegal, and not supported, and can result in unknown operation.
• Addressing is denoted as BG[ n] for bank group, BA[n] for bank address, and A[n] for row/col address.
• The NOP command is not allowed, except when exiting maximum power savings mode or when entering gear-down mode, and only a DES command should be used. 16Gb: x4, x8, x16 DDR4 SDRAM General Notes and Description CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 20 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

• Not all features described within this document may be available on the Rev. A (first) version.
• Not all specifications listed are finalized industry standards; best conservative esti- mates have been provided when an industry standard has not been finalized.
• Although it is implied throughout the specification, the DRAM must be used after V DD has reached the stable power-on level, which is achieved by toggling CKE at least once every 8192 × tREFI. However, in the event CKE is fixed HIGH, toggling CS_n at least once every 8192 × tREFI is an acceptable alternative. Placing the DRAM into self re- fresh mode also alleviates the need to toggle CKE.
• Not all features designated in the data sheet may be supported by earlier die revisions due to late definition by JEDEC.
• A x16 device's DQ bus is comprised of two bytes. If only one of the bytes needs to be used, use the lower byte for data transfers and terminate the upper byte as noted: – Connect UDQS_t to VDDQ or VSS/ VSSQ via a resistor in the 200 വ range. – Connect UDQS_c to the opposite rail via a resistor in the same 200 വ range. – Connect UDM to VDDQ via a large (10,000 വ) pull-up resistor. – Connect UDBI to VDDQ via a large (10,000 വ) pull-up resistor. – Connect DQ [15:8] individually to VDDQ via a large (10,000 വ) resistors, or float DQ [15:8] . Definitions of the Device-Pin Signal Level
• HIGH: A device pin is driving the logic 1 state.
• LOW: A device pin is driving the logic 0 state.
• High-Z: A device pin is tri-state.
• ODT: A device pin terminates with the ODT setting, which could be terminating or tri- state depending on the mode register setting. Definitions of the Bus Signal Level
• HIGH: One device on the bus is HIGH, and all other devices on the bus are either ODT or High-Z. The voltage level on the bus is nominally VDDQ.
• LOW: One device on the bus is LOW, and all other devices on the bus are either ODT or High-Z. The voltage level on the bus is nominally VOL(DC) if ODT was enabled, or VSSQ if High-Z.
• High-Z: All devices on the bus are High-Z. The voltage level on the bus is undefined as the bus is floating.
• ODT: At least one device on the bus is ODT , and all others are High-Z. The voltage lev- el on the bus is nominally VDDQ.
• The specification requires 8,192 refresh commands within 64ms between 0 oC and 85 The specification also requires 8,192 refresh commands within 32ms between 85 oC and 95 oC. This allows for a tREFI of 3.90625μs (the use of "3.9μs" is truncated from 3.90625μs). 16Gb: x4, x8, x16 DDR4 SDRAM General Notes and Description CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 21 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Figure 4: 1 Gig x 16 Functional Block Diagram /'46BW/'46BF 8'46BW8'46BF &ROXPQV DQG 5HDG GULYHUV '4> '4> 5($' ),)2 DQG GDWD 08; &ROXPQVDQG 8'%,BQ 8'0BQ /'%,BQ /'0BQ 8'46BW 8'46BF /'46BW /'46BF &.BW&.BF '// &.BW&.BF &5& '4> %& '%, :ULWH GULYHUV DQG LQSXW ORJLF 'DWD LQWHUIDFH &ROXPQ %&QLEEOH 5RZ DGGUHVV 08; DQG FRQWURO ORJLF 2'7 FRQWURO 9UHI'4 FRQWURO &5&DQG SDULW\\FRQWURO 27) &RQWURO ORJLF 0RGHUHJLVWHUV %$> %*>@ $$$ 5HIUHVK FRXQWHU 7R2'7RXWSXWGULYHUV 7R=4&RQWURO=4&$/ &.( &.BW&.BF 3$5 7(1 &RPPDQGGHFRGH 5$6BQ&$6BQ:(BQ &6BQ $&7BQ 5(6(7BQ 9UHI'4 $GGUHVV UHJLVWHU 27) &5& 3DULW\\ 9''4 577Z577Q577S %DQN %DQN %DQN %DQN %DQN %DQN %DQN %DQN ,2JDWLQJ '0PDVNORJLF &ROXPQ GHFRGHU %DQN %DQN*URXS %DQN %DQN %DQN %DQN %DQN %DQN *OREDO ,2JDWLQJ 5RZ DGGUHVV ODWFK DQG GHFRGHU &ROXPQ DGGUHVV FRXQWHU ODWFK 9''4 9''4 577Z577Q577S 9''4 577Z577Q577S $/(572'7 6HQVHDPSOLILHUV %DQN %DQN*URXS 0HPRU\\ DUUD\\ 6HQVHDPSOLILHUV %DQN %DQN %DQN 16Gb: x4, x8, x16 DDR4 SDRAM Functional Block Diagrams CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 23 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Figure 5: 78-Ball x4, x8 Ball Assignments 9664 9''4 1)'4 9''4 &2'71& &&.(1& 1)1) 7'46BF '46BF '46BW 1)'4 2'7 &.( $&7BQ $$3 3$5 1)1)'0BQ '%,BQ7'46BW 9'' 1)'4 &.BW &6BQ &$6BQ $%&BQ $1)1& 9664 9''4 966 1)'4 9''4 &.BF &&6BQ1& :(BQ 966 9''4 9664 966 9'' 7(11) 966 9'' 966 $/(57BQ 933 9'' 933 9''4 9664 966 9'' 966 9'' 95()&$ 966 5(6(7BQ 9'' 966 5$6BQ 1)1& Notes: 1. See Ball Descriptions. 2. A comma “,” separates the configuration; a slash “/” defines a mode register selectable function, command/address function, density, or package dependence. 3. Address bits (including bank groups) are density- and configuration-dependent (see Ad- dressing). 16Gb: x4, x8, x16 DDR4 SDRAM Ball Assignments CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 24 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Figure 6: 96-Ball x16 Ball Assignments 9''4 933 9''4 9'' 966 9664 9''4 9664 9'' 966 9'' 95()&$ 966 5(6(7BQ 9'' 966 9664 966 9664 9''4 ''4 &.( 9'' 664 /'46BF /'46BW 2'7 $&7BQ $$3 3$5 8'46BF 8'46BW &.BW &6BQ $%&BQ 1)1& 9664 9664 9664 9''4 966 9''4 &.BF 9''4 9'' 9664 9''4 966 9''4 9664 9'' 966 9'' 966 7(1 933 9'' 1)/'0BQ /'%,BQ $/(57BQ 1)8'0BQ 8'%,BQ &$6BQ :(BQ 5$6BQ Notes: 1. See Ball Descriptions. 2. A slash “/” defines a mode register selectable function, command/address function, den- sity, or package dependence. 3. Address bits (including bank groups) are density- and configuration-dependent (see Ad- dressing). 16Gb: x4, x8, x16 DDR4 SDRAM Ball Assignments CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 25 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

The pin description table below is a comprehensive list of all possible pins for DDR4 de- vices. All pins listed may not be supported on the device defined in this data sheet. See the Ball Assignments section to review all pins used on this device. Table 3: Ball Descriptions Symbol Type Description A[17:0] Input Address inputs: Provide the row address for ACTIVATE commands and the column address for READ/WRITE commands to select one location out of the memory array in the respective bank. (A10/AP, A12/BC_n, WE_n/A14, CAS_n/A15, RAS_n/A16 have addi- tional functions, see individual entries in this table.) The address inputs also provide the op-code during the MODE REGISTER SET command. A16 is used on some 8Gb and 16Gb parts. A17 connection is part-number specific; Contact vendor for more infor- mation. A10/AP Input Auto precharge: A10 is sampled during READ and WRITE commands to determine whether auto precharge should be performed to the accessed bank after a READ or WRITE operation. (HIGH = auto precharge; LOW = no auto precharge.) A10 is sam- pled during a PRECHARGE command to determine whether the PRECHARGE applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by the bank group and bank addresses. A12/BC_n Input Burst chop: A12/BC_n is sampled during READ and WRITE commands to determine if burst chop (on-the-fly) will be performed. (HIGH = no burst chop; LOW = burst chop- ped). See the Command Truth Table. ACT_n Input Command input: ACT_n indicates an ACTIVATE command. When ACT_n (along with CS_n) is LOW, the input pins RAS_n/A16, CAS_n/A15, and WE_n/A14 are treated as row address inputs for the ACTIVATE command. When ACT_n is HIGH (along with CS_n LOW), the input pins RAS_n/ A16, CAS_n/A15, and WE_n/A14 are treated as nor- mal commands that use the RAS_n, CAS_n, and WE_n signals. See the Command Truth Table. BA[1:0] Input Bank address inputs: Define the bank (within a bank group) to which an ACTIVATE, READ, WRITE, or PRECHARGE command is being applied. Also determines which mode register is to be accessed during a MODE REGISTER SET command. BG[1:0] Input Bank group address inputs: Define the bank group to which an ACTIVATE, READ, WRITE, or PRECHARGE command is being applied. Also determines which mode regis- ter is to be accessed during a MODE REGISTER SET command. BG[1:0] are used in the x4 and x8 configurations. BG1 is not used in the x16 configuration. C0/CKE1, C1/CS1_n, C2/ODT1 Input Stack address inputs: These inputs are used only when devices are stacked; that is, they are used in 2H, 4H, and 8H stacks for x4 and x8 configurations (these pins are not used in the x16 configuration, and are NC on the x4/x8 SDP). DDR4 will support a traditional DDP package, which uses these three signals for control of the second die (CS1_n, CKE1, ODT1). DDR4 is not expected to support a traditional QDP package. For all other stack configurations, such as a 4H or 8H, it is assumed to be a single-load (master/slave) type of configuration where C0, C1, and C2 are used as chip ID selects in conjunction with a single CS_n, CKE, and ODT signal. CK_t, CK_c Input Clock: Differential clock inputs. All address, command, and control input signals are sampled on the crossing of the positive edge of CK_t and the negative edge of CK_c. 16Gb: x4, x8, x16 DDR4 SDRAM Ball Descriptions CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 26 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Table 3: Ball Descriptions (Continued) Symbol Type Description CKE Input Clock enable: CKE HIGH activates and CKE LOW deactivates the internal clock sig- nals, device input buffers, and output drivers. Taking CKE LOW provides PRECHARGE POWER-DOWN and SELF REFRESH operations (all banks idle), or active power-down (row active in any bank). CKE is asynchronous for self refresh exit, however, timing parameters such as tXS are still calculated from the first rising clock edge where CKE HIGH satisfies tIS. After VREFCA has become stable during the power-on and initializa- tion sequence, it must be maintained during all operations (including SELF REFRESH). CKE must be maintained HIGH throughout read and write accesses. Input buffers (ex- cluding CK_t, CK_c, ODT, RESET_n, and CKE) are disabled during power-down. Input buffers (excluding CKE and RESET_n) are disabled during self refresh. CS_n Input Chip select: All commands are masked when CS_n is registered HIGH. CS_n provides for external rank selection on systems with multiple ranks. CS_n is considered part of the command code. DM_n, UDM_n LDM_n Input Input data mask: DM_n is an input mask signal for write data. Input data is masked when DM is sampled LOW coincident with that input data during a write access. DM is sampled on both edges of DQS. DM is not supported on x4 configurations. The UDM_n and LDM_n pins are used in the x16 configuration: UDM_n is associated with DQ[15:8]; LDM_n is associated with DQ[7:0]. The DM, DBI, and TDQS functions are en- abled by mode register settings. See the Data Mask section. ODT Input On-die termination: ODT (registered HIGH) enables termination resistance internal to the DDR4 SDRAM. When enabled, ODT (R TT) is applied only to each DQ, DQS_t, DQS_c, DM_n/DBI_n/TDQS_t, and TDQS_c signal for the x4 and x8 configurations (when the TDQS function is enabled via mode register). For the x16 configuration, R TT is applied to each DQ, UDQS_t, UDQS_c, LDQS_t, LDQS_c, UDM_n, and LDM_n signal. The ODT pin will be ignored if the mode registers are programmed to disable R TT. PAR Input Parity for command and address: This function can be enabled or disabled via the mode register. When enabled, the parity signal covers all command and address in- puts, including ACT_n, RAS_n/A16, CAS_n/A15, WE_n/A14, A[17:0], A10/AP, A12/BC_n, BA[1:0], and BG[1:0] with C0, C1, and C2 on 3DS only devices. Control pins NOT cov- ered by the parity signal are CS_n, CKE, and ODT. Unused address pins that are densi- ty- and configuration-specific should be treated internally as 0s by the DRAM parity logic. Command and address inputs will have parity check performed when com- mands are latched via the rising edge of CK_t and when CS_n is LOW. RAS_n/A16, CAS_n/A15, WE_n/A14 Input Command inputs: RAS_n/A16, CAS_n/A15, and WE_n/A14 (along with CS_n and ACT_n) define the command and/or address being entered. See the ACT_n descrip- tion in this table. RESET_n Input Active LOW asynchronous reset: Reset is active when RESET_n is LOW, and inac- tive when RESET_n is HIGH. RESET_n must be HIGH during normal operation. RESET_n is a CMOS rail-to-rail signal with DC HIGH and LOW at 80% and 20% of V DD (960 mV for DC HIGH and 240 mV for DC LOW). TEN Input Connectivity test mode: TEN is active when HIGH and inactive when LOW. TEN must be LOW during normal operation. TEN is a CMOS rail-to-rail signal with DC HIGH and LOW at 80% and 20% of V DD (960mV for DC HIGH and 240mV for DC LOW). On Micron 3DS devices, connectivity test mode is not supported and the TEN pin should be considered NF maintained LOW at all times. 16Gb: x4, x8, x16 DDR4 SDRAM Ball Descriptions CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 27 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Table 3: Ball Descriptions (Continued) Symbol Type Description DQ I/O Data input/output: Bidirectional data bus. DQ represents DQ[3:0], DQ[7:0], and DQ[15:0] for the x4, x8, and x16 configurations, respectively. If write CRC is enabled via mode register, the write CRC code is added at the end of data burst. Any one or all of DQ0, DQ1, DQ2, and DQ3 may be used to monitor the internal V REF level during test via mode register setting MR[4] A[4] = HIGH, training times change when ena- bled. During this mode, the R TT value should be set to High-Z. This measurement is for verification purposes and is NOT an external voltage supply pin. DBI_n, UDBI_n, LDBI_n I/O DBI input/output: Data bus inversion. DBI_n is an input/output signal used for data bus inversion in the x8 configuration. UDBI_n and LDBI_n are used in the x16 configu- ration; UDBI_n is associated with DQ[15:8], and LDBI_n is associated with DQ[7:0]. The DBI feature is not supported on the x4 configuration. DBI is not supported for 3DS devices and should be disabled in MR5. DBI can be configured for both READ (out- put) and WRITE (input) operations depending on the mode register settings. The DM, DBI, and TDQS functions are enabled by mode register settings. See the Data Bus In- version section. DQS_t, DQS_c, UDQS_t, UDQS_c, LDQS_t, LDQS_c I/O Data strobe: Output with READ data, input with WRITE data. Edge-aligned with READ data, centered-aligned with WRITE data. For the x16, LDQS corresponds to the data on DQ[7:0]; UDQS corresponds to the data on DQ[15:8]. For the x4 and x8 con- figurations, DQS corresponds to the data on DQ[3:0] and DQ[7:0], respectively. DDR4 SDRAM supports a differential data strobe only and does not support a single-ended data strobe. ALERT_n Output Alert output: This signal allows the DRAM to indicate to the system's memory con- troller that a specific alert or event has occurred. Alerts will include the command/ address parity error and the CRC data error when either of these functions is enabled in the mode register. TDQS_t, TDQS_c Output Termination data strobe: TDQS_t and TDQS_c are used by x8 DRAMs only. When enabled via the mode register, the DRAM will enable the same R TT termination resist- ance on TDQS_t and TDQS_c that is applied to DQS_t and DQS_c. When the TDQS function is disabled via the mode register, the DM/TDQS_t pin will provide the DATA MASK (DM) function, and the TDQS_c pin is not used. The TDQS function must be dis- abled in the mode register for both the x4 and x16 configurations. The DM function is supported only in x8 and x16 configurations. V DD Supply Power supply: 1.2V ±0.060V. VDDQ Supply DQ power supply: 1.2V ±0.060V. VPP Supply DRAM activating power supply: 2.5V –0.125V/+0.250V. VREFCA Supply Reference voltage for control, command, and address pins. VSS Supply Ground. VSSQ Supply DQ ground. ZQ Reference Reference ball for ZQ calibration: This ball is tied to an external 240˖ resistor (RZQ), which is tied to VSSQ. RFU – Reserved for future use. NC – No connect: No internal electrical connection is present. NF – No function: Internal connection is present but has no function. 16Gb: x4, x8, x16 DDR4 SDRAM Ball Descriptions CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 28 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Figure 7: 78-Ball FBGA – x4, x8 (VA) 0.155 Seating plane 0.1 A 123789 Ball A1 ID Ball A1 ID A 0.34 ±0.05 1.1 ±0.1

6.4 CTR

0.8 TYP

9.6 CTR

11 ±0.1 A B C D E F G H J K L M N 78X Ø0.47±0.05 Dimensions apply to solder balls post- reflow on Ø0.42 SMD ball pads.

1.8 CTR

10±0.1 Notes: 1. All dimensions are in millimeters. 2. Solder ball material: SAC302 (96.8% Sn, 3% Ag, 0.2% Cu). 16Gb: x4, x8, x16 DDR4 SDRAM Package Dimensions CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 29 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Figure 8: 78-Ball FBGA – x4, x8 (JC) Seating plane 0.12 A Ball A1 ID A 0.34 ±0.05 1.1 ±0.1 9 ±0.1 11 ±0.1 78X Ø0.47 ±0.05 Dimensions apply to solder balls post- reflow on Ø0.42 SMD ball pads. A B C D E F G H J K L M N 0.155 Notes: 1. All dimensions are in millimeters. 2. Solder ball material: SAC302 (96.8% Sn, 3% Ag, 0.2% Cu). 16Gb: x4, x8, x16 DDR4 SDRAM Package Dimensions CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 30 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Figure 9: 96-Ball FBGA – x16 (RC) 0.155 Seating plane 0.1 A Ball A1 ID Ball A1 ID A 0.34 ±0.05 1.1 ±0.1 10 ±0.1

12 CTR

13 ±0.1 96X Ø0.47 ±0.05 Dimensions apply to solder balls post- reflow on Ø0.42 SMD ball pads. A B C D E F G H J K L M N P R T Notes: 1. All dimensions are in millimeters. 2. Solder ball material: SAC302 (96.8% Sn, 3% Ag, 0.2% Cu). 16Gb: x4, x8, x16 DDR4 SDRAM Package Dimensions CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 31 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Figure 10: 96-Ball FBGA – x16 (KD) 0.155 Seating plane Ball A1 ID Ball A1 ID 0.34 ±0.05 1.1 ±0.1 9 ±0.1 13 ±0.1 96X Ø0.47 ±0.05 Dimensions apply to solder balls post-reflow on Ø0.42 SMD ball pads. A B C D E F G H J K L M N P R T A 0.12 A Notes: 1. All dimensions are in millimeters. 2. Solder ball material: SAC302 (96.8% Sn, 3% Ag, 0.2% Cu). 16Gb: x4, x8, x16 DDR4 SDRAM Package Dimensions CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 32 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

This simplified state diagram provides an overview of the possible state transitions and the commands to control them. Situations involving more than one bank, the enabling or disabling of on-die termination, and some other events are not captured in full de- tail. Figure 11: Simplified State Diagram Bank active ReadingWriting Activating Refreshing Self refresh Idle Active power- down ZQ calibration Power From any state applied Reset procedurePower-On Initialization MRS, MPR, write leveling, VREFDQ training Precharge power- down Writing Reading Automatic sequence Command sequence Precharging READ READ READ READ A READ A READ A PRE, PREA PRE, PREA PRE, PREA WRITE WRITEWRITE WRITE A WRITE A WRITE A PDE PDE PDX PDX SRX SRE REF ACT ZQCL ZQCL,ZQCS CKE_L CKE_L CKE_L MPSM PDA mode IVREFDQ, RTT, and so on Connectivity test RESET RESET RESET TEN = 0 MRS MRS SRX* SRX* SRX* = SRX with NOP MRS MRS MRS MRS TEN = 1 TEN = 1 16Gb: x4, x8, x16 DDR4 SDRAM State Diagram CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 33 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Table 4: State Diagram Command Definitions Command Description ACT Active MPR Multipurpose register MRS Mode register set PDE Enter power-down PDX Exit power-down PRE Precharge PREA Precharge all READ RD, RDS4, RDS8 READ A RDA, RDAS4, RDAS8 REF Refresh, fine granularity refresh RESET Start reset procedure SRE Self refresh entry SRX Self refresh exit TEN Boundary scan mode enable WRITE WR, WRS4, WRS8 with/without CRC WRITE A WRA, WRAS4, WRAS8 with/without CRC ZQCL ZQ calibration long ZQCS ZQ calibration short Note: 1. See the Command Truth Table for more details. 16Gb: x4, x8, x16 DDR4 SDRAM State Diagram CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 34 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

The DDR4 SDRAM is a high-speed dynamic random-access memory internally config- ured as sixteen banks (4 bank groups with 4 banks for each bank group) for x4/x8 devi- ces, and as eight banks for each bank group (2 bank groups with 4 banks each) for x16 devices. The device uses double data rate (DDR) architecture to achieve high-speed op- eration. DDR4 architecture is essentially an 8n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for a device module effectively consists of a single 8n-bit-wide, four-clock- cycle-data transfer at the internal DRAM core and eight corresponding n-bit-wide, one- half-clock-cycle data transfers at the I/O pins. Read and write accesses to the device are burst-oriented. Accesses start at a selected lo- cation and continue for a burst length of eight or a chopped burst of four in a program- med sequence. Operation begins with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BG[1:0] select the bank group for x4/x8, and BG0 selects the bank group for x16; BA[1:0] select the bank, and A[17:0] select the row. See the Addressing section for more details). The address bits registered coincident with the READ or WRITE command are used to select the starting column location for the burst operation, determine if the auto PRECHARGE command is to be issued (via A10), and select BC4 or BL8 mode on-the-fly (OTF) (via A12) if enabled in the mode register. Prior to normal operation, the device must be powered up and initialized in a prede- fined manner. The following sections provide detailed information covering device reset and initialization, register definition, command descriptions, and device operation. NOTE: The use of the NOP command is allowed only when exiting maximum power saving mode or when entering gear-down mode. 16Gb: x4, x8, x16 DDR4 SDRAM Functional Description CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 35 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

RESET and Initialization Procedure To ensure proper device function, the power-up and reset initialization default values for the following mode register (MR) settings are defined as:

• Gear-down mode (MR3 A[3]): 0 = 1/2 rate
• Per-DRAM addressability (MR3 A[4]): 0 = disable
• Maximum power-saving mode (MR4 A[1]): 0 = disable
• CS to command/address latency (MR4 A[8:6]): 000 = disable
• CA parity latency mode (MR5 A[2:0]): 000 = disable
• Hard post package repair mode (MR4 A[13]): 0 = disable
• Soft post package repair mode (MR4 A[5]): 0 = disable Power-Up and Initialization Sequence The following sequence is required for power-up and initialization: 1. Apply power (RESET_n and TEN should be maintained below 0.2 × V DD while sup- plies ramp up; all other inputs may be undefined). When supplies have ramped to a valid stable level, RESET_n must be maintained below 0.2 × V DD for a minimum of tPW_RESET_L and TEN must be maintained below 0.2 × VDD for a minimum of 700μs. CKE is pulled LOW anytime before RESET_n is de-asserted (minimum time of 10ns). The power voltage ramp time between 300mV to V DD,min must be no greater than 200ms, and during the ramp, VDD must be greater than or equal to VDDQ and (VDD - VDDQ) < 0.3V . VPP must ramp at the same time or up to 10 minutes prior to VDD, and VPP must be equal to or higher than VDD at all times. The total time for which VPP is powered and VDD is unpowered should not exceed 360 cu- mulative hours. After VDD has ramped and reached a stable level, RESET_n must go high within 10 minutes. After RESET_n goes high, the initialization sequence must be started within 3 seconds. For debug purposes, the 10 minute and 3 sec- ond delay limits may be extended to 60 minutes each provided the DRAM is oper- ated in this debug mode for no more than 360 cumulative hours. During power-up, the supply slew rate is governed by the limits stated in the table below and either condition A or condition B listed below must be met. Table 5: Supply Power-up Slew Rate Symbol Min Max Unit Comment VDD_SL, VDDQ_SL, VPP_SL 0.004 600 V/ms Measured between 300mV and 80% of supply minimum VDD_ona N/A 200 ms V DD maximum ramp time from 300mV to VDD minimum VDDQ_ona N/A 200 ms V DDQ maximum ramp time from 300mV to VDDQ minimum Note: 1. 20 MHz band-limited measurement.
• Condition A: – Apply V PP without any slope reversal before or at the same time as VDD and VDDQ. 16Gb: x4, x8, x16 DDR4 SDRAM RESET and Initialization Procedure CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 36 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

–V DD and VDDQ are driven from a single-power converter output and apply VDD/VDDQ without any slope reversal before or at the same time as VTT and VREFCA. – The voltage levels on all balls other than V DD, VDDQ, VSS, and VSSQ must be less than or equal to VDDQ and VDD on one side and must be greater than or equal to VSSQ and VSS on the other side. –V TT is limited to 0.76V MAX when the power ramp is complete. –V REFCA tracks VDD/2.

• Condition B: – Apply V PP without any slope reversal before or at the same time as VDD. – Apply V DD without any slope reversal before or at the same time as VDDQ. – Apply V DDQ without any slope reversal before or at the same time as VTT and VREFCA. – The voltage levels on all pins other than V PP, VDD, VDDQ, VSS, and VSSQ must be less than or equal to VDDQ and VDD on one side and must be larger than or equal to VSSQ and VSS on the other side. 2. After RESET_n is de-asserted, wait for a minimum of 500us, but no longer than 3 seconds, before allowing CKE to be registered HIGH at clock edge Td. During this time, the device will start internal state initialization; this will be done independ- ently of external clocks. A reasonable attempt was made in the design to power up with the following default MR settings: gear-down mode (MR3 A[3]): 0 = 1/2 rate; per-DRAM addressability (MR3 A[4]): 0 = disable; maximum power-down (MR4 A[1]): 0 = disable; CS to command/address latency (MR4 A[8:6]): 000 = disable; CA parity latency mode (MR5 A[2:0]): 000 = disable. However, it should be assumed that at power up the MR settings are undefined and should be programmed as shown below. 3. Clocks (CK_t, CK_c) need to be started and stabilized for at least 10ns or 5 tCK (whichever is larger) before CKE is registered HIGH at clock edge Td. Because CKE is a synchronous signal, the corresponding setup time to clock ( tIS) must be met. Also, a DESELECT command must be registered (with tIS setup time to clock) at clock edge Td. After the CKE is registered HIGH after RESET , CKE needs to be con- tinuously registered HIGH until the initialization sequence is finished, including expiration of tDLLK and tZQinit. 4. The device keeps its ODT in High-Z state as long as RESET_n is asserted. Further, the SDRAM keeps its ODT in High-Z state after RESET_n de-assertion until CKE is registered HIGH. The ODT input signal may be in an undefined state until tIS be- fore CKE is registered HIGH. When CKE is registered HIGH, the ODT input signal may be statically held either LOW or HIGH. If R TT(NOM) is to be enabled in MR1, the ODT input signal must be statically held LOW . In all cases, the ODT input sig- nal remains static until the power-up initialization sequence is finished, including the expiration of tDLLK and tZQinit. 5. After CKE is registered HIGH, wait a minimum of RESET CKE EXIT time, tXPR, be- fore issuing the first MRS command to load mode register (tXPR = MAX (tXS, 5 × tCK). 6. Issue MRS command to load MR3 with all application settings, wait tMRD. 7. Issue MRS command to load MR6 with all application settings, wait tMRD. 8. Issue MRS command to load MR5 with all application settings, wait tMRD. 9. Issue MRS command to load MR4 with all application settings, wait tMRD. 10. Issue MRS command to load MR2 with all application settings, wait tMRD. 11. Issue MRS command to load MR1 with all application settings, wait tMRD. 16Gb: x4, x8, x16 DDR4 SDRAM RESET and Initialization Procedure CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 37 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

1. Issue MRS command to load MR0 with all application settings, wait tMOD. 13. Issue a ZQCL command to start ZQ calibration. 14. Wait for tDLLK and tZQinit to complete. 15. The device will be ready for normal operation. Once the DRAM has been initial- ized, if the DRAM is in an idle state longer than 960ms, then either (a) REF com- mands must be issued within tREFI constraints (specification for posting allowed) or (b) CKE or CS_n must toggle once within every 960ms interval of idle time. For debug purposes, the 960ms delay limit maybe extended to 60 minutes provided the DRAM is operated in this debug mode for no more than 360 cumulative hours. A stable valid V DD level is a set DC level (0Hz to 250 KHz) and must be no less than VDD,min and no greater than VDD,max. If the set DC level is altered anytime after initializa- tion, the DLL reset and calibrations must be performed again after the new set DC level is stable. AC noise of ±60mV (greater than 250 KHz) is allowed on V DD provided the noise doesn't alter VDD to less than VDD,min or greater than VDD,max. A stable valid VDDQ level is a set DC level (0Hz to 250 KHz) and must be no less than VDDQ,min and no greater than VDDQ,max. If the set DC level is altered anytime after initial- ization, the DLL reset and calibrations must be performed again after the new set DC level is stable. AC noise of ±60mV (greater than 250 KHz) is allowed on V DDQ provided the noise doesn't alter VDDQ to less than VDDQ,min or greater than VDDQ,max. A stable valid VPP level is a set DC level (0Hz to 250 KHz) and must be no less than VPP ,min and no greater than VPP ,max. If the set DC level is altered anytime after initializa- tion, the DLL reset and calibrations must be performed again after the new set DC level is stable. AC noise of ±120mV (greater than 250KHz) is allowed on V PP provided the noise doesn't alter VPP to less than VPP ,min or greater than VPP ,max. 16Gb: x4, x8, x16 DDR4 SDRAM RESET and Initialization Procedure CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 38 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Figure 12: RESET and Initialization Sequence at Power-On Ramping CKE RTT BG, BA tPW_RESET_L CK_t, CK_c Command Note 1 Note 1 TdTc Don’t CareTime Break tIS ODT Th tMRD tMOD MRSMRS Valid Valid tMRD tMRD MRS MRxMRxMRx MRS MRx Ti Tj Tk RESET_n T = 500μs Valid TeTa Tb Tf ZQCL tIS Static LOW in case RTT(NOM) is enabled at time Tg, otherwise static HIGH or LOW tIS tIS tXPR Valid T (MIN) = 10ns VDD, VDDQ VPP tDLLK tZQinit tCKSRX Tg Notes: 1. From time point Td until Tk, a DES command must be applied between MRS and ZQCL commands. 2. MRS commands must be issued to all mode registers that have defined settings. 3. In general, there is no specific sequence for setting the MRS locations (except for de- pendent or co-related features, such as ENABLE DLL in MR1 prior to RESET DLL in MR0, for example). 4. TEN is not shown; however, it is assumed to be held LOW. RESET Initialization with Stable Power Sequence The following sequence is required for RESET at no power interruption initialization: 1. Assert RESET_n below 0.2 × V DD any time when reset is needed (all other inputs may be undefined). RESET_n needs to be maintained for minimum tPW_RESET . CKE is pulled LOW before RESET_n being de-asserted (minimum time 10ns). 2. Follow Steps 2 through 10 in the Reset and Initialization Sequence at Power-On Ramping procedure. When the reset sequence is complete, all counters except the refresh counters have been reset and the device is ready for normal operation. 16Gb: x4, x8, x16 DDR4 SDRAM RESET and Initialization Procedure CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 39 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Figure 13: RESET Procedure at Power Stable Condition CKE RTT BG, BA tPW_RESET_S CK_t, CK_c Command Note 1 Note 1 TdTc Don’t CareTime Break tIS ODT Th tMRD tMOD MRSMRS Valid Valid tMRD tMRD MRS MRxMRxMRx MRS MRx Ti Tj Tk RESET_n T = 500μs Valid TeTa Tb Tf ZQCL tIS Static LOW in case RTT(NOM) is enabled at time Tg, otherwise static HIGH or LOW tIS tIS tXPR Valid T (MIN) = 10ns VDD, VDDQ VPP tDLLK tZQinit tCKSRX Tg Notes: 1. From time point Td until Tk, a DES command must be applied between MRS and ZQCL commands. 2. MRS commands must be issued to all mode registers that have defined settings. 3. In general, there is no specific sequence for setting the MRS locations (except for de- pendent or co-related features, such as ENABLE DLL in MR1 prior to RESET DLL in MR0, for example). 4. TEN is not shown; however, it is assumed to be held LOW. Uncontrolled Power-Down Sequence In the event of an uncontrolled ramping down of VPP supply, VPP is allowed to be less than VDD provided the following conditions are met:

• Condition A: V PP and VDD/VDDQ are ramping down (as part of turning off) from nor- mal operating levels.
• Condition B: The amount that V PP may be less than VDD/VDDQ is less than or equal to 500mV .
• Condition C: The time V PP may be less than VDD is ื10ms per occurrence with a total accumulated time in this state ื100ms. 16Gb: x4, x8, x16 DDR4 SDRAM RESET and Initialization Procedure CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 40 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

• Condition D: The time V PP may be less than 2.0V and above VSS while turning off is ื15ms per occurrence with a total accumulated time in this state ื150ms. Programming Mode Registers For application flexibility, various functions, features, and modes are programmable in seven mode registers (MRn) provided by the device as user defined variables that must be programmed via a MODE REGISTER SET (MRS) command. Because the default val- ues of the mode registers are not defined, contents of mode registers must be fully ini- tialized and/or re-initialized; that is, they must be written after power-up and/or reset for proper operation. The contents of the mode registers can be altered by re-executing the MRS command during normal operation. When programming the mode registers, even if the user chooses to modify only a sub-set of the MRS fields, all address fields within the accessed mode register must be redefined when the MRS command is is- sued. MRS and DLL RESET commands do not affect array contents, which means these commands can be executed any time after power-up without affecting the array con- tents. The MRS command cycle time, tMRD, is required to complete the WRITE operation to the mode register and is the minimum time required between the two MRS commands shown in the tMRD Timing figure. Some of the mode register settings affect address/command/control input functionali- ty. In these cases, the next MRS command can be allowed when the function being up- dated by the current MRS command is completed. These MRS commands don’t apply tMRD timing to the next MRS command; however, the input cases have unique MR set- ting procedures, so refer to individual function descriptions:
• Gear-down mode
• Per-DRAM addressability
• CMD address latency
• CA parity latency mode REFDQ training value
• V REFDQ training mode
• V REFDQ training range Some mode register settings may not be supported because they are not required by certain speed bins. 16Gb: x4, x8, x16 DDR4 SDRAM Programming Mode Registers CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 41 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Maximum power savings mode , Per-DRAM addressability mode, and CA parity latency mode The mode register contents can be changed using the same command and timing re- quirements during normal operation as long as the device is in idle state; that is, all banks are in the precharged state with tRP satisfied, all data bursts are completed, and CKE is HIGH prior to writing into the mode register. If the RTT(NOM) feature is enabled in the mode register prior to and/or after an MRS command, the ODT signal must contin- uously be registered LOW, ensuring R TT is in an off state prior to the MRS command. The ODT signal may be registered HIGH after tMOD has expired. If the RTT(NOM) feature is disabled in the mode register prior to and after an MRS command, the ODT signal can be registered either LOW or HIGH before, during, and after the MRS command. The mode registers are divided into various fields depending on functionality and modes. In some mode register setting cases, function updating takes longer than tMOD. This type of MRS does not apply tMOD timing to the next valid command, excluding DES. These MRS command input cases have unique MR setting procedures, so refer to indi- vidual function descriptions. 16Gb: x4, x8, x16 DDR4 SDRAM Programming Mode Registers CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 43 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Mode register 0 (MR0) controls various device operating modes as shown in the follow- ing register definition table. Not all settings listed may be available on a die; only set- tings required for speed bin support are available. MR0 is written by issuing the MRS command while controlling the states of the BGx, BAx, and Ax address pins. The map- ping of address pins during the MRS command is shown in the following MR0 Register Definition table. Table 6: Address Pin Mapping Address bus BG1 BG0 BA1 BA0 A17 RAS CAS WE A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Mode register 2 1 2 0 1 9 1 8 1 7 ––– 1 3 1 2 1 1 1 0 9876543210 Note: 1. RAS_n, CAS_n, and WE_n must be LOW during MODE REGISTER SET command. Table 7: MR0 Register Definition Mode Register Description

21 RFU

0 = Must be programmed to 0 1 = Reserved 20:18 MR select 000 = MR0 001 = MR1 010 = MR2 011 = MR3 100 = MR4 101 = MR5 110 = MR6 111 = DNU

17 N/A on 4Gb and 8Gb, RFU

0 = Must be programmed to 0 1 = Reserved 13,11:9 WR (WRITE recovery)/RTP (READ-to-PRECHARGE) 0000 = 10 / 5 clocks 0001 = 12 / 6 clocks 0010 = 14 / 7 clocks 0011 = 16 / 8 / clocks 0100 = 18 / 9 clocks 0101 = 20 /10 clocks 0110 = 24 / 12 clocks 0111 = 22 / 11 clocks 1000 = 26 / 13 clocks1 1001 = 28 / 14 clocks2 1010 through 1111 = Reserved 16Gb: x4, x8, x16 DDR4 SDRAM Mode Register 0 CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 44 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Table 7: MR0 Register Definition (Continued) Mode Register Description

8 DLL reset

0 = No 1 = Yes

7 Test mode (TM) – Manufacturer use only

0 = Normal operating mode, must be programmed to 0 12, 6:4, 2 CAS latency (CL) – Delay in clock cycles from the internal READ command to first data-out 00000 = 9 clocks 00001 = 10 clocks 00010 = 11 clocks 00011 = 12 clocks 00100 = 13 clocks 00101 = 14 clocks 00110 = 15 clocks 00111 = 16 clocks 01000 = 18 clocks 01001 = 20 clocks 01010 = 22 clocks 01011 = 24 clocks 01100 = 23 clocks 01101 = 17 clocks1 01110 = 19 clocks1 01111 = 21 clocks 1 10000 = 25 clocks 10001 = 26 clocks 10011 = 28 clocks 10100 = 29 clocks 10101 = 30 clocks 10110 = 31 clocks 10111 = 32 clocks

3 Burst type (BT) – Data burst ordering within a READ or WRITE burst access

0 = Nibble sequential 1 = Interleave 1:0 Burst length (BL) – Data burst size associated with each read or write access 00 = BL8 (fixed) 01 = BC4 or BL8 (on-the-fly) 10 = BC4 (fixed) 11 = Reserved Notes: 1. Not allowed when 1/4 rate gear-down mode is enabled. 2. If WR requirement exceeds 28 clocks or RTP exceeds 14 clocks, WR should be set to 28 clocks and RTP should be set to 14 clocks. Burst Length, Type, and Order Accesses within a given burst may be programmed to sequential or interleaved order. The ordering of accesses within a burst is determined by the burst length, burst type, 16Gb: x4, x8, x16 DDR4 SDRAM Mode Register 0 CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 45 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

and the starting column address as shown in the following table. Burst length options include fixed BC4, fixed BL8, and on-the-fly (OTF), which allows BC4 or BL8 to be selec- ted coincidentally with the registration of a READ or WRITE command via A12/BC_n. Table 8: Burst Type and Burst Order Note 1 applies to the entire table Burst Length READ/ WRITE Starting Column Address (A[2, 1, 0]) Burst Type = Sequential (Decimal) Burst Type = Interleaved (Decimal) Notes BC4 READ 0 0 0 0, 1, 2, 3, T, T, T, T 0, 1, 2, 3, T, T, T, T 2, 3 BL8 READ 0 0 0 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 Notes: 1. 0...7 bit number is the value of CA[2:0] that causes this bit to be the first read during a burst. 2. When setting burst length to BC4 (fixed) in MR0, the internal WRITE operation starts two clock cycles earlier than for the BL8 mode, meaning the starting point for tWR and tWTR will be pulled in by two clocks. When setting burst length to OTF in MR0, the in- ternal WRITE operation starts at the same time as a BL8 (even if BC4 was selected during column time using A12/BC4_n) meaning that if the OTF MR0 setting is used, the starting point for tWR and tWTR will not be pulled in by two clocks as described in the BC4 (fixed) case. 3. T = Output driver for data and strobes are in High-Z. V = Valid logic level (0 or 1), but respective buffer input ignores level on input pins. X = “Don’t Care.” CAS Latency The CAS latency (CL) setting is defined in the MR0 Register Definition table. CAS laten- cy is the delay, in clock cycles, between the internal READ command and the availability of the first bit of output data. The device does not support half-clock latencies. The 16Gb: x4, x8, x16 DDR4 SDRAM Mode Register 0 CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 46 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

overall read latency (RL) is defined as additive latency (AL) + CAS latency (CL): RL = AL + CL. Test Mode The normal operating mode is selected by MR0[7] and all other bits set to the desired values shown in the MR0 Register Definition table. Programming MR0[7] to a value of 1 places the device into a DRAM manufacturer-defined test mode to be used only by the manufacturer, not by the end user. No operations or functionality is specified if MR0[7] = 1. Write Recovery (WR)/READ-to-PRECHARGE The programmed write recovery (WR) value is used for the auto precharge feature along with tRP to determine tDAL. WR for auto precharge (MIN) in clock cycles is calculated by dividing tWR (in ns) by tCK (in ns) and rounding to the next integer using the round- ing algorithms found in the Converting Time-Based Specifications to Clock-Based Re- quirements section. The WR value must be programmed to be equal to or larger than tWR (MIN). When both DM and write CRC are enabled in the mode register, the device calculates CRC before sending the write data into the array; tWR values will change when enabled. If there is a CRC error, the device blocks the WRITE operation and dis- cards the data. Internal READ-to-PRECHARGE (RTP) command delay for auto precharge (MIN) in clock cycles is calculated by dividing tRTP (in ns) by tCK (in ns) and rounding to the next integer using the rounding algorithms found in the Converting Time-Based Specifica- tions to Clock-Based Requirements section. The RTP value in the mode register must be programmed to be equal to or larger than RTP (MIN). The programmed RTP value is used with tRP to determine the ACT timing to the same bank. DLL RESET The DLL reset bit is self-clearing, meaning that it returns to the value of 0 after the DLL RESET function has been issued. After the DLL is enabled, a subsequent DLL RESET should be applied. Any time the DLL RESET function is used, tDLLK must be met before functions requiring the DLL can be used. Such as READ commands or synchronous ODT operations, for example. 16Gb: x4, x8, x16 DDR4 SDRAM Mode Register 0 CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 47 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Mode register 1 (MR1) controls various device operating modes as shown in the follow- ing register definition table. Not all settings listed may be available on a die; only set- tings required for speed bin support are available. MR1 is written by issuing the MRS command while controlling the states of the BGx, BAx, and Ax address pins. The map- ping of address pins during the MRS command is shown in the following MR1 Register Definition table. Table 9: Address Pin Mapping Address bus BG1 BG0 BA1 BA0 A17 RAS CAS WE A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Mode register 2 1 2 0 1 9 1 8 1 7 ––– 1 3 1 2 1 1 1 0 9876543210 Note: 1. RAS_n, CAS_n, and WE_n must be LOW during MODE REGISTER SET command. Table 10: MR1 Register Definition Mode Register Description 0 = Must be programmed to 0 1 = Reserved 20:18 MR select 000 = MR0 001 = MR1 010 = MR2 011 = MR3 100 = MR4 101 = MR5 110 = MR6 111 = DNU 0 = Must be programmed to 0 1 = Reserved

12 Data output disable (Qoff) – Output buffer disable

0 = Enabled (normal operation) 1 = Disabled (both ODI and R TT)

11 Termination data strobe (TDQS) – Additional termination pins (x8 configuration only)

0 = TDQS disabled 1 = TDQS enabled 16Gb: x4, x8, x16 DDR4 SDRAM Mode Register 1 CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 48 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Table 10: MR1 Register Definition (Continued) Mode Register Description 10, 9, 8 Nominal ODT (RTT(NOM) – Data bus termination setting 000 = RTT(NOM) disabled 001 = RZQ/4 (60 ohm) 010 = RZQ/2 (120 ohm) 011 = RZQ/6 (40 ohm) 100 = RZQ/1 (240 ohm) 101 = RZQ/5 (48 ohm) 110 = RZQ/3 (80 ohm) 111 = RZQ/7 (34 ohm)

7 Write leveling (WL) – Write leveling mode

0 = Disabled (normal operation) 1 = Enabled (enter WL mode) 13, 6, 5 Rx CTLE Control 000 = Vendor Default 001 = Vendor Defined 010 = Vendor Defined 011 = Vendor Defined 100 = Vendor Defined 101 = Vendor Defined 110 = Vendor Defined 111 = Vendor Defined 4, 3 Additive latency (AL) – Command additive latency setting 00 = 0 (AL disabled) 01 = CL - 1 10 = CL - 2 11 = Reserved 2, 1 Output driver impedance (ODI) – Output driver impedance setting 00 = RZQ/7 (34 ohm) 01 = RZQ/5 (48 ohm) 10 = Reserved (Although not JEDEC-defined and not tested, this setting will provide RZQ/6 or 40 ohm) 11 = Reserved

0 DLL enable – DLL enable feature

0 = DLL disabled 1 = DLL enabled (normal operation) Note: 1. Not allowed when 1/4 rate gear-down mode is enabled. DLL Enable/DLL Disable The DLL must be enabled for normal operation and is required during power-up initial- ization and upon returning to normal operation after having the DLL disabled. During normal operation (DLL enabled with MR1[0]) the DLL is automatically disabled when entering the SELF REFRESH operation and is automatically re-enabled upon exit of the SELF REFRESH operation. Any time the DLL is enabled and subsequently reset, tDLLK clock cycles must occur before a READ or SYNCHRONOUS ODT command can be is- sued to allow time for the internal clock to be synchronized with the external clock. Fail- 16Gb: x4, x8, x16 DDR4 SDRAM Mode Register 1 CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 49 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

ing to wait for synchronization to occur may result in a violation of the tDQSCK, tAON, or tAOF parameters. During tDLLK, CKE must continuously be registered HIGH. The device does not require DLL for any WRITE operation, except when RTT(WR) is enabled and the DLL is required for proper ODT operation. The direct ODT feature is not supported during DLL off mode. The ODT resistors must be disabled by continuously registering the ODT pin LOW and/or by programming the R TT(NOM) bits MR1[9,6,2] = 000 via an MRS command during DLL off mode. The dynamic ODT feature is not supported in DLL off mode; to disable dynamic ODT externally, use the MRS command to set RTT(WR), MR2[10:9] = 00. Output Driver Impedance Control The output driver impedance of the device is selected by MR1[2,1], as shown in the MR1 Register Definition table. ODT RTT(NOM) Values The device is capable of providing three different termination values: RTT(Park), RTT(NOM), and RTT(WR). The nominal termination value, RTT(NOM), is programmed in MR1. A sepa- rate value, RTT(WR), may be programmed in MR2 to enable a unique RTT value when ODT is enabled during WRITE operations. The RTT(WR) value can be applied during WRITE commands even when RTT(NOM) is disabled. A third RTT value, RTT(Park), is pro- gramed in MR5. RTT(Park) provides a termination value when the ODT signal is LOW . Additive Latency The ADDITIVE LATENCY (AL) operation is supported to make command and data buses efficient for sustainable bandwidths in the device. In this operation, the device al- lows a READ or WRITE command (either with or without auto precharge) to be issued immediately after the ACTIVATE command. The command is held for the time of AL be- fore it is issued inside the device. READ latency (RL) is controlled by the sum of the AL and CAS latency (CL) register settings. WRITE latency (WL) is controlled by the sum of the AL and CAS WRITE latency (CWL) register settings. Table 11: Additive Latency (AL) Settings A4 A3 AL 0 0 0 (AL disabled) 0 1 CL - 1 1 0 CL - 2 1 1 Reserved Note: 1. AL has a value of CL - 1 or CL - 2 based on the CL values programmed in the MR0 regis- ter. Rx CTLE Control The Mode Register for Rx CTLE Control MR1[A13,A6,A5] is vendor specific. Since CTLE circuits can not be typically bypassed a disable option is not provided. Instead, a vendor optimized setting is given. It should be noted that the settings are not specifically linear 16Gb: x4, x8, x16 DDR4 SDRAM Mode Register 1 CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 50 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

in relationship to the vendor optimized setting, so the host may opt to instead walk through all the provided options and use the setting that works best in their environ- ment. Write Leveling For better signal integrity, the device uses fly-by topology for the commands, addresses, control signals, and clocks. Fly-by topology benefits from a reduced number of stubs and their lengths, but it causes flight-time skew between clock and strobe at every DRAM on the DIMM. This makes it difficult for the controller to maintain tDQSS, tDSS, and tDSH specifications. Therefore, the device supports a write leveling feature that al- lows the controller to compensate for skew. Output Disable The device outputs may be enabled/disabled by MR1[12] as shown in the MR1 Register Definition table. When MR1[12] is enabled (MR1[12] = 1) all output pins (such as DQ and DQS) are disconnected from the device, which removes any loading of the output drivers. For example, this feature may be useful when measuring module power. For normal operation, set MR1[12] to 0. Termination Data Strobe Termination data strobe (TDQS) is a feature of the x8 device and provides additional termination resistance outputs that may be useful in some system configurations. Be- cause this function is available only in a x8 configuration, it must be disabled for x4 and x16 configurations. While TDQS is not supported in x4 or x16 configurations, the same termination resist- ance function that is applied to the TDQS pins is applied to the DQS pins when enabled via the mode register. The TDQS, DBI, and DATA MASK (DM) functions share the same pin. When the TDQS function is enabled via the mode register, the DM and DBI functions are not supported. When the TDQS function is disabled, the DM and DBI functions can be enabled sepa- rately. Table 12: TDQS Function Matrix TDQS Data Mask (DM) WRITE DBI READ DBI Disabled Enabled Disabled Enabled or disabled Disabled Enabled Enabled or disabled Disabled Disabled Enabled or disabled Enabled Disabled Disabled Disabled 16Gb: x4, x8, x16 DDR4 SDRAM Mode Register 1 CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 51 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Mode register 2 (MR2) controls various device operating modes as shown in the follow- ing register definition table. Not all settings listed may be available on a die; only set- tings required for speed bin support are available. MR2 is written by issuing the MRS command while controlling the states of the BGx, BAx, and Ax address pins. The map- ping of address pins during the MRS command is shown in the following MR2 Register Definition table. Table 13: Address Pin Mapping Address bus BG1 BG0 BA1 BA0 A17 RAS CAS WE A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Mode register 2 1 2 0 1 9 1 8 1 7 ––– 1 3 1 2 1 1 1 0 9876543210 Note: 1. RAS_n, CAS_n, and WE_n must be LOW during MODE REGISTER SET command. Table 14: MR2 Register Definition Mode Register Description 0 = Must be programmed to 0 1 = Reserved 20:18 MR select 000 = MR0 001 = MR1 010 = MR2 011 = MR3 100 = MR4 101 = MR5 110 = MR6 111 = DNU 0 = Must be programmed to 0 1 = Reserved

13 RFU

0 = Must be programmed to 0 1 = Reserved

12 WRITE data bus CRC

0 = Disabled 1 = Enabled 16Gb: x4, x8, x16 DDR4 SDRAM Mode Register 2 CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 52 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Table 14: MR2 Register Definition (Continued) Mode Register Description 11:9 Dynamic ODT (RTT(WR)) – Data bus termination setting during WRITEs 000 = RTT(WR) disabled (WRITE does not affect RTT value) 001 = RZQ/2 (120 ohm) 010 = RZQ/1 (240 ohm) 011 = High-Z 100 = RZQ/3 (80 ohm) 101 = Reserved 110 = Reserved 111 = Reserved 7:6 Low-power auto self refresh (LPASR) – Mode summary 00 = Manual mode - Normal operating temperature range (T C: -40°C–85°C) 01 = Manual mode - Reduced operating temperature range (TC: -40°C–45°C) 10 = Manual mode - Extended operating temperature range (TC: -40°C–105°C) 11 = ASR mode - Automatically switching among all modes 5:3 CAS WRITE latency (CWL) – Delay in clock cycles from the internal WRITE command to first data-in 1tCK WRITE preamble 000 = 9 (DDR4-1600)1 001 = 10 (DDR4-1866) 010 = 11 (DDR4-2133/1600) 011 = 12 (DDR4-2400/1866) 100 = 14 (DDR4-2666/2133) 101 = 16 (DDR4-2933,3200/2400) 110 = 18 (DDR4-2666) 111 = 20 (DDR4-2933, 3200) CAS WRITE latency (CWL) – Delay in clock cycles from the internal WRITE command to first data-in tCK WRITE preamble 000 = N/A 001 = N/A 010 = N/A 011 = N/A 100 = 14 (DDR4-2400) 101 = 16 (DDR4-2666/2400) 110 = 18 (DDR4-2933, 3200/2666) 111 = 20 (DDR4-2933, 3200) 8, 2 RFU 0 = Must be programmed to 0 1 = Reserved 1:0 RFU 0 = Must be programmed to 0 1 = Reserved Note: 1. Not allowed when 1/4 rate gear-down mode is enabled. 16Gb: x4, x8, x16 DDR4 SDRAM Mode Register 2 CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 53 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

CAS WRITE latency (CWL) is defined by MR2[5:3] as shown in the MR2 Register Defini- tion table. CWL is the delay, in clock cycles, between the internal WRITE command and the availability of the first bit of input data. The device does not support any half-clock latencies. The overall WRITE latency (WL) is defined as additive latency (AL) + parity la- tency (PL) + CAS WRITE latency (CWL): WL = AL +PL + CWL. Low-Power Auto Self Refresh Low-power auto self refresh (LPASR) is supported in the device. Applications requiring SELF REFRESH operation over different temperature ranges can use this feature to opti- mize the I DD6 current for a given temperature range as specified in the MR2 Register Definition table. Dynamic ODT In certain applications and to further enhance signal integrity on the data bus, it is de- sirable to change the termination strength of the device without issuing an MRS com- mand. This may be done by configuring the dynamic ODT (R TT(WR)) settings in MR2[11:9]. In write leveling mode, only RTT(NOM) is available. Write Cyclic Redundancy Check Data Bus The write cyclic redundancy check (CRC) data bus feature during writes has been added to the device. When enabled via the mode register, the data transfer size goes from the normal 8-bit (BL8) frame to a larger 10-bit UI frame, and the extra two UIs are used for the CRC information. 16Gb: x4, x8, x16 DDR4 SDRAM Mode Register 2 CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 54 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Mode register 3 (MR3) controls various device operating modes as shown in the follow- ing register definition table. Not all settings listed may be available on a die; only set- tings required for speed bin support are available. MR3 is written by issuing the MRS command while controlling the states of the BGx, BAx, and Ax address pins. The map- ping of address pins during the MRS command is shown in the following MR3 Register Definition table. Table 15: Address Pin Mapping Address bus BG1 BG0 BA1 BA0 A17 RAS CAS WE A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Mode register 2 1 2 0 1 9 1 8 1 7 ––– 1 3 1 2 1 1 1 0 9876543210 Note: 1. RAS_n, CAS_n, and WE_n must be LOW during MODE REGISTER SET command. Table 16: MR3 Register Definition Mode Register Description 0 = Must be programmed to 0 1 = Reserved 20:18 MR select 000 = MR0 001 = MR1 010 = MR2 011 = MR3 100 = MR4 101 = MR5 110 = MR6 111 = DNU 0 = Must be programmed to 0 1 = Reserved 0 = Must be programmed to 0 1 = Reserved 12:11 Multipurpose register (MPR) – Read format 00 = Serial 01 = Parallel 10 = Staggered 11 = Reserved 10:9 WRITE CMD latency when CRC/DM enabled 00 = 4CK (DDR4-1600) 01 = 5CK (DDR4-1866/2133/2400/2666) 10 = 6CK (DDR4-2933/3200) 11 = Reserved 16Gb: x4, x8, x16 DDR4 SDRAM Mode Register 3 CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 55 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Table 16: MR3 Register Definition (Continued) Mode Register Description 8:6 Fine granularity refresh mode 000 = Normal mode (fixed 1x) 001 = Fixed 2x 010 = Fixed 4x 011 = Reserved 100 = Reserved 101 = On-the-fly 1x/2x 110 = On-the-fly 1x/4x 111 = Reserved

5 Temperature sensor status

0 = Disabled 1 = Enabled

4 Per-DRAM addressability

0 = Normal operation (disabled) 1 = Enable

3 Gear-down mode – Ratio of internal clock to external data rate

0 = [1:1]; (1/2 rate data) 1 = [2:1]; (1/4 rate data)

2 Multipurpose register (MPR) access

0 = Normal operation 1 = Data flow from MPR 1:0 MPR page select 00 = Page 0 01 = Page 1 10 = Page 2 11 = Page 3 (restricted for DRAM manufacturer use only) Multipurpose Register The multipurpose register (MPR) is used for several features:

• Readout of the contents of the MR n registers
• WRITE and READ system patterns used for data bus calibration
• Readout of the error frame when the command address parity feature is enabled To enable MPR, issue an MRS command to MR3[2] = 1. MR3[12:11] define the format of read data from the MPR. Prior to issuing the MRS command, all banks must be in the idle state (all banks precharged and tRP met). After MPR is enabled, any subsequent RD or RDA commands will be redirected to a specific mode register. The mode register location is specified with the READ command using address bits. The MR is split into upper and lower halves to align with a burst length limitation of 8. Pow- er-down mode, SELF REFRESH, and any other nonRD/RDA or nonWR/WRA com- mands are not allowed during MPR mode. The RESET function is supported during MPR mode, which requires device re-initialization. 16Gb: x4, x8, x16 DDR4 SDRAM Mode Register 3 CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 56 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

WRITE Command Latency When CRC/DM is Enabled The WRITE command latency (WCL) must be set when both write CRC and DM are en- abled for write CRC persistent mode. This provides the extra time required when com- pleting a WRITE burst when write CRC and DM are enabled. This means at data rates less than or equal to 1600 MT/s then 4nCK is used, 5nCK or 6nCK are not allowed; at data rates greater than 1600 MT/s and less than or equal to 2666 MT/s then 5nCK is used, 4nCK or 6nCK are not allowed; and at data rates greater than 2666 MT/s and less than or equal to 3200 MT/s then 6nCK is used; 4nCK or 5nCK are not allowed. Fine Granularity Refresh Mode This mode had been added to DDR4 to help combat the performance penalty due to refresh lockout at high densities. Shortening tRFC and decreasing cycle time allows more accesses to the chip and allows for increased scheduling flexibility. Temperature Sensor Status This mode directs the DRAM to update the temperature sensor status at MPR Page 2, MPR0 [4,3]. The temperature sensor setting should be updated within 32ms; when an MPR read of the temperature sensor status bits occurs, the temperature sensor status should be no older than 32ms. Per-DRAM Addressability This mode allows commands to be masked on a per device basis providing any device in a rank (devices sharing the same command and address signals) to be programmed individually. As an example, this feature can be used to program different ODT or V REF values on DRAM devices within a given rank. Gear-Down Mode The device defaults in 1/2 rate (1N) clock mode and uses a low frequency MRS com- mand followed by a sync pulse to align the proper clock edge for operating the control lines CS_n, CKE, and ODT when in 1/4 rate (2N) mode. For operation in 1/2 rate mode, no MRS command or sync pulse is required. 16Gb: x4, x8, x16 DDR4 SDRAM Mode Register 3 CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 57 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Mode register 4 (MR4) controls various device operating modes as shown in the follow- ing register definition table. Not all settings listed may be available on a die; only set- tings required for speed bin support are available. MR4 is written by issuing the MRS command while controlling the states of the BGx, BAx, and Ax address pins. The map- ping of address pins during the MRS command is shown in the following MR4 Register Definition table. Table 17: Address Pin Mapping Address bus BG1 BG0 BA1 BA0 A17 RAS CAS WE A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Mode register 2 1 2 0 1 9 1 8 1 7 ––– 1 3 1 2 1 1 1 0 9876543210 Note: 1. RAS_n, CAS_n, and WE_n must be LOW during MODE REGISTER SET (MRS) command. Table 18: MR4 Register Definition Mode Register Description 0 = Must be programmed to 0 1 = Reserved 20:18 MR select 000 = MR0 001 = MR1 010 = MR2 011 = MR3 100 = MR4 101 = MR5 110 = MR6 111 = DNU 0 = Must be programmed to 0 1 = Reserved

13 Hard Post Package Repair (hPPR mode)

0 = Disabled 1 = Enabled

12 WRITE preamble setting

0 = 1 tCK toggle1 1 = 2tCK toggle (When operating in 2tCK WRITE preamble mode, CWL must be programmed to a value at least 1 clock greater than the lowest CWL setting supported in the applicable tCK range.)

11 READ preamble setting

0 = 1tCK toggle1 1 = 2tCK toggle

10 READ preamble training

0 = Disabled 1 = Enabled 16Gb: x4, x8, x16 DDR4 SDRAM Mode Register 4 CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 58 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Table 18: MR4 Register Definition (Continued) Mode Register Description

9 Self refresh abort mode

0 = Disabled 1 = Enabled 8:6 CMD (CAL) address latency 000 = 0 clocks (disabled) 001 =3 clocks 010 = 4 clocks 011 = 5 clocks 100 = 6 clocks 101 = 8 clocks 110 = Reserved 111 = Reserved 5 soft Post Package Repair (sPPR mode) 0 = Disabled 1 = Enabled

4 Internal V

0 = Disabled 1 = Enabled

3 Temperature controlled refresh mode

0 = Disabled 1 = Enabled

2 Temperature controlled refresh range

0 = Normal temperature mode 1 = Extended temperature mode

1 Maximum power savings mode

0 = Normal operation 1 = Enabled

0 RFU

0 = Must be programmed to 0 1 = Reserved Note: 1. Not allowed when 1/4 rate gear-down mode is enabled. Hard Post Package Repair Mode The hard post package repair (hPPR) mode feature is JEDEC optional for 4Gb DDR4 memories. Performing an MPR read to page 2 MPR0 [7] indicates whether hPPR mode is available (A7 = 1) or not available (A7 = 0). hPPR mode provides a simple and easy repair method of the device after placed in the system. One row per bank can be repaired. The repair process is irrevocable so great care should be exercised when using. Soft Post Package Repair Mode The soft post package repair (sPPR) mode feature is JEDEC optional for 4Gb and 8Gb DDR4 memories. Performing an MPR read to page 2 MPR0 [6] indicates whether sPPR mode is available (A6 = 1) or not available (A6 = 0). sPPR mode provides a simple and 16Gb: x4, x8, x16 DDR4 SDRAM Mode Register 4 CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 59 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

easy repair method of the device after placed in the system. One row per bank can be repaired. The repair process is revocable by either doing a reset or power-down or by rewriting a new address in the same bank. WRITE Preamble Programmable WRITE preamble, tWPRE, can be set to 1tCK or 2tCK via the MR4 register. The 1tCK setting is similar to DDR3. However, when operating in 2tCK WRITE preamble mode, CWL must be programmed to a value at least 1 clock greater than the lowest CWL setting supported in the applicable tCK range. Some even settings will require addition of 2 clocks. If the alternate longer CWL was used, the additional clocks will not be required. READ Preamble Programmable READ preamble tRPRE can be set to 1tCK or 2tCK via the MR4 register. Both the 1tCK and 2tCK DDR4 preamble settings are different from that defined for the DDR3 SDRAM. Both DDR4 READ preamble settings may require the memory controller to train (or read level) its data strobe receivers using the READ preamble training. READ Preamble Training Programmable READ preamble training can be set to 1tCK or 2tCK. This mode can be used by the memory controller to train or READ level its data strobe receivers. Temperature-Controlled Refresh When temperature-controlled refresh mode is enabled, the device may adjust the inter- nal refresh period to be longer than tREFI of the normal temperature range by skipping external REFRESH commands with the proper gear ratio. For example, the DRAM tem- perature sensor detected less than 45°C. Normal temperature mode covers the range of -40°C to 85°C, while the extended temperature range covers -40°C to 105°C. Command Address Latency COMMAND ADDRESS LATENCY (CAL) is a power savings feature and can be enabled or disabled via the MRS setting. CAL is defined as the delay in clock cycles ( tCAL) be- tween a CS_n registered LOW and its corresponding registered command and address. The value of CAL (in clocks) must be programmed into the mode register according to the tCAL(ns)/tCK(ns) rounding algorithms found in the Converting Time-Based Specifi- cations to Clock-Based Requirements section. Internal VREF Monitor This mode enables output of internally generated VREFDQ for monitoring on DQ0, DQ1, DQ2, and DQ3. May be used during VREFDQ training and test. While in this mode, RTT should be set to High-Z. VREF_time must be increased by 10ns if DQ load is 0pF , plus an additional 15ns per pF of loading. This measurement is for verification purposes and is NOT an external voltage supply pin. 16Gb: x4, x8, x16 DDR4 SDRAM Mode Register 4 CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 60 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Maximum Power Savings Mode This mode provides the lowest power mode where data retention is not required. When the device is in the maximum power saving mode, it does not need to guarantee data retention or respond to any external command (except the MAXIMUM POWER SAVING MODE EXIT command and during the assertion of RESET_n signal LOW). 16Gb: x4, x8, x16 DDR4 SDRAM Mode Register 4 CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 61 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Mode register 5 (MR5) controls various device operating modes as shown in the follow- ing register definition table. Not all settings listed may be available on a die; only set- tings required for speed bin support are available. MR5 is written by issuing the MRS command while controlling the states of the BGx, BAx, and Ax address pins. The map- ping of address pins during the MRS command is shown in the following MR5 Register Definition table. Table 19: Address Pin Mapping Address bus BG1 BG0 BA1 BA0 A17 RAS CAS WE A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Mode register 2 1 2 0 1 9 1 8 1 7 ––– 1 3 1 2 1 1 1 0 9876543210 Note: 1. RAS_n, CAS_n, and WE_n must be LOW during MODE REGISTER SET command. Table 20: MR5 Register Definition Mode Register Description 0 = Must be programmed to 0 1 = Reserved 20:18 MR select 000 = MR0 001 = MR1 010 = MR2 011 = MR3 100 = MR4 101 = MR5 110 = MR6 111 = DNU 0 = Must be programmed to 0 1 = Reserved 0 = Must be programmed to 0 1 = Reserved

12 Data bus inversion (DBI) – READ DBI enable

0 = Disabled 1 = Enabled

11 Data bus inversion (DBI) – WRITE DBI enable

0 = Disabled 1 = Enabled

10 Data mask (DM)

0 = Disabled 1 = Enabled 16Gb: x4, x8, x16 DDR4 SDRAM Mode Register 5 CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 62 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Table 20: MR5 Register Definition (Continued) Mode Register Description

9 CA parity persistent error mode

0 = Disabled 1 = Enabled 8:6 Parked ODT value (R TT(Park)) 000 = RTT(Park) disabled 001 = RZQ/4 (60 ohm) 010 = RZQ/2 (120 ohm) 011 = RZQ/6 (40 ohm) 100 = RZQ/1 (240 ohm) 101 = RZQ/5 (48 ohm) 110 = RZQ/3 (80 ohm) 111 = RZQ/7 (34 ohm)

5 ODT input buffer for power-down

0 = Buffer enabled 1 = Buffer disabled

4 CA parity error status

0 = Clear 1 = Error

3 CRC error status

0 = Clear 1 = Error 2:0 CA parity latency mode 000 = Disable 001 = 4 clocks (DDR4-1600/1866/2133) 010 = 5 clocks (DDR4-2400/2666) 011 = 6 clocks (DDR4-2933/3200) 100 = Reserved 101 = Reserved 110 = Reserved 111 = Reserved Note: 1. Not allowed when 1/4 rate gear-down mode is enabled. Data Bus Inversion The DATA BUS INVERSION (DBI) function has been added to the device and is suppor- ted only for x8 and x16 configurations (x4 is not supported). The DBI function shares a common pin with the DM and TDQS functions. The DBI function applies to both READ and WRITE operations; Write DBI cannot be enabled at the same time the DM function is enabled. Refer to the TDQS Function Matrix table for valid configurations for all three functions (TDQS/DM/DBI). DBI is not allowed during MPR READ operation; during an MPR read, the DRAM ignores the read DBI enable setting in MR5 bit A12. DBI is not supported for 3DS devices and should be disabled in MR5. 16Gb: x4, x8, x16 DDR4 SDRAM Mode Register 5 CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 63 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

The DATA MASK (DM) function, also described as a partial write, has been added to the device and is supported only for x8 and x16 configurations (x4 is not supported). The DM function shares a common pin with the DBI and TDQS functions. The DM function applies only to WRITE operations and cannot be enabled at the same time the write DBI function is enabled. Refer to the TDQS Function Matrix table for valid configurations for all three functions (TDQS/DM/DBI). CA Parity Persistent Error Mode Normal CA parity mode (CA parity persistent mode disabled) no longer performs CA parity checking while the parity error status bit remains set at 1. However, with CA pari- ty persistent mode enabled, CA parity checking continues to be performed when the parity error status bit is set to a 1. ODT Input Buffer for Power-Down This feature determines whether the ODT input buffer is on or off during power-down. If the input buffer is configured to be on (enabled during power-down), the ODT input signal must be at a valid logic level. If the input buffer is configured to be off (disabled during power-down), the ODT input signal may be floating and the device does not pro- vide R TT(NOM) termination. However, the device may provide RTT(Park) termination de- pending on the MR settings. This is primarily for additional power savings. CA Parity Error Status The device will set the error status bit to 1 upon detecting a parity error. The parity error status bit remains set at 1 until the device controller clears it explicitly using an MRS command. CRC Error Status The device will set the error status bit to 1 upon detecting a CRC error. The CRC error status bit remains set at 1 until the device controller clears it explicitly using an MRS command. CA Parity Latency Mode CA parity is enabled when a latency value, dependent on tCK, is programmed; this ac- counts for parity calculation delay internal to the device. The normal state of CA parity is to be disabled. If CA parity is enabled, the device must ensure there are no parity er- rors before executing the command. CA parity signal (PAR) covers ACT_n, RAS_n/A16 , CAS_n/A15, WE_n/A14, and the address bus including bank address and bank group bits. The control signals CKE, ODT , and CS_n are not included in the parity calculation. 16Gb: x4, x8, x16 DDR4 SDRAM Mode Register 5 CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 64 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Mode register 6 (MR6) controls various device operating modes as shown in the follow- ing register definition table. Not all settings listed may be available on a die; only set- tings required for speed bin support are available. MR6 is written by issuing the MRS command while controlling the states of the BGx, BAx, and Ax address pins. The map- ping of address pins during the MRS command is shown in the following MR6 Register Definition table. Table 21: Address Pin Mapping Address bus BG1 BG0 BA1 BA0 A17 RAS CAS WE A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Mode register 2 1 2 0 1 9 1 8 1 7 ––– 1 3 1 2 1 1 1 0 9876543210 Note: 1. RAS_n, CAS_n, and WE_n must be LOW during MODE REGISTER SET command. Table 22: MR6 Register Definition Mode Register Description 0 = Must be programmed to 0 1 = Reserved 20:18 MR select 000 = MR0 001 = MR1 010 = MR2 011 = MR3 100 = MR4 101 = MR5 110 = MR6 111 = DNU

17 NA on 4Gb and 8Gb, RFU

0 = Must be programmed to 0 1 = Reserved 12:10 Data Rate 000 = Data rateื 1333 Mb/s (1333 Mb/s) 001 = 1333 Mb/s <Data rate ื1866 Mb/s (1600, 1866 Mb/s) 010 = 1866 Mb/s <Data rate ื2400 Mb/s (2133, 2400 Mb/s) 011 = 2400 Mb/s <Data rate ื2666 Mb/s (2666 Mb/s) 100 = 2666 Mb/s <Data rate ื3200 Mb/s (2933, 3200 Mb/s) 101 = Reserved 110 = Reserved 111 = Reserved 16Gb: x4, x8, x16 DDR4 SDRAM Mode Register 6 CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 65 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Table 22: MR6 Register Definition (Continued) Mode Register Description 13, 9, 8 RFU Default = 000; Must be programmed to 000 001 = Reserved 010 = Reserved 011 = Reserved 100 = Reserved 101 = Reserved 110 = Reserved 111 = Reserved 7 V REF Calibration Enable 0 = Disable 1 = Enable 6 V REF Calibration Range 0 = Range 1 1 = Range 2 5:0 V REF Calibration Value See the VREFDQ Range and Levels table in the VREFDQ Calibration section Data Rate Programming The device controller must program the correct data rate according to the operating fre- quency. VREFDQ Calibration Enable VREFDQ calibration is where the device internally generates its own VREFDQ to be used by the DQ input receivers. The VREFDQ value will be output on any DQ of DQ[3:0] for evalu- ation only. The device controller is responsible for setting and calibrating the internal V REFDQ level using an MRS protocol (adjust up, adjust down, and so on). It is assumed that the controller will use a series of writes and reads in conjunction with VREFDQ ad- justments to optimize and verify the data eye. Enabling VREFDQ calibration must be used whenever values are being written to the MR6[6:0] register. VREFDQ Calibration Range The device defines two VREFDQ calibration ranges: Range 1 and Range 2. Range 1 sup- ports VREFDQ between 60% and 92% of VDDQ while Range 2 supports VREFDQ between 45% and 77% of VDDQ, as seen in VREFDQ Specification table. Although not a restriction, Range 1 was targeted for module-based designs and Range 2 was added to target point- to-point designs. VREFDQ Calibration Value Fifty settings provide approximately 0.65% of granularity steps sizes for both Range 1 and Range 2 of V REFDQ, as seen in VREFDQ Range and Levels table in the VREFDQ Calibra- tion section. 16Gb: x4, x8, x16 DDR4 SDRAM Mode Register 6 CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 66 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Table 23: Truth Table – Command Notes 1–5 apply to the entire table; Note 6 applies to all READ/WRITE commands Function Symbol Prev. CKE Pres. CKE CS_n ACT_n RAS_n/A16 CAS_n/A15 WE_n/A14 BG[1:0] BA [1:0] C[2:0] A12/BC_n A[13,11] A10/AP A[9:0] Notes MODE REGISTER SET MRS H H L H L L L BG BA V OP code 7 REFRESH REF H H L H L L H V V VVVVV Self refresh entry SRE H L L H L L H V V V V V V V 8, 9, 10 Self refresh exit SRX L H H X X X X X X X X X X X 8, 9, 10, 11LHHHHVVVVVVV Single-bank PRECHARGE PRE H H L H L H L BG BA V V V L V PRECHARGE all banks PREA H H L H L H L V V V V V H V Reserved for future use RFU H H LHLHH R F U Bank ACTIVATE ACT H H L L Row address (RA) BG BA V Row address (RA) WRITE BL8 fixed, BC4 fixed WR H H L H H L L BG BA V V V L CA BC4OTF WRS4 H H L H H L L BG BA V L V L CA BL8OTF WRS8 H H L H H L L BG BA V H V L CA WRITE with auto precharge BL8 fixed, BC4 fixed WRA H H L H H L L BG BA V V V H CA BC4OTF WRAS4 H H L H H L L BG BA V L V H CA BL8OTF WRAS8 H H L H H L L BG BA V H V H CA READ BL8 fixed, BC4 fixed RD H H L H H L H BG BA V V V L CA BC4OTF RDS4 H H L H H L H BG BA V L V L CA BL8OTF RDS8 H H L H H L H BG BA V H V L CA READ with auto precharge BL8 fixed, BC4 fixed RDA H H L H H L H BG BA V V V H CA BC4OTF RDAS4 H H L H H L H BG BA V L V H CA BL8OTF RDAS8 H H L H H L H BG BA V H V H CA NO OPERATION NOP H H L H H H H V V V V V V V 12 Device DESELECTED DES H H H X X X X X X X XXXX 1 3 Power-down entry PDE H L H X X X X X X X X X X X 10, 14 Power-down exit PDX L H H X X X X X XXXXXX 10, 14 ZQ CALIBRATION LONG ZQCL H H L H H H L X X X X X H X ZQ CALIBRATION SHORT ZQCS H H L H H H L X X X X X L X 16Gb: x4, x8, x16 DDR4 SDRAM Truth Tables CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 67 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Notes: 1. • BG = Bank group address

• BA = Bank address
• RA = Row address
• CA = Column address
• BC_n = Burst chop
• X = “Don’t Care”
• V = Valid 2. All DDR4 SDRAM commands are defined by states of CS_n, ACT_n, RAS_n/A16, CAS_n/ A15, WE_n/A14, and CKE at the rising edge of the clock. The MSB of BG, BA, RA, and CA are device density- and configuration-dependent. When ACT_n = H, pins RAS_n/A16, CAS_n/A15, and WE_n/A14 are used as command pins RAS_n, CAS_n, and WE_n, respec- tively. When ACT_n = L, pins RAS_n/A16, CAS_n/A15, and WE_n/A14 are used as address pins A16, A15, and A14, respectively. 3. RESET_n is enabled LOW and is used only for asynchronous reset and must be main- tained HIGH during any function. 4. Bank group addresses (BG) and bank addresses (BA) determine which bank within a bank group is being operated upon. For MRS commands, the BG and BA selects the spe- cific mode register location. 5. V means HIGH or LOW (but a defined logic level), and X means either defined or unde- fined (such as floating) logic level. 6. READ or WRITE bursts cannot be terminated or interrupted, and fixed/on-the-fly (OTF) BL will be defined by MRS. 7. During an MRS command, A17 is RFU and is device density- and configuration-depend- ent. 8. The state of ODT does not affect the states described in this table. The ODT function is not available during self refresh. 9. V PP and VREF (VREFCA) must be maintained during SELF REFRESH operation. 10. Refer to the Truth Table – CKE table for more details about CKE transition. 11. Controller guarantees self refresh exit to be synchronous. DRAM implementation has the choice of either synchronous or asynchronous. 12. The NO OPERATION (NOP) command may be used only when exiting maximum power saving mode or when entering gear-down mode. 13. The NOP command may not be used in place of the DESELECT command. 14. The power-down mode does not perform any REFRESH operation. 16Gb: x4, x8, x16 DDR4 SDRAM Truth Tables CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 68 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Table 24: Truth Table – CKE Notes 1–7, 9, and 20 apply to the entire table Current State CKE Command (n) Action (n) Notes Previous Cycle (n - 1) Present Cycle (n) Power-down L L X Maintain power-down 8, 10, 11 L H DES Power-down exit 8, 10, 12 Self refresh L L X Maintain self refresh 11, 13 L H DES Self refresh exit 8, 13, 14, 15 Bank(s) active H L DES Active power-down entry 8, 10, 12, 16 Reading H L DES Power-down entry 8, 10, 12, 16, 17 Writing H L DES Power-down entry 8, 10, 12, 16, 17 Precharging H L DES Power-down entry 8, 10, 12, 16, 17 Refreshing H L DES Precharge power-down entry 8, 12 All banks idle H L DES Precharge power-down entry 8, 10, 12, 16, 18 H L REFRESH Self refresh 16, 18, 19 Notes: 1. Current state is defined as the state of the DDR4 SDRAM immediately prior to clock edge n. 2. CKE (n) is the logic state of CKE at clock edge n; CKE (n-1) was the state of CKE at the previous clock edge. 3. COMMAND (n) is the command registered at clock edge n, and ACTION (n) is a result of COMMAND (n); ODT is not included here. 4. All states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document. 5. The state of ODT does not affect the states described in this table. The ODT function is not available during self refresh. 6. During any CKE transition (registration of CKE H->L or CKE H->L), the CKE level must be maintained until 1 nCK prior to tCKE (MIN) being satisfied (at which time CKE may tran- sition again). 7. DESELECT and NOP are defined in the Truth Table – Command table. 8. For power-down entry and exit parameters, see the Power-Down Modes section. 9. CKE LOW is allowed only if tMRD and tMOD are satisfied. 10. The power-down mode does not perform any REFRESH operations. 11. X = "Don’t Care" (including floating around V REF) in self refresh and power-down. X al- so applies to address pins. 12. The DESELECT command is the only valid command for power-down entry and exit. 13. V PP and VREFCA must be maintained during SELF REFRESH operation. 14. On self refresh exit, the DESELECT command must be issued on every clock edge occur- ring during the tXS period. READ or ODT commands may be issued only after tXSDLL is satisfied. 15. The DESELECT command is the only valid command for self refresh exit. 16. Self refresh cannot be entered during READ or WRITE operations. For a detailed list of restrictions see the SELF REFRESH Operation and Power-Down Modes sections. 17. If all banks are closed at the conclusion of the READ, WRITE, or PRECHARGE command, then precharge power-down is entered; otherwise, active power-down is entered. 16Gb: x4, x8, x16 DDR4 SDRAM Truth Tables CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 69 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

1. Idle state is defined as all banks are closed ( tRP, tDAL, and so on, satisfied), no data bursts are in progress, CKE is HIGH, and all timings from previous operations are satis- fied ( tMRD, tMOD, tRFC, tZQinit, tZQoper, tZQCS, and so on), as well as all self refresh ex- it and power-down exit parameters are satisfied (tXS, tXP, tXSDLL, and so on). 19. Self refresh mode can be entered only from the all banks idle state. 20. For more details about all signals, see the Truth Table – Command table; must be a legal command as defined in the table. NOP Command The NO OPERATION (NOP) command was originally used to instruct the selected DDR4 SDRAM to perform a NOP (CS_n = LOW and ACT_n, RAS_n/A16, CAS_n/A15, and WE_n/A14 = HIGH). This prevented unwanted commands from being registered during idle or wait states. NOP command general support has been removed and the com- mand should not be used unless specifically allowed, which is when exiting maximum power-saving mode or when entering gear-down mode. DESELECT Command The deselect function (CS_n HIGH) prevents new commands from being executed; therefore, with this command, the device is effectively deselected. Operations already in progress are not affected. DLL-Off Mode DLL-off mode is entered by setting MR1 bit A0 to 0, which will disable the DLL for sub- sequent operations until the A0 bit is set back to 1. The MR1 A0 bit for DLL control can be switched either during initialization or during self refresh mode. Refer to the Input Clock Frequency Change section for more details. The maximum clock frequency for DLL-off mode is specified by the parameter tCKDLL_OFF . Due to latency counter and timing restrictions, only one CL value and CWL value (in MR0 and MR2 respectively) are supported. The DLL-off mode is only required to sup- port setting both CL = 10 and CWL = 9. DLL-off mode will affect the read data clock-to-data strobe relationship ( tDQSCK), but not the data strobe-to-data relationship (tDQSQ, tQH). Special attention is needed to line up read data to the controller time domain. Compared with DLL-on mode, where tDQSCK starts from the rising clock edge (AL + CL) cycles after the READ command, the DLL-off mode tDQSCK starts (AL + CL - 1) cy- cles after the READ command. Another difference is that tDQSCK may not be small compared to tCK (it might even be larger than tCK), and the difference between tDQSCK (MIN) and tDQSCK (MAX) is significantly larger than in DLL-on mode. The tDQSCK (DLL-off) values are undefined and the user is responsible for training to the data-eye. The timing relations on DLL-off mode READ operation are shown in the following dia- gram, where CL = 10, AL = 0, and BL = 8. 16Gb: x4, x8, x16 DDR4 SDRAM NOP Command CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 70 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Figure 16: DLL-Off Mode Read Timing Operation CK_c CK_t Command T0 T1 T6 T7 T8 T9 T10 T11 T12 T13 T14 Address DQS_t, DQS_c (DLL-on) DQS_c (DLL-on) CL = 10, AL = 0 CL = 10, AL = 0 RL (DLL-on) = AL + CL = 10 RL (DLL-off) = AL + (CL - 1) = 9 tDQSCK (DLL-off) MAX tDQSCK (DLL-off) MIN tDQSCK (MAX) DQS_t, DQS_c (DLL-off) DQS_c (DLL-off) DQS_c (DLL-off) DQS_t, DQS_c (DLL-off) RD DES DES DES DES DES DES DES DES DES DES Don’t CareTransitioning data DIN b DIN b+1 DIN b+2 DIN b+3 DIN b+4 DIN b+5 DIN b+6 DIN b+7 DIN b DIN b+1 DIN b+2 DIN b+3 DIN b+4 DIN b+5 DIN b+6 DIN b+7 DIN b DIN b+1 DIN b+2 DIN b+3 DIN b+4 DIN b+5 DIN b+6 DIN b+7 tDQSCK (MIN) ARD 16Gb: x4, x8, x16 DDR4 SDRAM DLL-Off Mode CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 71 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

DLL-On/Off Switching Procedures The DLL-off mode is entered by setting MR1 bit A0 to 0; this will disable the DLL for subsequent operations until the A0 bit is set back to 1. DLL Switch Sequence from DLL-On to DLL-Off To switch from DLL-on to DLL-off requires the frequency to be changed during self re- fresh, as outlined in the following procedure: 1. Starting from the idle state (all banks pre-charged, all timings fulfilled, and, to dis- able the DLL, the DRAM on-die termination resistors, R TT(NOM), must be in High-Z before MRS to MR1.) 2. Set MR1 bit A0 to 1 to disable the DLL. 3. Wait tMOD. 4. Enter self refresh mode; wait until tCKSRE/tCKSRE_PAR is satisfied. 5. Change frequency, following the guidelines in the Input Clock Frequency Change section. 6. Wait until a stable clock is available for at least tCKSRX at device inputs. 7. Starting with the SELF REFRESH EXIT command, CKE must continuously be regis- tered HIGH until all tMOD timings from any MRS command are satisfied. In addi- tion, if any ODT features were enabled in the mode registers when self refresh mode was entered, the ODT signal must continuously be registered LOW until all tMOD timings from any MRS command are satisfied. If RTT(NOM) was disabled in the mode registers when self refresh mode was entered, the ODT signal is "Don't Care." 8. Wait tXS_FAST , tXS_ABORT , or tXS, and then set mode registers with appropriate values (an update of CL, CWL, and WR may be necessary; a ZQCL command can also be issued after tXS_FAST).

• tXS_FAST: ZQCL, ZQCS, and MRS commands. For MRS commands, only CL and WR/RTP registers in MR0, the CWL register in MR2, and gear-down mode in MR3 may be accessed provided the device is not in per-DRAM addressability mode. Access to other device mode registers must satisfy tXS timing.
• tXS_ABORT: If MR4 [9] is enabled, then the device aborts any ongoing refresh and does not increment the refresh counter. The controller can issue a valid command after a delay of tXS_ABORT . Upon exiting from self refresh, the device requires a minimum of one extra REFRESH command before it is put back into self refresh mode. This requirement remains the same regardless of the MRS bit setting for self refresh abort. tXS: ACT , PRE, PREA, REF , SRE, PDE, WR, WRS4, WRS8, WRA, WRAS4, WRAS8, RD, RDS4, RDS8, RDA, RDAS4, and RDAS8. 9. Wait tMOD to complete. The device is ready for the next command. 16Gb: x4, x8, x16 DDR4 SDRAM DLL-On/Off Switching Procedures CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 72 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Figure 17: DLL Switch Sequence from DLL-On to DLL-Off CK_c CK_t Ta Tb0 Tb1 Tc Td Te0 Te1 Tf Tg Th Don’t CareTime Break CKE Command Enter self refresh Exit self refresh ODT Valid SRE3 DES SRX 6 Valid Valid Valid Valid MRS2 tXS_FAST tXS_ABORTtRP tXS Note 4 tCPDED tIS tCKSRE/tCKSRE_PAR tCKSRX5 Valid Address Valid Valid7 Valid8 Valid9 tIS tCKESR/tCKESR_PAR Notes: 1. Starting in the idle state. R TT in stable state. 2. Disable DLL by setting MR1 bit A0 to 0. 3. Enter SR. 4. Change frequency. 5. Clock must be stable tCKSRX. 6. Exit SR. 7. Update mode registers allowed with DLL-off settings met. 16Gb: x4, x8, x16 DDR4 SDRAM DLL-On/Off Switching Procedures CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 73 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

DLL-Off to DLL-On Procedure To switch from DLL-off to DLL-on (with required frequency change) during self refresh: 1. Starting from the idle state (all banks pre-charged, all timings fulfilled, and DRAM ODT resistors (RTT(NOM)) must be in High-Z before self refresh mode is entered.) 2. Enter self refresh mode; wait until tCKSRE/tCKSRE_PAR are satisfied. 3. Change frequency (following the guidelines in the Input Clock Frequency Change section). 4. Wait until a stable clock is available for at least tCKSRX at device inputs. 5. Starting with the SELF REFRESH EXIT command, CKE must continuously be regis- tered HIGH until tDLLK timing from the subsequent DLL RESET command is sat- isfied. In addition, if any ODT features were enabled in the mode registers when self refresh mode was entered, the ODT signal must continuously be registered LOW or HIGH until tDLLK timing from the subsequent DLL RESET command is satisfied. If RTT(NOM) disabled in the mode registers when self refresh mode was entered, the ODT signal is "Don't Care." 6. Wait tXS or tXS_ABORT , depending on bit 9 in MR4, then set MR1 bit A0 to 0 to en- able the DLL. 7. Wait tMRD, then set MR0 bit A8 to 1 to start DLL reset. 8. Wait tMRD, then set mode registers with appropriate values; an update of CL, CWL, and WR may be necessary. After tMOD is satisfied from any proceeding MRS command, a ZQCL command can also be issued during or after tDLLK. 9. Wait for tMOD to complete. Remember to wait tDLLK after DLL RESET before ap- plying any command requiring a locked DLL. In addition, wait for tZQoper in case a ZQCL command was issued. The device is ready for the next command. Figure 18: DLL Switch Sequence from DLL-Off to DLL-On CK_c CK_t Ta Tb0 Tb1 Tc Td Te0 Te1 Tf Tg Th Don’t CareTime Break CKE Command Enter self refresh Exit self refresh ODT Valid SRE3 DES SRX 6 Valid Valid Valid Valid MRS2 tXS_ABORT tRP tXS tMRD Note 4Note 1 tCPDED tIS tCKSRE/tCKSRE_PAR tCKSRX5 Valid Address Valid Valid7 tIS Valid7 Valid7 tCKESR/tCKESR_PAR Notes: 1. Starting in the idle state. 16Gb: x4, x8, x16 DDR4 SDRAM DLL-On/Off Switching Procedures CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 74 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

1. Enter SR. 3. Change frequency. 4. Clock must be stable tCKSRX. 5. Exit SR. 6. Set DLL to on by setting MR1 to A0 = 0. 7. Update mode registers. 8. Issue any valid command. Input Clock Frequency Change After the device is initialized, it requires the clock to be stable during almost all states of normal operation. This means that after the clock frequency has been set and is in the stable state, the clock period is not allowed to deviate except for what is allowed by the clock jitter and spread spectrum clocking (SSC) specifications. The input clock frequen- cy can be changed from one stable clock rate to another stable clock rate only when in self refresh mode. Outside of self refresh mode, it is illegal to change the clock frequen- cy. After the device has been successfully placed in self refresh mode and tCKSRE/ tCKSRE_PAR have been satisfied, the state of the clock becomes a "Don’t Care." Follow- ing a "Don’t Care," changing the clock frequency is permissible, provided the new clock frequency is stable prior to tCKSRX. When entering and exiting self refresh mode for the sole purpose of changing the clock frequency, the self refresh entry and exit specifica- tions must still be met as outlined in SELF REFRESH Operation. For the new clock frequency, additional MRS commands to MR0, MR2, MR3, MR4, MR5, and MR6 may need to be issued to program appropriate CL, CWL, gear-down mode, READ and WRITE preamble, Command Address Latency, and data rate values. When the clock rate is being increased (faster), the MR settings that require additional clocks should be updated prior to the clock rate being increased. In particular, the PL latency must be disabled when the clock rate changes, ie. while in self refresh mode. For example, if changing the clock rate from DDR4-2133 to DDR4-2933 with CA parity mode enabled, MR5[2:0] must first change from PL = 4 to PL = disable prior to PL = 6. The correct procedure would be to (1) change PL = 4 to disable via MR5 [2:0], (2) enter self refresh mode, (3) change clock rate from DDR4-2133 to DDR4-2933, (4) exit self re- fresh mode, (5) Enable CA parity mode setting PL = 6 vis MR5 [2:0]. If the MR settings that require additional clocks are updated after the clock rate has been increased, for example. after exiting self refresh mode, the required MR settings must be updated prior to removing the DRAM from the IDLE state, unless the DRAM is RESET . If the DRAM leaves the IDLE state to enter self refresh mode or ZQ Calibration, the updating of the required MR settings may be deferred to the next time the DRAM enters the IDLE state. If MR6 is issued prior to self refresh entry for the new data rate value, DLL will relock automatically at self refresh exit. However, if MR6 is issued after self refresh entry, MR0 must be issued to reset the DLL. The device input clock frequency can change only within the minimum and maximum operating frequency specified for the particular speed grade. Any frequency change be- low the minimum operating frequency would require the use of DLL-on mode to DLL- off mode transition sequence (see DLL-On/Off Switching Procedures). 16Gb: x4, x8, x16 DDR4 SDRAM Input Clock Frequency Change CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 75 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

For better signal integrity, DDR4 memory modules use fly-by topology for the com- mands, addresses, control signals, and clocks. Fly-by topology has benefits from the re- duced number of stubs and their length, but it also causes flight-time skew between clock and strobe at every DRAM on the DIMM. This makes it difficult for the controller to maintain tDQSS, tDSS, and tDSH specifications. Therefore, the device supports a write leveling feature to allow the controller to compensate for skew. This feature may not be required under some system conditions, provided the host can maintain the tDQSS, tDSS, and tDSH specifications. The memory controller can use the write leveling feature and feedback from the device to adjust the DQS (DQS_t, DQS_c) to CK (CK_t, CK_c) relationship. The memory con- troller involved in the leveling must have an adjustable delay setting on DQS to align the rising edge of DQS with that of the clock at the DRAM pin. The DRAM asynchronously feeds back CK, sampled with the rising edge of DQS, through the DQ bus. The controller repeatedly delays DQS until a transition from 0 to 1 is detected. The DQS delay estab- lished though this exercise would ensure the tDQSS specification. Besides tDQSS, tDSS and tDSH specifications also need to be fulfilled. One way to achieve this is to combine the actual tDQSS in the application with an appropriate duty cycle and jitter on the DQS signals. Depending on the actual tDQSS in the application, the actual values for tDQSL and tDQSH may have to be better than the absolute limits provided in the AC Timing Parameters section in order to satisfy tDSS and tDSH specifications. A conceptual tim- ing of this scheme is shown below. Figure 19: Write Leveling Concept, Example 1 diff_DQS diff_DQS DQ diff_DQS DQ T0 T1 T2 T3 T4 T5 CK_c CK_t T6 T7 Tn T0 T1 T2 T3 T4 CK_c CK_t T5 T6 0 or 1 00 0 0 or 1 Push DQS to capture the 0-1 transition 11 1 Source Destination DQS driven by the controller during leveling mode must be terminated by the DRAM based on the ranks populated. Similarly, the DQ bus driven by the DRAM must also be terminated at the controller. All data bits carry the leveling feedback to the controller across the DRAM configura- tions: x4, x8, and x16. On a x16 device, both byte lanes should be leveled independently. Therefore, a separate feedback mechanism should be available for each byte lane. The upper data bits should provide the feedback of the upper diff_DQS(diff_UDQS)-to- clock relationship; the lower data bits would indicate the lower diff_DQS(diff_LDQS)- to-clock relationship. 16Gb: x4, x8, x16 DDR4 SDRAM Write Leveling CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 76 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

The figure below is another representative way to view the write leveling procedure. Al- though it shows the clock varying to a static strobe, this is for illustrative purpose only; the clock does not actually change phase, the strobe is what actually varies. By issuing multiple WL bursts, the DQS strobe can be varied to capture with fair accuracy the time at which the clock edge arrives at the DRAM clock input buffer. Figure 20: Write Leveling Concept, Example 2 XXX CK_t CK_c CK_t CK_c CK_t CK_c DQS_t/ DQS_c DQ (CK 0 to 1) tWLH tWLH tWLO tWLS tWLS 000000000000 0 000000 0 XXX 111111 11111 1111 111 111 1111 111 DQ (CK 1 to 0) DRAM Setting for Write Leveling and DRAM TERMINATION Function in that Mode The DRAM enters into write leveling mode if A7 in MR1 is HIGH. When leveling is fin- ished, the DRAM exits write leveling mode if A7 in MR1 is LOW (see the MR Leveling Procedures table). Note that in write leveling mode, only DQS terminations are activa- ted and deactivated via the ODT pin, unlike normal operation (see DRAM DRAM TER- MINATION Function in Leveling Mode table). Table 25: MR Settings for Leveling Procedures Function MR1 Enable Disable Write leveling enable A7 1 0 Output buffer mode (Q off) A12 0 1 Table 26: DRAM TERMINATION Function in Leveling Mode ODT Pin at DRAM DQS_t/DQS_c Termination DQ Termination RTT(NOM) with ODT HIGH On Off 16Gb: x4, x8, x16 DDR4 SDRAM Write Leveling CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 77 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Table 26: DRAM TERMINATION Function in Leveling Mode (Continued) ODT Pin at DRAM DQS_t/DQS_c Termination DQ Termination RTT(Park) with ODT LOW On Off Notes: 1. In write leveling mode, with the mode's output buffer either disabled (MR1[bit7] = 1 and MR1[bit12] = 1) or with its output buffer enabled (MR1[bit7] = 1 and MR1[bit12] = 0), all R TT(NOM) and RTT(Park) settings are supported. 2. R TT(WR) is not allowed in write leveling mode and must be set to disable prior to enter- ing write leveling mode. Procedure Description The memory controller initiates the leveling mode of all DRAM by setting bit 7 of MR1 to 1. When entering write leveling mode, the DQ pins are in undefined driving mode. During write leveling mode, only the DESELECT command is supported, other than MRS commands to change the Qoff bit (MR1[A12]) and to exit write leveling (MR1[A7]). Upon exiting write leveling mode, the MRS command performing the exit (MR1[A7] = 0) may also change the other MR1 bits. Because the controller levels one rank at a time, the output of other ranks must be disabled by setting MR1 bit A12 to 1. The controller may assert ODT after tMOD, at which time the DRAM is ready to accept the ODT signal, unless DODTLon or DODTLoff have been altered (the ODT internal pipe delay is in- creased when increasing WRITE latency [WL] or READ latency [RL] by the previous MR command), then ODT assertion should be delayed by DODTLon after tMOD is satisfied, which means the delay is now tMOD + DODTLon. The controller may drive DQS_t LOW and DQS_c HIGH after a delay of tWLDQSEN, at which time the DRAM has applied ODT to these signals. After tDQSL and tWLMRD, the controller provides a single DQS_t, DQS_c edge, which is used by the DRAM to sample CK driven from the controller. tWLMRD (MAX) timing is controller dependent. The DRAM samples CK status with the rising edge of DQS and provides feedback on all the DQ bits asynchronously after tWLO timing. There is a DQ output uncertainty of tWLOE defined to allow mismatch on DQ bits. The tWLOE period is defined from the transition of the earliest DQ bit to the corresponding transition of the latest DQ bit. There are no read strobes (DQS_t, DQS_c) needed for these DQs. The controller sam- ples incoming DQ and either increments or decrements DQS delay setting and launch- es the next DQS pulse after some time, which is controller dependent. After a 0-to-1 transition is detected, the controller locks the DQS delay setting, and write leveling is achieved for the device. The following figure shows the timing diagram and parameters for the overall write leveling procedure. 16Gb: x4, x8, x16 DDR4 SDRAM Write Leveling CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 78 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Figure 21: Write Leveling Sequence (DQS Capturing CK LOW at T1 and CK HIGH at T2) tMOD tWLDQSEN tWLMRD tWLH tDQSH6tDQSL6 tDQSH6tDQSL6 tWLS tWLH tWLS NOP CK_t CK_c5 Command T1 T2 Early Prime DQ1 ODT Late Prime DQ1 diff_DQS4 DESMRS2 DES DES DES DES DES DES DES DES DES Don’t CareUndefined Driving Mode Time Break tWLO tWLO tWLO tWLO tWLOE tWLOE DES3 Notes: 1. The device drives leveling feedback on all DQs. 2. MRS: Load MR1 to enter write leveling mode. 3. diff_DQS is the differential data strobe. Timing reference points are the zero crossings. DQS_t is shown with a solid line; DQS_c is shown with a dotted line. 4. CK_t is shown with a solid dark line; CK_c is shown with a dotted line. 5. DQS needs to fulfill minimum pulse width requirements, tDQSH (MIN) and tDQSL (MIN), as defined for regular WRITEs; the maximum pulse width is system dependent. 6. tWLDQSEN must be satisfied following equation when using ODT:

• DLL = Enable, then tWLDQSEN > tMOD (MIN) + DODTLon + tADC
• DLL = Disable, then tWLDQSEN > tMOD (MIN) + tAONAS Write Leveling Mode Exit Write leveling mode should be exited as follows: 1. After the last rising strobe edge (see ~T0), stop driving the strobe signals (see ~Tc0). Note that from this point on, DQ pins are in undefined driving mode and will remain undefined, until tMOD after the respective MR command (Te1). 2. Drive ODT pin LOW ( tIS must be satisfied) and continue registering LOW (see Tb0). 3. After R TT is switched off, disable write leveling mode via the MRS command (see Tc2). 4. After tMOD is satisfied (Te1), any valid command can be registered. (MR com- mands can be issued after tMRD [Td1]). 16Gb: x4, x8, x16 DDR4 SDRAM Write Leveling CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 79 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Figure 22: Write Leveling Exit tMOD tWLO ODTL (OFF) tIS tMRD CK_t T0 T1 T2 Ta0 Tb0 Tc0 Tc1 Tc2 Td0 Td1 Te0 Te1 CK_c Command ODT RTT(DQS_t) RTT(DQS_c) RTT(DQ) DQ1 DQS_t, DQS_c DESDES DES DES DES DES DES DES DES Address MR1 Valid Valid Valid Valid Don’t CareTransitioning Time Break RTT(NON) Undefined Driving Mode tADC (MAX) tADC (MIN) DES RTT(Park) result = 1 Notes: 1. The DQ result = 1 between Ta0 and Tc0 is a result of the DQS signals capturing CK_t HIGH just after the T0 state. 2. See previous figure for specific tWLO timing. 16Gb: x4, x8, x16 DDR4 SDRAM Write Leveling CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 80 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

1. CA parity = Disable, CS to CA latency = Enable, Read DBI = Disable. 6. Enabling CAL mode does not impact ODT control timings. ODT control timings should be maintained with the same timing relationship relative to the command/address bus as when CAL is disabled. 16Gb: x4, x8, x16 DDR4 SDRAM Command Address Latency CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 85 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Low-Power Auto Self Refresh Mode An auto self refresh mode is provided for application ease. Auto self refresh mode is en- abled by setting MR2[6] = 1 and MR2[7] = 1. The device will manage self refresh entry over the supported temperature range of the DRAM. In this mode, the device will change its self refresh rate as the DRAM operating temperature changes, going lower at low temperatures and higher at high temperatures. Manual Self Refresh Mode If auto self refresh mode is not enabled, the low-power auto self refresh mode register must be manually programmed to one of the three self refresh operating modes. This mode provides the flexibility to select a fixed self refresh operating mode at the entry of the self refresh, according to the system memory temperature conditions. The user is responsible for maintaining the required memory temperature condition for the mode selected during the SELF REFRESH operation. The user may change the selected mode after exiting self refresh and before entering the next self refresh. If the temperature condition is exceeded for the mode selected, there is a risk to data retention resulting in loss of data. Table 27: Auto Self Refresh Mode MR2[7] MR2[6] Low-Power Auto Self Refresh Mode SELF REFRESH Operation Operating Temperature Range for Self Refresh Mode (DRAM TCASE) 0 0 Normal Variable or fixed normal self refresh rate maintains data retention at the normal oper- ating temperature. User is required to ensure that 85°C DRAM T CASE (MAX) is not exceeded to avoid any risk of data loss. -40°C to 85°C 1 0 Extended temperature Variable or fixed high self refresh rate opti- mizes data retention to support the exten- ded temperature range. -40°C to 105°C 0 1 Reduced temperature Variable or fixed self refresh rate or any oth- er DRAM power consumption reduction con- trol for the reduced temperature range. User is required to ensure 45°C DRAM T CASE (MAX) is not exceeded to avoid any risk of data loss. -40°C to 45°C 1 1 Auto self refresh Auto self refresh mode enabled. Self refresh power consumption and data retention are optimized for any given operating tempera- ture condition. All of the above 16Gb: x4, x8, x16 DDR4 SDRAM Low-Power Auto Self Refresh Mode CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 86 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Figure 31: Auto Self Refresh Ranges 45°C-40°C IDD6 Tc85°C 105°C Reduced temperature range Normal temperature range 2x refresh rate 1x refresh rate 1/2x refresh rate Extended temperature range 16Gb: x4, x8, x16 DDR4 SDRAM Low-Power Auto Self Refresh Mode CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 87 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

The MULTIPURPOSE REGISTER (MPR) function, MPR access mode, is used to write/ read specialized data to/from the DRAM. The MPR consists of four logical pages, MPR Page 0 through MPR Page 3, with each page having four 8-bit registers, MPR0 through MPR3. Page 0 can be read by any of three readout modes (serial, parallel, or staggered) while Pages 1, 2, and 3 can be read by only the serial readout mode. Page 3 is for DRAM vendor use only. MPR mode enable and page selection is done with MRS commands. Data bus inversion (DBI) is not allowed during MPR READ operation. Once the MPR access mode is enabled (MR3[2] = 1), only the following commands are allowed: MRS, RD, RDA WR, WRA, DES, REF , and RESET; RDA/WRA have the same func- tionality as RD/WR which means the auto precharge part of RDA/WRA is ignored. Pow- er-down mode and SELF REFRESH command are not allowed during MPR enable mode. No other command can be issued within tRFC after a REF command has been issued; 1x refresh (only) is to be used during MPR access mode. While in MPR access mode, MPR read or write sequences must be completed prior to a REFRESH command. Figure 32: MPR Block Diagram Memory core (all banks precharged) MR3 [2] = 1 DQ,s DM_n/DBI_n, DQS_t, DQS_c Four multipurpose registers (pages), each with four 8-bit registers: Data patterns (RD/WR) Error log (RD) Mode registers (RD) DRAM manufacture only (RD) MPR data flow Table 28: MR3 Setting for the MPR Access Mode Address Operation Mode Description 10 = Staggered .... 11 = Reserved A2 MPR access 0 = Standard operation (MPR not enabled) 1 = MPR data flow enabled A[1:0] MPR page selection 00 = Page 0 .... 01 = Page 1 10 = Page 2 .... 11 = Page 3 Table 29: DRAM Address to MPR UI Translation MPR Location [7] [6] [5] [4] [3] [2] [1] [0] DRAM address – Ax A7 A6 A5 A4 A3 A2 A1 A0 MPR UI – UIx UI0 UI1 UI2 UI3 UI4 UI5 UI6 UI7 16Gb: x4, x8, x16 DDR4 SDRAM Multipurpose Register CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 88 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Table 30: MPR Page and MPRx Definitions Address MPR Location [7] [6] [5] [4] [3] [2] [1] [0] Note MPR Page 0 – Read or Write (Data Patterns) BA[1:0] 00 = MPR0 01010 1 01 Read/ Write (default value lis- ted) 01 = MPR1 00110 0 11 10 = MPR2 00001 1 11 11 = MPR3 00000 0 00 MPR Page 1 – Read-only (Error Log) BA[1:0] 00 = MPR0 A7 A6 A5 A4 A3 A2 A1 A0 Read-on- ly01 = MPR1 CAS_n/A WE_n/A1 A13 A12 A11 A10 A9 A8 10 = MPR2 PAR ACT_n BG1 BG0 BA1 BA0 A17 RAS_n/A 11 = MPR3 CRC er- ror sta- tus CA pari- ty error status CA parity latency: [5] = MR5[0] C2 C1 C0 MPR Page 2 – Read-only (MRS Readout) BA[1:0] 00 = MPR0 hPPR support sPPR support RTT(WR) MR2[11] Temperature sen- sor status2 CRC write enable MR2[12] RTT(WR) MR2[10:9] Read-on- ly 01 = MPR1 V REFDQ traing- ing range MR6[6] VREFDQ training value: [6:1] = MR6[5:0] Gear- down enable MR3[3] 10 = MPR2 CAS latency: [7:3] = MR0[6:4,2,12] CAS write latency [2:0] = MR2[5:3] 11 = MPR3 R TT(NOM): [7:5] = MR1[10:8] R TT(Park): [4:2] = MR5[8:6] R ON: [1:0] = MR2[2:1] MPR Page 3 – Read-only (Restricted, except for MPR3 [3:0]) BA[1:0] 00 = MPR0 DC DC DC DC DC DC DC DC Read-on- ly01 = MPR1 DC DC DC DC DC DC DC DC 10 = MPR2 DC DC DC DC DC DC DC DC 11 = MPR3 DC DC DC DC MAC MAC MAC MAC Notes: 1. DC = "Don't Care" 2. MPR[4:3] 00 = Sub 1X refresh; MPR[4:3] 01 = 1X refresh; MPR[4:3] 10 = 2X refresh; MPR[4:3] 11 = Reserved MPR Reads MPR reads are supported using BL8 and BC4 modes. Burst length on-the-fly is not sup- ported for MPR reads. Data bus inversion (DBI) is not allowed during MPR READ opera- tion; the device will ignore the Read DBI enable setting in MR5 [12] when in MPR mode. READ commands for BC4 are supported with a starting column address of A[2:0] = 000 16Gb: x4, x8, x16 DDR4 SDRAM Multipurpose Register CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 89 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

or 100. After power-up, the content of MPR Page 0 has the default values, which are de- fined in Table 30. MPR page 0 can be rewritten via an MPR WRITE command. The de- vice maintains the default values unless it is rewritten by the DRAM controller. If the DRAM controller does overwrite the default values (Page 0 only), the device will main- tain the new values unless re-initialized or there is power loss. Timing in MPR mode:

• Reads (back-to-back) from Page 0 may use tCCD_S or tCCD_L timing between READ commands
• Reads (back-to-back) from Pages 1, 2, or 3 may not use tCCD_S timing between READ commands; tCCD_L must be used for timing between READ commands The following steps are required to use the MPR to read out the contents of a mode reg- ister (MPR Page x, MPRy). 1. The DLL must be locked if enabled. 2. Precharge all; wait until tRP is satisfied. 3. MRS command to MR3[2] = 1 (Enable MPR data flow), MR3[12:11] = MPR read for- mat, and MR3[1:0] MPR page. a. MR3[12:11] MPR read format: 1. 00 = Serial read format 2. 01 = Parallel read format 3. 10 = staggered read format 4. 11 = RFU b. MR3[1:0] MPR page: 1. 00 = MPR Page 0 2. 01 = MPR Page 1 3. 10 = MPR Page 2 4. 11 = MPR Page 3 tMRD and tMOD must be satisfied. 5. Redirect all subsequent READ commands to specific MPR x location. 6. Issue RD or RDA command. a. BA1 and BA0 indicate MPR x location: 1. 00 = MPR0 2. 01 = MPR1 3. 10 = MPR2 4. 11 = MPR3 b. A12/BC = 0 or 1; BL8 or BC4 fixed-only, BC4 OTF not supported. 1. If BL = 8 and MR0 A[1:0] = 01, A12/BC must be set to 1 during MPR READ commands. c. A2 = burst-type dependant: 1. BL8: A2 = 0 with burst order fixed at 0, 1, 2, 3, 4, 5, 6, 7 2. BL8: A2 = 1 not allowed 3. BC4: A2 = 0 with burst order fixed at 0, 1, 2, 3, T , T , T , T 4. BC4: A2 = 1 with burst order fixed at 4, 5, 6, 7, T , T , T , T d. A[1:0] = 00, data burst is fixed nibble start at 00. e. Remaining address inputs, including A10, and BG1 and BG0 are "Don’t Care." 7. After RL = AL + CL, DRAM bursts data from MPR x location; MPR readout format determined by MR3[A12,11,1,0]. 8. Steps 5 through 7 may be repeated to read additional MPR x locations. 9. After the last MPR x READ burst, tMPRR must be satisfied prior to exiting. 10. Issue MRS command to exit MPR mode; MR3[2] = 0. 16Gb: x4, x8, x16 DDR4 SDRAM Multipurpose Register CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 90 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

1. After the tMOD sequence is completed, the DRAM is ready for normal operation from the core (such as ACT). MPR Readout Format The MPR read data format can be set to three different settings: serial, parallel, and staggered. MPR Readout Serial Format The serial format is required when enabling the MPR function to read out the contents of an MRx, temperature sensor status, and the command address parity error frame. However, data bus calibration locations (four 8-bit registers) can be programmed to read out any of the three formats. The DRAM is required to drive associated strobes with the read data similar to normal operation (such as using MRS preamble settings). Serial format implies that the same pattern is returned on all DQ lanes, as shown the table below, which uses values programmed into the MPR via [7:0] as 0111 1111. Table 31: MPR Readout Serial Format Serial UI0 UI1 UI2 UI3 UI4 UI5 UI6 UI7 x4 Device D Q 0 01111111 D Q 1 01111111 D Q 2 01111111 D Q 3 01111111 x8 Device D Q 0 01111111 D Q 1 01111111 D Q 2 01111111 D Q 3 01111111 D Q 4 01111111 D Q 5 01111111 D Q 6 01111111 D Q 7 01111111 x16 Device D Q 0 01111111 D Q 1 01111111 D Q 2 01111111 D Q 3 01111111 D Q 4 01111111 D Q 5 01111111 D Q 6 01111111 D Q 7 01111111 D Q 8 01111111 16Gb: x4, x8, x16 DDR4 SDRAM Multipurpose Register CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 91 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Table 31: MPR Readout Serial Format (Continued) Serial UI0 UI1 UI2 UI3 UI4 UI5 UI6 UI7 D Q 9 01111111 DQ10 0 1 1 1 1 1 1 1 DQ11 0 1 1 1 1 1 1 1 DQ12 0 1 1 1 1 1 1 1 DQ13 0 1 1 1 1 1 1 1 DQ14 0 1 1 1 1 1 1 1 DQ15 0 1 1 1 1 1 1 1 MPR Readout Parallel Format Parallel format implies that the MPR data is returned in the first data UI and then repea- ted in the remaining UIs of the burst, as shown in the table below. Data pattern location 0 is the only location used for the parallel format. RD/RDA from data pattern locations 1, 2, and 3 are not allowed with parallel data return mode. In this example, the pattern programmed in the data pattern location 0 is 0111 1111. The x4 configuration only out- puts the first four bits (0111 in this example). For the x16 configuration, the same pat- tern is repeated on both the upper and lower bytes. Table 32: MPR Readout – Parallel Format Parallel UI0 UI1 UI2 UI3 UI4 UI5 UI6 UI7 x4 Device D Q 0 00000000 D Q 1 11111111 D Q 2 11111111 D Q 3 11111111 x8 Device D Q 0 00000000 D Q 1 11111111 D Q 2 11111111 D Q 3 11111111 D Q 4 11111111 D Q 5 11111111 D Q 6 11111111 D Q 7 11111111 x16 Device D Q 0 00000000 D Q 1 11111111 D Q 2 11111111 D Q 3 11111111 D Q 4 11111111 16Gb: x4, x8, x16 DDR4 SDRAM Multipurpose Register CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 92 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Table 32: MPR Readout – Parallel Format (Continued) Parallel UI0 UI1 UI2 UI3 UI4 UI5 UI6 UI7 D Q 5 11111111 D Q 6 11111111 D Q 7 11111111 D Q 8 00000000 D Q 9 11111111 DQ10 1 1 1 1 1 1 1 1 DQ11 1 1 1 1 1 1 1 1 DQ12 1 1 1 1 1 1 1 1 DQ13 1 1 1 1 1 1 1 1 DQ14 1 1 1 1 1 1 1 1 DQ15 1 1 1 1 1 1 1 1 MPR Readout Staggered Format Staggered format of data return is defined as the staggering of the MPR data across the lanes. In this mode, an RD/RDA command is issued to a specific data pattern location and then the data is returned on the DQ from each of the different data pattern loca- tions. For the x4 configuration, an RD/RDA to data pattern location 0 will result in data from location 0 being driven on DQ0, data from location 1 being driven on DQ1, data from location 2 being driven on DQ2, and so on, as shown below. Similarly, an RD/RDA command to data pattern location 1 will result in data from location 1 being driven on DQ0, data from location 2 being driven on DQ1, data from location 3 being driven on DQ2, and so on. Examples of different starting locations are also shown. Table 33: MPR Readout Staggered Format, x4 x4 READ MPR0 Command x4 READ MPR1 Command x4 READ MPR2 Command x4 READ MPR3 Command Stagger UI[7:0] Stagger UI[7:0] Stagger UI[7:0] Stagger UI[7:0] DQ0 MPR0 DQ0 MPR1 DQ0 MPR2 DQ0 MPR3 DQ1 MPR1 DQ1 MPR2 DQ1 MPR3 DQ1 MPR0 DQ2 MPR2 DQ2 MPR3 DQ2 MPR0 DQ2 MPR1 DQ3 MPR3 DQ3 MPR0 DQ3 MPR1 DQ3 MPR2 It is expected that the DRAM can respond to back-to-back RD/RDA commands to the MPR for all DDR4 frequencies so that a sequence (such as the one that follows) can be created on the data bus with no bubbles or clocks between read data. In this case, the system memory controller issues a sequence of RD(MPR0), RD(MPR1), RD(MPR2), RD(MPR3), RD(MPR0), RD(MPR1), RD(MPR2), and RD(MPR3). Table 34: MPR Readout Staggered Format, x4 – Consecutive READs Stagger UI[7:0] UI[15:8] UI[23:16] UI[31:24] UI[39:32] UI[47:40] UI[55:48] UI[63:56] DQ0 MPR0 MPR1 MPR2 MPR3 MPR0 MPR1 MPR2 MPR3 DQ1 MPR1 MPR2 MPR3 MPR0 MPR1 MPR2 MPR3 MPR0 16Gb: x4, x8, x16 DDR4 SDRAM Multipurpose Register CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 93 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Table 34: MPR Readout Staggered Format, x4 – Consecutive READs (Continued) Stagger UI[7:0] UI[15:8] UI[23:16] UI[31:24] UI[39:32] UI[47:40] UI[55:48] UI[63:56] DQ2 MPR2 MPR3 MPR0 MPR1 MPR2 MPR3 MPR0 MPR1 DQ3 MPR3 MPR0 MPR1 MPR2 MPR3 MPR0 MPR1 MPR2 For the x8 configuration, the same pattern is repeated on the lower nibble as on the up- per nibble. READs to other MPR data pattern locations follow the same format as the x4 case. A read example to MPR0 for x8 and x16 configurations is shown below. Table 35: MPR Readout Staggered Format, x8 and x16 x8 READ MPR0 Command x16 READ MPR0 Command x16 READ MPR0 Command Stagger UI[7:0] Stagger UI[7:0] Stagger UI[7:0] DQ0 MPR0 DQ0 MPR0 DQ8 MPR0 DQ1 MPR1 DQ1 MPR1 DQ9 MPR1 DQ2 MPR2 DQ2 MPR2 DQ10 MPR2 DQ3 MPR3 DQ3 MPR3 DQ11 MPR3 DQ4 MPR0 DQ4 MPR0 DQ12 MPR0 DQ5 MPR1 DQ5 MPR1 DQ13 MPR1 DQ6 MPR2 DQ6 MPR2 DQ14 MPR2 DQ7 MPR3 DQ7 MPR3 DQ15 MPR3 MPR READ Waveforms The following waveforms show MPR read accesses. Figure 33: MPR READ Timing T0 Ta0 Ta1 CK_t CK_c DQ DQS_t, DQS_c tMODtMPRR Tb0 Tc0 Tc1 Tc2 Tc3 Td0 Td1 Te0 Tf0 Tf1 DES DES DES DES MRS 3 Valid4 DESCommand MRS 1PREA DES READ DES DES Valid Valid Valid Valid Valid Valid ValidValidValid Valid Add 2 Valid ValidAddress CKE PL5 + AL + CL tRP tMOD UI0 UI1 UI2 UI5 UI6 UI7 MPE Enable MPE Disable Don’t CareTime Break Notes: 1. tCCD_S = 4tCK, Read Preamble = 1tCK. 2. Address setting: A[1:0] = 00b (data burst order is fixed starting at nibble, always 00b here) 16Gb: x4, x8, x16 DDR4 SDRAM Multipurpose Register CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 94 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

A2 = 0b (for BL = 8, burst order is fixed at 0, 1, 2, 3, 4, 5, 6, 7) BA1 and BA0 indicate the MPR location A10 and other address pins are "Don’t Care," including BG1 and BG0. A12 is "Don’t Care" when MR0 A[1:0] = 00 or 10 and must be 1b when MR0 A[1:0] = 01 3. Multipurpose registers read/write disable (MR3 A2 = 0). 4. Continue with regular DRAM command. 5. Parity latency (PL) is added to data output delay when CA parity latency mode is ena- bled. Figure 34: MPR Back-to-Back READ Timing T0 T1 T2 DQ DQS_t, DQS_c T3 T4 T5 T6 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 Ta7 Ta8 Ta9 Ta10 DES DES DES DES DES DES DES DES DES DES DES DESCommand READDES DES DES DES READ Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid ValidAdd2Valid Valid Add 2 Valid ValidAddress CKE PL3 + AL + CL tCCD_S1 DQ DQS_t, DQS_c UI0 UI1 UI2 UI3 UI0 UI1 UI2 UI3 UI0 UI1 UI2 UI3 UI4 UI5 UI6 UI7 UI0 UI1 UI2 UI3 UI4 UI5 UI6 UI7 CK_t CK_c Don’t CareTime Break Notes: 1. tCCD_S = 4tCK, Read Preamble = 1tCK. 2. Address setting: A[1:0] = 00b (data burst order is fixed starting at nibble, always 00b here) A2 = 0b (for BL = 8, burst order is fixed at 0, 1, 2, 3, 4, 5, 6, 7; for BC = 4, burst order is fixed at 0, 1, 2, 3, T, T, T, T) BA1 and BA0 indicate the MPR location A10 and other address pins are "Don’t Care," including BG1 and BG0. A12 is "Don’t Care" when MR0 A[1:0] = 00 or 10 and must be 1b when MR0 A[1:0] = 01 3. Parity latency (PL) is added to data output delay when CA parity latency mode is ena- bled. 16Gb: x4, x8, x16 DDR4 SDRAM Multipurpose Register CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 95 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Figure 35: MPR READ-to-WRITE Timing T0 T1 T2 DQ DQS_t, DQS_c tMPRR Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 Tb0 Tb1 Tb2 DES DES DES DES WRITE DES DESCommand DESREAD DES DES DES DES Valid Valid Valid Valid Add 2 Valid ValidValidAdd1 Valid Valid Valid ValidAddress CKE PL3 + AL + CL UI2 UI3UI0 UI1 UI4 UI5 UI6 UI7 CK_t CK_c Don’t CareTime Break Notes: 1. Address setting: A[1:0] = 00b (data burst order is fixed starting at nibble, always 00b here) A2 = 0b (for BL = 8, burst order is fixed at 0, 1, 2, 3, 4, 5, 6, 7) BA1 and BA0 indicate the MPR location A10 and other address pins are "Don’t Care," including BG1 and BG0. A12 is "Don’t Care" when MR0 A[1:0] = 00 and must be 1b when MR0 A[1:0] = 01 2. Address setting: BA1 and BA0 indicate the MPR location A[7:0] = data for MPR BA1 and BA0 indicate the MPR location A10 and other address pins are "Don’t Care" 3. Parity latency (PL) is added to data output delay when CA parity latency mode is ena- bled. MPR Writes MPR access mode allows 8-bit writes to the MPR Page 0 using the address bus A[7:0]. Data bus inversion (DBI) is not allowed during MPR WRITE operation. The DRAM will maintain the new written values unless re-initialized or there is power loss. The following steps are required to use the MPR to write to mode register MPR Page 0. 1. The DLL must be locked if enabled. 2. Precharge all; wait until tRP is satisfied. 3. MRS command to MR3[2] = 1 (enable MPR data flow) and MR3[1:0] = 00 (MPR Page 0); writes to 01, 10, and 11 are not allowed. 4. tMRD and tMOD must be satisfied. 5. Redirect all subsequent WRITE commands to specific MPR x location. 6. Issue WR or WRA command: a. BA1 and BA0 indicate MPR x location 1. 00 = MPR0 2. 01 = MPR1 3. 10 = MPR2 4. 11 = MPR3 b. A[7:0] = data for MPR Page 0, mapped A[7:0] to UI[7:0]. 16Gb: x4, x8, x16 DDR4 SDRAM Multipurpose Register CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 96 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

c. Remaining address inputs, including A10, and BG1 and BG0 are "Don’t Care." 7. tWR_MPR must be satisfied to complete MPR WRITE. 8. Steps 5 through 7 may be repeated to write additional MPR x locations. 9. After the last MPR x WRITE, tMPRR must be satisfied prior to exiting. 10. Issue MRS command to exit MPR mode; MR3[2] = 0. 11. When the tMOD sequence is completed, the DRAM is ready for normal operation from the core (such as ACT). MPR WRITE Waveforms The following waveforms show MPR write accesses. Figure 36: MPR WRITE and WRITE-to-READ Timing T0 Ta0 Ta1 DQ DQS_t, DQS_c tRP tMOD tWR_MPR Tb0 Tc0 Tc1 Tc2 Td0 Td1 Td2 Td3 Td4 Td5 READ DES DES DES DES DES DESCommand MRS 1PREA DES WRITE DES DES Add Valid Valid Valid Add 2 Valid ValidValidValid Valid Add 2 Valid ValidAddress CKE PL3 + AL + CL UI2 UI3UI0 UI1 UI4 UI5 UI6 UI7 CK_t CK_c MPR Enable Don’t CareTime Break Notes: 1. Multipurpose registers read/write enable (MR3 A2 = 1). 2. Address setting: BA1 and BA0 indicate the MPR location A10 and other address pins are "Don’t Care" 3. Parity latency (PL) is added to data output delay when CA parity latency mode is ena- bled. 16Gb: x4, x8, x16 DDR4 SDRAM Multipurpose Register CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 97 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

A[7:0] = data for MPR A10 and other address pins are "Don’t Care" 2. 1x refresh is only allowed when MPR mode is enabled. 16Gb: x4, x8, x16 DDR4 SDRAM Multipurpose Register CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 100 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

The DDR4 SDRAM defaults in 1/2 rate (1N) clock mode and uses a low-frequency MRS command (the MRS command has relaxed setup and hold) followed by a sync pulse (first CS pulse after MRS setting) to align the proper clock edge for operating the control lines CS_n, CKE, and ODT when in 1/4 rate (2N) mode. Gear-down mode is only sup- ported at DDR4-2666 and faster. For operation in 1/2 rate mode, neither an MRS com- mand or a sync pulse is required. Gear-down mode may only be entered during initiali- zation or self refresh exit and may only be exited during self refresh exit. CAL mode and CA parity mode must be disabled prior to gear-down mode entry. The two modes may be enabled after tSYNC_GEAR and tCMD_GEAR periods have been satisfied. The gener- al sequence for operation in 1/4 rate during initialization is as follows: 1. The device defaults to a 1N mode internal clock at power-up/reset. 2. Assertion of reset. 3. Assertion of CKE enables the DRAM. 4. MRS is accessed with a low-frequency N × tCK gear-down MRS command. (NtCK static MRS command is qualified by 1N CS_n. ) 5. The memory controller will send a 1N sync pulse with a low-frequency N × tCK NOP command. tSYNC_GEAR is an even number of clocks. The sync pulse is on an even edge clock boundary from the MRS command. 6. Initialization sequence, including the expiration of tDLLK and tZQinit, starts in 2N mode after tCMD_GEAR from 1N sync pulse. The device resets to 1N gear-down mode after entering self refresh. The general se- quence for operation in gear-down after self refresh exit is as follows: 1. MRS is set to 1, via MR3[3], with a low-frequency N × tCK gear-down MRS com- mand. a. The N tCK static MRS command is qualified by 1N CS_n, which meets tXS or tXS_ABORT . b. Only a REFRESH command may be issued to the DRAM before the N tCK stat- ic MRS command. 2. The DRAM controller sends a 1N sync pulse with a low-frequency N × tCK NOP command. a. tSYNC_GEAR is an even number of clocks. b. The sync pulse is on even edge clock boundary from the MRS command. 3. A valid command not requiring locked DLL is available in 2N mode after tCMD_GEAR from the 1N sync pulse. a. A valid command requiring locked DLL is available in 2N mode after tXSDLL or tDLLK from the 1N sync pulse. 4. If operation is in 1N mode after self refresh exit, N × tCK MRS command or sync pulse is not required during self refresh exit. The minimum exit delay to the first valid command is tXS, or tXS_ABORT . The DRAM may be changed from 2N to 1N by entering self refresh mode, which will re- set to 1N mode. Changing from 2N to by any other means can result in loss of data and make operation of the DRAM uncertain. When operating in 2N gear-down mode, the following MR settings apply:

• CAS latency (MR0[6:4,2]): Even number of clocks
• Write recovery and read to precharge (MR0[11:9]): Even number of clocks
• Additive latency (MR1[4:3]): CL - 2
• CAS WRITE latency (MR2 A[5:3]): Even number of clocks 16Gb: x4, x8, x16 DDR4 SDRAM Gear-Down Mode CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 101 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Figure 43: Comparison Between Gear-Down Disable and Gear-Down Enable tRCD = 16 T33T1 T2 T3 T15 T16 T17 T18 T19 T30 T31 T32 DES DES DES DES DES DES DESCommand DESACT DES DES DES READ DQ CK_t CK_c RL =CL= 16 (AL = 0) T38T34 T35 T36 T37 AL = 0 (geardown = disable) Don’t CareTransitioning DataTime Break DOn + 3 DOn + 4 DOn + 5 DOn + 6 DOn + 7DOn + 2DOn + 1DOn DES DES DES DES DES DES DES DES DES DES DES DESCommand READACT DES DES DES DES READ DQ RL = AL + CL = 31 (AL = CL - 1 = 15) AL = CL - 1 (geardown = disable) DOn + 3 DOn + 4 DOn + 5 DOn + 6 DOn + 7DOn + 2DOn + 1DOn DES DES DES DES DES DES DES DESCommand ACT READ DES READ DQ AL + CL = RL = 30 (AL = CL - 2 = 14) DOn + 3 DOn + 4 DOn + 5 DOn + 6 DOn + 7DOn + 2DOn + 1DOn DES DES DES 16Gb: x4, x8, x16 DDR4 SDRAM Gear-Down Mode CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 103 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Maximum power-saving mode provides the lowest power mode where data retention is not required. When the device is in the maximum power-saving mode, it does not maintain data retention or respond to any external command, except the MAXIMUM POWER SAVING MODE EXIT command and during the assertion of RESET_n signal LOW . This mode is more like a “hibernate mode” than a typical power-saving mode. The intent is to be able to park the DRAM at a very low-power state; the device can be switched to an active state via the per-DRAM addressability (PDA) mode. Maximum Power-Saving Mode Entry Maximum power-saving mode is entered through an MRS command. For devices with shared control/address signals, a single DRAM device can be entered into the maxi- mum power-saving mode using the per-DRAM addressability MRS command. Large CS_n hold time to CKE upon the mode exit could cause DRAM malfunction; as a result, CA parity, CAL, and gear-down modes must be disabled prior to the maximum power- saving mode entry MRS command. The MRS command may use both address and DQ information, as defined in the Per- DRAM Addressability section. As illustrated in the figure below, after tMPED from the mode entry MRS command, the DRAM is not responsive to any input signals except CKE, CS_n, and RESET_n. All other inputs are disabled (external input signals may be- come High-Z). The system will provide a valid clock until tCKMPE expires, at which time clock inputs (CK) should be disabled (external clock signals may become High-Z). Figure 44: Maximum Power-Saving Mode Entry Ta0 Ta1 Ta2 Tb0 Tb1 Command MRSDES DES DES DES CK_t CK_c RESET_n Tc11Tb3 Tc0 Tc1 Tc2 Tc3 Tc4 Tc7 Tc5 Tc6 Tc8 Tc9 Tc10 Don’t CareTime Break CS_n CKE tMPED CKE LOW makes CS_n a care; CKE LOW followed by CS_n LOW followed by CKE HIGH exits mode MR4[A1=1] MPSM Enable) Address Valid tCKMPE 16Gb: x4, x8, x16 DDR4 SDRAM Maximum Power-Saving Mode CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 104 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

shown in the figure below. Because the clock receivers (CK_t, CK_c) are disabled during this mode, CS_n = LOW is captured by the rising edge of the CKE signal. If the CS_n sig- nal level is detected LOW, the DRAM clears the maximum power-saving mode MRS bit and begins the exit procedure from this mode. The external clock must be restarted and be stable by tCKMPX before the device can exit the maximum power-saving mode. Dur- ing the exit time (tXMP), only NOP and DES commands are allowed: NOP during tMPX_LH and DES the remainder of tXMP . After tXMP expires, valid commands not re- quiring a locked DLL are allowed; after tXMP_DLL expires, valid commands requiring a locked DLL are allowed. Figure 47: Maximum Power-Saving Mode Exit Ta0 tCKMPX tMPX_S tXMP tXMP_DLL Ta1 Ta2 Ta3 Tb0 NOP NOP NOP NOP NOP DES DESCommand CK_t CK_c RESET_n Te1Tb1 Tb2 Tb3 Tc0 Tc1 Tc2 Td1 Tc4 Td0 Td2 Td3 Te0 Don’t CareTime Break DES DES Valid DES DES CS_n CKE tMPX_LH 16Gb: x4, x8, x16 DDR4 SDRAM Maximum Power-Saving Mode CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 106 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Command/address (CA) parity takes the CA parity signal (PAR) input carrying the parity bit for the generated address and commands signals and matches it to the internally generated parity from the captured address and commands signals. CA parity is suppor- ted in the DLL enabled state only; if the DLL is disabled, CA parity is not supported. Figure 48: Command/Address Parity Operation CMD/ADDR DRAM Controller DRAM CMD/ADDR Even parity bit Even parity bit Even parity GEN Even parity GEN CMD/ADDR Compare parity bit CA parity is disabled or enabled via an MRS command. If CA parity is enabled by pro- gramming a non-zero value to CA parity latency in the MR, the DRAM will ensure that there is no parity error before executing commands. There is an additional delay re- quired for executing the commands versus when parity is disabled. The delay is pro- grammed in the MR when CA parity is enabled (parity latency) and applied to all com- mands which are registered by CS_n (rising edge of CK_t and falling CS_n). The com- mand is held for the time of the parity latency (PL) before it is executed inside the de- vice. The command captured by the input clock has an internal delay before executing and is determined with PL. ALERT_n will go active when the DRAM detects a CA parity error. CA parity covers ACT_n, RAS_n/A16, CAS_n/A15, WE_n/A14, the address bus including bank address and bank group bits, and C[2:0] on 3DS devices; the control signals CKE, ODT , and CS_n are not covered. For example, for a 4Gb x4 monolithic device, parity is computed across BG[1:0], BA[1:0], A16/RAS_n, A15/CAS_n, A14/ WE_n, A[13:0], and ACT_n. The DRAM treats any unused address pins internally as zeros; for example, if a common die has stacked pins but the device is used in a monolithic application, then the address pins used for stacking and not connected are treated internally as zeros. The convention for parity is even parity; for example, valid parity is defined as an even number of ones across the inputs used for parity computation combined with the pari- ty signal. In other words, the parity bit is chosen so that the total number of ones in the transmitted signal, including the parity bit, is even. If a DRAM device detects a CA parity error in any command qualified by CS_n, it will perform the following steps: 1. Ignore the erroneous command. Commands in the MAX N nCK window tPAR_UNKNOWN) prior to the erroneous command are not guaranteed to be exe- cuted. When a READ command in this NnCK window is not executed, the device 16Gb: x4, x8, x16 DDR4 SDRAM Command/Address Parity CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 107 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

does not activate DQS outputs. If WRITE CRC is enabled and a WRITE CRC occurs during the tPAR_UNKNOWN window, the WRITE CRC Error Status Bit located at MR5[3] may or may not get set. When CA Parity and WRITE CRC are both enabled and a CA Parity occurs, the WRITE CRC Error Status Bit should be reset. 2. Log the error by storing the erroneous command and address bits in the MPR er- ror log. 3. Set the parity error status bit in the mode register to 1. The parity error status bit must be set before the ALERT_n signal is released by the DRAM (that is, tPAR_ALERT_ON + tPAR_ALERT_PW (MIN)). 4. Assert the ALERT_n signal to the host (ALERT_n is active LOW) within tPAR_ALERT_ON time. 5. Wait for all in-progress commands to complete. These commands were received tPAR_UNKOWN before the erroneous command. 6. Wait for tRAS (MIN) before closing all the open pages. The DRAM is not executing any commands during the window defined by (tPAR_ALERT_ON + tPAR_ALERT_PW). 7. After tPAR_ALERT_PW (MIN) has been satisfied, the device may de-assert ALERT_n. a. When the device is returned to a known precharged state, ALERT_n is al- lowed to be de-asserted. 8. After ( tPAR_ALERT_PW (MAX)) the DRAM is ready to accept commands for nor- mal operation. Parity latency will be in effect; however, parity checking will not re- sume until the memory controller has cleared the parity error status bit by writing a zero. The DRAM will execute any erroneous commands until the bit is cleared; unless persistent mode is enabled.

• It is possible that the device might have ignored a REFRESH command during tPAR_ALERT_PW or the REFRESH command is the first erroneous frame, so it is rec- ommended that extra REFRESH cycles be issued, as needed.
• The parity error status bit may be read anytime after tPAR_ALERT_ON + tPAR_ALERT_PW to determine which DRAM had the error. The device maintains the error log for the first erroneous command until the parity error status bit is reset to a zero or a second CA parity occurs prior to resetting. The mode register for the CA parity error is defined as follows: CA parity latency bits are write only, the parity error status bit is read/write, and error logs are read-only bits. The DRAM controller can only program the parity error status bit to zero. If the DRAM con- troller illegally attempts to write a 1 to the parity error status bit, the DRAM can not be certain that parity will be checked; the DRAM may opt to block the DRAM controller from writing a 1 to the parity error status bit. The device supports persistent parity error mode. This mode is enabled by setting MR5[9] = 1; when enabled, CA parity resumes checking after the ALERT_n is de-asser- ted, even if the parity error status bit remains a 1. If multiple errors occur before the er- ror status bit is cleared the error log in MPR Page 1 should be treated as "Don’t Care." In persistent parity error mode the ALERT_n pulse will be asserted and de-asserted by the DRAM as defined with the MIN and MAX value tPAR_ALERT_PW . The DRAM controller must issue DESELECT commands once it detects the ALERT_n signal, this response time is defined as tPAR_ALERT_RSP . The following figures capture the flow of events on the CA bus and the ALERT_n signal. 16Gb: x4, x8, x16 DDR4 SDRAM Command/Address Parity CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 108 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Table 36: Mode Register Setting for CA Parity CA Parity Latency MR5[2:0]1 Applicable Speed Bin Parity Error Status Parity Persistent Mode Erroneous CA Frame 000 = Disabled N/A MR5 [4] 0 = Clear MR5 [4] 1 = Error MR5 [9] 0 = DisabledMR5 [9] 1 = Enabled C[2:0], ACT_n, BG1, BG0, BA[1:0], PAR, A17, A16/RAS_n, A15/ CAS_n, A14/WE_n, A[13:0] 001 = 4 clocks 1600, 1866, 2133 010 = 5 clocks 2400, 2666 011 = 6 clocks 2933, 3200 100 = 8 clocks RFU 101 = Reserved RFU 110 = Reserved RFU 111 = Reserved RFU Notes: 1. Parity latency is applied to all commands. 2. Parity latency can be changed only from a CA parity disabled state; for example, a direct change from PL = 3 to PL = 4 is not allowed. The correct sequence is PL = 3 to disabled to PL = 4. 3. Parity latency is applied to WRITE and READ latency. WRITE latency = AL + CWL + PL. READ latency = AL + CL + PL. Figure 49: Command/Address Parity During Normal Operation Don’t Care Time Break Command execution unknown Command not executed Command executed DES2 Valid3 ValidError CK_t CK_c Command/ Address Valid2 Valid2 Valid2 Valid3 Valid3 T0 T1 Ta0 Ta1 Tb0 Tc0 ALERT_n Tc1 tPAR_ALERT_ON Td0 Valid Valid ValidError tPAR_UNKNOWN2 Ta2 Te1 tPAR_ALERT_PW1 Te0 DES2 DES2 Valid2 tRPt > 2nCK Notes: 1. DRAM is emptying queues. Precharge all and parity checking are off until parity error status bit is cleared. 2. Command execution is unknown; the corresponding DRAM internal state change may or may not occur. The DRAM controller should consider both cases and make sure that the command sequence meets the specifications. If WRITE CRC is enabled and a WRITE CRC occurs during the tPAR_UNKNOWN window, the WRITE CRC Error Status Bit located at MR5[3] may or may not get set. 3. Normal operation with parity latency (CA parity persistent error mode disabled). Parity checking is off until parity error status bit is cleared. 16Gb: x4, x8, x16 DDR4 SDRAM Command/Address Parity CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 109 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Figure 57: Parity Exit Timing Example – tMOD_PAR Ta0 tMOD_PAR Ta1 Ta2 Tb0 Tb1 Tb2 Command MRS DES DES DES Valid DES Parity latency CK_t CK_c Disable parity Don’t CareTime Break PL = N Updating setting Note: 1. tMOD_PAR = tMOD + N; where N is the programmed parity latency. 16Gb: x4, x8, x16 DDR4 SDRAM Command/Address Parity CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 113 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Figure 58: CA Parity Flow Diagram CA latched in Yes CA process start MR5[2:0] set parity latency (PL) MR5[4] set parity error status to 0 MR5[9] enable/disable persistent mode No Yes No Yes No Yes No Yes No CA parity enabled CA error Persistent mode enabled Good CA processed Good CA processed Good CA processed Ignore bad CMD Ignore bad CMD Log error/ set parity status Internal precharge all ALERT_n HIGH Command execution unknown Command execution unknown Normal operation ready MR5[4] reset to 0 if desired Normal operation ready MR5[4] reset to 0 if desired Yes No CA parity error ALERT_n LOW 44 to 144 CKs ALERT_n LOW 44 to 144 CKs Internal precharge all ALERT_n HIGH Command execution unknown Command execution unknown No Yes Log error/ set parity status MR5[4] = 0 @ ADDR/CMD latched MR5[4] = 0 @ ADDR/CMD latched CA parity error Normal operation ready Bad CA processed Operation ready? 16Gb: x4, x8, x16 DDR4 SDRAM Command/Address Parity CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 114 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

DDR4 allows programmability of a single, specific DRAM on a rank. As an example, this feature can be used to program different ODT or VREF values on each DRAM on a given rank. Because per-DRAM addressability (PDA) mode may be used to program optimal VREF for the DRAM, the data set up for first DQ0 transfer or the hold time for the last DQ0 transfer cannot be guaranteed. The DRAM may sample DQ0 on either the first fall- ing or second rising DQS transfer edge. This supports a common implementation be- tween BC4 and BL8 modes on the DRAM. The DRAM controller is required to drive DQ0 to a stable LOW or HIGH state during the length of the data transfer for BC4 and BL8 cases. Note, both fixed and on-the-fly (OTF) modes are supported for BC4 and BL8 dur- ing PDA mode. 1. Before entering PDA mode, write leveling is required.

• BL8 or BC4 may be used. 2. Before entering PDA mode, the following MR settings are possible: TT(Park) MR5 A[8:6] = Enable
• R TT(NOM) MR1 A[10:8] = Enable 3. Enable PDA mode using MR3 [4] = 1. (The default programed value of MR3[4] = 0.) 4. In PDA mode, all MRS commands are qualified with DQ0. The device captures DQ0 by using DQS signals. If the value on DQ0 is LOW, the DRAM executes the MRS command. If the value on DQ0 is HIGH, the DRAM ignores the MRS com- mand. The controller can choose to drive all the DQ bits. 5. Program the desired DRAM and mode registers using the MRS command and DQ0. 6. In PDA mode, only MRS commands are allowed. 7. The MODE REGISTER SET command cycle time in PDA mode, AL + CWL + BL/2 - 0.5 tCK + tMRD_PDA + PL, is required to complete the WRITE operation to the mode register and is the minimum time required between two MRS commands. 8. Remove the device from PDA mode by setting MR3[4] = 0. (This command re- quires DQ0 = 0.) Note: Removing the device from PDA mode will require programming the entire MR3 when the MRS command is issued. This may impact some PDA values programmed within a rank as the EXIT command is sent to the rank. To avoid such a case, the PDA enable/disable control bit is located in a mode register that does not have any PDA mode controls. In PDA mode, the device captures DQ0 using DQS signals the same as in a normal WRITE operation; however, dynamic ODT is not supported. Extra care is required for the ODT setting. If R TT(NOM) MR1 [10:8] = enable, device data termination needs to be controlled by the ODT pin, and applies the same timing parameters (defined below). Symbol Parameter DODTLon Direct ODT turnon latency DODTLoff Direct ODT turn off latency tADC R TT change timing skew tAONAS Asynchronous R TT(NOM) turn-on delay tAOFAS Asynchronous R TT(NOM) turn-off delay 16Gb: x4, x8, x16 DDR4 SDRAM Per-DRAM Addressability CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 115 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Figure 61: MRS PDA Exit &.BW &.BF 2'7 577 W3'$B6 &:/$/3/ W02'B3'$ '46BW '46BF 05$ 3'$GLVDEOH 056 9DOLG '2'7/RII :/ '2'7/RQ :/ W3'$B+ 577 3DUN 577 120 577 3DUN Note: 1. R TT(Park) = Enable; RTT(NOM) = Enable; WRITE preamble set = 2tCK; and DLL = On. 16Gb: x4, x8, x16 DDR4 SDRAM Per-DRAM Addressability CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 117 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

The VREFDQ level, which is used by the DRAM DQ input receivers, is internally gener- ated. The DRAM VREFDQ does not have a default value upon power-up and must be set to the desired value, usually via VREFDQ calibration mode. If PDA or PPR modes (hPPR or sPPR) are used prior to VREFDQ calibration, VREFDQ should initially be set at the midpoint between the VDD,max, and the LOW as determined by the driver and ODT termination selected with wide voltage swing on the input levels and setup and hold times of ap- proximately 0.75UI. The memory controller is responsible for V REFDQ calibration to de- termine the best internal VREFDQ level. The VREFDQ calibration is enabled/disabled via MR6[7], MR6[6] selects Range 1 (60% to 92.5% of VDDQ) or Range 2 (45% to 77.5% of VDDQ), and an MRS protocol using MR6[5:0] to adjust the VREFDQ level up and down. MR6[6:0] bits can be altered using the MRS command if MR6[7] is enabled. The DRAM controller will likely use a series of writes and reads in conjunction with V REFDQ adjust- ments to obtain the best VREFDQ, which in turn optimizes the data eye. The internal VREFDQ specification parameters are voltage range, step size, VREF step time, VREF full step time, and VREF valid level. The voltage operating range specifies the minimum required VREF setting range for DDR4 SDRAM devices. The minimum range is defined by VREFDQ,min and VREFDQ,max. As noted, a calibration sequence, determined by the DRAM controller, should be performed to adjust VREFDQ and optimize the timing and voltage margin of the DRAM data input receivers. The internal VREFDQ voltage value may not be exactly within the voltage range setting coupled with the VREF set tolerance; the device must be calibrated to the correct internal VREFDQ voltage. Figure 62: VREFDQ Voltage Range VDDQ VREF range VSWING small VSWING large System variance Total range VREF,max VREF,min 16Gb: x4, x8, x16 DDR4 SDRAM VREFDQ Calibration CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 118 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Table 37: VREFDQ Range and Levels MR6[5:0] Range 1 MR6[6] 0 Range 2 MR6[6] 1 MR6[5:0] Range 1 MR6[6] 0 Range 2 MR6[6] 1 00 0000 60.00% 45.00% 01 1010 76.90% 61.90% 00 0001 60.65% 45.65% 01 1011 77.55% 62.55% 00 0010 61.30% 46.30% 01 1100 78.20% 63.20% 00 0011 61.95% 46.95% 01 1101 78.85% 63.85% 00 0100 62.60% 47.60% 01 1110 79.50% 64.50% 00 0101 63.25% 48.25% 01 1111 80.15% 65.15% 00 0110 63.90% 48.90% 10 0000 80.80% 65.80% 00 0111 64.55% 49.55% 10 0001 81.45% 66.45% 00 1000 65.20% 50.20% 10 0010 82.10% 67.10% 00 1001 65.85% 50.85% 10 0011 82.75% 67.75% 00 1010 66.50% 51.50% 10 0100 83.40% 68.40% 00 1011 67.15% 52.15% 10 0101 84.05% 69.05% 00 1100 67.80% 52.80% 10 0110 84.70% 69.70% 00 1101 68.45% 53.45% 10 0111 85.35% 70.35% 00 1110 69.10% 54.10% 10 1000 86.00% 71.00% 00 1111 69.75% 54.75% 10 1001 86.65% 71.65% 01 0000 70.40% 55.40% 10 1010 87.30% 72.30% 01 0001 71.05% 56.05% 10 1011 87.95% 72.95% 01 0010 71.70% 56.70% 10 1100 88.60% 73.60% 01 0011 72.35% 57.35% 10 1101 89.25% 74.25% 01 0100 73.00% 58.00% 10 1110 89.90% 74.90% 01 0101 73.65% 58.65% 10 1111 90.55% 75.55% 01 0110 74.30% 59.30% 11 0000 91.20% 76.20% 01 0111 74.95% 59.95% 11 0001 91.85% 76.85% 01 1000 75.60% 60.60% 11 0010 92.50% 77.50% 01 1001 76.25% 61.25% 11 0011 to 11 1111 = Reserved VREFDQ Step Size The VREF step size is defined as the step size between adjacent steps. VREF step size rang- es from 0.5% VDDQ to 0.8% VDDQ. However, for a given design, the device has one value for VREF step size that falls within the range. The VREF set tolerance is the variation in the VREF voltage from the ideal setting. This ac- counts for accumulated error over multiple steps. There are two ranges for VREF set tol- erance uncertainty. The range of VREF set tolerance uncertainty is a function of number of steps n. The VREF set tolerance is measured with respect to the ideal line, which is based on the MIN and MAX VREF value endpoints for a specified range. The internal VREFDQ voltage 16Gb: x4, x8, x16 DDR4 SDRAM VREFDQ Calibration CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 119 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

value may not be exactly within the voltage range setting coupled with the VREF set tol- erance; the device must be calibrated to the correct internal VREFDQ voltage. Figure 63: Example of VREF Set Tolerance and Step Size VREF VREF step size VREF set tolerance VREF set tolerance Straight line (endpoint fit) Actual VREF output Digital Code Note: 1. Maximum case shown. VREFDQ Increment and Decrement Timing The VREF increment/decrement step times are defined by VREF ,time. VREF ,time is defined from t0 to t1, where t1 is referenced to the VREF voltage at the final DC level within the VREF valid tolerance (VREF ,val_tol). The VREF valid level is defined by VREF ,val tolerance to qualify the step time t1. This parameter is used to insure an adequate RC time constant behavior of the voltage level change after any V REF increment/decrement adjustment. 16Gb: x4, x8, x16 DDR4 SDRAM VREFDQ Calibration CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 120 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Figure 64: VREFDQ Timing Diagram for VREF,time Parameter MRS VREF setting adjustment Command DQ VREF VREF_time t0 t1 Old VREF setting New VREF settingUpdating VREF setting Don’t Care CK_t CK_c Note: 1. t0 is referenced to the MRS command clock t1 is referenced to VREF,tol VREFDQ calibration mode is entered via an MRS command, setting MR6[7] to 1 (0 disa- bles VREFDQ calibration mode) and setting MR6[6] to either 0 or 1 to select the desired range (MR6[5:0] are "Don't Care"). After VREFDQ calibration mode has been entered, VREFDQ calibration mode legal commands may be issued once tVREFDQE has been sat- isfied. Legal commands for VREFDQ calibration mode are ACT , WR, WRA, RD, RDA, PRE, DES, and MRS to set VREFDQ values, and MRS to exit VREFDQ calibration mode. Also, after VREFDQ calibration mode has been entered, “dummy” WRITE commands are allowed prior to adjusting the VREFDQ value the first time VREFDQ calibration is performed after initialization. Setting VREFDQ values requires MR6[7] be set to 1 and MR6[6] be unchanged from the initial range selection; MR6[5:0] may be set to the desired VREFDQ values. If MR6[7] is set to 0, MR6[6:0] are not written. VREF ,time-short or VREF ,time-long must be satisfied after each MR6 command to set VREFDQ value before the internal VREFDQ value is valid. If PDA mode is used in conjunction with VREFDQ calibration, the PDA mode require- ment that only MRS commands are allowed while PDA mode is enabled is not waived. That is, the only V REFDQ calibration mode legal commands noted above that may be used are the MRS commands: MRS to set VREFDQ values and MRS to exit VREFDQ calibra- tion mode. The last MR6[6:0] setting written to MR6 prior to exiting VREFDQ calibration mode is the range and value used for the internal VREFDQ setting. VREFDQ calibration mode may be exited when the DRAM is in idle state. After the MRS command to exit VREFDQ calibra- tion mode has been issued, DES must be issued until tVREFDQX has been satisfied where any legal command may then be issued. VREFDQ setting should be updated if the die temperature changes too much from the calibration temperature. The following are typical script when applying the above rules for VREFDQ calibration routine when performing VREFDQ calibration in Range 1:

• MR6[7:6]10 [5:0]XXXXXXX. 16Gb: x4, x8, x16 DDR4 SDRAM VREFDQ Calibration CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 121 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

– Subsequent legal commands while in V REFDQ calibration mode: ACT , WR, WRA, RD, RDA, PRE, DES, and MRS (to set VREFDQ values and exit VREFDQ calibration mode).

• All subsequent V REFDQ calibration MR setting commands are MR6[7:6]10 [5:0]VVVVVV . – "VVVVVV" are desired settings for V REFDQ.
• Issue ACT/WR/RD looking for pass/fail to determine V CENT (midpoint) as needed.
• To exit V REFDQ calibration, the last two VREFDQ calibration MR commands are: – MR6[7:6]10 [5:0]VVVVVV* where VVVVVV* = desired value for V REFDQ. – MR6[7]0 [6:0]XXXXXXX to exit V REFDQ calibration mode. The following are typical script when applying the above rules for VREFDQ calibration routine when performing VREFDQ calibration in Range 2:
• MR6[7:6]11 [5:0]XXXXXXX. – Subsequent legal commands while in V REFDQ calibration mode: ACT , WR, WRA, RD, RDA, PRE, DES, and MRS (to set VREFDQ values and exit VREFDQ calibration mode).
• All subsequent V REFDQ calibration MR setting commands are MR6[7:6]11 [5:0]VVVVVV . – "VVVVVV" are desired settings for V REFDQ.
• Issue ACT/WR/RD looking for pass/fail to determine V CENT (midpoint) as needed.
• To exit V REFDQ calibration, the last two VREFDQ calibration MR commands are: – MR6[7:6]11 [5:0]VVVVVV* where VVVVVV* = desired value for V REFDQ. – MR6[7]0 [6:0]XXXXXXX to exit V REFDQ calibration mode. Note: Range may only be set or changed when entering VREFDQ calibration mode; changing range while in or exiting VREFDQ calibration mode is illegal. Figure 65: VREFDQ Training Mode Entry and Exit Timing Diagram T0 T1 Ta0 Ta1 Tb0 CK_c CK_t Command Tb1 Tc0 MRS WRDESCMDDESDES CMD DES Tc1 Td0 Td1 Td2 tVREFDQE VREFDQ training on tVREFDQX DES MRS 1,2 DES New VREFDQ value or write New VREFDQ value or write VREFDQ training off Don’t Care Notes: 1. New V REFDQ values are not allowed with an MRS command during calibration mode en- try. 2. Depending on the step size of the latest programmed V REF value, VREF must be satisfied before disabling VREFDQ training mode. 16Gb: x4, x8, x16 DDR4 SDRAM VREFDQ Calibration CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 122 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Table 38: VREFDQ Settings (VDDQ = 1.2V) RON ODT Vx – VIN LOW (mV) VREFDQ (mv) VREFDQ (%VDDQ) 34 ohm 34 ohm 600 900 75% 40 ohm 550 875 73% 48 ohm 500 850 71% 60 ohm 435 815 68% 80 ohm 360 780 65% 120 ohm 265 732 61% 240 ohm 150 675 56% 48 ohm 34 ohm 700 950 79% 40 ohm 655 925 77% 48 ohm 600 900 75% 60 ohm 535 865 72% 80 ohm 450 825 69% 120 ohm 345 770 64% 240 ohm 200 700 58% Figure 70: VREFDQ Equivalent Circuit RXer VREFDQ (internal) RON ODT Vx VDDQ VDDQ 16Gb: x4, x8, x16 DDR4 SDRAM VREFDQ Calibration CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 125 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Connectivity test (CT) mode is similar to boundary scan testing but is designed to sig- nificantly speed up the testing of electrical continuity of pin interconnections between the device and the memory controller on the PC boards. Designed to work seamlessly with any boundary scan device, CT mode is supported in all ×4, ×8, and ×16 non-3DS devices (JEDEC states CT mode for ×4 and ×8 is not required on 4Gb and is an optional feature on 8Gb and above). 3DS devices do not support CT mode and the TEN pin should be considered RFU maintained LOW at all times. Contrary to other conventional shift-register-based test modes, where test patterns are shifted in and out of the memory devices serially during each clock, the CT mode allows test patterns to be entered on the test input pins in parallel and the test results to be extracted from the test output pins of the device in parallel. These two functions are al- so performed at the same time, significantly increasing the speed of the connectivity check. When placed in CT mode, the device appears as an asynchronous device to the external controlling agent. After the input test pattern is applied, the connectivity test results are available for extraction in parallel at the test output pins after a fixed propa- gation delay time. Note: A reset of the device is required after exiting CT mode (see RESET and Initializa- tion Procedure). Pin Mapping Only digital pins can be tested using the CT mode. For the purposes of a connectivity check, all the pins used for digital logic in the device are classified as one of the follow- ing types:

• Test enable (TEN): When asserted HIGH, this pin causes the device to enter CT mode. In CT mode, the normal memory function inside the device is bypassed and the I/O pins appear as a set of test input and output pins to the external controlling agent. Additionally, the device will set the internal V REFDQ to VDDQ × 0.5 during CT mode (this is the only time the DRAM takes direct control over setting the internal VREFDQ). The TEN pin is dedicated to the connectivity check function and will not be used dur- ing normal device operation.
• Chip select (CS_n): When asserted LOW, this pin enables the test output pins in the device. When de-asserted, these output pins will be High-Z. The CS_n pin in the de- vice serves as the CS_n pin in CT mode.
• Test input: A group of pins used during normal device operation designated as test input pins. These pins are used to enter the test pattern in CT mode.
• Test output: A group of pins used during normal device operation designated as test output pins. These pins are used for extraction of the connectivity test results in CT mode.
• RESET_n: This pin must be fixed high level during CT mode, as in normal function. 16Gb: x4, x8, x16 DDR4 SDRAM Connectivity Test Mode CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 126 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Table 39: Connectivity Mode Pin Description and Switching Levels CT Mode Pins Pin Name During Normal Memory Operation Switching Level Notes Test enable TEN CMOS (20%/80% V DD) 1, 2 Chip select CS_n V REFCA ±200mV 3 Test input A BA[1:0], BG[1:0], A[9:0], A10/AP, A11, A12/BC_n, A13, WE_n/A14, CAS_n/A15, RAS_n/A16, A17, CKE, ACT_n, ODT, CLK_t, CLK_c, PAR VREFCA ±200mV 3 B LDM_n/LDBI_n, UDM_n/UDBI_n; DM_n/DBI_n V REFDQ ±200mV 4 C ALERT_n CMOS (20%/80% V DD) 2, 5 D RESET_n CMOS (20%/80% V DD)2 Test output DQ[15:0], UDQS_t, UDQS_c, LDQS_t, LDQS_c; DQS_t, DQS_c V TT ±100mV 6 Notes: 1. TEN: Connectivity test mode is active when TEN is HIGH and inactive when TEN is LOW. TEN must be LOW during normal operation. 2. CMOS is a rail-to-rail signal with DC HIGH at 80% and DC LOW at 20% of V DD (960mV for DC HIGH and 240mV for DC LOW.) 3. V REFCA should be VDD/2. 4. V REFDQ should be VDDQ/2. 5. ALERT_n switching level is not a final setting. 6. V TT should be set to VDD/2. Minimum Terms Definition for Logic Equations The test input and output pins are related by the following equations, where INV de- notes a logical inversion operation and XOR a logical exclusive OR operation: MT0 = XOR (A1, A6, PAR) MT1 = XOR (A8, ALERT_n, A9) MT2 = XOR (A2, A5, A13) or XOR (A2, A5, A13, A17) MT3 = XOR (A0, A7, A11) MT4 = XOR (CK_c, ODT , CAS_n/A15) MT5 = XOR (CKE, RAS_n/A16, A10/AP) MT6 = XOR (ACT_n, A4, BA1) MT7 = ×16: XOR (DMU_n/DBIU_n , DML_n/DBIL_n, CK_t) = x8: XOR (BG1, DML_n/DBIL_n, CK_t) = x4: XOR (BG1, CK_t) MT8 = XOR (WE_n/A14, A12 / BC, BA0) MT9 = XOR (BG0, A3, RESET_n and TEN) Logic Equations for a x4 Device DQ0 = XOR (MT0, MT1) DQ1 = XOR (MT2, MT3) DQ2 = XOR (MT4, MT5) DQ3 = XOR (MT6, MT7) DQS_t = MT8 DQS_c = MT9 16Gb: x4, x8, x16 DDR4 SDRAM Connectivity Test Mode CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 127 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Logic Equations for a x8 Device DQ0 = MT0 DQ5 = MT5 DQ1 = MT1 DQ6 = MT6 DQ2 = MT2 DQ7 = MT7 DQ3 = MT3 DQS_t = MT8 DQ4 = MT4 DQS_c = MT9 Logic Equations for a x16 Device DQ0 = MT0 DQ10 = INV DQ2 DQ1 = MT1 DQ11 = INV DQ3 DQ2 = MT2 DQ12 = INV DQ4 DQ3 = MT3 DQ13 = INV DQ5 DQ4 = MT4 DQ14 = INV DQ6 DQ5 = MT5 DQ15 = INV DQ7 DQ6 = MT6 LDQS_t = MT8 DQ7 = MT7 LDQS_c = MT9 DQ8 = INV DQ0 UDQS_t = INV LDQS_t DQ9 = INV DQ1 UDQS_c = INV LDQS_c CT Input Timing Requirements Prior to the assertion of the TEN pin, all voltage supplies, including VREFCA, must be val- id and stable and RESET_n registered high prior to entering CT mode. Upon the asser- tion of the TEN pin HIGH with RESET_n, CKE, and CS_n held HIGH; CLK_t, CLK_c, and CKE signals become test inputs within tCTECT_Valid. The remaining CT inputs become valid tCT_Enable after TEN goes HIGH when CS_n allows input to begin sampling, pro- vided inputs were valid for at least tCT_Valid. While in CT mode, refresh activities in the memory arrays are not allowed; they are initiated either externally (auto refresh) or in- ternally (self refresh). The TEN pin may be asserted after the DRAM has completed power-on. After the DRAM is initialized and V REFDQ is calibrated, CT mode may no longer be used. The TEN pin may be de-asserted at any time in CT mode. Upon exiting CT mode, the states and the integrity of the original content of the memory array are unknown. A full reset of the memory device is required. After CT mode has been entered, the output signals will be stable within tCT_Valid after the test inputs have been applied as long as TEN is maintained HIGH and CS_n is main- tained LOW . 16Gb: x4, x8, x16 DDR4 SDRAM Connectivity Test Mode CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 128 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Figure 71: Connectivity Test Mode Entry tCTCKE_Valid T = 10ns CS_n CT Inputs CT Outputs tCT_Enable tCKSRX tCTCKE_Valid >10ns tCT_IS >0ns T = 500μsT = 200μs tIS tCT_Valid tCT_Valid tCT_Valid TEN Valid input Valid input Valid input Valid input Valid input Valid input Valid Valid RESET_n CKE CK_c CK_t Ta Tb Tc Td tCT_IS tCT_IS tCT_IS tCT_IS Don’t Care 16Gb: x4, x8, x16 DDR4 SDRAM Connectivity Test Mode CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 129 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Rows can be accessed a limited number of times within a certain time period before ad- jacent rows require refresh. The maximum activate count (MAC) is the maximum num- ber of activates that a single row can sustain within a time interval of equal to or less than the maximum activate window ( tMAW) before the adjacent rows need to be re- freshed, regardless of how the activates are distributed over tMAW . Micron's DDR4 devices automatically perform a type of TRR mode in the background and provide an MPR Page 3 MPR3[3:0] of 1000, indicating there is no restriction to the number of ACTIVATE commands to a given row in a refresh period provided DRAM tim- ing specifications are not violated. However, specific attempts to by-pass TRR may re- sult in data disturb. Table 40: MAC Encoding of MPR Page 3 MPR3 [7] [6] [5] [4] [3] [2] [1] [0] MAC Comments xxxx0000 Untested The device has not been tested for MAC. xxxx0001 tMAC = 700K xxxx0010 tMAC = 600K xxxx 0011 tMAC = 500K xxxx0100 tMAC = 400K xxxx0101 tMAC = 300K xxxx0110 Reserved xxxx0111 tMAC = 200K x x x x 1 0 0 0 Unlimited There is no restriction to the number of AC- TIVATE commands to a given row in a re- fresh period provided DRAM timing specifi- cations are not violated. x x x x 1 0 0 1 Reserved x x x x : : : : Reserved x x x x 1 1 1 1 Reserved Note: 1. MAC encoding in MPR Page 3 MPR3. 16Gb: x4, x8, x16 DDR4 SDRAM Excessive Row Activation CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 130 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

JEDEC defines two modes of Post Package Repair (PPR): soft Post Package Repair (sPPR) and hard Post Package Repair (hPPR). sPPR is non-persistent so the repair row maybe altered; that is, sPPR is NOT a permanent repair and even though it will repair a row, the repair can be reversed, reassigned via another sPPR, or made permanent via hPPR. Hard Post Package Repair is persistent so once the repair row is assigned for a hPPR ad- dress, further PPR commands to a previous hPPR section should not be performed, that is, hPPR is a permanent repair; once repaired, it cannot be reversed. The controller pro- vides the failing row address in the hPPR/sPPR sequence to the device to perform the row repair. hPPR Mode and sPPR Mode may not be enabled at the same time. JEDEC states hPPR is optional for 4Gb and sPPR is optional for 4Gb and 8Gb parts how- ever Micron 4Gb and 8Gb DDR4 DRAMs should have both sPPR and hPPR support. The hPPR support is identified via an MPR read from MPR Page 2, MPR0[7] and sPPR sup- port is identified via an MPR read from MPR Page 2, MPR0[6]. The JEDEC minimum support requirement for DDR4 PPR (hPPR or sPPR) is to provide one row of repair per bank group (BG), x4/x8 have 4 BG and x16 has 2 BG; this is a total of 4 repair rows available on x4/x8 and 2 repair rows available on x16. Micron PPR sup- port exceeds the JEDEC minimum requirements; Micron DDR4 DRAMs have at least one row of repair for each bank which is essentially 4 row repairs per BG for a total of 16 repair rows for x4 and x8 and 8 repair rows for x16; a 4x increase in repair rows. JEDEC requires the user to have all sPPR row repair addresses reset and cleared prior to enabling hPPR Mode. Micron DDR4 PPR does not have this restriction, the existing sPPR row repair addresses are not required to be cleared prior to entering hPPR mode. Each bank in a BG is PPR independent: sPPR or hPPR issued to a bank will not alter a sPPR row repair existing in a different bank. sPPR followed by sPPR to same bank When PPR is issued to a bank for the first time and is a sPPR command, the repair row will be a sPPR. When a subsequent sPPR is issued to the same bank, the previous sPPR repair row will be cleared and used for the subsequent sPPR address as the sPPR opera- tion is non-persistent. sPPR followed by hPPR to same bank When a PPR is issued to a bank for the first time and is a sPPR command, the repair row will be a sPPR. When a subsequent hPPR is issued to the same bank, the initial sPPR repair row will be cleared and used for the hPPR address. If a further subsequent PPR (hPPR or sPPR) is issued to the same bank, the further subsequent PPR ( hPPR or sPPR) repair row will not clear or overwrite the previous hPPR address as the hPPR operation is persistent. hPPR followed by hPPR or sPPR to same bank When a PPR is issued to a bank for the first time and is a hPPR command, the repair row will be a hPPR. When a subsequent PPR (hPPR or sPPR) is issued to the same bank, the subsequent PPR ( hPPR or sPPR) repair row will not clear or overwrite the initial hPPR address as the initial hPPR is persistent. 16Gb: x4, x8, x16 DDR4 SDRAM Post Package Repair CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 131 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

All banks must be precharged and idle. DBI and CRC modes must be disabled. Both sPPR and hPPR must be disabled. sPPR is disabled with MR4[5] = 0. hPPR is disabled with MR4[13] = 0, which is the normal state, and hPPR is enabled with MR4 [13]= 1, which is the hPPR enabled state. There are two forms of hPPR mode. Both forms of hPPR have the same entry requirement as defined in the sections below. The first com- mand sequence uses a WRA command and supports data retention with a REFRESH operation except for the bank containing the row that is being repaired; JEDEC has re- laxed this requirement and allows BA[0] to be a don't care regarding the banks which are not required to maintain data a REFRESH operation during hPPR. The second com- mand sequence uses a WR command (a REFRESH operation can't be performed in this command sequence). The second command sequence doesn't support data retention for the target DRAM. hPPR Row Repair - Entry As stated above, all banks must be precharged and idle. DBI and CRC modes must be disabled, and all timings must be followed as shown in the timing diagram that follows. All other commands except those listed in the following sequences are illegal. 1. Issue MR4[13] 1 to enter hPPR mode enable. a. All DQ are driven HIGH. 2. Issue four consecutive guard key commands (shown in the table below) to MR0 with each command separated by tMOD. The PPR guard key settings are the same whether performing sPPR or hPPR mode. a. Any interruption of the key sequence by other commands, such as ACT , WR, RD, PRE, REF , ZQ, and NOP , are not allowed. b. If the guard key bits are not entered in the required order or interrupted with other MR commands, hPPR will not be enabled, and the programming cycle will result in a NOP . c. When the hPPR entry sequence is interrupted and followed by ACT and WR commands, these commands will be conducted as normal DRAM com- mands. d. JEDEC allows A6:0 to be "Don't Care" on 4Gb and 8Gb devices from a suppli- er perspective and the user should rely on vendor datasheet. Table 41: PPR MR0 Guard Key Settings MR0 BG1:0 BA1:0 A17:12 A11 A10 A9 A8 A7 A6:0 First guard key 0 0 xxxxxx 1 1 0 0 1 1111111 Second guard key 0 0 xxxxxx 0 1 1 1 1 1111111 Third Guard key 0 0 xxxxxx 1 0 1 1 1 1111111 Fourth guard key 0 0 xxxxxx 0 0 1 1 1 1111111 hPPR Row Repair – WRA Initiated (REF Commands Allowed) 1. Issue an ACT command with failing BG and BA with the row address to be re- paired. 2. Issue a WRA command with BG and BA of failing row address. a. The address must be at valid levels, but the address is "Don't Care." 16Gb: x4, x8, x16 DDR4 SDRAM Hard Post Package Repair CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 132 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

1. All DQ of the target DRAM should be driven LOW for 4 nCK (bit 0 through bit 7) after WL (WL = CWL + AL + PL) in order for hPPR to initiate repair. a. Repair will be initiated to the target DRAM only if all DQ during bit 0 through bit 7 are LOW . The bank under repair does not get the REFRESH command applied to it. b. Repair will not be initiated to the target DRAM if any DQ during bit 0 through bit 7 is HIGH. 1. JEDEC states: All DQs of target DRAM should be LOW for 4 tCK. If HIGH is driven to all DQs of a DRAM consecutively for equal to or longer than tCK, then DRAM does not conduct hPPR and retains data if REF com- mand is properly issued; if all DQs are neither LOW for 4tCK nor HIGH for equal to or longer than 2tCK, then hPPR mode execution is un- known. c. DQS should function normally. 4. REF command may be issued anytime after the WRA command followed by WL + 4nCK + tWR + tRP . a. Multiple REF commands are issued at a rate of tREFI or tREFI/2, however back-to-back REF commands must be separated by at least tREFI/4 when the DRAM is in hPPR mode. b. All banks except the bank under repair will perform refresh. 5. Issue PRE after tPGM time so that the device can repair the target row during tPGM time. a. Wait tPGM_Exit after PRE to allow the device to recognize the repaired target row address. 6. Issue MR4[13] 0 command to hPPR mode disable. a. Wait tPGMPST for hPPR mode exit to complete. b. After tPGMPST has expired, any valid command may be issued. The entire sequence from hPPR mode enable through hPPR mode disable may be re- peated if more than one repair is to be done. After completing hPPR mode, MR0 must be re-programmed to a prehPPR mode state if the device is to be accessed. After hPPR mode has been exited, the DRAM controller can confirm if the target row was repaired correctly by writing data into the target row and reading it back. 16Gb: x4, x8, x16 DDR4 SDRAM Hard Post Package Repair CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 133 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Table 42: DDR4 hPPR Timing Parameters DDR4-1600 through DDR4-3200 Parameter Symbol Min Max Unit hPPR programming time tPGM ×4, ×8 1000 – ms ×16 2000 – ms hPPR precharge exit time tPGM_Exit 15 – ns hPPR exit time tPGMPST 50 – μs sPPR Row Repair Soft post package repair (sPPR) is a way to quickly, but temporarily, repair a row ele- ment in a bank on a DRAM device, where hPPR takes longer but permanently repairs a row element. sPPR mode is entered in a similar fashion as hPPR, sPPR uses MR4[5] while hPPR uses MR4[13]. sPPR is disabled with MR4[5] = 0, which is the normal state, and sPPR is enabled with MR4[5] = 1, which is the sPPR enabled state. sPPR requires the same guard key sequence as hPPR to qualify the MR4 PPR entry. After sPPR entry, an ACT command will capture the target bank and target row, herein seed row, where the row repair will be made. After tRCD time, a WR command is used to se- lect the individual DRAM, through the DQ bits, to transfer the repair address into an in- ternal register in the DRAM. After a write recovery time and PRE command, the sPPR mode can be exited and normal operation can resume. The DRAM will retain the soft repair information as long as V DD remains within the op- erating region unless rewritten by a subsequent sPPR entry to the same bank. If DRAM power is removed or the DRAM is reset, the soft repair will revert to the unrepaired state. hPPR and sPPR should not be enabled at the same time; Micron sPPR does not have to be disabled and cleared prior to entering hPPR mode. With sPPR, Micron DDR4 can repair one row per bank. When a subsequent sPPR re- quest is made to the same bank, the subsequently issued sPPR address will replace the previous sPPR address. When the hPPR resource for a bank is used up, the bank should be assumed to not have available resources for sPPR. If a repair sequence is issued to a bank with no repair resource available, the DRAM will ignore the programming se- quence. The bank receiving sPPR change is expected to retain memory array data in all rows ex- cept for the seed row and its associated row addresses. If the data in the memory array in the bank under sPPR repair is not required to be retained, then the handling of the seed row’s associated row addresses is not of interest and can be ignored. If the data in the memory array is required to be retained in the bank under sPPR mode, then prior to executing the sPPR mode, the seed row and its associated row addresses should be backed up and subsequently restored after sPPR has been completed. sPPR associated seed row addresses are specified in the Table below; BA0 is not required by Micron DRAMs however it is JEDEC reserved. Table 43: sPPR Associated Rows sPPR Associated Row Address BA0* A17 A16 A15 A14 A13 A1 A0 16Gb: x4, x8, x16 DDR4 SDRAM sPPR Row Repair CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 136 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

All banks must be precharged and idle. DBI and CRC modes must be disabled, and all sPPR timings must be followed as shown in the timing diagram that follows. All other commands except those listed in the following sequences are illegal. 1. Issue MR4[5] 1 to enter sPPR mode enable. a. All DQ are driven HIGH. 2. Issue four consecutive guard key commands (shown in the table below) to MR0 with each command separated by tMOD. Please note that JEDEC recently added the four guard key entry used for hPPR to sPPR entry; early DRAMs may not re- quire four guard key entry code. A prudent controller design should accommodate either option in case an earlier DRAM is used. a. Any interruption of the key sequence by other commands, such as ACT , WR, RD, PRE, REF , ZQ, and NOP , are not allowed. b. If the guard key bits are not entered in the required order or interrupted with other MR commands, sPPR will not be enabled, and the programming cycle will result in a NOP . c. When the sPPR entry sequence is interrupted and followed by ACT and WR commands, these commands will be conducted as normal DRAM com- mands. d. JEDEC allows A6:0 to be "Don't Care" on 4Gb and 8Gb devices from a suppli- er perspective and the user should rely on vendor datasheet. Table 44: PPR MR0 Guard Key Settings MR0 BG1:0 BA1:0 A17:12 A11 A10 A9 A8 A7 A6:0 First guard key 0 0 xxxxxx 1 1 0 0 1 1111111 Second guard key 0 0 xxxxxx 0 1 1 1 1 1111111 Third guard key 0 0 xxxxxx 1 0 1 1 1 1111111 Fourth guard key 0 0 xxxxxx 0 0 1 1 1 1111111 3. After tMOD, issue an ACT command with failing BG and BA with the row address to be repaired. 4. After tRCD, issue a WR command with BG and BA of failing row address. a. The address must be at valid levels, but the address is a "Don't Care." 5. All DQ of the target DRAM should be driven LOW for 4 nCK (bit 0 through bit 7) after WL (WL = CWL + AL + PL) in order for sPPR to initiate repair. a. Repair will be initiated to the target DRAM only if all DQ during bit 0 through bit 7 are LOW . b. Repair will not be initiated to the target DRAM if any DQ during bit 0 through bit 7 is HIGH. 1. JEDEC states: All DQs of target DRAM should be LOW for 4 tCK. If HIGH is driven to all DQs of a DRAM consecutively for equal to or longer than the first 2 tCK, then DRAM does not conduct hPPR and retains data if REF command is properly issued; if all DQs are neither LOW for 4tCK nor HIGH for equal to or longer than the first 2tCK, then hPPR mode ex- ecution is unknown. c. DQS should function normally. 6. REF command may NOT be issued at anytime while in sPPR mode. 7. Issue PRE after tWR time so that the device can repair the target row during tWR time. a. Wait tPGM_Exit_s after PRE to allow the device to recognize the repaired tar- get row address. 16Gb: x4, x8, x16 DDR4 SDRAM sPPR Row Repair CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 137 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

hPPR/sPPR Support Identifier Table 46: DDR4 Repair Mode Support Identifier MPR Page 2 A7 A6 A5 A4 A3 A2 A1 A0 UI0 UI1 UI2 UI3 UI4 UI5 UI6 UI7 MPR0 hPPR 1 sPPR2 RTT_WR Temp sensor CRC RTT_WR Notes: 1. 0 = hPPR mode is not available, 1 = hPPR mode is available. 2. 0 = sPPR mode is not available, 1 = sPPR mode is available. 3. Gray shaded areas are for reference only. ACTIVATE Command The ACTIVATE command is used to open (activate) a row in a particular bank for subse- quent access. The values on the BG[1:0] inputs select the bank group, the BA[1:0] inputs select the bank within the bank group, and the address provided on inputs A[17:0] se- lects the row within the bank. This row remains active (open) for accesses until a PRE- CHARGE command is issued to that bank. A PRECHARGE command must be issued be- fore opening a different row in the same bank. Bank-to-bank command timing for AC- TIVATE commands uses two different timing parameters, depending on whether the banks are in the same or different bank group. tRRD_S (short) is used for timing be- tween banks located in different bank groups. tRRD_L (long) is used for timing between banks located in the same bank group. Another timing restriction for consecutive ACTI- VATE commands [issued at tRRD (MIN)] is tFAW (four activate window). Because there is a maximum of four banks in a bank group, the tFAW parameter applies across differ- ent bank groups (five ACTIVATE commands issued at tRRD_L (MIN) to the same bank group would be limited by tRC). Figure 78: tRRD Timing T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 tRRD_S T10 T11 Don’t Care BG a DESACT ACTDES DES DES DES DES DES DES DES CK_t CK_c Command Bank Group (BG) Bank cBank Row n BG b Bank c Row n BG b Bank d Row nAddress tRRD_L ACT Notes: 1. tRRD_S; ACTIVATE-to-ACTIVATE command period (short); applies to consecutive ACTI- VATE commands to different bank groups (that is, T0 and T4). 2. tRRD_L; ACTIVATE-to-ACTIVATE command period (long); applies to consecutive ACTI- VATE commands to the different banks in the same bank group (that is, T4 and T10). 16Gb: x4, x8, x16 DDR4 SDRAM hPPR/sPPR Support Identifier CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 139 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Figure 79: tFAW Timing T0 Ta0 Tb0 Tc0 Tc1 Tc2 tRRD tRRD Td0 Td1 Don’t Care Time Break Valid ValidACT ACTValid Valid Valid Valid Valid NOP CK_t CK_c Command Bank Group (BG) ValidBank Valid ACT ACT Address tFAW ACT Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid tRRD Note: 1. tFAW; four activate windows. PRECHARGE Command The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row activation for a specified time ( tRP) after the PRECHARGE command is issued. An exception to this is the case of concurrent auto precharge, where a READ or WRITE command to a different bank is allowed as long as it does not interrupt the data transfer in the current bank and does not violate any other timing parameters. After a bank is precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued to that bank. A PRECHARGE command is allowed if there is no open row in that bank (idle state) or if the previously open row is already in the process of precharging. However, the precharge period will be determined by the last PRECHARGE command issued to the bank. The auto precharge feature is engaged when a READ or WRITE command is issued with A10 HIGH. The auto precharge feature uses the RAS lockout circuit to internally delay the PRECHARGE operation until the ARRAY RESTORE operation has completed. The RAS lockout circuit feature allows the PRECHARGE operation to be partially or com- pletely hidden during burst READ cycles when the auto precharge feature is engaged. The PRECHARGE operation will not begin until after the last data of the burst write se- quence is properly stored in the memory array. REFRESH Command The REFRESH command (REF) is used during normal operation of the device. This command is nonpersistent, so it must be issued each time a refresh is required. The de- vice requires REFRESH cycles at an average periodic interval of tREFI. When CS_n, RAS_n/A16, and CAS_n/A15 are held LOW and WE_n/A14 HIGH at the rising edge of the clock, the device enters a REFRESH cycle. All banks of the SDRAM must be pre- charged and idle for a minimum of the precharge time, tRP (MIN), before the REFRESH command can be applied. The refresh addressing is generated by the internal DRAM re- fresh controller. This makes the address bits “Don’t Care” during a REFRESH command. An internal address counter supplies the addresses during the REFRESH cycle. No con- trol of the external address bus is required once this cycle has started. When the RE- FRESH cycle has completed, all banks of the SDRAM will be in the precharged (idle) 16Gb: x4, x8, x16 DDR4 SDRAM PRECHARGE Command CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 140 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

state. A delay between the REFRESH command and the next valid command, except DES, must be greater than or equal to the minimum REFRESH cycle time tRFC (MIN), as shown in Figure 80 (page 141). Note: The tRFC timing parameter depends on memory density. In general, a REFRESH command needs to be issued to the device regularly every tREFI interval. To allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh interval is provided for postponing and pulling- in the REFRESH command. A limited number REFRESH commands can be postponed depending on refresh mode: a maximum of 8 REFRESH commands can be postponed when the device is in 1X refresh mode; a maximum of 16 REFRESH commands can be postponed when the device is in 2X refresh mode; and a maximum of 32 REFRESH commands can be postponed when the device is in 4X refresh mode. When 8 consecutive REFRESH commands are postponed, the resulting maximum inter- val between the surrounding REFRESH commands is limited to 9 × tREFI (see Figure 81 (page 142)). For both the 2X and 4X refresh modes, the maximum interval between sur- rounding REFRESH commands allowed is limited to 17 × tREFI2 and 33 × tREFI4, re- spectively. A limited number REFRESH commands can be pulled-in as well. A maximum of 8 addi- tional REFRESH commands can be issued in advance or “pulled-in” in 1X refresh mode, a maximum of 16 additional REFRESH commands can be issued when in advance in 2X refresh mode, and a maximum of 32 additional REFRESH commands can be issued in advance when in 4X refresh mode. Each of these REFRESH commands reduces the number of regular REFRESH commands required later by one. The resulting maximum interval between two surrounding REFRESH commands is limited to 9 × tREFI (Fig- ure 82 (page 142)), 17 × tRFEI2, or 33 × tREFI4. At any given time, a maximum of 16 REF commands can be issued within 2 × tREFI, 32 REF2 commands can be issued within 4 × tREFI2, and 64 REF4 commands can be issued within 8 × tREFI4 (larger densities are limited by tRFC1, tRFC2, and tRFC4, respectively, which must still be met). Figure 80: REFRESH Command Timing DESREF DES REF Valid Valid Valid Valid REF Valid ValidValid CK_t CK_c Command tRFC tRFC (MIN) tREFI (MAX 9 × tREFI) Don’t CareTime Break T0 T1 Ta0 Ta1 Tb0 Tb1 Tb2 Tb3 Tc0 Tc1 Tc2 Tc3 ValidDESDES DRAM must be idle DRAM must be idle Notes: 1. Only DES commands are allowed after a REFRESH command is registered until tRFC (MIN) expires. 2. Time interval between two REFRESH commands may be extended to a maximum of 9 × tREFI. 16Gb: x4, x8, x16 DDR4 SDRAM REFRESH Command CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 141 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Figure 81: Postponing REFRESH Commands (Example) W

8 REF-Commands postponed

tREFI9 × tREFI Figure 82: Pulling In REFRESH Commands (Example) W

8 REF-Commands pulled-in

tREFI 9 × tREFI 16Gb: x4, x8, x16 DDR4 SDRAM REFRESH Command CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 142 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Temperature-Controlled Refresh Mode During normal operation, temperature-controlled refresh (TCR) mode disabled, the de- vice must have a REFRESH command issued once every tREFI, except for what is al- lowed by posting (see REFRESH Command section). This means a REFRESH command must be issued once every 7.8μs if T C is less than or equal to 85°C, once every 3.9μs if TC is greater than 85°C, once every 1.95μs if TC is greater than 95°C, regardless of which Temperature Mode is selected (MR4[2]). TCR mode is disabled by setting MR4[3] = 0 while TCR mode is enabled by setting MR4[3] = 1. When TCR mode is enabled (MR4[3] = 1), the Temperature Mode must be selected where MR4[2] = 0 enables the Normal Temperature Mode while MR4[2] = 1 enables the Extended Temperature Mode. When TCR mode is enabled, the device will register the externally supplied REFRESH command and adjust the internal refresh period to be longer than tREFI of the normal temperature range, when allowed, by skipping REFRESH commands with the proper gear ratio. TCR mode has two Temperature Modes to select between the normal tem- perature range and the extended temperature range; the correct Temperature Mode must be selected so the internal control operates correctly. The DRAM must have the correct refresh rate applied externally; the internal refresh rate is determined by the DRAM based upon the temperature. Normal Temperature Mode REFRESH commands should be issued to the device with the refresh period equal to tREFI of normal temperature range (-40°C to 85°C). The system must guarantee that the TC does not exceed 85°C when tREFI of the normal temperature range is used. The de- vice may adjust the internal refresh period to be longer than tREFI of the normal tem- perature range by skipping external REFRESH commands with the proper gear ratio when T C is below 85°C. The internal refresh period is automatically adjusted inside the DRAM, and the DRAM controller does not need to provide any additional control. Extended Temperature Mode REFRESH commands should be issued to the device with the refresh period equal to tREFI of extended temperature range (85°C to 95°C, or 95°C to 105°C) . The system must guarantee that the TC does not exceed 95°C, or 105°C. Even though the external refresh supports the extended temperature range, the device may adjust its internal refresh pe- riod to be equal to or longer than tREFI of the normal temperature range (-40°C to 85°C) by skipping external REFRESH commands with the proper gear ratio when TC is equal to or below 85°C. The internal refresh period is automatically adjusted inside the DRAM, and the DRAM controller does not need to provide any additional control. Table 47: Normal tREFI Refresh (TCR Enabled) Normal Temperature Mode Extended Temperature Mode Temperature External Refresh Period Internal Refresh Period External Refresh Period Internal Refresh Period TC ื 85°C 7.8μs ุ7.8μs 3.9μs 1 ุ7.8μs 85°C < TC ื 95°C 3.9μs 16Gb: x4, x8, x16 DDR4 SDRAM Temperature-Controlled Refresh Mode CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 143 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Table 47: Normal tREFI Refresh (TCR Enabled) (Continued) Normal Temperature Mode Extended Temperature Mode Temperature External Refresh Period Internal Refresh Period External Refresh Period Internal Refresh Period 95°C < TC ื 105°C 1.95μs Note: 1. If the external refresh period is slower than 3.9μs, the device will refresh internally at too slow of a refresh rate and will violate refresh specifications. 16Gb: x4, x8, x16 DDR4 SDRAM Temperature-Controlled Refresh Mode CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 144 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Figure 83: TCR Mode Example1 External REFRESH commands are not ignored At least every other external REFRESH ignored Controller 85°C TC ” 95°C TC ” 85°C Controller issues REFRESH commands at extended temperature rate REFRESHExternal tREFI 3.9μs Internal tREFI 3.9μs Internal tREFI •7.8μs REFRESH REFRESH REFRESH REFRESH REFRESH REFRESH REFRESH REFRESH REFRESH REFRESH REFRESH REFRESH REFRESH REFRESH REFRESH REFRESH REFRESH Note: 1. TCR enabled with Extended Temperature Mode selected. 16Gb: x4, x8, x16 DDR4 SDRAM Temperature-Controlled Refresh Mode CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 145 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Fine Granularity Refresh Mode Mode Register and Command Truth Table The REFRESH cycle time (tRFC) and the average refresh interval (tREFI) can be pro- grammed by the MRS command. The appropriate setting in the mode register will set a single set of REFRESH cycle times and average refresh interval for the device (fixed mode), or allow the dynamic selection of one of two sets of REFRESH cycle times and average refresh interval for the device (on-the-fly mode [OTF]). OTF mode must be ena- bled by MRS before any OTF REFRESH command can be issued. Table 48: MRS Definition MR3[8] MR3[7] MR3[6] Refresh Rate Mode 0 0 0 Normal mode (fixed 1x) 0 0 1 Fixed 2x 0 1 0 Fixed 4x 0 1 1 Reserved 1 0 0 Reserved 1 0 1 On-the-fly 1x/2x 1 1 0 On-the-fly 1x/4x 1 1 1 Reserved There are two types of OTF modes (1x/2x and 1x/4x modes) that are selectable by pro- gramming the appropriate values into the mode register MR3 [8:6]. When either of the two OTF modes is selected, the device evaluates the BG0 bit when a REFRESH com- mand is issued, and depending on the status of BG0, it dynamically switches its internal refresh configuration between 1x and 2x (or 1x and 4x) modes, and then executes the corresponding REFRESH operation. Table 49: REFRESH Command Truth Table Refresh CS_n ACT_n RAS_n/A CAS_n/A WE_n/ A13 BG1 BG0 A10/ AP A[9:0], A[12:11], A[20:16] MR3[8:6 Fixed rate L H L L H V V V V 0vv OTF: 1x L H L L H V L V V 1vv OTF: 2x L H L L H V H V V 101 OTF: 4x L H L L H V H V V 110 tREFI and tRFC Parameters The default refresh rate mode is fixed 1x mode where REFRESH commands should be issued with the normal rate; that is, tREFI1 = tREFI(base) (for TC ื 85°C), and the dura- tion of each REFRESH command is the normal REFRESH cycle time (tRFC1). In 2x mode (either fixed 2x or OTF 2x mode), REFRESH commands should be issued to the device at the double frequency ( tREFI2 = tREFI(base)/2) of the normal refresh rate. In 4x mode, the REFRESH command rate should be quadrupled (tREFI4 = tREFI(base)/4). Per 16Gb: x4, x8, x16 DDR4 SDRAM Fine Granularity Refresh Mode CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 146 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

each mode and command type, the tRFC parameter has different values as defined in the following table. For discussion purposes, the REFRESH command that should be issued at the normal refresh rate and has the normal REFRESH cycle duration may be referred to as an REF1x command. The REFRESH command that should be issued at the double frequency tREFI2 = tREFI(base)/2) may be referred to as a REF2x command. Finally, the REFRESH command that should be issued at the quadruple rate (tREFI4 = tREFI(base)/4) may be referred to as a REF4x command. In the fixed 1x refresh rate mode, only REF1x commands are permitted. In the fixed 2x refresh rate mode, only REF2x commands are permitted. In the fixed 4x refresh rate mode, only REF4x commands are permitted. When the on-the-fly 1x/2x refresh rate mode is enabled, both REF1x and REF2x commands are permitted. When the OTF 1x/4x refresh rate mode is enabled, both REF1x and REF4x commands are permitted. Table 50: tREFI and tRFC Parameters Refresh Mode Parameter 2Gb 4Gb 8Gb 16Gb Units tREFI (base) 7.8 7.8 7.8 7.8 μs 1x mode tREFI1 -40°C ื TC ื 85°C tREFI(base) tREFI(base) tREFI(base) tREFI(base) μs 85°C ื TC ื 95°C tREFI(base)/2 tREFI(base)/2 tREFI(base)/2 tREFI(base)/2 μs 95°C ื TC ื 105°C tREFI(base)/4 tREFI(base)/4 tREFI(base)/4 tREFI(base)/4 μs tRFC1 160 260 350 350 ns 2x mode tREFI2 -40°C ื TC ื 85°C tREFI(base)/2 tREFI(base)/2 tREFI(base)/2 tREFI(base)/2 μs 85°C ื TC ื 95°C tREFI(base)/4 tREFI(base)/4 tREFI(base)/4 tREFI(base)/4 μs 95°C ื TC ื 105°C tREFI(base)/8 tREFI(base)/8 tREFI(base)/8 tREFI(base)/8 μs tRFC2 110 160 260 260 ns 4x mode tREFI4 -40°C ื TC ื 85°C tREFI(base)/4 tREFI(base)/4 tREFI(base)/4 tREFI(base)/4 μs 85°C ื TC ื 95°C tREFI(base)/8 tREFI(base)/8 tREFI(base)/8 tREFI(base)/8 μs 95°C ื TC ื 105°C tREFI(base)/16 tREFI(base)/16 tREFI(base)/16 tREFI(base)/16 μs tRFC4 90 110 160 160 ns 16Gb: x4, x8, x16 DDR4 SDRAM Fine Granularity Refresh Mode CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 147 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Figure 84: 4Gb with Fine Granularity Refresh Mode Example 1x Mode (-40°C to 85°C) 2x Mode (-40°C to 85°C) 4x Mode (-40°C to 85°C) Normal Temperature Operation – -40°C to 85°C REF@260ns REF@160ns REF@110ns REF@110ns REF@160ns REF@110ns REF@110ns REF@260ns REF@160ns REF@110ns REF@110ns REF@160ns REF@110ns REF@110nsREF@260ns REF@160ns REF@110ns tREFI = 7.8μs tREFI = 7.8μs tREFI = 3.9μstREFI = 3.9μstREFI = 3.9μstREFI = 3.9μs 1x Mode (-40°C to 105°C) 2x Mode (-40°C to 105°C) 4x Mode (-40°C to 105°C) REF@260ns REF@160ns REF@110ns REF@110ns REF@160ns REF@110ns REF@110ns REF@260ns REF@160ns REF@110ns REF@110ns REF@160ns REF@110ns REF@110nsREF@260ns REF@260ns REF@260ns REF@160ns REF@160ns REF@160ns REF@160ns REF@160ns REF@110ns REF@110ns REF@110ns REF@110ns REF@110ns REF@110ns REF@110ns REF@110ns REF@110ns tREFI = 3.9μstREFI = 3.9μstREFI = 3.9μstREFI = 3.9μs Extended Temperature Operation – -40°C to 105°C 16Gb: x4, x8, x16 DDR4 SDRAM Fine Granularity Refresh Mode CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 148 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

If the refresh rate is changed by either MRS or OTF . New tREFI and tRFC parameters will be applied from the moment of the rate change. When the REF1x command is issued to the DRAM, tREF1 and tRFC1 are applied from the time that the command was issued; when the REF2x command is issued, tREF2 and tRFC2 should be satisfied. Figure 85: OTF REFRESH Command Timing REF1 DESDES DES ValidDES REF2 DESValid Valid DESDES DESREF2 tRFC1 (MIN) tRFC2 (MIN) tREFI1 tREFI2 Don’t Care Command CK_t CK_c The following conditions must be satisfied before the refresh rate can be changed. Oth- erwise, data retention cannot be guaranteed.

• In the fixed 2x refresh rate mode or the OTF 1x/2x refresh mode, an even number of REF2x commands must be issued because the last change of the refresh rate mode with an MRS command before the refresh rate can be changed by another MRS com- mand.
• In the OTF1x/2x refresh rate mode, an even number of REF2x commands must be is- sued between any two REF1x commands.
• In the fixed 4x refresh rate mode or the OTF 1x/4x refresh mode, a multiple-of-four number of REF4x commands must be issued because the last change of the refresh rate with an MRS command before the refresh rate can be changed by another MRS command.
• In the OTF1x/4x refresh rate mode, a multiple-of-four number of REF4x commands must be issued between any two REF1x commands. There are no special restrictions for the fixed 1x refresh rate mode. Switching between fixed and OTF modes keeping the same rate is not regarded as a refresh rate change. Usage with TCR Mode If the temperature controlled refresh mode is enabled, only the normal mode (fixed 1x mode, MR3[8:6] = 000) is allowed. If any other refresh mode than the normal mode is selected, the temperature controlled refresh mode must be disabled. Self Refresh Entry and Exit The device can enter self refresh mode anytime in 1x, 2x, and 4x mode without any re- striction on the number of REFRESH commands that have been issued during the mode before the self refresh entry. However, upon self refresh exit, extra REFRESH com- mand(s) may be required, depending on the condition of the self refresh entry. The conditions and requirements for the extra REFRESH command(s) are defined as follows:
• In the fixed 2x refresh rate mode or the enable-OTF 1x/2x refresh rate mode, it is rec- ommended there be an even number of REF2x commands before entry into self re- fresh after the last self refresh exit, REF1x command, or MRS command that set the 16Gb: x4, x8, x16 DDR4 SDRAM Fine Granularity Refresh Mode CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 149 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

refresh mode. If this condition is met, no additional REFRESH commands are re- quired upon self refresh exit. In the case that this condition is not met, either one ex- tra REF1x command or two extra REF2x commands must be issued upon self refresh exit. These extra REFRESH commands are not counted toward the computation of the average refresh interval ( tREFI).

• In the fixed 4x refresh rate mode or the enable-OTF 1x/4x refresh rate mode, it is rec- ommended there be a multiple-of-four number of REF4x commands before entry in- to self refresh after the last self refresh exit, REF1x command, or MRS command that set the refresh mode. If this condition is met, no additional refresh commands are re- quired upon self refresh exit. When this condition is not met, either one extra REF1x command or four extra REF4x commands must be issued upon self refresh exit. These extra REFRESH commands are not counted toward the computation of the average refresh interval ( tREFI). There are no special restrictions on the fixed 1x refresh rate mode. This section does not change the requirement regarding postponed REFRESH com- mands. The requirement for the additional REFRESH command(s) described above is independent of the requirement for the postponed REFRESH commands. 16Gb: x4, x8, x16 DDR4 SDRAM Fine Granularity Refresh Mode CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 150 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

The SELF REFRESH command can be used to retain data in the device, even if the rest of the system is powered down. When in self refresh mode, the device retains data with- out external clocking. The device has a built-in timer to accommodate SELF REFRESH operation. The SELF REFRESH command is defined by having CS_n, RAS_n, CAS_n, and CKE held LOW with WE_n and ACT_n HIGH at the rising edge of the clock. Before issuing the SELF REFRESH ENTRY command, the device must be idle with all banks in the precharge state and tRP satisfied. Idle state is defined as: All banks are closed (tRP , tDAL, and so on, satisfied), no data bursts are in progress, CKE is HIGH, and all timings from previous operations are satisfied (tMRD, tMOD, tRFC, tZQinit, tZQoper, tZQCS, and so on). After the SELF REFRESH ENTRY command is registered, CKE must be held LOW to keep the device in self refresh mode. The DRAM automatically disables ODT termination, regardless of the ODT pin, when it enters self refresh mode and auto- matically enables ODT upon exiting self refresh. During normal operation (DLL_on), the DLL is automatically disabled upon entering self refresh and is automatically ena- bled (including a DLL reset) upon exiting self refresh. When the device has entered self refresh mode, all of the external control signals, except CKE and RESET_n, are “Don’t Care.” For proper SELF REFRESH operation, all power supply and reference pins (V DD, VDDQ, VSS, VSSQ, VPP, and VREFCA) must be at valid levels. The DRAM internal VREFDQ generator circuitry may remain on or be turned off depend- ing on the MR6 bit 7 setting. If the internal VREFDQ circuit is on in self refresh, the first WRITE operation or first write-leveling activity may occur after tXS time after self re- fresh exit. If the DRAM internal VREFDQ circuitry is turned off in self refresh, it ensures that the VREFDQ generator circuitry is powered up and stable within the tXSDLL period when the DRAM exits the self refresh state. The first WRITE operation or first write-lev- eling activity may not occur earlier than tXSDLL after exiting self refresh. The device ini- tiates a minimum of one REFRESH command internally within the tCKE period once it enters self refresh mode. The clock is internally disabled during a SELF REFRESH operation to save power. The minimum time that the device must remain in self refresh mode is tCKESR/ tCKESR_PAR. The user may change the external clock frequency or halt the external clock tCKSRE/tCKSRE_PAR after self refresh entry is registered; however, the clock must be restarted and tCKSRX must be stable before the device can exit SELF REFRESH oper- ation. The procedure for exiting self refresh requires a sequence of events. First, the clock must be stable prior to CKE going back HIGH. Once a SELF REFRESH EXIT command (SRX, combination of CKE going HIGH and DESELECT on the command bus) is registered, the following timing delay must be satisfied: Commands that do not require locked DLL: tXS = ACT , PRE, PREA, REF , SRE, and PDE.

• tXS_FAST = ZQCL, ZQCS, and MRS commands. For an MRS command, only DRAM CL, WR/RTP register, and DLL reset in MR0; RTT(NOM) register in MR1; the CWL and RTT(WR) registers in MR2; and gear-down mode register in MR3; WRITE and READ pre- amble registers in MR4; RTT(PARK) register in MR5; Data rate and VREFDQ calibration value registers in MR6 may be accessed provided the DRAM is not in per-DRAM mode. Access to other DRAM mode registers must satisfy tXS timing. WRITE com- mands (WR, WRS4, WRS8, WRA, WRAS4, and WRAS8) that require synchronous ODT and dynamic ODT controlled by the WRITE command require a locked DLL. 16Gb: x4, x8, x16 DDR4 SDRAM SELF REFRESH Operation CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 151 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Commands that require locked DLL in the normal operating range:

• tXSDLL – RD, RDS4, RDS8, RDA, RDAS4, and RDAS8 (unlike DDR3, WR, WRS4, WRS8, WRA, WRAS4, and WRAS8 because synchronous ODT is required). Depending on the system environment and the amount of time spent in self refresh, ZQ CALIBRATION commands may be required to compensate for the voltage and tempera- ture drift described in the ZQ CALIBRATION Commands section. To issue ZQ CALIBRA- TION commands, applicable timing requirements must be satisfied (see the ZQ Calibra- tion Timing figure). CKE must remain HIGH for the entire self refresh exit period tXSDLL for proper opera- tion except for self refresh re-entry. Upon exit from self refresh, the device can be put back into self refresh mode or power-down mode after waiting at least tXS period and issuing one REFRESH command (refresh period of tRFC). The DESELECT command must be registered on each positive clock edge during the self refresh exit interval tXS. ODT must be turned off during tXSDLL. The use of self refresh mode introduces the possibility that an internally timed refresh event can be missed when CKE is raised for exit from self refresh mode. Upon exit from self refresh, the device requires a minimum of one extra REFRESH command before it is put back into self refresh mode. Figure 86: Self Refresh Entry/Exit Timing CK_t CK_c Command DES DES SRE ADDR CKE ODT SRX Valid 1 Valid2 Valid Valid tRP tXS tXSDLL tCKESR/tCKESR_PAR tCPDEDtIS tCKSRE/tCKSRE_PAR tCKSRX Enter Self Refresh Exit Self Refresh T0 T1 Ta0 Td0 Td1 Te0 Tc0 Don’t Care Tf0 Time Break Tb0 Tg0 tXS_FAST Valid3 Valid Valid Valid Valid Valid Notes: 1. Only MRS (limited to those described in the SELF REFRESH Operation section), ZQCS, or ZQCL commands are allowed. 2. Valid commands not requiring a locked DLL. 3. Valid commands requiring a locked DLL. 16Gb: x4, x8, x16 DDR4 SDRAM SELF REFRESH Operation CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 152 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Figure 87: Self Refresh Entry/Exit Timing with CAL Mode &.BW &.BF 7 7 7 &RPPDQG $''5 ZR&6BQ &6BQ &.( 'RQ¶W&DUH 7 7 7D 7D7 7E 7E7D 7D 7E 9DOLG 9DOLG'(665( 9DOLG W&.65( W;6B)$67 W&.65; 1RWH1RWH Notes: 1. tCAL = 3nCK, tCPDED = 4nCK, tCKSRE/tCKSRE_PAR = 8nCK, tCKSRX = 8nCK, tXS_FAST = tREFC4 (MIN) + 10ns. 2. CS_n = HIGH, ACT_n = "Don't Care," RAS_n/A16 = "Don't Care," CAS_n/A15 = "Don't Care," WE_n/A14 = "Don't Care." 3. Only MRS (limited to those described in the SELF REFRESH Operations section), ZQCS, or ZQCL commands are allowed. 4. The figure only displays tXS_FAST timing, but tCAL must also be added to any tXS and tXSDLL associated commands during CAL mode. Self Refresh Abort The exit timing from self refresh exit to the first valid command not requiring a locked DLL is tXS. The value of tXS is (tRFC1 + 10ns). This delay allows any refreshes started by the device time to complete. tRFC continues to grow with higher density devices, so tXS will grow as well. An MRS bit enables the self refresh abort mode. If the bit is disabled, the controller uses tXS timings (location MR4, bit 9). If the bit is enabled, the device aborts any ongoing refresh and does not increment the refresh counter. The controller can issue a valid command not requiring a locked DLL after a delay of tXS_ABORT . Upon exit from self refresh, the device requires a minimum of one extra REFRESH com- mand before it is put back into self refresh mode. This requirement remains the same irrespective of the setting of the MRS bit for self refresh abort. 16Gb: x4, x8, x16 DDR4 SDRAM SELF REFRESH Operation CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 153 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Figure 88: Self Refresh Abort CK_t CK_c Command DES DES SRE ADDR CKE ODT SRX Valid 1 Valid2 Valid Valid tRP tXS_ABORT tXSDLL tCKESR/tCKESR_PAR tCPDEDtIS tCKSRE/tCKSRE_PAR tCKSRX Enter Self Refresh Exit Self Refresh T0 T1 Ta0 Td0 Td1 Te0 Tc0 Don’t Care Tf0 Time Break Tb0 Tg0 tXS_FAST Valid3 Valid Valid Valid Valid Valid Notes: 1. Only MRS (limited to those described in the SELF REFRESH Operation section), ZQCS, or ZQCL commands are allowed. 2. Valid commands not requiring a locked DLL with self refresh abort mode enabled in the mode register. 3. Valid commands requiring a locked DLL. Self Refresh Exit with NOP Command Exiting self refresh mode using the NO OPERATION command (NOP) is allowed under a specific system application. This special use of NOP allows for a common command/ address bus between active DRAM devices and DRAM(s) in maximum power saving mode. Self refresh mode may exit with NOP commands provided:

• The device entered self refresh mode with CA parity, CAL, and gear-down disabled. tMPX_S and tMPX_LH are satisfied.
• NOP commands are only issued during tMPX_LH window. No other command is allowed during the tMPX_LH window after an SELF REFRESH EX- IT (SRX) command is issued. 16Gb: x4, x8, x16 DDR4 SDRAM SELF REFRESH Operation CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 154 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Figure 89: Self Refresh Exit with NOP Command &.BW &.BF 7D 7D 7D 7G7E 7E 7E 7G 7F7E 7F 7F 7F 7H 7H 7F 7G 7G &.( 2'7 W&.65; W03;B/+W03;B6 &RPPDQG $''5 &6BQ 'RQ¶W&DUH 9DOLG 9DOLG 9DOLG 9DOLG 65; 123 123 123 123 W;6 W;6'//W;6 9DOLG 1RWH1RWH '(6 9DOLG 9DOLG 9DOLG 9DOLG 16Gb: x4, x8, x16 DDR4 SDRAM SELF REFRESH Operation CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 155 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Power-down is synchronously entered when CKE is registered LOW (along with a DESE- LECT command). CKE is not allowed to go LOW when the following operations are in progress: MRS command, MPR operations, ZQCAL operations, DLL locking, or READ/ WRITE operations. CKE is allowed to go LOW while any other operations, such as ROW ACTIVATION, PRECHARGE or auto precharge, or REFRESH, are in progress, but the power-down I DD specification will not be applied until those operations are complete. The timing diagrams that follow illustrate power-down entry and exit. For the fastest power-down exit timing, the DLL should be in a locked state when pow- er-down is entered. If the DLL is not locked during power-down entry, the DLL must be reset after exiting power-down mode for proper READ operation and synchronous ODT operation. DRAM design provides all AC and DC timing and voltage specification as well as proper DLL operation with any CKE intensive operations as long as the control- ler complies with DRAM specifications. During power-down, if all banks are closed after any in-progress commands are com- pleted, the device will be in precharge power-down mode; if any bank is open after in- progress commands are completed, the device will be in active power-down mode. Entering power-down deactivates the input and output buffers, excluding CK, CKE, and RESET_n. In power-down mode, DRAM ODT input buffer deactivation is based on Mode Register 5, bit 5 (MR5[5]). If it is configured to 0b, the ODT input buffer remains on and the ODT input signal must be at valid logic level. If it is configured to 1b, the ODT input buffer is deactivated and the DRAM ODT input signal may be floating and the device does not provide R TT(NOM) termination. Note that the device continues to provide RTT(Park) termination if it is enabled in MR5[8:6]. To protect internal delay on the CKE line to block the input signals, multiple DES commands are needed during the CKE switch off and on cycle(s); this timing period is defined as tCPDED. CKE LOW will result in deactivation of command and address receivers after tCPDED has expired. Table 51: Power-Down Entry Definitions DRAM Status DLL Power- Down Exit Relevant Parameters Active (a bank or more open) On Fast tXP to any valid command. Precharged (all banks precharged) On Fast tXP to any valid command. The DLL is kept enabled during precharge power-down or active power-down. In pow- er-down mode, CKE is LOW, RESET_n is HIGH, and a stable clock signal must be main- tained at the inputs of the device. ODT should be in a valid state, but all other input sig- nals are "Don't Care." (If RESET_n goes LOW during power-down, the device will be out of power-down mode and in the reset state.) CKE LOW must be maintained until tCKE has been satisfied. Power-down duration is limited by 9 × tREFI. The power-down state is synchronously exited when CKE is registered HIGH (along with DES command). CKE HIGH must be maintained until tCKE has been satisfied. The ODT input signal must be at a valid level when the device exits from power-down mode, independent of MR1 bit [10:8] if R TT(NOM) is enabled in the mode register. If RTT(NOM) is disabled, the ODT input signal may remain floating. A valid, executable command can 16Gb: x4, x8, x16 DDR4 SDRAM Power-Down Mode CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 156 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

be applied with power-down exit latency, tXP , after CKE goes HIGH. Power-down exit la- tency is defined in the AC Specifications table. Figure 90: Active Power-Down Entry and Exit CK_t CK_c Command DES DES DES DES DES Address CKE Enter power-down mode Exit power-down mode tPD Valid Valid Valid Valid tCPDED Valid Valid ODT (ODT buffer enabled - MR5[5] = 0)2 tIH tIH tIS tIS T0 T1 T2 Ta0 Ta1 Tb0 Tb1 Tc0 DES tXP tCKE Don’t CareTime Break ODT (ODT buffer disabled - MR5[5] = 1)3 Refer to ODT Power-Down Entry/Exit with ODT Buffer Disable Mode figures Notes: 1. Valid commands at T0 are ACT, DES, or PRE with one bank remaining open after comple- tion of the PRECHARGE command. 2. ODT pin driven to a valid state; MR5[5] = 0 (normal setting). 3. ODT pin drive/float timing requirements for the ODT input buffer disable option (for ad- ditional power savings during active power-down) is described in the section for ODT In- put Buffer Disable Mode for Power-Down (page 164); MR5[5] = 1. 16Gb: x4, x8, x16 DDR4 SDRAM Power-Down Mode CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 157 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Figure 101: REFRESH Command to Power-Down Entry with CAL &.BW &.BF $GGUHVV &.( W3' '(6 9DOLG 9DOLG W,+ W,+W,6 W,6 7 7 7D 7E 7E 7F 7F 7G 7G 7H 7H 7I 'RQ¶W&DUH7LPH%UHDN &6BQ 16Gb: x4, x8, x16 DDR4 SDRAM Power-Down Mode CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 163 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

ODT Input Buffer Disable Mode for Power-Down DRAM does not provide RTT_NOM termination during power-down when ODT input buffer deactivation mode is enabled in MR5 bit A5. To account for DRAM internal delay on CKE line to disable the ODT buffer and block the sampled output, the host controller must continuously drive ODT to either low or high when entering power down (from tDODTLoff+1 prior to CKE low till tCPDED after CKE low). The ODT signal is allowed to float after tCPDEDmin has expired. In this mode, RTT_NOM termination corresponding to sampled ODT at the input when CKE is registered low (and tANPD before that) may be either RTT_NOM or RTT_PARK. tANPD is equal to (WL-1) and is counted backwards from PDE. Figure 102: ODT Power-Down Entry with ODT Buffer Disable Mode diff_CK tDODTLoff +1 tCPDED (MIN) CKE ODT Floating DRAM_RTT_sync (DLL enabled) CA parity disabled DRAM_RTT_async (DLL disabled) RTT(Park)RTT(NOM) tCPDED (MIN) + tADC (MAX) tADC (MIN) DODTLoff RTT(Park)RTT(NOM) tAONAS (MIN) tCPDED (MIN) + tAOFAS (MAX) 16Gb: x4, x8, x16 DDR4 SDRAM ODT Input Buffer Disable Mode for Power-Down CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 164 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Figure 103: ODT Power-Down Exit with ODT Buffer Disable Mode diff_CK CKE ODT_A (DLL enabled) tADC (MAX)tXP tXP Floating DRAM_RTT_A RTT(Park) RTT(NOM) tADC (MIN) DODTLon ODT_B (DLL disabled) Floating DRAM_RTT_B RTT(Park) tAONAS (MIN) tAOFAS (MAX) RTT(NOM) 16Gb: x4, x8, x16 DDR4 SDRAM ODT Input Buffer Disable Mode for Power-Down CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 165 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

The CRC write data feature takes the CRC generated data from the DRAM controller and compares it to the internally CRC generated data and determines whether the two match (no CRC error) or do not match (CRC error). Figure 104: CRC Write Data Operation Data DRAM Controller DRAM Data CRC Code CRC Code CRC engine Data CRC Code CRC engine Compare CRC WRITE CRC DATA Operation A DRAM controller generates a CRC checksum using a 72-bit CRC tree and forms the write data frames, as shown in the following CRC data mapping tables for the x4, x8, and x16 configurations. A x4 device has a CRC tree with 32 input data bits used, and the re- maining upper 40 bits D[71:32] being 1s. A x8 device has a CRC tree with 64 input data bits used, and the remaining upper 8 bits dependant upon whether DM_n/DBI_n is used (1s are sent when not used). A x16 device has two identical CRC trees each, one for the lower byte and one for the upper byte, with 64 input data bits used by each, and the remaining upper 8 bits on each byte dependant upon whether DM_n/DBI_n is used (1s are sent when not used). For a x8 and x16 DRAMs, the DRAM memory controller must send 1s in transfer 9 location whether or not DM_n/DBI_n is used. The DRAM checks for an error in a received code word D[71:0] by comparing the re- ceived checksum against the computed checksum and reports errors using the ALERT_n signal if there is a mismatch. The DRAM can write data to the DRAM core without waiting for the CRC check for full writes when DM is disabled. If bad data is written to the DRAM core, the DRAM memory controller will try to overwrite the bad data with good data; this means the DRAM controller is responsible for data coherency when DM is disabled. However, in the case where both CRC and DM are enabled via 16Gb: x4, x8, x16 DDR4 SDRAM CRC Write Data Feature CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 166 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

MRS (that is, persistent mode), the DRAM will not write bad data to the core when a CRC error is detected. DBI_n and CRC Both Enabled The DRAM computes the CRC for received written data D[71:0]. Data is not inverted back based on DBI before it is used for computing CRC. The data is inverted back based on DBI before it is written to the DRAM core. DM_n and CRC Both Enabled When both DM and write CRC are enabled in the DRAM mode register, the DRAM cal- culates CRC before sending the write data into the array. If there is a CRC error, the DRAM blocks the WRITE operation and discards the data. If a CRC error is encountered from a WRITE with auto precharge (WRA), the DRAM will not block the precharge. The Nonconsecutive WRITE (BL8/BC4-OTF) with 2 tCK Preamble and Write CRC in Same or Different Bank Group and the WRITE (BL8/BC4-OTF/Fixed) with 1tCK Preamble and Write CRC in Same or Different BankGroup figures in the WRITE Operation section show timing differences when DM is enabled. DM_n and DBI_n Conflict During Writes with CRC Enabled Both write DBI_n and DM_n can not be enabled at the same time; read DBI_n and DM_n can be enabled at the same time. CRC and Write Preamble Restrictions When write CRC is enabled:

• And 1 tCK WRITE preamble mode is enabled, a tCCD_S or tCCD_L of 4 clocks is not allowed.
• And 2 tCK WRITE preamble mode is enabled, a tCCD_S or tCCD_L of 6 clocks is not allowed. CRC Simultaneous Operation Restrictions When write CRC is enabled, neither MPR writes nor per-DRAM mode is allowed. CRC Polynomial The CRC polynomial used by DDR4 is the ATM-8 HEC, X8 + X2 + X1 + 1. A combinatorial logic block implementation of this 8-bit CRC for 72 bits of data in- cludes 272 two-input XOR gates contained in eight 6-XOR-gate-deep trees. The CRC polynomial and combinatorial logic used by DDR4 is the same as used on GDDR5. The error coverage from the DDR4 polynomial used is shown in the following table. Table 52: CRC Error Detection Coverage Error Type Detection Capability Random single-bit errors 100% Random double-bit errors 100% 16Gb: x4, x8, x16 DDR4 SDRAM CRC Write Data Feature CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 167 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Table 52: CRC Error Detection Coverage (Continued) Error Type Detection Capability Random odd count errors 100% Random multibit UI vertical column error detection excluding DBI bits 100% CRC Combinatorial Logic Equations module CRC8_D72; // polynomial: (0 1 2 8) // data width: 72 // convention: the first serial data bit is D[71] //initial condition all 0 implied // "^" = XOR function [7:0] nextCRC8_D72; input [71:0] Data; input [71:0] D; reg [7:0] CRC; begin D = Data; CRC[0] = CRC[1] = ]^D[0]; CRC[2] = CRC[3] = CRC[4] = CRC[5] = 16Gb: x4, x8, x16 DDR4 SDRAM CRC Write Data Feature CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 168 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

CRC[6] = CRC[7] = nextCRC8_D72 = CRC; Burst Ordering for BL8 DDR4 supports fixed WRITE burst ordering [A2:A1:A0 = 0:0:0] when write CRC is ena- bled in BL8 (fixed). CRC Data Bit Mapping Table 53: CRC Data Mapping for x4 Devices, BL8 Func- tion Transfer 0 1 2 3 4 5 6 7 8 9 DQ0 D0 D1 D2 D3 D4 D5 D6 D7 CRC0 CRC4 DQ1 D8 D9 D10 D11 D12 D13 D14 D15 CRC1 CRC5 DQ2 D16 D17 D18 D19 D20 D21 D22 D23 CRC2 CRC6 DQ3 D24 D25 D26 D27 D28 D29 D30 D31 CRC3 CRC7 Table 54: CRC Data Mapping for x8 Devices, BL8 Func- tion Transfer 0 1 2 3 4 5 6 7 8 9 DQ0 D0 D1 D2 D3 D4 D5 D6 D7 CRC0 1 DQ1 D8 D9 D10 D11 D12 D13 D14 D15 CRC1 1 DQ2 D16 D17 D18 D19 D20 D21 D22 D23 CRC2 1 DQ3 D24 D25 D26 D27 D28 D29 D30 D31 CRC3 1 DQ4 D32 D33 D34 D35 D36 D37 D38 D39 CRC4 1 DQ5 D40 D41 D42 D43 D44 D45 D46 D47 CRC5 1 DQ6 D48 D49 D50 D51 D52 D53 D54 D55 CRC6 1 DQ7 D56 D57 D58 D59 D60 D61 D62 D63 CRC7 1 DM_n/ DBI_n D64 D65 D66 D67 D68 D69 D70 D71 1 1 A x16 device is treated as two x8 devices; a x16 device will have two identical CRC trees implemented. CRC[7:0] covers data bits D[71:0], and CRC[15:8] covers data bits D[143:72]. 16Gb: x4, x8, x16 DDR4 SDRAM CRC Write Data Feature CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 169 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Table 55: CRC Data Mapping for x16 Devices, BL8 Func- tion Transfer 0 1 2 3 4 5 6 7 8 9 DQ0 D0 D1 D2 D3 D4 D5 D6 D7 CRC0 1 DQ1 D8 D9 D10 D11 D12 D13 D14 D15 CRC1 1 DQ2 D16 D17 D18 D19 D20 D21 D22 D23 CRC2 1 DQ3 D24 D25 D26 D27 D28 D29 D30 D31 CRC3 1 DQ4 D32 D33 D34 D35 D36 D37 D38 D39 CRC4 1 DQ5 D40 D41 D42 D43 D44 D45 D46 D47 CRC5 1 DQ6 D48 D49 D50 D51 D52 D53 D54 D55 CRC6 1 DQ7 D56 D57 D58 D59 D60 D61 D62 D63 CRC7 1 LDM_n/ LDBI_n D64 D65 D66 D67 D68 D69 D70 D71 1 1 DQ8 D72 D73 D74 D75 D76 D77 D78 D79 CRC8 1 DQ9 D80 D81 D82 D83 D84 D85 D86 D87 CRC9 1 DQ10 D88 D89 D90 D91 D92 D93 D94 D95 CRC10 1 DQ11 D96 D97 D98 D99 D100 D101 D102 D103 CRC11 1 DQ12 D104 D105 D106 D107 D108 D109 D110 D111 CRC12 1 DQ13 D112 D113 D114 D115 D116 D117 D118 D119 CRC13 1 DQ14 D120 D121 D122 D123 D124 D125 D126 D127 CRC14 1 DQ15 D128 D129 D130 D131 D132 D133 D134 D135 CRC15 1 UDM_n/ UDBI_n D136 D137 D138 D139 D140 D141 D142 D143 1 1 CRC Enabled With BC4 If CRC and BC4 are both enabled, then address bit A2 is used to transfer critical data first for BC4 writes. CRC with BC4 Data Bit Mapping For a x4 device, the CRC tree inputs are 16 data bits, and the inputs for the remaining bits are 1. When A2 = 1, data bits D[7:4] are used as inputs for D[3:0], D[15:12] are used as inputs to D[11:8], and so forth, for the CRC tree. Table 56: CRC Data Mapping for x4 Devices, BC4 Function Transfer 0 1 2 3 4 5 6 7 8 9 A2 = 0 D Q 0 D 0 D 1 D 2 D 3 1111 CRC0 CRC4 D Q 1 D 8 D 9 D 1 0 D 1 1 1111 CRC1 CRC5 D Q 2 D 1 6 D 1 7 D 1 8 D 1 9 1111 CRC2 CRC6 16Gb: x4, x8, x16 DDR4 SDRAM CRC Write Data Feature CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 170 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Table 56: CRC Data Mapping for x4 Devices, BC4 (Continued) Function Transfer 0 1 2 3 4 5 6 7 8 9 DQ3 D24 D25 D26 D27 1 1 1 1 CRC3 CRC7 A2 = 1 DQ0 D4 D5 D6 D7 1 1 1 1 CRC0 CRC4 DQ1 D12 D13 D14 D15 1 1 1 1 CRC1 CRC5 DQ2 D20 D21 D22 D23 1 1 1 1 CRC2 CRC6 DQ3 D28 D29 D30 D31 1 1 1 1 CRC3 CRC7 For a x8 device, the CRC tree inputs are 36 data bits. When A2 = 0, the input bits D[67:64]) are used if DBI_n or DM_n functions are enabled; if DBI_n and DM_n are disabled, then D[67:64]) are 1. When A2 = 1, data bits D[7:4] are used as inputs for D[3:0], D[15:12] are used as inputs to D[11:8], and so forth, for the CRC tree. The input bits D[71:68]) are used if DBI_n or DM_n functions are enabled; if DBI_n and DM_n are disabled, then D[71:68]) are 1. Table 57: CRC Data Mapping for x8 Devices, BC4 Function Transfer 0 1 2 3 4 5 6 7 8 9 A2 = 0 DQ0 D0 D1 D2 D3 1 1 1 1 CRC0 1 DQ1 D8 D9 D10 D11 1 1 1 1 CRC1 1 DQ2 D16 D17 D18 D19 1 1 1 1 CRC2 1 DQ3 D24 D25 D26 D27 1 1 1 1 CRC3 1 DQ4 D32 D33 D34 D35 1 1 1 1 CRC4 1 DQ5 D40 D41 D42 D43 1 1 1 1 CRC5 1 DQ6 D48 D49 D50 D51 1 1 1 1 CRC6 1 DQ7 D56 D57 D58 D59 1 1 1 1 CRC7 1 DM_n/DBI_n D64 D65 D66 D67 1 1 1111 A2 = 1 DQ0 D4 D5 D6 D7 1 1 1 1 CRC0 1 DQ1 D12 D13 D14 D15 1 1 1 1 CRC1 1 DQ2 D20 D21 D22 D23 1 1 1 1 CRC2 1 DQ3 D28 D29 D30 D31 1 1 1 1 CRC3 1 DQ4 D36 D37 D38 D39 1 1 1 1 CRC4 1 DQ5 D44 D45 D46 D47 1 1 1 1 CRC5 1 DQ6 D52 D53 D54 D55 1 1 1 1 CRC6 1 DQ7 D60 D61 D62 D63 1 1 1 1 CRC7 1 DM_n/DBI_n D68 D69 D70 D71 1 1 1111 There are two identical CRC trees for x16 devices, each have CRC tree inputs of 36 bits. 16Gb: x4, x8, x16 DDR4 SDRAM CRC Write Data Feature CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 171 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

When A2 = 0, input bits D[67:64] are used if DBI_n or DM_n functions are enabled; if DBI_n and DM_n are disabled, then D[67:64] are 1s. The input bits D[139:136] are used if DBI_n or DM_n functions are enabled; if DBI_n and DM_n are disabled, then D[139:136] are 1s. When A2 = 1, data bits D[7:4] are used as inputs for D[3:0], D[15:12] are used as inputs for D[11:8], and so forth, for the CRC tree. Input bits D[71:68] are used if DBI_n or DM_n functions are enabled; if DBI_n and DM_n are disabled, then D[71:68] are 1s. The input bits D[143:140] are used if DBI_n or DM_n functions are enabled; if DBI_n and DM_n are disabled, then D[143:140] are 1s. Table 58: CRC Data Mapping for x16 Devices, BC4 Function Transfer 0 1 2 3 4 5 6 7 8 9 A2 = 0 DQ0 D0 D1 D2 D3 1 1 1 1 CRC0 1 DQ1 D8 D9 D10 D11 1 1 1 1 CRC1 1 DQ2 D16 D17 D18 D19 1 1 1 1 CRC2 1 DQ3 D24 D25 D26 D27 1 1 1 1 CRC3 1 DQ4 D32 D33 D34 D35 1 1 1 1 CRC4 1 DQ5 D40 D41 D42 D43 1 1 1 1 CRC5 1 DQ6 D48 D49 D50 D51 1 1 1 1 CRC6 1 DQ7 D56 D57 D58 D59 1 1 1 1 CRC7 1 LDM_n/LDBI_n D64 D65 D66 D67 1 1 1111 DQ8 D72 D73 D74 D75 1 1 1 1 CRC8 1 DQ9 D80 D81 D82 D83 1 1 1 1 CRC9 1 DQ10 D88 D89 D90 D91 1 1 1 1 CRC10 1 DQ11 D96 D97 D98 D99 1 1 1 1 CRC11 1 DQ12 D104 D105 D106 D107 1 1 1 1 CRC12 1 DQ13 D112 D113 D114 D115 1 1 1 1 CRC13 1 DQ14 D120 D121 D122 D123 1 1 1 1 CRC14 1 DQ15 D128 D129 D130 D131 1 1 1 1 CRC15 1 UDM_n/UDBI_n D136 D137 D138 D139 1 1 1111 A2 = 1 DQ0 D4 D5 D6 D7 1 1 1 1 CRC0 1 DQ1 D12 D13 D14 D15 1 1 1 1 CRC1 1 DQ2 D20 D21 D22 D23 1 1 1 1 CRC2 1 DQ3 D28 D29 D30 D31 1 1 1 1 CRC3 1 DQ4 D36 D37 D38 D39 1 1 1 1 CRC4 1 DQ5 D44 D45 D46 D47 1 1 1 1 CRC5 1 DQ6 D52 D53 D54 D55 1 1 1 1 CRC6 1 DQ7 D60 D61 D62 D63 1 1 1 1 CRC7 1 LDM_n/LDBI_n D68 D69 D70 D71 1 1 1111 16Gb: x4, x8, x16 DDR4 SDRAM CRC Write Data Feature CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 172 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Table 58: CRC Data Mapping for x16 Devices, BC4 (Continued) Function Transfer 0 1 2 3 4 5 6 7 8 9 DQ8 D76 D77 D78 D79 1 1 1 1 CRC8 1 DQ9 D84 D85 D86 D87 1 1 1 1 CRC9 1 DQ10 D92 D93 D94 D95 1 1 1 1 CRC10 1 DQ11 D100 D101 D102 D103 1 1 1 1 CRC11 1 DQ12 D108 D109 D110 D111 1 1 1 1 CRC12 1 DQ13 D116 D117 D118 D119 1 1 1 1 CRC13 1 DQ14 D124 D125 D126 D127 1 1 1 1 CRC14 1 DQ15 D132 D133 D134 D135 1 1 1 1 CRC15 1 UDM_n/UDBI_n D140 D141 D142 D143 1 1 1111 CRC Equations for x8 Device in BC4 Mode with A2 = 0 and A2 = 1 The following example is of a CRC tree when x8 is used in BC4 mode (x4 and x16 CRC trees have similar differences). CRC[0], A2=0 = CRC[0], A2=1 = CRC[1], A2=0 = CRC[1], A2=1 = CRC[2], A2=0 = CRC[2], A2=1 = CRC[3], A2=0 = CRC[3], A2=1 = 16Gb: x4, x8, x16 DDR4 SDRAM CRC Write Data Feature CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 173 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

CRC[4], A2=0 = CRC[4], A2=1 = CRC[5], A2=0 = CRC[5], A2=1 = CRC[6], A2=0 = CRC[6], A2=1 = CRC[7], A2=0 = CRC[7], A2=1 = CRC Error Handling The CRC error mechanism shares the same ALERT_n signal as CA parity for reporting write errors to the DRAM. The controller has two ways to distinguish between CRC er- rors and CA parity errors: 1) Read DRAM mode/MPR registers, and 2) Measure time ALERT_n is LOW . To speed up recovery for CRC errors, CRC errors are only sent back as a "short" pulse; the maximum pulse width is roughly ten clocks (unlike CA parity where ALERT_n is LOW longer than 45 clocks). The ALERT_n LOW could be longer than the maximum limit at the controller if there are multiple CRC errors as the ALERT_n signals are connected by a daisy chain bus. The latency to ALERT_n signal is defined as tCRC_ALERT in the following figure. The DRAM will set the error status bit located at MR5[3] to a 1 upon detecting a CRC error, which will subsequently set the CRC error status flag in the MPR error log HIGH (MPR Page1, MPR3[7]). The CRC error status bit (and CRC error status flag) remains set at 1 until the DRAM controller clears the CRC error status bit using an MRS command to set MR5[3] to a 0. The DRAM controller, upon seeing an error as a pulse width, will retry the write transactions. The controller should consider the worst-case delay for ALERT_n (during initialization) and backup the transactions accordingly. The DRAM controller may also be made more intelligent and correlate the write CRC error to a spe- cific rank or a transaction. 16Gb: x4, x8, x16 DDR4 SDRAM CRC Write Data Feature CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 174 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Figure 105: CRC Error Reporting Dx T0 T1 T2 T3 T4 T5 T6 Ta0 Ta1 Ta2 Ta3 Tb0 CK_t CK_c DQIN Dx+1 Dx+2 Dx+3 Dx+4 Dx+5 Dx+6 Dx+7 CRCy 1 ALERT_n CRC ALERT_PW (MIN) Tb1 tCRC_ALERT CRC ALERT_PW (MAX) Don’t CareTransition Data Notes: 1. D[71:1] CRC computed by DRAM did not match CRC[7:0] at T5 and started error generat- ing process at T6. 2. CRC ALERT_PW is specified from the point where the DRAM starts to drive the signal LOW to the point where the DRAM driver releases and the controller starts to pull the signal up. 3. Timing diagram applies to x4, x8, and x16 devices. 16Gb: x4, x8, x16 DDR4 SDRAM CRC Write Data Feature CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 175 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

CRC Write Data Flow Diagram Figure 106: CA Parity Flow Diagram Capture data Transfer Data Internally Transfer data internally Yes DRAM write process start MR2 12 enable CRC MR5 3 set CRC error clear to 0 MR5 10 enable/disable DM MR3[10:9] WCL if DM enabled No No Yes Yes No ALERT_n LOW 6 to 10 CKs ALERT_n HIGH Set error status PAGE1 MPR3[7] 1 Set error flag MR5[A3] 1 Transfer data internally Yes No Yes No CRC enabled CA error Persistent mode enabled MR5[A3] and PAGE1 MPR3[7] remain set to 1 No Yes DRAM CRC same as controller CRC DRAM CRC same as controller CRC MR5[3] = 0 at WRITE WRITE burst completed WRITE burst completed WRITE burst completed WRITE burst completed WRITE burst completed Bad data written MR5 3 reset to 0 if desired ALERT_n LOW 6 to 10 CKs ALERT_n HIGH Set error status PAGE1 MPR3[7] 1 Set error flag MR5[A3] 1 Yes No MR5[A3] and PAGE1 MPR3[7] remain set to 1 MR5[3] = 0 at WRITE WRITE burst rejected Bad data not written MR5 3 reset to 0 if desired 16Gb: x4, x8, x16 DDR4 SDRAM CRC Write Data Feature CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 176 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

The DATA BUS INVERSION (DBI) function is supported only for x8 and x16 configura- tions (it is not supported on x4 devices). DBI opportunistically inverts data bits, and in conjunction with the DBI_n I/O, less than half of the DQs will switch LOW for a given DQS strobe edge. The DBI function shares a common pin with the DATA MASK (DM) and TDQS functions. The DBI function applies to either or both READ and WRITE oper- ations: Write DBI cannot be enabled at the same time the DM function is enabled, and DBI is not allowed during MPR READ operation. Valid configurations for TDQS, DM, and DBI functions are shown below. Table 59: DBI vs. DM vs. TDQS Function Matrix Read DBI Write DBI Data Mask (DM) TDQS (x8 only) Enabled (or Disabled) MR5[12]=1 (or MR5[12] = 0) Disabled MR5[11] = 0 Disabled MR5[10] = 0 Disabled MR1[11] = 0 Enabled MR5[11] = 1 Disabled MR5[10] = 0 Disabled MR1[11] = 0 Disabled MR5[11] = 0 Enabled MR5[10] = 1 Disabled MR1[11] = 0 Disabled MR5[12] = 0 Disabled MR5[11] = 0 Disabled MR5[10] = 0 Enabled MR1[11] = 1 DBI During a WRITE Operation If DBI_n is sampled LOW on a given byte lane during a WRITE operation, the DRAM in- verts write data received on the DQ inputs prior to writing the internal memory array. If DBI_n is sampled HIGH on a given byte lane, the DRAM leaves the data received on the DQ inputs noninverted. The write DQ frame format is shown below for x8 and x16 con- figurations (the x4 configuration does not support the DBI function). Table 60: DBI Write, DQ Frame Format (x8) Function Transfer 0 1 2 3 4 5 6 7 DQ[7:0] Byte 0 Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 Byte 6 Byte 7 DM_n or DBI_n DM0 or DBI0 DM1 or DBI1 DM2 or DBI2 DM3 or DBI3 DM4 or DBI4 DM5 or DBI5 DM6 or DBI6 DM7 or DBI7 Table 61: DBI Write, DQ Frame Format (x16) Function Transfer, Lower (L) and Upper(U) 0 1 2 3 4 5 6 7 DQ[7:0] LByte 0 LByte 1 LByte 2 LByte 3 LByte 4 LByte 5 LByte 6 LByte 7 LDM_n or LDBI_n LDM0 or LDBI0 LDM1 or LDBI1 LDM2 or LDBI2 LDM3 or LDBI3 LDM4 or LDBI4 LDM5 or LDBI5 LDM6 or LDBI6 LDM7 or LDBI7 DQ[15:8] UByte 0 UByte 1 UByte 2 UByte 3 UByte 4 UByte 5 UByte 6 UByte 7 16Gb: x4, x8, x16 DDR4 SDRAM Data Bus Inversion CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 177 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Table 61: DBI Write, DQ Frame Format (x16) (Continued) Function Transfer, Lower (L) and Upper(U) 0 1 2 3 4 5 6 7 UDM_n or UDBI_n UDM0 or UDBI0 UDM1 or UDBI1 UDM2 or UDBI2 UDM3 or UDBI3 UDM4 or UDBI4 UDM5 or UDBI5 UDM6 or UDBI6 UDM7 or UDBI7 DBI During a READ Operation If the number of 0 data bits within a given byte lane is greater than four during a READ operation, the DRAM inverts read data on its DQ outputs and drives the DBI_n pin LOW; otherwise, the DRAM does not invert the read data and drives the DBI_n pin HIGH. The read DQ frame format is shown below for x8 and x16 configurations (the x4 configuration does not support the DBI function). Table 62: DBI Read, DQ Frame Format (x8) Function Transfer Byte 0 1 2 3 4 5 6 7 DQ[7:0] Byte 0 Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 Byte 6 Byte 7 DBI_n DBI0 DBI1 DBI2 DBI3 DBI4 DBI5 DBI6 DBI7 Table 63: DBI Read, DQ Frame Format (x16) Function Transfer Byte, Lower (L) and Upper(U) 0 1 2 3 4 5 6 7 DQ[7:0] LByte 0 LByte 1 LByte 2 LByte 3 LByte 4 LByte 5 LByte 6 LByte 7 LDBI_n LDBI0 LDBI1 LDBI2 LDBI3 LDBI4 LDBI5 LDBI6 LDBI7 DQ[15:8] UByte 0 UByte 1 UByte 2 UByte 3 UByte 4 UByte 5 UByte 6 UByte 7 UDBI_n UDBI0 UDBI1 UDBI2 UDBI3 UDBI4 UDBI5 UDBI6 UDBI7 16Gb: x4, x8, x16 DDR4 SDRAM Data Bus Inversion CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 178 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

The DATA MASK (DM) function, also described as PARTIAL WRITE, is supported only for x8 and x16 configurations (it is not supported on x4 devices). The DM function shares a common pin with the DBI_n and TDQS functions. The DM function applies only to WRITE operations and cannot be enabled at the same time the WRITE DBI function is enabled. The valid configurations for the TDQS, DM, and DBI functions are shown here. Table 64: DM vs. TDQS vs. DBI Function Matrix Data Mask (DM) TDQS (x8 only) Write DBI Read DBI Enabled MR5[10] = 1 Disabled MR1[11] = 0 Disabled MR5[11] = 0 Enabled or Disabled MR5[12] = 1 or MR5[12] = 0 Disabled MR5[10] = 0 Enabled MR1[11] = 1 Disabled MR5[11] = 0 Disabled MR5[12] = 0 Disabled MR1[11] = 0 Enabled MR5[11] = 1 Enabled or Disabled MR5[12] = 1 or MR5[12] = 0 Disabled MR1[11] = 0 Disabled MR5[11] = 0 Enabled (or Disabled) MR5[12] = 1 (or MR5[12] = 0) When enabled, the DM function applies during a WRITE operation. If DM_n is sampled LOW on a given byte lane, the DRAM masks the write data received on the DQ inputs. If DM_n is sampled HIGH on a given byte lane, the DRAM does not mask the data and writes this data into the DRAM core. The DQ frame format for x8 and x16 configurations is shown below. If both CRC write and DM are enabled (via MRS), the CRC will be checked and valid prior to the DRAM writing data into the DRAM core. If a CRC error occurs while the DM feature is enabled, CRC write persistent mode will be enabled and data will not be written into the DRAM core. In the case of CRC write enabled and DM disabled (via MRS), that is, CRC write nonpersistent mode, data is written to the DRAM core even if a CRC error occurs. Table 65: Data Mask, DQ Frame Format (x8) Function Transfer 0 1 2 3 4 5 6 7 DQ[7:0] Byte 0 Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 Byte 6 Byte 7 DM_n or DBI_n DM0 or DBI0 DM1 or DBI1 DM2 or DBI2 DM3 or DBI3 DM4 or DBI4 DM5 or DBI5 DM6 or DBI6 DM7 or DBI7 Table 66: Data Mask, DQ Frame Format (x16) Function Transfer, Lower (L) and Upper (U) 0 1 2 3 4 5 6 7 DQ[7:0] LByte 0 LByte 1 LByte 2 LByte 3 LByte 4 LByte 5 LByte 6 LByte 7 16Gb: x4, x8, x16 DDR4 SDRAM Data Mask CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 179 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Table 66: Data Mask, DQ Frame Format (x16) (Continued) Function Transfer, Lower (L) and Upper (U) 0 1 2 3 4 5 6 7 LDM_n or LDBI_n LDM0 or LDBI0 LDM1 or LDBI1 LDM2 or LDBI2 LDM3 or LDBI3 LDM4 or LDBI4 LDM5 or LDBI5 LDM6 or LDBI6 LDM7 or LDBI7 DQ[15:8] UByte 0 UByte 1 UByte 2 UByte 3 UByte 4 UByte 5 UByte 6 UByte 7 UDM_n or UDBI_n UDM0 or UDBI0 UDM1 or UDBI1 UDM2 or UDBI2 UDM3 or UDBI3 UDM4 or UDBI4 UDM5 or UDBI5 UDM6 or UDBI6 UDM7 or UDBI7 16Gb: x4, x8, x16 DDR4 SDRAM Data Mask CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 180 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Programmable Preamble Modes and DQS Postambles The device supports programmable WRITE and READ preamble modes, either the nor- mal 1tCK preamble mode or special 2tCK preamble mode. The 2tCK preamble mode places special timing constraints on many operational features as well as being suppor- ted for data rates of DDR4-2400 and faster. The WRITE preamble 1 tCK or 2tCK mode can be selected independently from READ preamble 1tCK or 2tCK mode. READ preamble training is also supported; this mode can be used by the DRAM con- troller to train or "read level" the DQS receivers. There are tCCD restrictions under some circumstances:

• When 2 tCK READ preamble mode is enabled, a tCCD_S or tCCD_L of 5 clocks is not allowed.
• When 2 tCK WRITE preamble mode is enabled and write CRC is not enabled, a tCCD_S or tCCD_L of 5 clocks is not allowed.
• When 2 tCK WRITE preamble mode is enabled and write CRC is enabled, a tCCD_S or tCCD_L of 6 clocks is not allowed. WRITE Preamble Mode MR4[12] = 0 selects 1tCK WRITE preamble mode while MR4[12] = 1 selects 2tCK WRITE preamble mode. Examples are shown in the figures below. Figure 107: 1tCK vs. 2tCK WRITE Preamble Mode DQ CK_c CK_t Preamble 2tCK Mode D0 D1 D2 D3 D4 D5 D6 D7 WL WR DQ DQS_t, DQS_c DQS_t, DQS_c CK_c CK_t Preamble 1tCK Mode D0 D1 D2 D3 D4 D5 D6 D7 WR WL 16Gb: x4, x8, x16 DDR4 SDRAM Programmable Preamble Modes and DQS Postambles CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 181 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

CWL has special considerations when in the 2tCK WRITE preamble mode. The CWL val- ue selected in MR2[5:3], as seen in table below, requires at least one additional clock when the primary CWL value and 2 tCK WRITE preamble mode are used; no additional clocks are required when the alternate CWL value and 2tCK WRITE preamble mode are used. Table 67: CWL Selection CWL - Primary Choice CWL - Alternate Choice Speed Bin 1tCK Preamble 2tCK Preamble 1tCK Preamble 2tCK Preamble DDR4-1600 9 N/A 11 N/A DDR4-1866 10 N/A 12 N/A DDR4-2133 11 N/A 14 N/A DDR4-2400 12 14 16 16 DDR4-2666 14 16 18 18 DDR4-2933 16 18 20 20 DDR4-3200 16 18 20 20 Note: 1. CWL programmable requirement for MR2[5:3]. When operating in 2tCK WRITE preamble mode, tWTR (command based) and tWR (MR0[11:9]) must be programmed to a value 1 clock greater than the tWTR and tWR set- ting normally required for the applicable speed bin to be JEDEC compliant; however, Micron's DDR4 DRAMs do not require these additional tWTR and tWR clocks. The CAS_n-to-CAS_n command delay to either a different bank group (tCCD_S) or the same bank group (tCCD_L) have minimum timing requirements that must be satisfied be- tween WRITE commands and are stated in the Timing Parameters by Speed Bin tables. Figure 108: 1tCK vs. 2tCK WRITE Preamble Mode, tCCD = 4 DQ DQS_t, DQS_c tCCD = 4 WL Preamble 1tCK Mode D0 D1 WRITE WRITE D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 CK_t CK_c CMD DQ DQS_t, DQS_c tCCD = 4 WL Preamble 2tCK Mode D0 D1 WRITE WRITE D2 D3 D4 D5 D6 D7 D0 D1 CK_t CK_c CMD 16Gb: x4, x8, x16 DDR4 SDRAM Programmable Preamble Modes and DQS Postambles CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 182 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

MR4[11] = 0 selects 1tCK READ preamble mode and MR4[11] = 1 selects 2tCK READ pre- amble mode. Examples are shown in the following figure. Figure 111: 1tCK vs. 2tCK READ Preamble Mode DQ DQS_t, DQS_c DQS_t, DQS_c CK_c CK_t Preamble 2tCK Mode D0 D1 D2 D3 D4 D5 D6 D7 CL RD DQ CK_c CK_t Preamble 1tCK Mode D0 D1 D2 D3 D4 D5 D6 D7 RD CL READ Preamble Training DDR4 supports READ preamble training via MPR reads; that is, READ preamble train- ing is allowed only when the DRAM is in the MPR access mode. The READ preamble training mode can be used by the DRAM controller to train or "read level" its DQS re- ceivers. READ preamble training is entered via an MRS command (MR4[10] = 1 is ena- bled and MR4[10] = 0 is disabled). After the MRS command is issued to enable READ preamble training, the DRAM DQS signals are driven to a valid level by the time tSDO is satisfied. During this time, the data bus DQ signals are held quiet, that is, driven HIGH. The DQS_t signal remains driven LOW and the DQS_c signal remains driven HIGH until an MPR Page0 READ command is issued (MPR0 through MPR3 determine which pat- tern is used), and when CAS latency (CL) has expired, the DQS signals will toggle nor- mally depending on the burst length setting. To exit READ preamble training mode, an MRS command must be issued, MR4[10] = 0. 16Gb: x4, x8, x16 DDR4 SDRAM Programmable Preamble Modes and DQS Postambles CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 184 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Figure 114: READ Postamble DQ CK_c CK_t 2tCK Mode D0 D1 D2 D3 D4 D5 D6 D7 CL RD DQ DQS_t, DQS_c DQS_t, DQS_c CK_c CK_t 1tCK Mode D0 D1 D2 D3 D4 D5 D6 D7 RD CL Postamble Postamble 16Gb: x4, x8, x16 DDR4 SDRAM Programmable Preamble Modes and DQS Postambles CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 186 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

DDR4 supports bank grouping: x4/x8 DRAMs have four bank groups (BG[1:0]), and each bank group is comprised of four subbanks (BA[1:0]); x16 DRAMs have two bank groups (BG[0]), and each bank group is comprised of four subbanks. Bank accesses to different banks' groups require less time delay between accesses than bank accesses to within the same bank's group. Bank accesses to different bank groups require tCCD_S (or short) delay between commands while bank accesses within the same bank group require tCCD_L (or long) delay between commands. Figure 115: Bank Group x4/x8 Block Diagram Local I/O gating Global I/O gating Bank 0 Memory Array Sense amplifiers Bank 1 Bank 2 Bank 3 Local I/O gating Bank 0 Memory Array Sense amplifiers Bank 1 Bank 2 Bank 3 Local I/O gating Bank 0 Memory Array Sense amplifiers Bank 1 Bank 2 Bank 3 Local I/O gating Bank 0 Memory Array Sense amplifiers Bank 1 Bank 2 Bank 3 CMD/ADDR registerCMD/ADDR Data I/O Bank Group 0 Bank Group 1 Bank Group 2 Bank Group 3 Notes: 1. Bank accesses to different bank groups require tCCD_S. 2. Bank accesses within the same bank group require tCCD_L. Table 68: DDR4 Bank Group Timing Examples Parameter DDR4-1600 DDR4-2133 DDR4-2400 tCCD_S 4 nCK 4 nCK 4 nCK tCCD_L 4 nCK or 6.25ns 4 nCK or 5.355ns 4 nCK or 5ns tRRD_S (½K) 4 nCK or 5ns 4 nCK or 3.7ns 4 nCK or 3.3ns tRRD_L (½K) 4 nCK or 6ns 4 nCK or 5.3ns 4 nCK or 4.9ns tRRD_S (1K) 4 nCK or 5ns 4 nCK or 3.7ns 4 nCK or 3.3ns tRRD_L (1K) 4 nCK or 6ns 4 nCK or 5.3ns 4 nCK or 4.9ns tRRD_S (2K) 4 nCK or 6ns 4 nCK or 5.3ns 4 nCK or 5.3ns tRRD_L (2K) 4 nCK or 7.5ns 4 nCK or 6.4ns 4 nCK or 6.4ns 16Gb: x4, x8, x16 DDR4 SDRAM Bank Access Operation CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 187 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Figure 120: tWTR_L Timing (WRITE-to-READ, Same Bank Group, CRC and DM Disabled) T0 Tb0T1 T2 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 Ta7 Valid Valid Valid Valid Valid READ ValidCommand ValidWRITE Valid Valid Valid Valid BGaBank Group BGa Bank cBank Col n Bank c Col nAddress CK_t CK_c Tb1 Don’t CareTransitioning DataTime Break DQ WL tWPRE tWPST RL tWTR_L DIn + 3 DIn + 4 DIn + 5 DIn + 6 DIn + 7DIn + 2DIn + 1DIn DQS, DQS_c Note: 1. tWTR_L: delay from start of internal write transaction to internal READ command to the same bank group. 16Gb: x4, x8, x16 DDR4 SDRAM Bank Access Operation CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 190 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

The read timings shown below are applicable in normal operation mode, that is, when the DLL is enabled and locked. Note: tDQSQ = both rising/falling edges of DQS; no tAC defined. Rising data strobe edge parameters: tDQSCK (MIN)/(MAX) describes the allowed range for a rising data strobe edge rela- tive to CK.

• tDQSCK is the actual position of a rising strobe edge relative to CK.
• tQSH describes the DQS differential output HIGH time.
• tDQSQ describes the latest valid transition of the associated DQ pins.
• tQH describes the earliest invalid transition of the associated DQ pins. Falling data strobe edge parameters: tQSL describes the DQS differential output LOW time.
• tDQSQ describes the latest valid transition of the associated DQ pins.
• tQH describes the earliest invalid transition of the associated DQ pins. 16Gb: x4, x8, x16 DDR4 SDRAM READ Operation CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 191 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Figure 121: Read Timing Definition CK_t CK_c DQS_c DQS_t tDQSCK tDQSCK tDQSQtDQSQ Rising strobe region window Rising strobe region window tQSH/DQS_c tQSH/DQS_t tQH tQH tDQSCK (MAX)tDQSCK (MIN) tDQSCK (MAX)tDQSCK (MIN) Associated DQ Pins tDQSCKi tDQSCK MIN tDQSCKi Rising strobe region window Rising strobe region window tDQSCKi tDQSCK center tDQSCKi Rising strobe region window Rising strobe region window tDQSCKi tDQSCK MAX tDQSCKi Table 69: Read-to-Write and Write-to-Read Command Intervals Access Type Bank Group Timing Parameters Note Read-to-Write, mini- mum Same CL - CWL + RBL/2 + 1 tCK + tWPRE 1, 2 Different CL - CWL + RBL/2 + 1 tCK + tWPRE 1, 2 Write-to-Read, mini- mum Same CWL + WBL/2 + tWTR_L 1, 3 Different CWL + WBL/2 + tWTR_S 1, 3 Notes: 1. These timings require extended calibrations times tZQinit and tZQCS. 2. RBL: READ burst length associated with READ command, RBL = 8 for fixed 8 and on-the- fly mode 8 and RBL = 4 for fixed BC4 and on-the-fly mode BC4. 3. WBL: WRITE burst length associated with WRITE command, WBL = 8 for fixed 8 and on- the-fly mode 8 or BC4 and WBL = 4 for fixed BC4 only. Read Timing – Clock-to-Data Strobe Relationship The clock-to-data strobe relationship shown below is applicable in normal operation mode, that is, when the DLL is enabled and locked. 16Gb: x4, x8, x16 DDR4 SDRAM READ Operation CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 192 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Rising data strobe edge parameters:

• tDQSCK (MIN)/(MAX) describes the allowed range for a rising data strobe edge rela- tive to CK.
• tDQSCK is the actual position of a rising strobe edge relative to CK.
• tQSH describes the data strobe high pulse width.
• tHZ(DQS) DQS strobe going to high, nondrive level (shown in the postamble section of the figure below). Falling data strobe edge parameters: tQSL describes the data strobe low pulse width.
• tLZ(DQS) DQS strobe going to low, initial drive level (shown in the preamble section of the figure below). Figure 122: Clock-to-Data Strobe Relationship RL measured to this point DQS_t, DQS_c Early Strobe CK_t CK_c tLZ(DQS) MIN tLZ(DQS) MAX DQS_t, DQS_c Late Strobe tDQSCK (MIN) tDQSCK (MAX) tDQSCK (MAX) tDQSCK (MAX) tDQSCK (MAX) tDQSCK (MIN) tDQSCK (MIN) tDQSCK (MIN) tHZ(DQS) MIN tHZ(DQS) MAX tRPRE tRPRE tQSH tQSL tQSH tQSL tQSH tQSL tQSH tQSL tQSH tQSL Bit 0 Bit 1 Bit 2 Bit 7 Bit 6Bit 4Bit 3 Bit 5 Bit 0 Bit 1 Bit 2 Bit 7 Bit 6Bit 4Bit 3 Bit 5 tRPST tRPST Notes: 1. Within a burst, the rising strobe edge will vary within tDQSCKi while at the same volt- age and temperature. However, when the device, voltage, and temperature variations are incorporated, the rising strobe edge variance window can shift between tDQSCK (MIN) and tDQSCK (MAX). A timing of this window's right edge (latest) from rising CK_t, CK_c is limited by a devi- ce's actual tDQSCK (MAX). A timing of this window's left inside edge (earliest) from ris- ing CK_t, CK_c is limited by tDQSCK (MIN). 2. Notwithstanding Note 1, a rising strobe edge with tDQSCK (MAX) at T(n) can not be im- mediately followed by a rising strobe edge with tDQSCK (MIN) at T(n + 1) because other timing relationships (tQSH, tQSL) exist: if tDQSCK(n + 1) < 0: tDQSCK(n) < 1.0 tCK - (tQSH (MIN) + tQSL (MIN)) - | tDQSCK(n + 1) |. 3. The DQS_t, DQS_c differential output HIGH time is defined by tQSH, and the DQS_t, DQS_c differential output LOW time is defined by tQSL. 4. tLZ(DQS) MIN and tHZ(DQS) MIN are not tied to tDQSCK (MIN) (early strobe case), and tLZ(DQS) MAX and tHZ(DQS) MAX are not tied to tDQSCK (MAX) (late strobe case). 5. The minimum pulse width of READ preamble is defined by tRPRE (MIN). 6. The maximum READ postamble is bound by tDQSCK (MIN) plus tQSH (MIN) on the left side and tHZDSQ (MAX) on the right side. 7. The minimum pulse width of READ postamble is defined by tRPST (MIN). 16Gb: x4, x8, x16 DDR4 SDRAM READ Operation CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 193 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

1. The maximum READ preamble is bound by tLZDQS (MIN) on the left side and tDQSCK (MAX) on the right side. Read Timing – Data Strobe-to-Data Relationship The data strobe-to-data relationship is shown below and is applied when the DLL is en- abled and locked. Note: tDQSQ: both rising/falling edges of DQS; no tAC defined. Rising data strobe edge parameters: tDQSQ describes the latest valid transition of the associated DQ pins.

• tQH describes the earliest invalid transition of the associated DQ pins. Falling data strobe edge parameters:
• tDQSQ describes the latest valid transition of the associated DQ pins.
• tQH describes the earliest invalid transition of the associated DQ pins. Data valid window parameters: tDVWd is the Data Valid Window per device per UI and is derived from [tQH - tDQSQ] of each UI on a given DRAM
• tDVWp is the Data Valid Window per pin per UI and is derived [tQH - tDQSQ] of each UI on a pin of a given DRAM Figure 123: Data Strobe-to-Data Relationship CK_t CK_c Command3 READ Bank, Col n DES DES DES DES DES DES DES DES DES DES Address4 DQS_t, DQS_c DQ2 (Last data ) DQ2 (First data no longer) All DQ collectively RL = AL + CL tDQSQ (MAX) tRPRE (1nCK) tRPST tQH tQH tDVWp tDVWp tDVWd tDVWd T0 T1 T2 T9 T10 T11 T12 T13 Don’t Care T14 T15 T16 DOUT n + 2 DOUT n + 1 DOUT n + 4 DOUT n + 5 DOUT n + 6 DOUT n + 7 DOUT n + 2 DOUT n + 1 DOUT n + 3 DOUT n + 4 DOUT n + 5 DOUT n + 6 DOUT n + 7 tDQSQ (MAX) DOUT n DOUT n + 2 DOUT n + 1 DOUT n + 3 DOUT n + 4 DOUT n + 5 DOUT n + 6 DOUT n + 7 DOUT n DOUT n + 3 DOUT n Notes: 1. BL = 8, RL = 11 (AL = 0, CL = 1) , Premable = 1 tCK. 2. D OUTn = data-out from column n. 3. DES commands are shown for ease of illustration; other commands may be valid at these times. 4. BL8 setting activated by either MR0[A1:0 = 00] or MR0[A1:0 = 01] and A12 = 1 during READ commands at T0. 5. Output timings are referenced to V DDQ, and DLL on for locking. 6. tDQSQ defines the skew between DQS to data and does not define DQS to clock. 16Gb: x4, x8, x16 DDR4 SDRAM READ Operation CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 194 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

1. Early data transitions may not always happen at the same DQ. Data transitions of a DQ can vary (either early or late) within a burst. tLZ(DQS), tLZ(DQ), tHZ(DQS), and tHZ(DQ) Calculations tHZ and tLZ transitions occur in the same time window as valid data transitions. These parameters are referenced to a specific voltage level that specifies when the device out- put is no longer driving tHZ(DQS) and tHZ(DQ), or begins driving tLZ(DQS) and tLZ(DQ). The figure below shows a method to calculate the point when the device is no longer driving tHZ(DQS) and tHZ(DQ), or begins driving tLZ(DQS) and tLZ(DQ), by measuring the signal at two different voltages. The actual voltage measurement points are not critical as long as the calculation is consistent. tLZ(DQS), tLZ(DQ), tHZ(DQS), and tHZ(DQ) are defined as singled-ended parameters. Figure 124: tLZ and tHZ Method for Calculating Transitions and Endpoints CK_t CK_c tLZ tHZ DQ 0.7 × VDDQ 0.4 × VDDQ DQ Begin point: Extrapolated point at VDDQ VDDQ VSW2 Begin point: Extrapolated point (low level) VDDQ tLZ(DQ): CK_t, CK_c rising crossing at RL tHZ(DQ) with BL8: CK_t, CK_c rising crossing at RL + 4CK tHZ(DQ) with BC4: CK_t, CK_c rising crossing at RL + 2CK VSW1 VSW2 VSW1 0.7 × VDDQ 0.4 × VDDQ Notes: 1. V sw1 = (0.70 - 0.04) × VDDQ for both tLZ and tHZ. 2. V sw2 = (0.70 + 0.04) × VDDQ for both tLZ and tHZ. 3. Extrapolated point (low level) = V DDQ/(50 + 34) × 34 = 0.4 × VDDQ Driver impedance = RZQ/7 = 34˖ VTT test load = 50˖ to VDDQ. 16Gb: x4, x8, x16 DDR4 SDRAM READ Operation CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 195 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Figure 125: tRPRE Method for Calculating Transitions and Endpoints DQS_t CK_t CK_c Resulting differential signal relevant for tRPRE specification Single-ended signal provided as background information DQS_c DQS_t, DQS_c DQS_t DQS_c DQS_t DQS_c VSW1 VSW2 0.7 × VDDQ 0.7 × VDDQ 0.4 × VDDQ 0.4 × VDDQ VDDQ VDDQ VDDQ 0.7 × VDDQ 0.3 × VDDQ 0.6 × VDDQ 0.4 × VDDQ VDD /2 tRPRE begins (t1) tRPRE ends (t2) Notes: 1. V sw1 = (0.3 - 0.04) × VDDQ. 3. DQS_t and DQS_c low level = V DDQ/(50 + 34) × 34 = 0.4 × VDDQ Driver impedance = RZQ/7 = 34˖ VTT test load = 50˖ to VDDQ. 16Gb: x4, x8, x16 DDR4 SDRAM READ Operation CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 196 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Figure 126: tRPST Method for Calculating Transitions and Endpoints DQS_t, DQS_c VSW1 VSW2 DQS_t tRPST ends (t2) CK_t CK_c Resulting differential signal relevant for tRPST specification Single-ended signal provided as background information DQS_c DQS_t DQS_c tRPST begins (t1) 0.7 × VDDQ 0.7 × VDDQ 0.4 × VDDQ 0.4 × VDDQ VDDQ VDDQ VDDQ 0.7 × VDDQ –0.3 × VDDQ –0.6 × VDDQ VDD /2 Notes: 1. V sw1 = (–0.3 - 0.04) × VDDQ. 3. DQS_t and DQS_c low level = V DDQ/(50 + 34) × 34 = 0.4 × VDDQ Driver impedance = RZQ/7 = 34˖ VTT test load = 50˖ to VDDQ. 16Gb: x4, x8, x16 DDR4 SDRAM READ Operation CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 197 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

DDR4 READ commands support bursts of BL8 (fixed), BC4 (fixed), and BL8/BC4 on- the-fly (OTF); OTF uses address A12 to control OTF when OTF is enabled:

• A12 = 0, BC4 (BC4 = burst chop)
• A12 = 1, BL8 READ commands can issue precharge automatically with a READ with auto precharge command (RDA), and is enabled by A10 HIGH:
• READ command with A10 = 0 (RD) performs standard read, bank remains active after READ burst.
• READ command with A10 = 1 (RDA) performs read with auto precharge, bank goes in to precharge after READ burst. Figure 127: READ Burst Operation, RL = 11 (AL = 0, CL = 11, BL8) CL = 11 RL = AL + CL tRPRE T1 T2 Ta1 Ta0 Ta2 Ta3 Ta4 Ta5 Ta6 Ta7 Ta8 Ta9 DES DES DES DES DES DESCommand DESREAD DES DES DES DES DES DQ CK_t CK_c Don’t CareTransitioning DataTime Break DOn + 3 DOn + 4 DOn + 5 DOn + 6 DOn + 7DOn + 2DOn + 1DOn Bank Group Address DQS_t DQS_c BGa Address Bankcol n tRPST Notes: 1. BL8, RL = 0, AL = 0, CL = 11, Preamble = 1 tCK. 2. DO n = data-out from column n. 3. DES commands are shown for ease of illustration; other commands may be valid at these times. 4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during READ command at T0. 5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable. 16Gb: x4, x8, x16 DDR4 SDRAM READ Operation CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 198 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Figure 128: READ Burst Operation, RL = 21 (AL = 10, CL = 11, BL8) CL = 11AL = 10 RL = AL + CL tRPRE T1 Ta0 Ta1 Ta2 Ta3 Tb0 Tb1 Tb2 Tb3 Tb4 Tb5 Tb6 DES DES DES DES DESCommand DESREAD DES DES DES DES DQ CK_t CK_c Don’t CareTransitioning DataTime Break DOn + 3 DOn + 4 DOn + 5 DOn + 6 DOn + 7DOn + 2DOn + 1DOn Bank Group Address DQS_t DQS_c BGa Address Bankcol n tRPST DESDES Notes: 1. BL8, RL = 21, AL = (CL - 1), CL = 11, Preamble = 1 tCK. 2. DO n = data-out from column n. 3. DES commands are shown for ease of illustration; other commands may be valid at these times. 4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during READ command at T0. 5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable. 16Gb: x4, x8, x16 DDR4 SDRAM READ Operation CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 199 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

1. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during READ commands at T0 and WRITE commands at T8. 5. When operating in 2 tCK WRITE preamble mode, CWL may need to be programmed to a value at least 1 clock greater than the lowest CWL setting. 6. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable, Write CRC = Disable. Figure 141: READ (BC4) OTF to WRITE (BC4) OTF with 1tCK Preamble in Same or Different Bank Group READ to WRITE command delay = RL +BL/2 - WL + 2 tCK 4 Clocks tRPRE RL = 11 tRPST T1 T5 T6 T7 DES DES DES DES DES DES DESCommand DESREAD DES WRITE DES DES DQ CK_t CK_c DQS_t, DQS_c WL = 9 T20T14T8 T9 T10 T11 T12 T13 T19T15 T16 T17 T18 Don’t CareTransitioning DataTime Break DOn + 1 DOn + 2 DOn + 3 DIb DIb + 1 DIb + 2 DIb + 3DOn DES DES DES DES DES Bank Group Address Address Bank Col n Bank Col b BGa BGa or BGb tWPRE tWPST tWTR tWR Notes: 1. BC = 4, RL = 11 (CL = 11, AL = 0), READ preamble = 1 tCK, WL = 9 (CWL = 9, AL = 0), WRITE preamble = 1tCK. 2. DO n = data-out from column n; DI b = data-in from column b. 3. DES commands are shown for ease of illustration; other commands may be valid at these times. 4. BC4 (OTF) setting activated by MR0[1:0] = 01 and A12 = 0 during READ commands at T0 and WRITE commands at T6. 5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable, Write CRC = Disable. 16Gb: x4, x8, x16 DDR4 SDRAM READ Operation CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 206 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Figure 142: READ (BC4) OTF to WRITE (BC4) OTF with 2tCK Preamble in Same or Different Bank Group READ to WRITE command delay = RL +BL/2 - WL + 3 tCK 4 Clocks tRPRE RL = 11 tRPST T1 T5 T6 T7 DES DES DES DES DES DES DESCommand DESREAD DES WRITE DES DES DQ CK_t CK_c DQS_t, DQS_c WL = 10 T20T14T8 T9 T10 T11 T12 T13 T19T15 T16 T17 T18 Don’t CareTransitioning DataTime Break DOn + 1 DOn + 2 DOn + 3 DIb DIb + 1 DIb + 2 DIb + 3DOn DES DES DES DES DES Bank Group Address Address Bank Col n Bank Col b BGa BGa or BGb tWPRE tWPST tWTR tWR Notes: 1. BC = 4, RL = 11 (CL = 11, AL = 0), READ preamble = 2 tCK, WL = 10 (CWL = 9 + 1 [see Note 5], AL = 0), WRITE preamble = 2tCK. 2. DO n = data-out from column n; DI b = data-in from column b. 3. DES commands are shown for ease of illustration; other commands may be valid at these times. 4. BC4 (OTF) setting activated by MR0[1:0] = 01 and A12 = 0 during READ commands at T0 and WRITE commands at T6. 5. When operating in 2 tCK WRITE preamble mode, CWL may need to be programmed to a value at least 1 clock greater than the lowest CWL setting. 6. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable, Write CRC = Disable. Figure 143: READ (BC4) Fixed to WRITE (BC4) Fixed with 1tCK Preamble in Same or Different Bank Group READ to WRITE command delay = RL +BL/2 - WL + 2 tCK tRPRE RL = 11 tRPST T1 T5 T6 T7 DES DES DES DES DES DES DESCommand DESREAD DES WRITE DES DES DQ CK_t CK_c DQS_t, DQS_c WL = 9 T20T14T8 T9 T10 T11 T12 T13 T19T15 T16 T17 T18 Don’t CareTransitioning DataTime Break DOn + 1 DOn + 2 DOn + 3 DIb DIb + 1 DIb + 2 DIb + 3DOn DES DES DES DES DES Bank Group Address Address Bank Col n Bank Col b BGa or BGb tWPRE tWPST tWTR tWR BGa

2 Clocks

Notes: 1. BC = 4, RL = 11 (CL = 11, AL = 0), READ preamble = 1 tCK, WL = 9 (CWL = 9, AL = 0), WRITE preamble = 1tCK. 2. DO n = data-out from column n; DI b = data-in from column b. 16Gb: x4, x8, x16 DDR4 SDRAM READ Operation CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 207 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

1. DES commands are shown for ease of illustration; other commands may be valid at these times. 4. BC4 (fixed) setting activated by MR0[1:0] = 01. 5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable, Write CRC = Disable. Figure 144: READ (BC4) Fixed to WRITE (BC4) Fixed with 2tCK Preamble in Same or Different Bank Group READ to WRITE command delay = RL +BL/2 - WL + 3 tCK 2 Clocks tRPRE RL = 11 tRPST T1 T5 T6 T7 DES DES DES DES DES DES DESCommand DESREAD DES WRITE DES DES DQ CK_t CK_c DQS_t, DQS_c WL = 10 T20T14T8 T9 T10 T11 T12 T13 T19T15 T16 T17 T18 Don’t CareTransitioning DataTime Break DOn + 1 DOn + 2 DOn + 3 DIb DIb + 1 DIb + 2 DIb + 3DOn DES DES DES DES DES Bank Group Address Address Bank Col n Bank Col b BGa BGa or BGb tWPRE tWPST tWTR tWR Notes: 1. BC = 4, RL = 11 (CL = 11, AL = 0), READ preamble = 2 tCK, WL = 9 (CWL = 9 + 1 [see Note 5], AL = 0), WRITE preamble = 2tCK. 2. DO n = data-out from column n; DI b = data-in from column b. 3. DES commands are shown for ease of illustration; other commands may be valid at these times. 4. BC4 (fixed) setting activated by MR0[1:0] = 10. 5. When operating in 2 tCK WRITE preamble mode, CWL may need to be programmed to a value at least 1 clock greater than the lowest CWL setting. 6. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable, Write CRC = Disable. 16Gb: x4, x8, x16 DDR4 SDRAM READ Operation CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 208 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Figure 145: READ (BC4) to WRITE (BL8) OTF with 1tCK Preamble in Same or Different Bank Group READ to WRITE command delay = RL +BL/2 - WL + 2 tCK tWPRE RL = 11 tWPST DES DES DES DES DES DES DESCommand DESREAD DES WRITE DES DES DQ CK_t CK_c DQS_t, DQS_c WL = 9 T5 T6 T7 T20T14T8 T9 T10 T11 T12 T13 T19T15 T16 T17 T18 Don’t CareTransitioning DataTime Break DOn + 1 DOn + 2 DOn + 3 DIn + 4 DIn + 5 DIn + 6 DIn + 7DIb DIb + 1 DIb + 2 DIb + 3DOn DES DES DES DES DES Bank Group Address Address Bank Col n Bank Col b BGa BGa or BGb tRPRE tRPST tWTR tWR

4 Clocks

Notes: 1. BL = 8, RL = 11 (CL = 11, AL = 0), READ preamble = 1 tCK, WL = 9 (CWL = 9, AL = 0), WRITE preamble = 1tCK. 2. DO n = data-out from column n; DI b = data-in from column b. 3. DES commands are shown for ease of illustration; other commands may be valid at these times. 4. BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during WRITE commands at T0. BL8 setting activated by MR0[1:0] = 01 and A12 = 1 during READ commands at T6. 5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable, Write CRC = Disable. Figure 146: READ (BC4) to WRITE (BL8) OTF with 2tCK Preamble in Same or Different Bank Group READ to WRITE command delay = RL +BL/2 - WL + 3 tCK tWPRE RL = 11 tWPST DES DES DES DES DES DES DESCommand DESREAD DES WRITE DES DES DQ CK_t CK_c DQS_t, DQS_c WL = 10 T5 T6 T7 T20T14T8 T9 T10 T11 T12 T13 T19T15 T16 T17 T18 Don’t CareTransitioning DataTime Break DOn + 1 DOn + 2 DOn + 3 DIn + 4 DIn + 5 DIn + 6 DIn + 7DIb DIb + 1 DIb + 2 DIb + 3DOn DES DES DES DES DES Bank Group Address Address Bank Col n Bank Col b BGa BGa or BGb tRPRE tRPST tWTR tWR Notes: 1. BL = 8, RL = 11 (CL = 11, AL = 0), READ preamble = 2 tCK, WL = 10 (CWL = 9 + 1 [see Note 5], AL = 0), WRITE preamble = 2tCK. 2. DO n = data-out from column n; DI b = data-in from column b. 3. DES commands are shown for ease of illustration; other commands may be valid at these times. 4. BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during WRITE commands at T0. BL8 setting activated by MR0[1:0] = 01 and A12 = 1 during READ commands at T6. 16Gb: x4, x8, x16 DDR4 SDRAM READ Operation CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 209 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

1. BL8 setting activated by MR0[1:0] = 01 and A12 = 1 during READ commands at T0. BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during WRITE commands at T8. 5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable, Write CRC = Disable. READ Operation Followed by PRECHARGE Operation The minimum external READ command to PRECHARGE command spacing to the same bank is equal to AL + tRTP with tRTP being the internal READ command to PRECHARGE command delay. Note that the minimum ACT to PRE timing, tRAS, must be satisfied as well. The minimum value for the internal READ command to PRECHARGE command delay is given by tRTP (MIN) = MAX (4 × nCK, 7.5ns). A new bank ACTIVATE command may be issued to the same bank if the following two conditions are satisfied simultane- ously:

• The minimum RAS precharge time ( tRP [MIN]) has been satisfied from the clock at which the precharge begins.
• The minimum RAS cycle time ( tRC [MIN]) from the previous bank activation has been satisfied. Figure 149: READ to PRECHARGE with 1tCK Preamble RL = AL + CL tRTP tRP T1 T2 T3 T6 DES DES DES DES DES DES DESCommand READDES DES DES DES PRE DQ BC4 Opertaion CK_t CK_c DQS_t, DQS_c T20 T21T14T7 T10 T11 T12 T13 T19T15 T16 T17 T18 Don’t CareTransitioning DataTime Break DOn + 1 DOn + 2 DOn + 3DOn DES ACT DES DES DES Bank Group Address BGa BGa or BGb BGa Address Bank a Col n Bank a (or all) Bank a Row b DQ BL8 Opertaion DQS_t, DQS_c DOn + 1 DOn + 2 DOn + 3 DOn + 4 DOn + 5 DOn + 6 DOn + 7DOn Notes: 1. RL = 11 (CL = 11, AL = 0 ), Preamble = 1 tCK, tRTP = 6, tRP = 11. 2. DO n = data-out from column n. 3. DES commands are shown for ease of illustration; other commands may be valid at these times. 4. The example assumes that tRAS (MIN) is satisfied at the PRECHARGE command time (T7) and that tRC (MIN) is satisfied at the next ACTIVATE command time (T18). 5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable. 16Gb: x4, x8, x16 DDR4 SDRAM READ Operation CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 211 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

1. DES commands are shown for ease of illustration; other commands may be valid at these times. 4. The example assumes that tRAS (MIN) is satisfied at the PRECHARGE command time (T16) and that tRC (MIN) is satisfied at the next ACTIVATE command time (T27). 5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable. Figure 152: READ with Auto Precharge and 1tCK Preamble RL = AL + CL tRTP tRP T1 T2 T3 T6 DES DES DES DES DES DES DESCommand RDADES DES DES DES PRE DQ BC4 Opertaion CK_t CK_c DQS_t, DQS_c T20 T21T14T7 T10 T11 T12 T13 T19T15 T16 T17 T18 Don’t CareTransitioning DataTime Break DOn + 1 DOn + 2 DOn + 3DOn DES ACT DES DES DES Bank Group Address BGa BGa Address Bank a Col n Bank a Col n BGa or BGb Bank a Row b DQ BL8 Opertaion DQS_t, DQS_c DOn + 1 DOn + 2 DOn + 3 DOn + 4 DOn + 5 DOn + 6 DOn + 7DOn Notes: 1. RL = 11 (CL = 11, AL = 0 ), Preamble = 1 tCK, tRTP = 6, tRP = 11. 2. DO n = data-out from column n. 3. DES commands are shown for ease of illustration; other commands may be valid at these times. 4. tRTP = 6 setting activated by MR0[A11:9 = 001]. 5. The example assumes that tRC (MIN) is satisfied at the next ACTIVATE command time (T18). 6. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable. 16Gb: x4, x8, x16 DDR4 SDRAM READ Operation CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 213 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

1. DO n (or b) = data-out from column n (or b); DBI n (or b) = data bus inversion from col- umn n (or b). 3. DES commands are shown for ease of illustration; other commands may be valid at these times. 4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during READ commands at T0 and T4. 5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Enable. READ Operation with Command/Address Parity (CA Parity) Figure 155: Consecutive READ (BL8) with 1tCK Preamble and CA Parity in Different Bank Group tCCD_S = 4 tRPRE RL = 15 T1 T2 T3 T4 T7 T8 DES DES DES DES DES DES DESCommand DESREAD DES DES READ DES DQ CK_t CK_c DQS_t, DQS_c RL = 15 T16T13 T14 T15 T21T17 T18 T19 T20 T21 T20 Don’t CareTransitioning DataTime Break DOn + 1 DOn + 2 DOn + 3 DOb + 1 DOb + 2 DOb + 7DOn DES DES DES DES DES Bank Group Address BGa BGb Address Parity Bank Col n Bank Col b tRPST DOn + 4 DOn + 5 DOn + 6 DOn + 7 DOb DOb + 5 DOb + 6DOb + 3 DOb +4 _ Notes: 1. BL = 8, AL = 0, CL = 11, PL = 4, (RL = CL + AL + PL = 15), Preamble = 1 tCK. 2. DO n (or b) = data-out from column n (or b). 3. DES commands are shown for ease of illustration; other commands may be valid at these times. 4. BL8 setting activated by either MR0[A1:A0 = 00] or MR0[A1:A0 = 01] and A12 = 1 during READ commands at T0 and T4. 5. CA parity = Enable, CS to CA latency = Disable, Read DBI = Disable. 16Gb: x4, x8, x16 DDR4 SDRAM READ Operation CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 215 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Figure 156: READ (BL8) to WRITE (BL8) with 1tCK Preamble and CA Parity in Same or Different Bank Group READ to WRITE command delay = RL +BL/2 - WL + 2 tCK 4 Clocks tRPRE RL = 15 tRPST T1 T7 T8 T9 DES DES DES DES DES DES DESCommand DESREAD DES WRITE DES DES DQ CK_t CK_c DQS_t, DQS_c WL = 13 T22T16T14 T15 T21T17 T18 T19 T20 T25 T26 T24T23 Don’t CareTransitioning DataTime Break DOn + 1 DOn + 2 DOn + 3 DOn + 4 DOn + 5 DOn + 6 DOn + 7 DIb DIb + 1 DIb + 2 DIb + 3 DIb + 4 DIb + 5 DIb + 6 DIb + 7DOn DES DES DES DES DES Bank Group Address Address Parity Bank Col n Bank Col b BGa BGa or BGb tWPRE tWPST tWTR tWR Notes: 1. BL = 8, AL = 0, CL = 11, PL = 4, (RL = CL + AL + PL = 15), READ preamble = 1 tCK, CWL = 9, AL = 0, PL = 4, (WL = CL + AL + PL = 13), WRITE preamble = 1tCK. 2. DO n = data-out from column n, DI b = data-in from column b. 3. DES commands are shown for ease of illustration; other commands may be valid at these times. 4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during READ commands at T0 and WRITE command at T8. 5. CA parity = Enable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable, Write CRC = Disable. 16Gb: x4, x8, x16 DDR4 SDRAM READ Operation CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 216 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

READ Followed by WRITE with CRC Enabled Figure 157: READ (BL8) to WRITE (BL8 or BC4: OTF) with 1tCK Preamble and Write CRC in Same or Different Bank Group READ to WRITE command delay = RL +BL/2 - WL + 2 tCK 4 Clocks tRPRE RL = 11 tRPST T1 T7 T8 T9 T10 T11 T12 T13 DES DES DES DES DES DES DESCommand DESREAD DES WRITE DES DES DQ x4, BL = 8 CK_t CK_c DQS_t, DQS_c WL = 9 T22T16T14 T15 T21T17 T18 T19 T20 Don’t CareTransitioning DataTime Break DOn + 1 DOn + 2 DOn + 3 DOn + 4 DOn + 5 DOn + 6 DOn + 7 DIb DIb + 1 DIb + 2 DIb + 3 DIb + 4 DIb + 5 DIb + 6 DIb + 7 CRC CRCDOn DES DES DES DES DES Bank Group Address Address Bank Col n Bank Col b BGa BGa or BGb DQ x8/X16, BL = 8 DOn + 1 DOn + 2 DOn + 3 DOn + 4 DOn + 5 DOn + 6 DOn + 7 DIb DIb + 1 DIb + 2 DIb + 3 DIb + 4 DIb + 5 DIb + 6 DIb + 7 CRCDOn DQ x4, READ: BL = 8, WRITE: BC = 4 (OTF) DQ x8/X16, READ: BL = 8, WRITE: BC = 4 (OTF) DOn + 1 DOn + 2 DOn + 3 DOn + 4 DOn + 5 DOn + 6 DOn + 7 DIb DIb + 1 DIb + 2 CRC CRCDOn tWPRE tWPST tWTR tWR DOn + 1 DOn + 2 DOn + 3 DOn + 4 DOn + 5 DOn + 6 DOn + 7 DIb DIb + 1 DIb + 2 DIb + 3 CRCDOn DIb + 3 Notes: 1. BL = 8 (or BC = 4: OTF for Write), RL = 11 (CL = 11, AL = 0), READ preamble = 1 tCK, WL = 9 (CWL = 9, AL = 0), WRITE preamble = 1tCK. 2. DO n = data-out from column n, DI b = data-in from column b. 3. DES commands are shown for ease of illustration; other commands may be valid at these times. 4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during READ commands at T0 and WRITE commands at T8. 5. BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during WRITE commands at T8. 6. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable, Write CRC = Enable. 16Gb: x4, x8, x16 DDR4 SDRAM READ Operation CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 217 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

1. DI n (or b) = data-in from column n (or b). 3. DES commands are shown for ease of illustration; other commands may be valid at these times. 4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during READ commands at T3 and T7. 5. CA parity = Disable, CS to CA latency = Enable, Read DBI = Disable, Write DBI = Disable, Write CRC = Disable. 6. Enabling CAL mode does not impact ODT control timings. The same timing relationship relative to the command/address bus as when CAL is disabled should be maintained. Figure 160: Consecutive READ (BL8) with CAL (4tCK) and 1tCK Preamble in Different Bank Group tCAL = 4 tCAL = 4 tCCD_S = 4 tRPRE RL = 11 T1 T2 T3 T4 DES DES DES DES DES DESCommand w/o CS_n DES DES READ READ DES DES DQ CK_t CK_c DQS_t, DQS_c RL = 11 T5 T6 T7 T8 T24T22 T23T16T14 T15 T18 T19 T21 Don’t CareTransitioning DataTime Break DIn + 1 DIn + 2 DIn + 5 DIn + 6 DIn + 7 DIb DIb + 1 DIb + 2 DIb + 5 DIb + 6 DIb + 7DIn DES DES DES DES DES Bank Group Address Address Bank Col n Bank Col b BGa BGb tRPST CS_n Notes: 1. BL = 8, RL = 11 (CL = 11, AL = 0), READ preamble = 1 tCK. 2. DI n (or b) = data-in from column n (or b). 3. DES commands are shown for ease of illustration; other commands may be valid at these times. 4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during READ commands at T3 and T8. 5. CA parity = Disable, CS to CA latency = Enable, Read DBI = Disable, Write DBI = Disable, Write CRC = Disable. 6. Enabling CAL mode does not impact ODT control timings. The same timing relationship relative to the command/address bus as when CAL is disabled should be maintained. 16Gb: x4, x8, x16 DDR4 SDRAM READ Operation CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 219 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

The write timings shown in the following figures are applicable in normal operation mode, that is, when the DLL is enabled and locked. Write Timing – Clock-to-Data Strobe Relationship The clock-to-data strobe relationship is shown below and is applicable in normal oper- ation mode, that is, when the DLL is enabled and locked. Rising data strobe edge parameters: tDQSS (MIN) to tDQSS (MAX) describes the allowed range for a rising data strobe edge relative to CK.

• tDQSS is the actual position of a rising strobe edge relative to CK.
• tDQSH describes the data strobe high pulse width.
• tWPST strobe going to HIGH, nondrive level (shown in the postamble section of the graphic below). Falling data strobe edge parameters: tDQSL describes the data strobe low pulse width.
• tWPRE strobe going to LOW, initial drive level (shown in the preamble section of the graphic below). 16Gb: x4, x8, x16 DDR4 SDRAM WRITE Operation CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 220 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Figure 161: Write Timing Definition WL = AL + CWL T0 T1 T2 T7 T8 T9 T10 T11 T12 T13 T14 Don’t CareTime Break Transitioning Data Bank, Col n DESWRITE DESDES DES DES DES DES DES DES DES CK_t CK_c Command3 DQ2 DQS_t, DQS_c DQS_t, DQS_c DQS_t, DQS_c Address4 tWPSTaa DM_n tWPST (MIN) tDQSL tDQSS (MIN) DIN n DIN n + 2 DIN n + 3DQ2 DQ2 tDQSS (MAX) tDQSS (nominal) tDQSL tWPRE(1nCK) tDQSL tDQSS tDQSS tDSS tDSS tDSS tDSS tDSS tDSH tDSH tDSH tDSH tDSS tDSS tDSS tDSS tDSS tDSS tDSS tDSS tDSS tDSS tDSH tDSH tDSH tDSH tDSH tDSH tDSH tDSH tDQSLtDQSH tDQSLtDQSH tDQSLtDQSH tDQSH tDQSLtDQSH tDQSLtDQSH tDQSLtDQSH tDQSH tDQSLtDQSH tDQSLtDQSH tDQSLtDQSH tDQSH tWPRE(1nCK) tWPRE(1nCK) tDQSH (MIN) tDQSH (MIN) tDQSH (MIN) tWPST (MIN) tDQSL (MIN) tDQSL (MIN) tDQSL (MIN) DIN n + 4 DIN n + 6 DIN n + 7 DIN n DIN n + 2 DIN n + 3 DIN n + 4 DIN n + 6 DIN n + 7 DIN n DIN n + 2 DIN n + 3 DIN n + 4 DIN n + 6 DIN n + 7 Notes: 1. BL8, WL = 9 (AL = 0, CWL = 9). 2. D INn = data-in from column n. 3. DES commands are shown for ease of illustration; other commands may be valid at these times. 4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during WRITE command at T0. 5. tDQSS must be met at each rising clock edge. 16Gb: x4, x8, x16 DDR4 SDRAM WRITE Operation CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 221 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Figure 162: tWPRE Method for Calculating Transitions and Endpoints '46BW W:35(HQGV W &.BW &.BF 9'' 5HVXOWLQJGLIIHUHQWLDOVLJQDOUHOHYDQWIRUW:35(VSHFLILFDWLRQ 6LQJOHHQGHGVLJQDOSURYLGHGDVEDFNJURXQGLQIRUPDWLRQ '46BF '46BW'46BF '46BW '46BF '46BW '46BF W:35(EHJLQV W 96: 96: 95()'4 95()'4 95()'4 9,+',))'46 9,+',))3HDN Notes: 1. V sw1 = (0.1) × VIH,diff,DQS. 2. V sw2 = (0.9) × VIH,diff,DQS. 16Gb: x4, x8, x16 DDR4 SDRAM WRITE Operation CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 222 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Figure 163: tWPST Method for Calculating Transitions and Endpoints '46BW'46BF 96: 96: '46BW W:367HQGV W &.BW &.BF 5HVXOWLQJGLIIHUHQWLDOVLJQDOUHOHYDQWIRU W:367VSHFLILFDWLRQ 6LQJOHHQGHGVLJQDOSURYLGHGDVEDFNJURXQGLQIRUPDWLRQ '46BF '46BW '46BF W:367EHJLQV W 9'' 95()'4 95()'4 95()'4 9,/',))'46 9,/',))3HDN Notes: 1. V sw1 =(0.9) × VIL,diff,DQS. 2. V sw2 = (0.1) × VIL,diff,DQS. Write Timing – Data Strobe-to-Data Relationship The DQ input receiver uses a compliance mask (Rx) for voltage and timing as shown in the figure below. The receiver mask (Rx mask) defines the area where the input signal must not encroach in order for the DRAM input receiver to be able to successfully cap- ture a valid input signal. The Rx mask is not the valid data-eye. TdiVW and V diVW define the absolute maximum Rx mask. 16Gb: x4, x8, x16 DDR4 SDRAM WRITE Operation CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 223 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Figure 166: Rx Mask DQ-to-DQS Timings DQS, DQs Data-In at DRAM BallDQS, DQs Data-In at DRAM Ball Rx Mask Rx Mask – Alternative View Rx Mask Rx Mask Rx Mask Rx Mask DQS_t Rx Mask 0.5 × TdiVW0.5 × TdiVW tDQS2DQ +0.5 × TdiVW tDQS2DQ +0.5 × TdiVW DQy DRAMc Rx Mask DQz DRAMc Rx Mask DQz DRAMb Rx Mask DQy DRAMb Rx Mask DQS_cDQS_c DQS_t DQx–z DRAMa DQy DRAMc DQz DRAMc DQz DRAMb DQy DRAMb DQx–z DRAMaRx Mask TdiVW TdiVW 0.5 × TdiVW0.5 × TdiVW tDQS2DQ tDQ2DQ tDQ2DQ tDQ2DQ tDQ2DQ tDQ2DQ tDQS2DQ tDQ2DQ VdiVWVdiVWVdiVWVdiVWVdiVW VdiVWVdiVWVdiVWVdiVWVdiVW TdiVW TdiVW TdiVW TdiVW Notes: 1. DQx represents an optimally centered mask. DQy represents earliest valid mask. DQz represents latest valid mask. 2. DRAMa represents a DRAM without any DQS/DQ skews. DRAMb represents a DRAM with early skews (negative tDQS2DQ). DRAMc represents a DRAM with delayed skews (positive tDQS2DQ). 3. This figure shows the skew allowed between DRAM-to-DRAM and between DQ-to-DQ for a DRAM. Signals assume data is center-aligned at DRAM latch. TdiPW is not shown; composite data-eyes shown would violate TdiPW. V CENTDQ,midpoint is not shown but is assumed to be midpoint of VdiVW. The previous figure shows the basic Rx mask requirements. Converting the Rx mask re- quirements to a classical DQ-to-DQS relationship is shown in the following figure. It should become apparent that DRAM write training is required to take full advantage of the Rx mask. 16Gb: x4, x8, x16 DDR4 SDRAM WRITE Operation CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 225 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Figure 167: Rx Mask DQ-to-DQS DRAM-Based Timings DQS_c DQS_t Rx Mask DQS, DQs Data-In at DRAM Ball VdiVW VdiVWVdiVWVdiVWVdiVWVdiVW DQx , y, z DQS_c DQS_t Rx Mask DQS, DQs Data-In at DRAM Ball tDSx tDHx DQx–z DRAMaDRAMa DRAMb DRAMb DRAMc DRAMc TdiPW TdiPW Rx Mask vs. Composite Data-Eye Rx Mask vs. UI Data-Eye TdiPW *Skew *Skew tDSy tDHy DQy Rx Mask TdiVW tDQ2DQ DQz TdiPW TdiVW TdiVW tDSz tDHz DQy tDQ2DQ DQz TdiPW Rx Mask TdiVW tDQ2DQ Rx Mask TdiVW Rx Mask TdiVW tDQ2DQ Notes: 1. DQx represents an optimally centered mask. DQy represents earliest valid mask. DQz represents latest valid mask. 2. *Skew = tDQS2DQ + 0.5 × TdiVW DRAMa represents a DRAM without any DQS/DQ skews. DRAMb represents a DRAM with the earliest skews (negative tDQS2DQ, tDQSy > *Skew). DRAMc represents a DRAM with the latest skews (positive tDQS2DQ, tDQHz > *Skew). 3. tDS/tDH are traditional data-eye setup/hold edges at DC levels. tDS and tDH are not specified; tDH and tDS may be any value provided the pulse width and Rx mask limits are not violated. tDH (MIN) > TdiVW + tDS (MIN) + tDQ2DQ. The DDR4 SDRAM's input receivers are expected to capture the input data with an Rx mask of TdiVW provided the minimum pulse width is satisfied. The DRAM controller will have to train the data input buffer to utilize the Rx mask specifications to this maxi- 16Gb: x4, x8, x16 DDR4 SDRAM WRITE Operation CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 226 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

mum benefit. If the DRAM controller does not train the data input buffers, then the worst case limits have to be used for the Rx mask (TdiVW + 2 × tDQS2DQ), which will generally be the classical minimum ( tDS and tDH) and is required as well. Figure 168: Example of Data Input Requirements Without Training tDS VdiVW 0.5 × VdiVW 0.5 × VdiVW tDH 0.5 × TdiVW + tDQS2DQ TdiVW + 2 × tDQS2DQ 0.5 × TdiVW + tDQS2DQ VCENTDQ,midpoint VIL(DC) VIH(DC) DQS_c DQS_t Rx Mask WRITE Burst Operation The following write timing diagrams are intended to help understand each write pa- rameter's meaning and are only examples. Each parameter will be defined in detail sep- arately. In these write timing diagrams, CK and DQS are shown aligned, and DQS and DQ are shown center-aligned for the purpose of illustration. DDR4 WRITE command supports bursts of BL8 (fixed), BC4 (fixed), and BL8/BC4 on- the-fly (OTF); OTF uses address A12 to control OTF when OTF is enabled:

• A12 = 0, BC4 (BC4 = burst chop)
• A12 = 1, BL8 WRITE commands can issue precharge automatically with a WRITE with auto pre- charge (WRA) command, which is enabled by A10 HIGH.
• WRITE command with A10 = 0 (WR) performs standard write, bank remains active af- ter WRITE burst
• WRITE command with A10 = 1 (WRA) performs write with auto precharge, bank goes into precharge after WRITE burst The DATA MASK (DM) function is supported for the x8 and x16 configurations only (the DM function is not supported on x4 devices). The DM function shares a common pin with the DBI_n and TDQS functions. The DM function only applies to WRITE opera- tions and cannot be enabled at the same time the DBI function is enabled.
• If DM_n is sampled LOW on a given byte lane, the DRAM masks the write data re- ceived on the DQ inputs. 16Gb: x4, x8, x16 DDR4 SDRAM WRITE Operation CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 227 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

• If DM_n is sampled HIGH on a given byte lane, the DRAM does not mask the data and writes this data into the DRAM core.
• If CRC write is enabled, then DM enabled (via MRS) will be selected between write CRC nonpersistent mode (DM disabled) and write CRC persistent mode (DM ena- bled). Figure 169: WRITE Burst Operation, WL = 9 (AL = 0, CWL = 9, BL8) tWPRE T1 T7 T2 T8 T9 T10 T11 T12 T13 DES DES DES DES DES DES DESCommand DESWRITE DES DES DES DES DQ CK_t CK_c DQS_t, DQS_c WL = AL + CWL = 9 T16T14 T15 Don’t CareTransitioning DataTime Break DIn + 1 DIn + 2 DIn + 3 DIn + 4 DIn + 5 DIn + 6 DIn + 7DIn Bank Group Address Address Bank Col n BGa tWPST Notes: 1. BL8, WL = 0, AL = 0, CWL = 9, Preamble = 1 tCK. 2. DI n = Data-in from column n. 3. DES commands are shown for ease of illustration; other commands may be valid at these times. 4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during WRITE command at T0. 5. CA parity = Disable, CS to CA Latency = Disable, Read DBI = Disable. 16Gb: x4, x8, x16 DDR4 SDRAM WRITE Operation CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 228 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

1. DES commands are shown for ease of illustration; other commands may be valid at these times. 4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during WRITE commands at T0 and T4. 5. CA parity = Disable, CS to CA latency = Disable, Write DBI = Disable, Write CRC = Disable. 6. The write recovery time ( tWR) and write timing parameter (tWTR) are referenced from the first rising clock edge after the last write data shown at T17. Figure 172: Consecutive WRITE (BL8) with 2tCK Preamble in Different Bank Group tCCD_S = 4 4 Clocks tWPRE WL = AL + CWL = 10 T1 T2 T3 T4 DES DES DES DES DES DES DESCommand DESWRITE DES DES WRITE DES DQ CK_t CK_c DQS_t, DQS_c WL = AL + CWL = 10 T7 T8 T9 T10 T11 T12 T13 T16 T14 T15 T17 T18 T19 Don’t CareTransitioning DataTime Break DIn + 1 DIn + 2 DIn + 3 DIn + 4 DIn + 5 DIn + 6 DIn + 7 DIb DIb + 1 DIb + 2 DIb + 3 DIb + 4 DIb + 5 DIb + 6 DIb + 7DIn DES DES DES DES DES Bank Group Address Address Bank Col n Bank Col b BGa BGb tWPST tWTR tWR Notes: 1. BL8, AL = 0, CWL = 9 + 1 = 10 (see Note 7), Preamble = 2 tCK. 2. DI n (or b) = data-in from column n (or column b). 3. DES commands are shown for ease of illustration; other commands may be valid at these times. 4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during WRITE commands at T0 and T4. 5. CA parity = Disable, CS to CA latency = Disable, Write DBI = Disable, Write CRC = Disable. 6. The write recovery time ( tWR) and write timing parameter (tWTR) are referenced from the first rising clock edge after the last write data shown at T17. 7. When operating in 2 tCK WRITE preamble mode, CWL may need to be programmed to a value at least 1 clock greater than the lowest CWL setting supported in the applicable tCK range, which means CWL = 9 is not allowed when operating in 2tCK WRITE pream- ble mode. 16Gb: x4, x8, x16 DDR4 SDRAM WRITE Operation CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 230 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

1. CA parity = Disable, CS to CA latency = Disable, Write DBI = Disable, Write CRC = Disable. 6. tCCD_S/L = 5 isn’t allowed in 2tCK preamble mode. 7. The write recovery time ( tWR) and write timing parameter (tWTR) are referenced from the first rising clock edge after the last write data shown at T20. 8. When operating in 2 tCK WRITE preamble mode, CWL may need to be programmed to a value at least 1 clock greater than the lowest CWL setting supported in the applicable tCK range, which means CWL = 9 is not allowed when operating in 2tCK WRITE pream- ble mode. Figure 175: WRITE (BC4) OTF to WRITE (BC4) OTF with 1tCK Preamble in Different Bank Group tCCD_S = 4 4 Clocks tWPRE WL = AL + CWL = 9 T1 T2 T3 T4 DES DES DES DES DES DES DESCommand DESWRITE DES DES WRITE DES DQ CK_t CK_c DQS_t, DQS_c WL = AL + CWL = 9 T7 T8 T9 T10 T11 T12 T13 T16 T14 T15 T17 T18 T19 Don’t CareTransitioning DataTime Break DIn + 1 DIn + 2 DIn + 3 DIb DIb + 1 DIb + 2 DIb + 3DIn DES DES DES DES DES Bank Group Address Address Bank Col n Bank Col b BGa BGb tWPRE tWTR tWR tWPSTtWPST Notes: 1. BC4, AL = 0, CWL = 9, Preamble = 1 tCK. 2. DI n (or b) = data-in from column n (or column b). 3. DES commands are shown for ease of illustration; other commands may be valid at these times. 4. BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during WRITE commands at T0 and T4. 5. CA parity = Disable, CS to CA latency = Disable, Write DBI = Disable, Write CRC = Disable. 6. The write recovery time ( tWR) and write timing parameter (tWTR) are referenced from the first rising clock edge after the last write data shown at T17. 16Gb: x4, x8, x16 DDR4 SDRAM WRITE Operation CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 232 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

1. DES commands are shown for ease of illustration; other commands may be valid at these times. 4. BC4 (fixed) setting activated by MR0[1:0] = 10. 5. CA parity = Disable, CS to CA latency = Disable, Write DBI = Disable, Write CRC = Disable. 6. The write recovery time ( tWR) and write timing parameter (tWTR) are referenced from the first rising clock edge after the last write data shown at T15. Figure 178: WRITE (BL8) to WRITE (BC4) OTF with 1tCK Preamble in Different Bank Group tCCD_S = 4 4 Clocks tWPRE WL = AL + CWL = 9 T1 T2 T3 T4 DES DES DES DES DES DES DESCommand DESWRITE DES DES WRITE DES DQ CK_t CK_c DQS_t, DQS_c WL = AL + CWL = 9 T7 T8 T9 T10 T11 T12 T13 T16 T14 T15 T17 T18 T19 Don’t CareTransitioning DataTime Break DIn + 1 DIn + 2 DIn + 3 DIn + 4 DIn + 5 DIn + 6 DIn + 7 DIb DIb + 1 DIb + 2 DIb + 3DIn DES DES DES DES DES Bank Group Address Address Bank Col n Bank Col b BGa BGb tWTR tWR tWPST Notes: 1. BL = 8/BC = 4, AL = 0, CL = 9, Preamble = 1 tCK. 2. DI n (or b) = data-in from column n (or column b). 3. DES commands are shown for ease of illustration; other commands may be valid at these times. 4. BL8 setting activated by MR0[1:0] = 01 and A12 = 1 during WRITE command at T0. BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during WRITE command at T4. 5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write CRC = Disable. 6. The write recovery time ( tWR) and write timing parameter (tWTR) are referenced from the first rising clock edge after the last write data shown at T17. 16Gb: x4, x8, x16 DDR4 SDRAM WRITE Operation CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 234 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Figure 179: WRITE (BC4) OTF to WRITE (BL8) with 1tCK Preamble in Different Bank Group tCCD_S = 4 tWPRE tWPRE WL = AL + CWL = 9 T1 T2 T3 T4 DES DES DES DES DES DES DESCommand DESWRITE DES DES WRITE DES DQ CK_t CK_c DQS_t, DQS_c WL = AL + CWL = 9 T7 T8 T9 T10 T11 T12 T13 T16 T14 T15 T17 T18 T19 Don’t CareTransitioning DataTime Break DIn + 1 DIn + 2 DIn + 3 DIb DIb + 1 DIb + 2 DIb + 3 DIb + 4 DIb + 5 DIb + 6 DIb + 7DIn DES DES DES DES DES Bank Group Address Address Bank Col n Bank Col b BGa BGb tWTR tWR tWPSTtWPST Notes: 1. BL = 8/BC = 4, AL = 0, CL = 9, Preamble = 1 tCK. 2. DI n (or b) = data-in from column n (or column b). 3. DES commands are shown for ease of illustration; other commands may be valid at these times. 4. BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during WRITE command at T0. BL8 setting activated by MR0[1:0] = 01 and A12 = 1 during WRITE command at T4. 5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write CRC = Disable. 6. The write recovery time ( tWR) and write timing parameter (tWTR) are referenced from the first rising clock edge after the last write data shown at T17. WRITE Operation Followed by READ Operation Figure 180: WRITE (BL8) to READ (BL8) with 1tCK Preamble in Different Bank Group DIb DIb + 1 DIb + 2 DIb + 3 DIb + 4 DIb + 5 DIb + 6 tWTR_S = 2 tWPRE WL = AL + CWL = 9 RL = AL + CL = 11 T1 T7 DES DES DES DES READ DES DESCommand DESWRITE DES DES DES DES DQ CK_t CK_c DQS_t, DQS_c T8 T9 T10 T11 T12 T13 T16 T14 T15 T24 T25 T26 T27 T28 T29 Don’t CareTransitioning DataTime Break DIn + 1 DIn + 2 DIn + 3 DIn + 4 DIn + 5 DIn + 6 DIn + 7DIn DES DES DES DES DES Bank Group Address Address Bank Col n Bank Col b BGa BGb tRPRE tWPST Notes: 1. BL = 8, WL = 9 (CWL = 9, AL = 0), CL = 11, READ preamble = 1 tCK, WRITE preamble = 1tCK. 2. DI b = data-in from column b. 3. DES commands are shown for ease of illustration; other commands may be valid at these times. 16Gb: x4, x8, x16 DDR4 SDRAM WRITE Operation CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 235 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

1. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during WRITE command at T0 and READ command at T15. 5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable, Write CRC = Disable. 6. The write timing parameter ( tWTR_S) is referenced from the first rising clock edge after the last write data shown at T13. Figure 181: WRITE (BL8) to READ (BL8) with 1tCK Preamble in Same Bank Group tWTR_L = 4 tWPRE WL = AL + CWL = 9 RL = AL + CL = 11 T1 T7 DES DES DES DES DES DESDESCommand DESWRITE DES DES DES READ DQ CK_t CK_c DQS_t, DQS_c T8 T9 T10 T11 T12 T13 T16 T14 T15 T17 T18 T26 T27 T28 T29 Don’t CareTransitioning DataTime Break DIn + 1 DIn + 2 DIn + 3 DIn + 4 DIn + 5 DIn + 6 DIn + 7DIn DES DES DES DES DES Bank Group Address Address Bank Col n Bank Col b BGa BGa tRPRE tWPST DIb DIb + 1 DIb + 2

Notes: 1. BL = 8, WL = 9 (CWL = 9, AL = 0), CL = 11, READ preamble = 1 tCK, WRITE preamble = 1tCK. 2. DI b = data-in from column b. 3. DES commands are shown for ease of illustration; other commands may be valid at these times. 4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during WRITE command at T0 and READ command at T17. 5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable, Write CRC = Disable. 6. The write timing parameter ( tWTR_L) is referenced from the first rising clock edge after the last write data shown at T13. 16Gb: x4, x8, x16 DDR4 SDRAM WRITE Operation CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 236 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Figure 182: WRITE (BC4) OTF to READ (BC4) OTF with 1tCK Preamble in Different Bank Group tWTR_S = 2 tWPRE WL = AL + CWL = 9 RL = AL + CL = 11 T1 T7 DES DES DES DES READ DES DESCommand DESWRITE DES DES DES DES DQ CK_t CK_c DQS_t, DQS_c T8 T9 T10 T11 T12 T13 T16 T14 T15 T24 T25 T26 T27 T28 T29 Don’t CareTransitioning DataTime Break DIn + 1 DIn + 2 DIn + 3DIn DES DES DES DES DES Bank Group Address Address Bank Col n Bank Col b BGa BGb tRPRE tWPST tRPST DIb DIb + 1 DIb + 2 DIb + 3 Notes: 1. BC = 4, WL = 9 (CWL = 9, AL = 0), CL = 11, READ preamble = 1 tCK, WRITE preamble = 1tCK. 2. DI b = data-in from column b. 3. DES commands are shown for ease of illustration; other commands may be valid at these times. 4. BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during WRITE command at T0 and READ command at T15. 5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable, Write CRC = Disable. 6. The write timing parameter ( tWTR_S) is referenced from the first rising clock edge after the last write data shown at T13. Figure 183: WRITE (BC4) OTF to READ (BC4) OTF with 1tCK Preamble in Same Bank Group tWTR_L = 4 tWPRE WL = AL + CWL = 9 RL = AL + CL = 11 T1 T7 DES DES DES DES DES DES READCommand DESWRITE DES DES DES DES DQ CK_t CK_c DQS_t, DQS_c T8 T9 T10 T11 T12 T13 T16 T14 T15 T17 T18 T26 T27 T28 T29 Don’t CareTransitioning DataTime Break DIn + 1 DIn + 2 DIn + 3DIn DES DES DES DES DES Bank Group Address Address Bank Col n Bank Col b BGa BGa tRPRE tWPST DIb DIb + 1 DIb + 2 Notes: 1. BC = 4, WL = 9 (CWL = 9, AL = 0), CL = 11, READ preamble = 1 tCK, WRITE preamble = 1tCK. 2. DI b = data-in from column b. 3. DES commands are shown for ease of illustration; other commands may be valid at these times. 4. BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during WRITE command at T0 and READ command at T17. 16Gb: x4, x8, x16 DDR4 SDRAM WRITE Operation CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 237 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

1. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable, Write CRC = Disable. 6. The write timing parameter ( tWTR_L) is referenced from the first rising clock edge after the last write data shown at T13. Figure 184: WRITE (BC4) Fixed to READ (BC4) Fixed with 1 tCK Preamble in Different Bank Group tWTR_S = 2 tWPRE WL = AL + CWL = 9 RL = AL + CL = 11 T1 T7 DES DES DES DES DES DES READCommand DESWRITE DES DES DES DES DQ CK_t CK_c DQS_t, DQS_c T8 T9 T10 T11 T12 T13 T23 T14 T22 T24 T25 T26 T27 T28 T29 Don’t CareTransitioning DataTime Break DIn + 1 DIn + 2 DIn + 3DIn DES DES DES DES DES Bank Group Address Address Bank Col n Bank Col b BGa BGb tRPRE tWPST tRPST DIb DIb + 1 DIb + 2 DIb + 3

Notes: 1. BC = 4, WL = 9 (CWL = 9, AL = 0), CL = 11, READ preamble = 1 tCK, WRITE preamble = 1tCK. 2. DI b = data-in from column b. 3. DES commands are shown for ease of illustration; other commands may be valid at these times. 4. BC4 setting activated by MR0[1:0] = 10. 5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable, Write CRC = Disable. 6. The write timing parameter ( tWTR_S) is referenced from the first rising clock edge after the last write data shown at T11. Figure 185: WRITE (BC4) Fixed to READ (BC4) Fixed with 1tCK Preamble in Same Bank Group tWTR_L = 4 tWPRE WL = AL + CWL = 9 RL = AL + CL = 11 T1 T7 DES DES DES DES DES DESREADCommand DESWRITE DES DES DES DES DQ CK_t CK_c DQS_t, DQS_c T8 T9 T10 T11 T12 T13 T16 T14 T15 T24 T25 T26 T27 T28 T29 Don’t CareTransitioning DataTime Break DIn + 1 DIn + 2 DIn + 3DIn DES DES DES DES DES Bank Group Address Address Bank Col n Bank Col b BGa BGa tRPRE tWPST tRPST DIb DIb + 1 DIb + 2 DIb + 3 Notes: 1. BC = 4, WL = 9 (CWL = 9, AL = 0), C L = 11, READ preamble = 1 tCK, WRITE preamble = 1tCK. 2. DI b = data-in from column b. 16Gb: x4, x8, x16 DDR4 SDRAM WRITE Operation CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 238 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

1. DES commands are shown for ease of illustration; other commands may be valid at these times. 4. BC4 setting activated by MR0[1:0] = 10. 5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable, Write CRC = Disable. 6. The write timing parameter ( tWTR_L) is referenced from the first rising clock edge after the last write data shown at T11. WRITE Operation Followed by PRECHARGE Operation The minimum external WRITE command to PRECHARGE command spacing is equal to WL (AL + CWL) plus either 4tCK (BL8/BC4-OTF) or 2tCK (BC4-fixed) plus tWR. The min- imum ACT to PRE timing, tRAS, must be satisfied as well. Figure 186: WRITE (BL8/BC4-OTF) to PRECHARGE with 1tCK Preamble WL = AL + CWL = 9 tWR = 12 tRP T1 T2 T3 T4 DES DES DES DES DES DES DESCommand DESWRITE DES DES DES DES DQ BC4 (OTF) Opertaion CK_t CK_c DQS_t, DQS_c T14T7 T8 T9 T10 T11 T12 T13 T26T22 T23 T24 T25 Don’t CareTransitioning DataTime Break DIn + 1 DIn + 2 DIn + 3DIn DES DES DES PRE DES Address BGa, Bank b Col n BGa, Bank b (or all) DQ BL8 Opertaion DQS_t, DQS_c DIn + 1 DIn + 2 DIn + 3 DIn + 4 DIn + 5 DIn + 6 DIn + 7DIn

Notes: 1. BL = 8 with BC4-OTF, WL = 9 (CWL = 9, AL = 0 ), Preamble = 1 tCK, tWR = 12. 2. DI n = data-in from column n. 3. DES commands are shown for ease of illustration; other commands may be valid at these times. 4. BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during WRITE command at T0. BL8 setting activated by MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during WRITE command at T0. 5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, CRC = Disable. 6. The write recovery time ( tWR) is referenced from the first rising clock edge after the last write data shown at T13. tWR specifies the last burst WRITE cycle until the PRECHARGE command can be issued to the same bank. 16Gb: x4, x8, x16 DDR4 SDRAM WRITE Operation CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 239 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Figure 187: WRITE (BC4-Fixed) to PRECHARGE with 1tCK Preamble WL = AL + CWL = 9 tWR = 12 tRP T1 T2 T3 T4 DES DES DES DES DES DES DESCommand DESWRITE DES DES DES DES DQ BC4 (Fixed) Opertaion CK_t CK_c DQS_t, DQS_c T14T7 T8 T9 T10 T11 T12 T13 T26T22 T23 T24 T25 Don’t CareTransitioning DataTime Break DIn + 1 DIn + 2 DIn + 3DIn DES PRE DES DES DES Address BGa, Bank b Col n BGa, Bank b (or all) Notes: 1. BC4 = fixed, WL = 9 (CWL = 9, AL = 0 ), Preamble = 1 tCK, tWR = 12. 2. DI n = data-in from column n. 3. DES commands are shown for ease of illustration; other commands may be valid at these times. 4. BC4 setting activated by MR0[1:0] = 10. 5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, CRC = Disable. 6. The write recovery time ( tWR) is referenced from the first rising clock edge after the last write data shown at T11. tWR specifies the last burst WRITE cycle until the PRECHARGE command can be issued to the same bank. Figure 188: WRITE (BL8/BC4-OTF) to Auto PRECHARGE with 1tCK Preamble WL = AL + CWL = 9 tWR = 12 tRP T1 T2 T3 T4 DES DES DES DES DES DES DESCommand DESWRITE DES DES DES DES DQ BC4 (OTF) Opertaion CK_t CK_c DQS_t, DQS_c T14T7 T8 T9 T10 T11 T12 T13 T26T22 T23 T24 T25 Don’t CareTransitioning DataTime Break DIn + 1 DIn + 2 DIn + 3DIn DES DES DES DES DES Address BGa, Bank b Col n DQ BL8 Opertaion DQS_t, DQS_c DIn + 1 DIn + 2 DIn + 3 DIn + 4 DIn + 5 DIn + 6 DIn + 7DIn Notes: 1. BL = 8 with BC4-OTF, WL = 9 (CWL = 9, AL = 0 ), Preamble = 1 tCK, tWR = 12. 2. DI n = data-in from column n. 3. DES commands are shown for ease of illustration; other commands may be valid at these times. 4. BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during WRITE command at T0. BL8 setting activated by MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during WRITE com- mand at T0. 5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, CRC = Disable. 16Gb: x4, x8, x16 DDR4 SDRAM WRITE Operation CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 240 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

1. The write recovery time ( tWR) is referenced from the first rising clock edge after the last write data shown at T13. tWR specifies the last burst WRITE cycle until the PRECHARGE command can be issued to the same bank. Figure 189: WRITE (BC4-Fixed) to Auto PRECHARGE with 1tCK Preamble WL = AL + CWL = 9 tWR = 12 tRP T1 T2 T3 T4 DES DES DES DES DES DES DESCommand DESWRITE DES DES DES DES DQ BC4 (Fixed) Opertaion CK_t CK_c DQS_t, DQS_c T14T7 T8 T9 T10 T11 T12 T13 T26T22 T23 T24 T25 Don’t CareTransitioning DataTime Break DIn + 1 DIn + 2 DIn + 3DIn DES DES DES DES DES Address BGa, Bank b Col n

Notes: 1. BC4 = fixed, WL = 9 (CWL = 9, AL = 0 ), Preamble = 1 tCK, tWR = 12. 2. DI n = data-in from column n. 3. DES commands are shown for ease of illustration; other commands may be valid at these times. 4. BC4 setting activated by MR0[1:0] = 10. 5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, CRC = Disable. 6. The write recovery time ( tWR) is referenced from the first rising clock edge after the last write data shown at T11. tWR specifies the last burst WRITE cycle until the PRECHARGE command can be issued to the same bank. 16Gb: x4, x8, x16 DDR4 SDRAM WRITE Operation CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 241 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

WRITE Operation with WRITE DBI Enabled Figure 190: WRITE (BL8/BC4-OTF) with 1tCK Preamble and DBI WL = AL + CWL = 9 tWR tWTR T1 T2 T3 T4 DES DES DES DES DES DES DESCommand DESWRITE DES DES DES DES DQ BC4 (OTF) Opertaion CK_t CK_c DQS_t, DQS_c T5 T6 T14T7 T8 T9 T10 T11 T12 T13 T15 T16 T17 Don’t CareTransitioning Data DIn + 1 DIn + 2 DIn + 3DIn DES DES DES DES DES Address BGa Address Bank, Col n DQ DBI_n BL8 Opertaion DQS_t, DQS_c DIn + 1 DIn + 2 DIn + 3 DIn + 4 DIn + 5 DIn + 6 DIn + 7DIn DIn + 1 DIn + 2 DIn + 3 DIn + 4 DIn + 5 DIn + 6 DIn + 7DIn DBI_n DIn + 1 DIn + 2 DIn + 3DIn Notes: 1. BL = 8 with BC4-OTF, WL = 9 (CWL = 9, AL = 0 ), Preamble = 1 tCK. 2. DI n = data-in from column n. 3. DES commands are shown for ease of illustration; other commands may be valid at these times. 4. BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during WRITE command at T0. BL8 setting activated by MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during WRITE com- mand at T0. 5. CA parity = Disable, CS to CA latency = Disable, Write DBI = Enabled, Write CRC = Disa- bled. 6. The write recovery time ( tWR_DBI) is referenced from the first rising clock edge after the last write data shown at T13. 16Gb: x4, x8, x16 DDR4 SDRAM WRITE Operation CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 242 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Figure 191: WRITE (BC4-Fixed) with 1tCK Preamble and DBI WL = AL + CWL = 9 tWR tWTR T1 T2 T3 T4 DES DES DES DES DES DES DESCommand DESWRITE DES DES DES DES DQ BC4 (Fixed) Opertaion CK_t CK_c DQS_t, DQS_c T5 T6 T14T7 T8 T9 T10 T11 T12 T13 T15 T16 T17 Don’t CareTransitioning Data DIn + 1 DIn + 2 DIn + 3DIn DES DES DES DES DES Address BGa Address Bank, Col n DBI_n DIn + 1 DIn + 2 DIn + 3DIn Notes: 1. BC4 = fixed, WL = 9 (CWL = 9, AL = 0 ), Preamble = 1 tCK. 2. DI n = data-in from column n. 3. DES commands are shown for ease of illustration; other commands may be valid at these times. 4. BC4 setting activated by MR0[1:0] = 10. 5. CA parity = Disable, CS to CA latency = Disable, Write DBI = Enabled, Write CRC = Disa- bled. 16Gb: x4, x8, x16 DDR4 SDRAM WRITE Operation CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 243 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

WRITE Operation with CA Parity Enabled Figure 192: Consecutive Write (BL8) with 1tCK Preamble and CA Parity in Different Bank Group tCCD_S = 4 4 Clocks tWPRE WL = PL + AL + CWL = 13 T1 T2 T3 T4 DES DES DES DES DES DES DESCommand DESWRITE DES DES WRITE DES DQ CK_t CK_c DQS_t, DQS_c WL = PL + AL + CWL = 13 T20 T21 T22 T23T11 T12 T13 T16 T14 T15 T17 T18 T19 Don’t CareTransitioning DataTime Break DIn + 1 DIn + 2 DIn + 3 DIn + 4 DIn + 5 DIn + 6 DIn + 7 DIb DIb + 1 DIb + 2 DIb + 3 DIb + 4 DIb + 5 DIb + 6 DIb + 7DIn DES DES DES DES DES Bank Group Address Address Bank Col n Bank Col b BGa BGb tWPST tWTR tWR Parity Valid Valid Notes: 1. BL = 8, WL = 9 (CWL = 13, AL = 0 ), Preamble = 1 tCK. 2. DI n = data-in from column n. 3. DES commands are shown for ease of illustration; other commands may be valid at these times. 4. BL8 setting activated by MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during WRITE com- mands at T0 and T4. 5. CA parity = Enable, CS to CA latency = Disable, Write DBI = Enabled, Write CRC = Disa- ble. 6. The write recovery time ( tWR) and write timing parameter (tWTR) are referenced from the first rising clock edge after the last write data shown at T21. 16Gb: x4, x8, x16 DDR4 SDRAM WRITE Operation CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 244 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

WRITE Operation with Write CRC Enabled Figure 193: Consecutive WRITE (BL8/BC4-OTF) with 1tCK Preamble and Write CRC in Same or Differ- ent Bank Group tCCD_S/L = 5 tWPRE WL = AL + CWL = 9 T1 T2 T3 T4 DES DES DES DES DES DES DESCommand DESWRITE DES DES DES WRITE DQ x4, BL = 8 CK_t CK_c DQS_t, DQS_c WL = AL + CWL = 9 T5 T8 T9 T10 T11 T12 T13 T16 T14 T15 T17 T18 T19 Don’t CareTransitioning DataTime Break DIn + 1 DIn + 2 DIn + 3 DIn + 4 DIn + 5 DIn + 6 DIn + 7 CRC DIn + 7 CRC CRC CRC DIb DIb + 1 DIb + 2 DIb + 3 DIb + 4 DIb + 5 DIb + 6 DIb + 7 CRC CRCDIn DES DES DES DES DES Bank Group Address Address Bank Col n Bank Col b BGa BGa or BGb DQ x8/X16, BL = 8 DIn + 1 DIn + 2 DIn + 3 DIn + 4 DIn + 5 DIn + 6 DIb DIb + 1 DIb + 2 DIb + 3 DIb + 4 DIb + 5 DIb + 6 DIb + 7 CRCDIn CRC DQ x4, BC = 4 (OTF) DQ x8/X16, BC = 4 (OTF) DIn + 1 DIn + 2 DIn + 3 DIb DIb + 1 DIb + 2 CRC CRCDIn tWPST tWTR tWR DIn + 1 DIn + 2 DIn + 3 DIb DIb + 1 DIb + 2 DIb + 3 CRCDIn DIb + 3 CRC Notes: 1. BL8/BC4-OTF, AL = 0, CWL = 9, Preamble = 1 tCK, tCCD_S/L = 5tCK. 2. DI n (or b) = data-in from column n (or column b). 3. DES commands are shown for ease of illustration; other commands may be valid at these times. 4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during WRITE commands at T0 and T5. 5. BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during WRITE commands at T0 and T5. 6. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write CRC = Enable. 7. The write recovery time ( tWR) and write timing parameter (tWTR) are referenced from the first rising clock edge after the last write data shown at T18. 16Gb: x4, x8, x16 DDR4 SDRAM WRITE Operation CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 245 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Figure 194: Consecutive WRITE (BC4-Fixed) with 1tCK Preamble and Write CRC in Same or Different Bank Group tCCD_S/L = 5 tWPRE WL = AL + CWL = 9 T1 T2 T3 T4 DES DES DES DES DES DES DESCommand DESWRITE DES DES DES WRITE CK_t CK_c DQS_t, DQS_c WL = AL + CWL = 9 T5 T8 T9 T10 T11 T12 T13 T16 T14 T15 T17 T18 T19 Don’t CareTransitioning DataTime Break CRC DES DES DES DES DES Bank Group Address Address Bank Col n Bank Col b BGa BGa or BGb CRC CRC DQ x4, BC = 4 (Fixed) DQ x8/X16, BC = 4 (Fixed) DIn + 1 DIn + 2 DIn + 3 DIb DIb + 1 DIb + 2 CRC CRCDIn tWPST tWTR tWR DIn + 1 DIn + 2 DIn + 3 DIb DIb + 1 DIb + 2 DIb + 3 CRCDIn DIb + 3 Notes: 1. BC4-fixed, AL = 0, CWL = 9, Preamble = 1 tCK, tCCD_S/L = 5tCK. 2. DI n (or b) = data-in from column n (or column b). 3. DES commands are shown for ease of illustration; other commands may be valid at these times. 4. BC4 setting activated by MR0[1:0] = 10 during WRITE commands at T0 and T5. 5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write CRC = Enable, DM = Disable. 6. The write recovery time ( tWR) and write timing parameter (tWTR) are referenced from the first rising clock edge after the last write data shown at T16. 16Gb: x4, x8, x16 DDR4 SDRAM WRITE Operation CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 246 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Figure 195: Nonconsecutive WRITE (BL8/BC4-OTF) with 1tCK Preamble and Write CRC in Same or Dif- ferent Bank Group W&&'B6/ W:35( :/ $/&:/ 7 7 7 7 '4[ &.BW &.BF '46BW '46BF :/ $/&:/ 77 7 7 7 7 7 7 7 7 7 7 7 'RQ¶W&DUH7UDQVLWLRQLQJ'DWD7LPH%UHDN ',Q &5& &5& &5& %DQN*URXS $GGUHVV $GGUHVV %DQN &ROQ %DQN &ROE %*D %*DRU %*E '4[; &5& '4[ 27) '4[; 27) W:367 W:75 W:5 ',E &5& &ORFNV Notes: 1. BL8/BC4-OTF, AL = 0, CWL = 9, Preamble = 1 tCK, tCCD_S/L = 6tCK. 2. DI n (or b) = data-in from column n (or column b). 3. DES commands are shown for ease of illustration; other commands may be valid at these times. 4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during WRITE commands at T0 and T6. 5. BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during WRITE commands at T0 and T6. 6. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write CRC = Enable, DM = Disable. 7. The write recovery time ( tWR) and write timing parameter (tWTR) are referenced from the first rising clock edge after the last write data shown at T19. 16Gb: x4, x8, x16 DDR4 SDRAM WRITE Operation CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 247 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Figure 196: Nonconsecutive WRITE (BL8/BC4-OTF) with 2tCK Preamble and Write CRC in Same or Dif- ferent Bank Group tCCD_S/L = 7 tWPRE WL = AL + CWL = 10 DES DES DES DES DES DES DESCommand DESWRITE DES DES DESWRITE DQ x4, BL = 8 CK_t CK_c DQS_t, DQS_c WL = AL + CWL = 10 T22T21T7 T20T8 T9 T10 T11 T12 T13 T16 T14 T15 T17 T18 T19 Don’t CareTransitioning DataTime Break DIn + 1 DIn + 2 DIn + 3 DIn + 4 DIn + 5 DIn + 6 DIn + 7 CRC DIn + 7 CRC CRC CRC DIb DIb + 1 DIb + 2 DIb + 3 DIb + 4 DIb + 5 DIb + 6 DIb + 7 CRC CRCDIn DES DES DES DES DES Bank Group Address Address Bank Col n Bank Col b BGa BGa or BGb DQ x8/X16, BL = 8 DIn + 1 DIn + 2 DIn + 3 DIn + 4 DIn + 5 DIn + 6 DIb DIb + 1 DIb + 2 DIb + 3 DIb + 4 DIb + 5 DIb + 6 DIb + 7 CRCDIn CRC DQ x4, BC = 4 (OTF) DQ x8/X16, BC = 4 (OTF) DIn + 1 DIn + 2 DIn + 3 DIb DIb + 1 DIb + 2 CRC CRCDIn tWPRE tWPST tWTR tWR DIn + 1 DIn + 2 DIn + 3 DIb DIb + 1 DIb + 2 DIb + 3 CRCDIn DIb + 3 CRC Notes: 1. BL8/BC4-OTF, AL = 0, CWL = 9 + 1 = 10 (see Note 9), Preamble = 2 tCK, tCCD_S/L = 7tCK (see Note 7). 2. DI n (or b) = data-in from column n (or column b). 3. DES commands are shown for ease of illustration; other commands may be valid at these times. 4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during WRITE commands at T0 and T7. 5. BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during WRITE commands at T0 and T7. 6. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write CRC = Enable, DM = Disable. 7. tCCD_S/L = 6tCK is not allowed in 2tCK preamble mode if minimum tCCD_S/L allowed in 1tCK preamble mode would have been 6 clocks. 8. The write recovery time ( tWR) and write timing parameter (tWTR) are referenced from the first rising clock edge after the last write data shown at T21. 9. When operating in 2 tCK WRITE preamble mode, CWL may need to be programmed to a value at least 1 clock greater than the lowest CWL setting supported in the applicable tCK range. That means CWL = 9 is not allowed when operating in 2tCK WRITE preamble mode. 16Gb: x4, x8, x16 DDR4 SDRAM WRITE Operation CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 248 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Figure 197: WRITE (BL8/BC4-OTF/Fixed) with 1tCK Preamble and Write CRC in Same or Different Bank Group tWPRE WL = AL + CWL = 9 T1 T2 T6 T7 DES DES DES DES DES DES DESCommand DESWRITE DES DES DESDESDES DQ x4, BL = 8 CK_t CK_c DQS_t, DQS_c T20T8 T9 T10 T11 T12 T13 T16 T14 T15 T17 T18 T19 Don’t CareTransitioning DataTime Break DIn + 1 DIn + 2 DIn + 3 DIn + 4 DIn + 5 DIn + 6 DIn + 7 CRC DIn + 7 CRC CRC CRC DIn DES DES DES DES DES Bank Group Address Address Bank Col n BGa DQ x8/X16, BL = 8 DIn + 1 DIn + 2 DIn + 3 DIn + 4 DIn + 5 DIn + 6DIn CRC DQ x4, BC = 4 (OTF/Fixed) DQ x8/X16, BC = 4 (OTF/Fixed) DIn + 1 DIn + 2 DIn + 3DIn tWR_CRC_DM tWPST DIn + 1 DIn + 2 DIn + 3DIn DMn + 7DMx4/x8/x16 BL = 8 DMn + 1 DMn + 2 DMn + 3 DMn + 4 DMn + 5 DMn + 6DMn CRC DM x4/x8/x16 BC = 4 (OTF / Fixed) DMn + 1 DMn + 2 DMn + 3DMn Notes: 1. BL8/BC4, AL = 0, CWL = 9, Preamble = 1 tCK. 2. DI n (or b) = data-in from column n (or column b). 3. DES commands are shown for ease of illustration; other commands may be valid at these times. 4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during WRITE command at T0. 5. BC4 setting activated by either MR0[1:0] = 10 or MR0[1:0] = 01 and A12 = 0 during WRITE command at T0. 6. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write CRC = Enable, DM = Enable. 7. The write recovery time ( tWR_CRC_DM) and write timing parameter (tWTR_S_CRC_DM/ tWTR_L_CRC_DM) are referenced from the first rising clock edge after the last write da- ta shown at T13. 16Gb: x4, x8, x16 DDR4 SDRAM WRITE Operation CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 249 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Generally, if timing parameters are violated, a complete reset/initialization procedure has to be initiated to make sure that the device works properly. However, for certain mi- nor violations, it is desirable that the device is guaranteed not to "hang up" and that er- rors are limited to that specific operation. A minor violation does not include a major timing violation (for example, when a DQS strobe misses in the tDQSCK window). For the following, it will be assumed that there are no timing violations with regard to the WRITE command itself (including ODT , and so on) and that it does satisfy all timing requirements not mentioned below. Data Setup and Hold Violations If the data-to-strobe timing requirements (tDS, tDH) are violated, for any of the strobe edges associated with a WRITE burst, then wrong data might be written to the memory location addressed with this WRITE command. In the example, the relevant strobe edges for WRITE Burst A are associated with the Subsequent reads from that location might result in unpredictable read data; however, the device will work properly otherwise. Strobe-to-Strobe and Strobe-to-Clock Violations If the strobe timing requirements (tDQSH, tDQSL, tWPRE, tWPST) or the strobe to clock timing requirements (tDSS, tDSH, tDQSS) are violated, for any of the strobe edges asso- ciated with a WRITE burst, then wrong data might be written to the memory location addressed with the offending WRITE command. Subsequent reads from that location might result in unpredictable read data; however, the device will work properly other- wise with the following constraints:

• Both write CRC and data burst OTF are disabled; timing specifications other than tDQSH, tDQSL, tWPRE, tWPST , tDSS, tDSH, tDQSS are not violated.
• The offending write strobe (and preamble) arrive no earlier or later than six DQS tran- sition edges from the WRITE latency position.
• A READ command following an offending WRITE command from any open bank is allowed.
• One or more subsequent WR or a subsequent WRA (to same bank as offending WR) may be issued tCCD_L later, but incorrect data could be written. Subsequent WR and WRA can be either offending or non-offending writes. Reads from these writes may provide incorrect data.
• One or more subsequent WR or a subsequent WRA (to a different bank group) may be issued tCCD_S later, but incorrect data could be written. Subsequent WR and WRA can be either offending or non-offending writes. Reads from these writes may provide incorrect data.
• After one or more precharge commands (PRE or PREA) are issued to the device after an offending WRITE command and all banks are in precharged state (idle state), a subsequent, non-offending WR or WRA to any open bank will be able to write correct data. 16Gb: x4, x8, x16 DDR4 SDRAM Write Timing Violations CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 250 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

A ZQ CALIBRATION command is used to calibrate DRAM RON and ODT values. The de- vice needs a longer time to calibrate the output driver and on-die termination circuits at initialization and a relatively smaller time to perform periodic calibrations. The ZQCL command is used to perform the initial calibration during the power-up ini- tialization sequence. This command may be issued at any time by the controller de- pending on the system environment. The ZQCL command triggers the calibration en- gine inside the DRAM and, after calibration is achieved, the calibrated values are trans- ferred from the calibration engine to DRAM I/O, which is reflected as an updated out- put driver and ODT values. The first ZQCL command issued after reset is allowed a timing period of tZQinit to per- form the full calibration and the transfer of values. All other ZQCL commands except the first ZQCL command issued after reset are allowed a timing period of tZQoper. The ZQCS command is used to perform periodic calibrations to account for voltage and temperature variations. A shorter timing window is provided to perform the calibration and transfer of values as defined by timing parameter tZQCS. One ZQCS command can effectively correct a minimum of 0.5% (ZQ correction) of RON and RTT impedance error within 64 nCK for all speed bins assuming the maximum sensitivities specified in the Output Driver and ODT Voltage and Temperature Sensitivity tables. The appropriate in- terval between ZQCS commands can be determined from these tables and other appli- cation-specific parameters. One method for calculating the interval between ZQCS commands, given the temperature (T drift_rate) and voltage (Vdrift_rate) drift rates that the device is subjected to in the application, is illustrated. The interval could be defined by the following formula: ZQcorrection (Tsense x Tdrift_rate) + (Vsense x Tdrift_rate) Where Tsense = MAX(dRTTdT , dRONdTM) and Vsense = MAX(dRTTdV , dRONdVM) define the temperature and voltage sensitivities. For example, if Tsens = 1.5%/°C, Vsens = 0.15%/mV , Tdriftrate = 1 °C/sec and Vdriftrate = 15 mV/sec, then the interval between ZQCS commands is calculated as: 0.5 = 0.133 §128ms No other activities should be performed on the DRAM channel by the controller for the duration of tZQinit, tZQoper, or tZQCS. The quiet time on the DRAM channel allows ac- curate calibration of output driver and on-die termination values. After DRAM calibra- tion is achieved, the device should disable the ZQ current consumption path to reduce power. All banks must be precharged and tRP met before ZQCL or ZQCS commands are issued by the controller. ZQ CALIBRATION commands can also be issued in parallel to DLL lock time when coming out of self refresh. Upon self refresh exit, the device will not perform an I/O cali- 16Gb: x4, x8, x16 DDR4 SDRAM ZQ CALIBRATION Commands CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 251 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

bration without an explicit ZQ CALIBRATION command. The earliest possible time for a ZQ CALIBRATION command (short or long) after self refresh exit is tXS, tXS_Abort, or tXS_FAST depending on operation mode. In systems that share the ZQ resistor between devices, the controller must not allow any overlap of tZQoper, tZQinit, or tZQCS between the devices. Figure 198: ZQ Calibration Timing T0 T1 Ta0 DQ Bus tZQinit_tZQoper Don’t Care Ta1 Ta2 Ta3 Tb0 Tb1 Tc0 Tc1 Tc2 ZQCS DES DES DES Valid Valid Valid Valid Valid Command DES ZQCL DES DES Valid Valid Valid Valid High-Z or RTT(Park) Activities Note 3 Note 2 Note 1 ActivitiesHigh-Z or RTT(Park) Time Break Address Valid Valid Valid Valid A10 CKE Valid ValidODT CK_t CK_c tZQCS Notes: 1. CKE must be continuously registered HIGH during the calibration procedure. 2. During ZQ calibration, the ODT signal must be held LOW and DRAM continues to pro- vide RTT_PARK. 3. All devices connected to the DQ bus should be High-Z during the calibration procedure. 16Gb: x4, x8, x16 DDR4 SDRAM ZQ CALIBRATION Commands CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 252 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

The on-die termination (ODT) feature enables the device to change termination resist- ance for each DQ, DQS, and DM_n/DBI_n signal for x4 and x8 configurations (and TDQS for the x8 configuration when enabled via A11 = 1 in MR1) via the ODT control pin, WRITE command, or default parking value with MR setting. For the x16 configura- tion, ODT is applied to each UDQ, LDQ, UDQS, LDQS, UDM_n/UDBI_n, and LDM_n/ LDBI_n signal. The ODT feature is designed to improve the signal integrity of the mem- ory channel by allowing the DRAM controller to independently change termination re- sistance for any or all DRAM devices. If DBI read mode is enabled while the DRAM is in standby, either DM mode or DBI write mode must also be enabled if R TT(NOM) or RTT(Park) is desired. More details about ODT control modes and ODT timing modes can be found further along in this document. The ODT feature is turned off and not supported in self refresh mode. Figure 199: Functional Representation of ODT ODT VDDQ RTT Switch DQ, DQS, DM, TDQS To other circuitry such as RCV, . . . The switch is enabled by the internal ODT control logic, which uses the external ODT pin and other control information. The value of RTT is determined by the settings of mode register bits (see Mode Register). The ODT pin will be ignored if the mode register MR1 is programmed to disable R TT(NOM) [MR1[10,9,8] = 0,0,0] and in self refresh mode. ODT Mode Register and ODT State Table The ODT mode of the DDR4 device has four states: data termination disable, RTT(NOM), RTT(WR), and RTT(Park). The ODT mode is enabled if any of MR1[10:8] (RTT(NOM)), MR2[11:9] (RTT(WR)), or MR5[8:6] (RTT(Park)) are non-zero. When enabled, the value of RTT is determined by the settings of these bits. RTT control of each RTT condition is possible with a WR or RD command and ODT pin.

• R TT(WR): The DRAM (rank) that is being written to provide termination regardless of ODT pin status (either HIGH or LOW).
• R TT(NOM): DRAM turns ON RTT(NOM) if it sees ODT asserted HIGH (except when ODT is disabled by MR1).
• R TT(Park): Default parked value set via MR5 to be enabled and RTT(NOM) is not turned on.
• The Termination State Table that follows shows various interactions. The RTT values have the following priority:
• Data termination disable
• R TT(WR)
• R TT(NOM)
• R TT(Park) 16Gb: x4, x8, x16 DDR4 SDRAM On-Die Termination CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 253 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Table 70: Termination State Table Case RTT(Park) RTT(NOM)1 RTT(WR)2 ODT Pin ODT READS3 ODT Stand- by7 ODT WRITES A4 Disabled Disabled Disabled Don't Care Off (High-Z) Off (High-Z) Off (High-Z) Enabled Don't Care Off (High-Z) Off (High-Z) R TT(WR) B5 Enabled Disabled Disabled Don't Care Off (High-Z) R TT(Park) RTT(Park) Enabled Don't Care Off (High-Z) R TT(Park) RTT(WR) C6 Disabled Enabled Disabled Low Off (High-Z) Off (High-Z) Off (High-Z) High Off (High-Z) R TT(NOM) RTT(NOM) Enabled Low Off (High-Z) Off (High-Z) R TT(WR) High Off (High-Z) R TT(NOM) RTT(WR) D6 Enabled Enabled Disabled Low Off (High-Z) R TT(Park) RTT(Park) High Off (High-Z) R TT(NOM) RTT(NOM) Enabled Low Off (High-Z) R TT(Park) RTT(WR) High Off (High-Z) R TT(NOM) RTT(WR) Notes: 1. If R TT(NOM) MR is disabled, power to the ODT receiver will be turned off to save power. 2. If R TT(WR) is enabled, RTT(WR) will be activated by a WRITE command for a defined period time independent of the ODT pin and MR setting of RTT(Park)/RTT(NOM). This is described in the Dynamic ODT section. 3. When a READ command is executed, the DRAM termination state will be High-Z for a defined period independent of the ODT pin and MR setting of RTT(Park)/RTT(NOM). This is described in the ODT During Read section. 4. Case A is generally best for single-rank memories. 5. Case B is generally best for dual-rank, single-slotted memories. 6. Case C and Case D are generally best for multi-slotted memories. 7. The ODT feature is turned off and not supported in self refresh mode. ODT Read Disable State Table Upon receiving a READ command, the DRAM driving data disables ODT after RL - (2 or 3) clock cycles, where 2 = 1tCK preamble mode and 3 = 2tCK preamble mode. ODT stays off for a duration of BL/2 + (2 or 3) + (0 or 1) clock cycles, where 2 = 1tCK preamble mode, 3 = 2tCK preamble mode, 0 = CRC disabled, and 1 = CRC enabled. Table 71: Read Termination Disable Window Preamble CRC Start ODT Disable After Read Duration of ODT Disable 1tCK Disabled RL - 2 BL/2 + 2 Enabled RL - 2 BL/2 + 3 2tCK Disabled RL - 3 BL/2 + 3 Enabled RL - 3 BL/2 + 4 16Gb: x4, x8, x16 DDR4 SDRAM ODT Mode Register and ODT State Table CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 254 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Synchronous ODT mode is selected whenever the DLL is turned on and locked. Based on the power-down definition, these modes include the following:

• Any bank active with CKE HIGH
• Refresh with CKE HIGH
• Idle mode with CKE HIGH
• Active power-down mode
• Precharge power-down mode In synchronous ODT mode, R TT(NOM) will be turned on DODTLon clock cycles after ODT is sampled HIGH by a rising clock edge and turned off DODTLoff clock cycles after ODT is registered LOW by a rising clock edge. The ODT latency is determined by the programmed values for: CAS WRITE latency (CWL), additive latency (AL), and parity la- tency (PL), as well as the programmed state of the preamble. ODT Latency and Posted ODT The ODT latencies for synchronous ODT mode are summarized in the table below. For details, refer to the latency definitions. Table 72: ODT Latency at DDR4-1600/-1866/-2133/-2400/-2666/-3200 Applicable when write CRC is disabled Symbol Parameter 1tCK Preamble 2tCK Preamble Unit DODTLon Direct ODT turn-on latency CWL + AL + PL - 2 CWL + AL + PL - 3 tCK DODTLoff Direct ODT turn-off latency CWL + AL + PL - 2 CWL + AL + PL - 3 RODTLoff READ command to internal ODT turn-off latency CL + AL + PL - 2 CL + AL + PL - 3 RODTLon4 READ command to R TT(Park) turn-on la- tency in BC4-fixed RODTLoff + 4 RODTLoff + 5 RODTLon8 READ command to R TT(Park) turn-on la- tency in BL8/BC4-OTF RODTLoff + 6 RODTLoff + 7 ODTH4 ODT Assertion time, BC4 mode 4 5 ODTH8 ODT Assertion time, BL8 mode 6 7 Timing Parameters In synchronous ODT mode, the following parameters apply:
• DODTLon, DODTLoff, RODTLoff, RODTLon4, RODTLon8, and tADC (MIN)/(MAX).
• tADC (MIN) and tADC (MAX) are minimum and maximum RTT change timing skew between different termination values. These timing parameters apply to both the syn- chronous ODT mode and the data termination disable mode. When ODT is asserted, it must remain HIGH until minimum ODTH4 (BC = 4) or ODTH8 (BL = 8) is satisfied. If write CRC mode or 2 tCK preamble mode is enabled, ODTH should be adjusted to account for it. ODTHx is measured from ODT first regis- tered HIGH to ODT first registered LOW or from the registration of a WRITE command. 16Gb: x4, x8, x16 DDR4 SDRAM Synchronous ODT Mode CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 255 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Because the DRAM cannot terminate with RTT and drive with RON at the same time, RTT may nominally not be enabled until the end of the postamble as shown in the example below. At cycle T26 the device turns on the termination when it stops driving, which is determined by tHZ. If the DRAM stops driving early (that is, tHZ is early), then tADC (MIN) timing may apply. If the DRAM stops driving late (that is, tHZ is late), then the DRAM complies with tADC (MAX) timing. Using CL = 11 as an example for the figure below: PL = 0, AL = CL - 1 = 10, RL = PL + AL + CL = 21, CWL= 9; RODTLoff = RL - 2 = 19, DODTLon = PL + AL + CWL - 2 = 17, 1tCK preamble. Figure 202: ODT During Reads GLIIB&. '2'7/RQ :/ 5/ $/&/3/ 52'7/RII 5/ &RPPDQG 2'7 '46B2'7 W&.3UHDPEOH 577 3DUN W$'& 0,1 W$'& 0$; 77 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 W$'& 0,1 W$'& 0$; $GGUHVV $ '46GLII 7UDQVLWLRQLQJ 577 120 '46B2'7 W&.3UHDPEOH 577 3DUN W$'& 0,1 W$'& 0$; W$'& 0,1 W$'& 0$; 577 120 '4B2'7 W&.3UHDPEOH 577 3DUN W$'& 0,1 W$'& 0$; Q&. W$'& 0$; Q&. W$'& 0,1 W$'& 0$; 577 120 '4B2'7 W&.3UHDPEOH 577 3DUN W$'& 0,1 W$'& 0,1 W$'& 0$; 577 120 16Gb: x4, x8, x16 DDR4 SDRAM Synchronous ODT Mode CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 257 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

In certain application cases and to further enhance signal integrity on the data bus, it is desirable that the termination strength of the device can be changed without issuing an MRS command. This requirement is supported by the dynamic ODT feature. Functional Description Dynamic ODT mode is enabled if bit A9 or A10 of MR2 is set to 1.

• Three R TT values are available: RTT(NOM), RTT(WR), and RTT(Park). – The value for R TT(NOM) is preselected via bits MR1[10:8]. – The value for R TT(WR) is preselected via bits MR2[11:9]. – The value for R TT(Park) is preselected via bits MR5[8:6].
• During operation without WRITE commands, the termination is controlled as fol- lows: – Nominal termination strength R TT(NOM) or RTT(Park) is selected. –R TT(NOM) on/off timing is controlled via ODT pin and latencies DODTLon and DODTLoff, and RTT(Park) is on when ODT is LOW .
• When a WRITE command (WR, WRA, WRS4, WRS8, WRAS4, and WRAS8) is regis- tered, and if dynamic ODT is enabled, the termination is controlled as follows: – Latency ODTLcnw after the WRITE command, termination strength R TT(WR) is se- lected. – Latency ODTLcwn8 (for BL8, fixed by MRS or selected OTF) or ODTLcwn4 (for BC4, fixed by MRS or selected OTF) after the WRITE command, termination strength R TT(WR) is de-selected. One or two clocks will be added into or subtracted from ODTLcwn8 and ODTLcwn4, depending on write CRC mode and/or 2tCK preamble enablement. The following table shows latencies and timing parameters relevant to the on-die termi- nation control in dynamic ODT mode. The dynamic ODT feature is not supported in DLL-off mode. An MRS command must be used to set R TT(WR) to disable dynamic ODT externally (MR2[11:9] = 000). Table 73: Dynamic ODT Latencies and Timing (1tCK Preamble Mode and CRC Disabled) Name and Descrip- tion Abbr. Defined from Defined to 1600/1866/ 2133/2400 2666 2933/3200 Unit ODT latency for change from RTT(Park)/ RTT(NOM) to RTT(WR) ODTLc nw Registering ex- ternal WRITE command Change RTT strength from RTT(Park)/ RTT(NOM) to RTT(WR) ODTLcnw = WL - 2 tCK ODT latency for change from RTT(WR) to RTT(Park)/RTT(NOM) (BC = ODTLc wn4 Registering ex- ternal WRITE command Change RTT strength from RTT(WR) to RTT(Park)/ RTT(NOM) ODTLcwn4 = 4 + ODTLcnw tCK ODT latency for change from RTT(WR) to RTT(Park)/RTT(NOM) (BL = ODTLc wn8 Registering ex- ternal WRITE command Change RTT strength from RTT(NOM) to RTT(WR) ODTLcwn8 = 6 + ODTLcnw tCK (AVG) 16Gb: x4, x8, x16 DDR4 SDRAM Dynamic ODT CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 258 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Table 73: Dynamic ODT Latencies and Timing (1tCK Preamble Mode and CRC Disabled) (Continued) Name and Descrip- tion Abbr. Defined from Defined to 1600/1866/ 2133/2400 2666 2933/3200 Unit RTT change skew tADC ODTLcnw ODTLcwn RTT valid tADC (MIN) = 0.30 tADC (MAX) = 0.70 tADC (MIN) = 0.28 tADC (MAX) = 0.72 tADC (MIN) = 0.26 tADC (MAX) = 0.74 tCK (AVG) Table 74: Dynamic ODT Latencies and Timing with Preamble Mode and CRC Mode Matrix Symbol 1tCK Parameter 2tCK Parameter UnitCRC Off CRC On CRC Off CRC On ODTLcnw1 WL - 2 WL - 2 WL - 3 WL - 3 tCK ODTLcwn4 ODTLcnw + 4 ODTLcnw + 7 ODTLcnw + 5 ODTLcnw + 8 ODTLcwn8 ODTLcnw + 6 ODTLcnw + 7 ODTLcnw + 7 ODTLcnw + 8 Note: 1. ODTLcnw = WL - 2 (1 tCK preamble) or WL - 3 (2tCK preamble). Figure 203: Dynamic ODT (1t CK Preamble; CL = 14, CWL = 11, BL = 8, AL = 0, CRC Disabled) diff_CK ODTLcwn ODTLcnw DODTLon = WL - 2 DODTLoff = WL - 2 Command ODT RTT RTT(Park) RTT(NOM) RTT(Park)RTT(WR) tADC (MAX) tADC (MAX) T1T0 T2 T5 T6 T7 T14 T8 T9 T10 T11 T15 T16 T17 T18 T19 T20 T21 T22 T23 T24 tADC (MIN)tADC (MIN)tADC (MIN)tADC (MIN) tADC (MAX) RTT(Park) tADC (MAX) WR Transitioning Notes: 1. ODTLcnw = WL - 2 (1 tCK preamble) or WL - 3 (2tCK preamble). 2. If BC4, then ODTLcwn = WL + 4 if CRC disabled or WL + 5 if CRC enabled; If BL8, then ODTLcwn = WL + 6 if CRC disabled or WL + 7 if CRC enabled. 16Gb: x4, x8, x16 DDR4 SDRAM Dynamic ODT CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 259 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Figure 204: Dynamic ODT Overlapped with RTT(NOM) (CL = 14, CWL = 11, BL = 8, AL = 0, CRC Disabled) diff_CK Command ODT T1T0 T2 T5 T6 T7 T25T12T9 T10 T11 T15 T16 T17 T18 T19 T20 T21 T22 T23 T24 WR ODTLcnw DODTLoff = CWL -2 ODTLcwn8 RTT RTT_NOM RTT_NOM RTT_PARKRTT_WR tADC (MAX) tADC (MAX) tADC (MIN)tADC (MIN)tADC (MIN) tADC (MAX) Note: 1. Behavior with WR command issued while ODT is registered HIGH. 16Gb: x4, x8, x16 DDR4 SDRAM Dynamic ODT CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 260 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Asynchronous ODT mode is selected when the DRAM runs in DLL-off mode. In asyn- chronous ODT timing mode, the internal ODT command is not delayed by either addi- tive latency (AL) or the parity latency (PL) relative to the external ODT signal (RTT(NOM)). In asynchronous ODT mode, two timing parameters apply: tAONAS (MIN/MAX), and tAOFAS (MIN/MAX). RTT(NOM) Turn-on Time

• Minimum R TT(NOM) turn-on time (tAONAS [MIN]) is when the device termination cir- cuit leaves RTT(Park) and ODT resistance begins to turn on.
• Maximum R TT(NOM) turn-on time (tAONAS [MAX]) is when the ODT resistance has reached RTT(NOM).
• tAONAS (MIN) and tAONAS (MAX) are measured from ODT being sampled HIGH. RTT(NOM) Turn-off Time
• Minimum R TT(NOM) turn-off time (tAOFAS [MIN]) is when the device's termination circuit starts to leave RTT(NOM).
• Maximum R TT(NOM) turn-off time (tAOFAS [MAX]) is when the on-die termination has reached RTT(Park).
• tAOFAS (MIN) and tAOFAS (MAX) are measured from ODT being sampled LOW . Figure 205: Asynchronous ODT Timings with DLL Off diff_CK tAONAS (MAX) CKE ODT RTT RTT(Park) RTT(NOM) tAONAS (MIN) tAONAS (MAX) tAONAS (MIN) tIH tIS tIH tIS T1T0 T2 T3 T4 T5 T6 Ti Ti + 1 Ti + 2 Ti + 3 Ti + 4 Ti + 5 Ti + 6 Ta Tb Transitioning 16Gb: x4, x8, x16 DDR4 SDRAM Asynchronous ODT Mode CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 261 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other condi- tions outside those indicated in the operational sections of this specification is not im- plied. Exposure to absolute maximum rating conditions for extended periods may ad- versely affect reliability. Although "unlimited" row accesses to the same row is allowed within the refresh period; excessive row accesses to the same row over a long term can result in degraded operation. Table 75: Absolute Maximum Ratings Symbol Parameter Min Max Unit Notes VDD Voltage on VDD pin relative to VSS –0.4 1.5 V 1 VDDQ Voltage on VDDQ pin relative to VSS –0.4 1.5 V 1 VPP Voltage on VPP pin relative to VSS –0.4 3.0 V 3 VIN, VOUT Voltage on any pin relative to VSS –0.4 1.5 V TSTG Storage temperature –55 150 °C 2 Notes: 1. V DD and VDDQ must be within 300mV of each other at all times, and VREF must not be greater than 0.6 × VDDQ. When VDD and VDDQ are <500mV, VREF can be ื300mV. 2. Storage temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to the JESD51-2 standard. 3. V PP must be equal to or greater than VDD/VDDQ at all times when powered. DRAM Component Operating Temperature Range Operating temperature, TOPER, is the case surface temperature on the center/top side of the DRAM. For measurement conditions, refer to the JEDEC document JESD51-2. Table 76: Temperature Range Symbol Parameter Min Max Unit Notes TOPER Normal operating temperature range -40 85 °C 1 Extended temperature range (optional) >85 105 °C 2 Notes: 1. The normal temperature range specifies the temperatures at which all DRAM specifica- tions will be supported. During operation, the DRAM case temperature must be main- tained between 0°C to 85°C under all operating conditions for the commercial offering; The industrial and automotive temperature offerings allow the case temperature to go below 0°C to -40°C. 2. Some applications require operation of the commercial, industrial, and automotive tem- perature DRAMs in the extended temperature range (between 85°C and 105°C case temperature). Full specifications are supported in this range, but the following addition- al conditions apply:

• Refer to tREFI and tRFC parameters table for tREFI requirements when operating above 85°C
• If SELF REFRESH operation is required in the extended temperature range, it is manda- tory to use either the manual self refresh mode with extended temperature range ca- 16Gb: x4, x8, x16 DDR4 SDRAM Electrical Specifications CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 262 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

pability (MR2[6] = 0 and MR2 [7] = 1) or enable the optional auto self refresh mode Electrical Characteristics – AC and DC Operating Conditions Supply Operating Conditions Table 77: Recommended Supply Operating Conditions Symbol Parameter Rating Unit NotesMin Typ Max VDD Supply voltage 1.14 1.2 1.26 V 1, 2, 3, 4, 5 VDDQ Supply voltage for output 1.14 1.2 1.26 V 1, 2, 6 VPP Wordline supply voltage 2.375 2.5 2.750 V 7 Notes: 1. Under all conditions V DDQ must be less than or equal to VDD. 2. V DDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together. 3. V DD slew rate between 300mV and 80% of VDD,min shall be between 0.004 V/ms and 600 V/ms, 20 MHz band-limited measurement. 4. V DD ramp time from 300mV to VDD,min shall be no longer than 200ms. 5. A stable valid V DD level is a set DC level (0 Hz to 250 KHz) and must be no less than VDD,min and no greater than VDD,max. If the set DC level is altered anytime after initializa- tion, the DLL reset and calibrations must be performed again after the new set DC level is final. AC noise of ±60mV (greater than 250 KHz) is allowed on V DD provided the noise doesn't alter VDD to less than VDD,min or greater than VDD,max. 6. A stable valid V DDQ level is a set DC level (0 Hz to 250 KHz) and must be no less than VDDQ,min and no greater than VDDQ,max. If the set DC level is altered anytime after initial- ization, the DLL reset and calibrations must be performed again after the new set DC level is final. AC noise of ±60mV (greater than 250 KHz) is allowed on V DDQ provided the noise doesn't alter VDDQ to less than VDDQ,min or greater than VDDQ,max. 7. A stable valid V PP level is a set DC level (0 Hz to 250 KHz) and must be no less than VPP,min and no greater than VPP,max. If the set DC level is altered anytime after initializa- tion, the DLL reset and calibrations must be performed again after the new set DC level is final. AC noise of ±120mV (greater than 250 KHz) is allowed on V PP provided the noise doesn't alter VPP to less than VPP,min or greater than VPP,max. Table 78: VDD Slew Rate Symbol Min Max Unit Notes VDD_sl 0.004 600 V/ms 1, 2 VDD_on – 200 ms 3 Notes: 1. Measurement made between 300mV and 80% V DD (minimum level). 2. The DC bandwidth is limited to 20 MHz. 3. Maximum time to ramp V DD from 300 mV to VDD minimum. 16Gb: x4, x8, x16 DDR4 SDRAM Electrical Characteristics – AC and DC Operating Conditions CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 263 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Table 79: Leakages Condition Symbol Min Max Unit Notes Input leakage (excluding ZQ and TEN) I IN –2 2 μA 1 ZQ leakage I ZQ –50 10 μA 1 TEN leakage I TEN –6 10 μA 1, 2 VREFCA leakage I VREFCA –2 2 μA 3 Output leakage: VOUT = VDDQ IOZpd –1 0 μ A 4 Output leakage: VOUT = VSSQ IOZpu –50 – μA 4, 5 Notes: 1. Input under test 0V < V IN < 1.1V. 2. Additional leakage due to weak pull-down. 3. V REFCA = VDD/2, VDD at valid level after initialization. 4. DQs are disabled. 5. ODT is disabled with the ODT input HIGH. VREFCA Supply VREFCA is to be supplied to the DRAM and equal to VDD/2. The VREFCA is a reference sup- ply input and therefore does not draw biasing current. The DC-tolerance limits and AC-noise limits for the reference voltages VREFCA are illus- trated in the figure below. The figure shows a valid reference voltage VREF(t) as a function of time (VREF stands for VREFCA). VREF(DC) is the linear average of VREF(t) over a very long period of time (1 second). This average has to meet the MIN/MAX requirements. Fur- thermore, V REF(t) may temporarily deviate from VREF(DC) by no more than ±1% VDD for the AC-noise limit. Figure 206: VREFDQ Voltage Range VREF AC-noise VREF(DC) VREF(DC) MAX VREF(t) VREF(DC) MIN VDD/2 VSS Time Voltage VDD 16Gb: x4, x8, x16 DDR4 SDRAM Electrical Characteristics – AC and DC Operating Conditions CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 264 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

The voltage levels for setup and hold time measurements are dependent on VREF. VREF is understood as VREF(DC), as defined in the above figure. This clarifies that DC-variations of VREF affect the absolute voltage a signal has to reach to achieve a valid HIGH or LOW level, and therefore, the time to which setup and hold is measured. System timing and voltage budgets need to account for V REF(DC) deviations from the optimum position within the data-eye of the input signals. This also clarifies that the DRAM setup/hold specification and derating values need to include time and voltage associated with V REF AC-noise. Timing and voltage effects due to AC-noise on VREF up to the specified limit (±1% of VDD) are included in DRAM timings and their associated deratings. VREFDQ Supply and Calibration Ranges The device internally generates its own VREFDQ. DRAM internal VREFDQ specification pa- rameters: voltage range, step size, VREF step time, VREF full step time, and VREF valid level are used to help provide estimated values for the internal VREFDQ and are not pass/fail limits. The voltage operating range specifies the minimum required range for DDR4 SDRAM devices. The minimum range is defined by V REFDQ,min and VREFDQ,max. A cali- bration sequence should be performed by the DRAM controller to adjust VREFDQ and optimize the timing and voltage margin of the DRAM data input receivers. Table 80: VREFDQ Specification Parameter Symbol Min Typ Max Unit Notes Range 1 VREFDQ operating points V REFDQ R1 60% – 92% V DDQ 1, 2 Range 2 VREFDQ operating points V REFDQ R2 45% – 77% V DDQ 1, 2 VREF step size V REF,step 0.5% 0.65% 0.8% V DDQ 3 VREF set tolerance V REF,set_tol –1.625% 0% 1.625% V DDQ 4, 5, 6 VREF step time V REF,time – – 150 ns 9, 10, 11 VREF valid tolerance V REF_val_tol –0.15% 0% 0.15% V DDQ 12 Notes: 1. V REF(DC) voltage is referenced to VDDQ(DC). VDDQ(DC) is 1.2V. 2. DRAM range 1 or range 2 is set by the MRS6[6]6. 3. V REF step size increment/decrement range. VREF at DC level. 4. V REF,new = VREF,old ±n × VREF,step; n = number of steps. If increment, use “+,” if decrement, use “-.” 5. For n >4, the minimum value of V REF setting tolerance = VREF,new - 1.625% × VDDQ. The maximum value of VREF setting tolerance = VREF,new + 1.625% × VDDQ. 6. Measured by recording the MIN and MAX values of the V REF output over the range, drawing a straight line between those points, and comparing all other VREF output set- tings to that line. 7. For n ื4, the minimum value of VREF setting tolerance = VREF,new - 0.15% × VDDQ. The maximum value of VREF setting tolerance = VREF,new + 0.15% × VDDQ. 8. Measured by recording the MIN and MAX values of the V REF output across four consecu- tive steps (n = 4), drawing a straight line between those points, and comparing all VREF output settings to that line. 9. Time from MRS command to increment or decrement one step size for V REF. 10. Time from MRS command to increment or decrement more than one step size up to the full range of VREF. 11. If the V REF monitor is enabled, VREF must be derated by +10ns if DQ bus load is 0pF and an additional +15 ns/pF of DQ bus loading. 16Gb: x4, x8, x16 DDR4 SDRAM Electrical Characteristics – AC and DC Operating Conditions CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 265 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

1. Only applicable for DRAM component-level test/characterization purposes. Not applica- ble for normal mode of operation. VREF valid qualifies the step times, which will be char- acterized at the component level. VREFDQ Ranges MR6[6] selects range 1 (60% to 92.5% of VDDQ) or range 2 (45% to 77.5% of VDDQ), and MR6[5:0] sets the VREFDQ level, as listed in the following table. The values in MR6[6:0] will update the VDDQ range and level independent of MR6[7] setting. It is recommended MR6[7] be enabled when changing the settings in MR6[6:0], and it is highly recommen- ded MR6[7] be enabled when changing the settings in MR6[6:0] multiple times during a calibration routine. Table 81: V REFDQ Range and Levels MR6[5:0] MR6[6] 0 = Range 1 MR6[6] 1 = Range 2 MR6[5:0] MR6[6] 0 = Range 1 MR6[6] 1 = Range 2 00 0000 60.00% 45.00% 01 1010 76.90% 61.90% 00 0001 60.65% 45.65% 01 1011 77.55% 62.55% 00 0010 61.30% 46.30% 01 1100 78.20% 63.20% 00 0011 61.95% 46.95% 01 1101 78.85% 63.85% 00 0100 62.60% 47.60% 01 1110 79.50% 64.50% 00 0101 63.25% 48.25% 01 1111 80.15% 65.15% 00 0110 63.90% 48.90% 10 0000 80.80% 65.80% 00 0111 64.55% 49.55% 10 0001 81.45% 66.45% 00 1000 65.20% 50.20% 10 0010 82.10% 67.10% 00 1001 65.85% 50.85% 10 0011 82.75% 67.75% 00 1010 66.50% 51.50% 10 0100 83.40% 68.40% 00 1011 67.15% 52.15% 10 0101 84.05% 69.05% 00 1100 67.80% 52.80% 10 0110 84.70% 69.70% 00 1101 68.45% 53.45% 10 0111 85.35% 70.35% 00 1110 69.10% 54.10% 10 1000 86.00% 71.00% 00 1111 69.75% 54.75% 10 1001 86.65% 71.65% 01 0000 70.40% 55.40% 10 1010 87.30% 72.30% 01 0001 71.05% 56.05% 10 1011 87.95% 72.95% 01 0010 71.70% 56.70% 10 1100 88.60% 73.60% 01 0011 72.35% 57.35% 10 1101 89.25% 74.25% 01 0100 73.00% 58.00% 10 1110 89.90% 74.90% 01 0101 73.65% 58.65% 10 1111 90.55% 75.55% 01 0110 74.30% 59.30% 11 0000 91.20% 76.20% 01 0111 74.95% 59.95% 11 0001 91.85% 76.85% 01 1000 75.60% 60.60% 11 0010 92.50% 77.50% 01 1001 76.25% 61.25% 11 0011 to 11 1111 are reserved 16Gb: x4, x8, x16 DDR4 SDRAM Electrical Characteristics – AC and DC Operating Conditions CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 266 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Electrical Characteristics – AC and DC Single-Ended Input Measurement Levels RESET_n Input Levels Table 82: RESET_n Input Levels (CMOS) Parameter Symbol Min Max Unit Note AC input high voltage V IH(AC)_RESET 0.8 × VDD VDD V1 DC input high voltage V IH(DC)_RESET 0.7 × VDD VDD V2 DC input low voltage V IL(DC)_RESET VSS 0.3 × VDD V3 AC input low voltage V IL(AC)_RESET VSS 0.2 × VDD V4 Rising time tR_RESET – 1 μs 5 RESET pulse width after power-up tPW_RESET_S 1 – μs 6, 7 RESET pulse width during power-up tPW_RESET_L 200 – μs 6 Notes: 1. Overshoot should not exceed the V IN shown in the Absolute Maximum Ratings table. 2. After RESET_n is registered HIGH, the RESET_n level must be maintained above VIH(DC)_RESET, otherwise operation will be uncertain until it is reset by asserting RESET_n signal LOW. 3. After RESET_n is registered LOW, the RESET_n level must be maintained below V IL(DC)_RE- SET during tPW_RESET, otherwise the DRAM may not be reset. 4. Undershoot should not exceed the V IN shown in the Absolute Maximum Ratings table. 5. Slope reversal (ring-back) during this level transition from LOW to HIGH should be miti- gated as much as possible. 6. RESET is destructive to data contents. 7. See RESET Procedure at Power Stable Condition figure. Figure 207: RESET_n Input Slew Rate Definition tR_RESET tPW_RESET VIH(AC)_RESET,min VIL(AC)_RESET,max VIH(DC)_RESET,min VIL(DC)_RESET,max Command/Address Input Levels Table 83: Command and Address Input Levels: DDR4-1600 Through DDR4-2400 Parameter Symbol Min Max Unit Note AC input high voltage V IH(AC) VREF + 100 V DD5 mV 1, 2, 3 DC input high voltage V IH(DC) VREF + 75 V DD mV 1, 2 16Gb: x4, x8, x16 DDR4 SDRAM Electrical Characteristics – AC and DC Single-Ended Input Measurement Levels CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 267 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Table 83: Command and Address Input Levels: DDR4-1600 Through DDR4-2400 (Continued) Parameter Symbol Min Max Unit Note DC input low voltage V IL(DC) VSS VREF - 75 mV 1, 2 AC input low voltage V IL(AC) VSS5V REF - 100 mV 1, 2, 3 Reference voltage for CMD/ADDR inputs V REFFCA(DC) 0.49 × VDD 0.51 × VDD V4 Notes: 1. For input except RESET_n. V REF = VREFCA(DC). 2. V REF = VREFCA(DC). 3. Input signal must meet V IL/VIH(AC) to meet tIS timings and VIL/VIH(DC) to meet tIH timings. 4. The AC peak noise on V REF may not allow VREF to deviate from VREFCA(DC) by more than ±1% VDD (for reference: approximately ±12mV). 5. Refer to “Overshoot and Undershoot Specifications.” Table 84: Command and Address Input Levels: DDR4-2666 Parameter Symbol Min Max Unit Note AC input high voltage V IH(AC) VREF + 90 V DD5 mV 1, 2, 3 DC input high voltage V IH(DC) VREF + 65 V DD mV 1, 2 DC input low voltage V IL(DC) VSS VREF - 65 mV 1, 2 AC input low voltage V IL(AC) VSS5V REF - 90 mV 1, 2, 3 Reference voltage for CMD/ADDR inputs V REFFCA(DC) 0.49 × VDD 0.51 × VDD V4 Notes: 1. For input except RESET_n. V REF = VREFCA(DC). 2. V REF = VREFCA(DC). 3. Input signal must meet V IL/VIH(AC) to meet tIS timings and VIL/VIH(DC) to meet tIH timings. 4. The AC peak noise on V REF may not allow VREF to deviate from VREFCA(DC) by more than ±1% VDD (for reference: approximately ±12mV). 5. Refer to “Overshoot and Undershoot Specifications.” Table 85: Command and Address Input Levels: DDR4-2933 and DDR4-3200 Parameter Symbol Min Max Unit Note AC input high voltage V IH(AC) VREF + 90 V DD5 mV 1, 2, 3 DC input high voltage V IH(DC) VREF + 65 V DD mV 1, 2 DC input low voltage V IL(DC) VSS VREF - 65 mV 1, 2 AC input low voltage V IL(AC) VSS5V REF - 90 mV 1, 2, 3 Reference voltage for CMD/ADDR inputs V REFFCA(DC) 0.49 × VDD 0.51 × VDD V4 Notes: 1. For input except RESET_n. V REF = VREFCA(DC). 2. V REF = VREFCA(DC). 3. Input signal must meet V IL/VIH(AC) to meet tIS timings and VIL/VIH(DC) to meet tIH timings. 4. The AC peak noise on V REF may not allow VREF to deviate from VREFCA(DC) by more than ±1% VDD (for reference: approximately ±12mV). 5. Refer to “Overshoot and Undershoot Specifications.” 16Gb: x4, x8, x16 DDR4 SDRAM Electrical Characteristics – AC and DC Single-Ended Input Measurement Levels CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 268 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Table 86: Single-Ended Input Slew Rates Parameter Symbol Min Max Unit Note Single-ended input slew rate – CA SR CA 1.0 7.0 V/ns 1, 2, 3, 4 Notes: 1. For input except RESET_n. 2. V REF = VREFCA(DC). 3. tIS/tIH timings assume SRCA = 1V/ns. 4. Measured between V IH(AC) and VIL(AC) for falling edges and between VIL(AC) and VIH(AC) for rising edges Figure 208: Single-Ended Input Slew Rate Definition TRseTFse VIH(DC) VIH(AC) VIL(AC) VIL(DC) VREFCA Command, Control, and Address Setup, Hold, and Derating The total tIS (setup time) and tIH (hold time) required is calculated to account for slew rate variation by adding the data sheet tIS (base) values, the VIL(AC)/VIH(AC) points, and tIH (base) values, the VIL(DC)/VIH(DC) points; to the ˂tIS and ˂tIH derating values, re- spectively. The base values are derived with single-end signals at 1V/ns and differential clock at 2 V/ns. Example: tIS (total setup time) = tIS (base) + ˂tIS. For a valid transition, the input signal has to remain above/below VIH(AC)/VIL(AC) for the time defined by tVAC. Although the total setup time for slow slew rates might be negative (for example, a valid input signal will not have reached VIH(AC)/VIL(AC) at the time of the rising clock transi- tion), a valid input signal is still required to complete the transition and to reach V IH(AC)/VIL(AC). For slew rates that fall between the values listed in derating tables, the derating values may be obtained by linear interpolation. Setup (tIS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(DC)max and the first crossing of VIH(AC)min that does not ring back be- low VIH(DC)min . Setup (tIS) nominal slew rate for a falling signal is defined as the slew 16Gb: x4, x8, x16 DDR4 SDRAM Electrical Characteristics – AC and DC Single-Ended Input Measurement Levels CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 269 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

rate between the last crossing of VIH(DC)min and the first crossing of VIL(AC)max that does not ring back above VIL(DC)max. Hold (tIH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(DC)max and the first crossing of VIH(AC)min that does not ring back be- low VIH(DC)min. Hold (tIH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VIH(DC)min and the first crossing of VIL(AC)minthat does not ring back above VIL(DC)max. Table 87: Command and Address Setup and Hold Values Referenced – AC/DC-Based Symbol 1600 1866 2133 2400 2666 2933 3200 Unit Reference tIS(base, AC100) 115 100 80 62 – – – ps V IH(AC)/VIL(AC) tIH(base, DC75) 140 125 105 87 – – – ps V IH(DC)/VIL(DC) tIS(base, AC90) –––– 5 5 4 8 4 0 p s V IH(AC)/VIL(AC) tIH(base, DC65) –––– 8 0 7 3 6 5 p s V IH(DC)/VIL(DC) tIS/tIH(Vref) 215 200 180 162 145 138 130 ps V IH(DC)/VIL(DC) Table 88: Derating Values for tIS/tIH – AC100DC75-Based ˂˂tIS with AC100 Threshold, ˂tIH with DC75 Threshold Derating (ps) – AC/DC-Based CMD/ ADDR Slew Rate V/ns CK, CK# Differential Slew Rate 7.0 76 54 76 55 77 56 79 58 82 60 86 64 94 73 111 89 6.0 73 53 74 53 75 54 77 56 79 58 83 63 92 71 108 88 5.0 70 50 71 51 72 52 74 54 76 56 80 60 88 68 105 85 4.0 65 46 66 47 67 48 69 50 71 52 75 56 83 65 100 81 3.0 57 40 57 41 58 42 60 44 63 46 67 50 75 58 92 75 2.0 40 28 41 28 42 29 44 31 46 33 50 38 58 46 75 63 1.5 23 15 24 16 25 17 27 19 29 21 33 25 42 33 58 50 16Gb: x4, x8, x16 DDR4 SDRAM Electrical Characteristics – AC and DC Single-Ended Input Measurement Levels CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 270 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Table 89: Derating Values for tIS/tIH – AC90/DC65-Based ˂˂tIS with AC90 Threshold, ˂tIH with DC65 Threshold Derating (ps) – AC/DC-Based CMD/ ADDR Slew Rate V/ns CK, CK# Differential Slew Rate 7.0 68 47 69 47 70 48 72 50 73 52 77 56 85 63 100 78 6.0 66 45 67 46 68 47 69 49 71 50 75 54 83 62 98 77 5.0 63 43 64 44 65 45 66 46 68 48 72 52 80 60 95 75 4.0 59 40 59 40 60 41 62 43 64 45 68 49 75 56 90 71 3.0 51 34 52 35 53 36 54 38 56 40 60 43 68 51 83 66 2.0 36 24 37 24 38 25 39 27 41 29 45 33 53 40 68 55 1.5 21 13 22 13 23 14 24 16 26 18 30 22 38 29 53 44 Data Receiver Input Requirements The following parameters apply to the data receiver Rx MASK operation detailed in the Write Timing section, Data Strobe-to-Data Relationship. The rising edge slew rates are defined by srr1 and srr2. The slew rate measurement points for a rising edge are shown in the figure below. A LOW-to-HIGH transition time, tr1, is measured from 0.5 × V diVW,max below VCENTDQ,midpoint to the last transition through 0.5 × VdiVW,max above VCENTDQ,midpoint; tr2 is measured from the last transition through 0.5 × VdiVW,max above VCENTDQ,midpoint to the first transition through the 0.5 × VIHL(AC)min above VCENTDQ,midpoint. The falling edge slew rates are defined by srf1 and srf2. The slew rate measurement points for a falling edge are shown in the figure below. A HIGH-to-LOW transition time, tf1, is measured from 0.5 × V diVW,max above VCENTDQ,midpoint to the last transition through 0.5 × VdiVW,max below VCENTDQ,midpoint; tf2 is measured from the last transition through 0.5 × VdiVW,max below VCENTDQ,midpoint to the first transition through the 0.5 × VIHL(AC)min below VCENTDQ,midpoint. 16Gb: x4, x8, x16 DDR4 SDRAM Electrical Characteristics – AC and DC Single-Ended Input Measurement Levels CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 271 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Figure 209: DQ Slew Rate Definitions VIHL(AC)min 0.5 × VIHL(AC)min 0.5 × VIHL(AC)min VIHL(AC)min 0.5 × VIHL(AC)min 0.5 × VIHL(AC)min 0.5 × VdiVW,max 0.5 × VdiVW,max VCENTDQ,midpoint VdiVW,max 0.5 × VdiVW,max 0.5 × VdiVW,max VdiVW,max tr1 tr2 VCENTDQ,midpoint tf1 tf2 Rx Mask Rx Mask Notes: 1. Rising edge slew rate equation srr1 = V diVW,max/(tr1). 2. Rising edge slew rate equation srr2 = (V IHL(AC)min - VdiVW,max )/(2 × tr2). 3. Falling edge slew rate equation srf1 = V diVW,max/(tf1). 4. Falling edge slew rate equation srf2 = (V IHL(AC)min - VdiVW,max )/(2 × tf2). Table 90: DQ Input Receiver Specifications Note 1 applies to the entire table Parameter Symbol DDR4-1600, 1866, 2133 DDR4-2400 DDR4-2666 DDR4-2933 DDR4-3200 Unit Not esMin Max Min Max Min Max Min Max Min Max VIN Rx mask input peak-to-peak VdiVW – 136 – 130 – 120 – 115 – 110 mV 2, 3 DQ Rx input tim- ing window DQ AC input swing peak-to- peak V IHL(AC) 186 – 160 – 150 – 145 – 140 – mV 4, 5 16Gb: x4, x8, x16 DDR4 SDRAM Electrical Characteristics – AC and DC Single-Ended Input Measurement Levels CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 272 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Table 90: DQ Input Receiver Specifications (Continued) Note 1 applies to the entire table Parameter Symbol DDR4-1600, 1866, 2133 DDR4-2400 DDR4-2666 DDR4-2933 DDR4-3200 Unit Not esMin Max Min Max Min Max Min Max Min Max DQ input pulse width DQS-to-DQ Rx mask offset tDQS2D Q DQ-to-DQ Rx mask offset Input slew rate over VdiVW if tCK ุ 0.937ns srr1, srf1 1 9 1 9 1 9 1 9 1 9 V/ns 9 Input slew rate over VdiVW if 0.937ns > tCK ุ 0.625ns srr1, srf1 – – 1.25 9 1.25 9 1.25 9 1.25 9 V/ns 9 Rising input slew rate over 1/2 V IHL(AC) srr2 0.2 × srr1 9 0.2 × srr1 9 0.2 × srr1 9 0.2 × srr1 9 0.2 × srr1

9 V/ns 10

V IHL(AC) srf2 0.2 × srf1 9 0.2 × srf1 9 0.2 × srf1 9 0.2 × srf1 9 0.2 × srf1 Notes: 1. All Rx mask specifications must be satisfied for each UI. For example, if the minimum in- put pulse width is violated when satisfying TdiVW (MIN), VdiVW,max, and minimum slew rate limits, then either TdiVW (MIN) or minimum slew rates would have to be increased to the point where the minimum input pulse width would no longer be violated. 2. Data Rx mask voltage and timing total input valid window where V diVW is centered around VCENTDQ,midpoint after VREFDQ training is completed. The data Rx mask is applied per bit and should include voltage and temperature drift terms. The input buffer design specification is to achieve at least a BER =1 e- 16 when the Rx mask is not violated. 3. Defined over the DQ internal V REF range 1. 4. Overshoot and undershoot specifications apply. 5. DQ input pulse signal swing into the receiver must meet or exceed V IHL(AC)min. VIHL(AC)min is to be achieved on an UI basis when a rising and falling edge occur in the same UI (a valid TdiPW). 6. DQ minimum input pulse width defined at the V CENTDQ,midpoint. 7. DQS-to-DQ Rx mask offset is skew between DQS and DQ within a nibble (x4) or word (x8, x16 [for x16, the upper and lower bytes are treated as separate x8s]) at the SDRAM balls over process, voltage, and temperature. 8. DQ-to-DQ Rx mask offset is skew between DQs within a nibble (x4) or word (x8, x16) at the SDRAM balls for a given component over process, voltage, and temperature. 9. Input slew rate over V diVW mask centered at VCENTDQ,midpoint. Slowest DQ slew rate to fastest DQ slew rate per transition edge must be within 1.7V/ns of each other. 10. Input slew rate between V diVW mask edge and VIHL(AC)min points. The following figure shows the Rx mask relationship to the input timing specifications relative to system tDS and tDH. The classical definition for tDS/tDH required a DQ rising 16Gb: x4, x8, x16 DDR4 SDRAM Electrical Characteristics – AC and DC Single-Ended Input Measurement Levels CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 273 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

and falling edges to not violate tDS and tDH relative to the DQS strobe at any time; how- ever, with the Rx mask tDS and tDH can shift relative to the DQS strobe provided the input pulse width specification is satisfied and the Rx mask is not violated. Figure 210: Rx Mask Relative to tDS/tDH tDH = Greater of 0.5 × TdiVW or 0.5 × (TdiPW + VdiVW/tr1) tDS = Greater of 0.5 × TdiVW or 0.5 × (TdiPW + VdiVW/tf1) VdiVW 0.5 × VdiVW tf1 tr1 0.5 × VdiVW TdiPW TdiVW VCENTDQ,pin mean VIL(DC) VIH(DC) DQS_c DQS_t Rx Mask The following figure and table show an example of the worst case Rx mask required if the DQS and DQ pins do not have DRAM controller to DRAM write DQ training. The figure and table show that without DRAM write DQ training, the Rx mask would in- crease from 0.2UI to essentially 0.54UI. This would also be the minimum tDS and tDH required as well. 16Gb: x4, x8, x16 DDR4 SDRAM Electrical Characteristics – AC and DC Single-Ended Input Measurement Levels CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 274 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Figure 211: Rx Mask Without Write Training tDS VdiVW 0.5 × VdiVW 0.5 × VdiVW tDH 0.5 × TdiVW + tDQS2DQ TdiVW + 2 × tDQS2DQ 0.5 × TdiVW + tDQS2DQ VCENTDQ,midpoint VIL(DC) VIH(DC) DQS_c DQS_t Rx Mask Table 91: Rx Mask and tDS/tDH without Write Training DDR4 VIHL(AC) (mV) TdiPW (UI) VdiVW (mV) TdiVW (UI) tDQS2DQ (UI) tDQ2DQ (UI) Rx Mask with Write Train (ps) tDS + tDH (ps) 1600 186 0.58 136 0.2 ±0.17 0.1 125 338 2133 186 0.58 136 0.2 ±0.17 0.1 94 253 Note: 1. V IHL(AC), VdiVW, and VILH(DC) referenced to VCENTDQ,midpoint. Connectivity Test (CT) Mode Input Levels Table 92: TEN Input Levels (CMOS) Parameter Symbol Min Max Unit Note TEN AC input high voltage V IH(AC)_TEN 0.8 × VDD VDD V1 TEN DC input high voltage V IH(DC)_TEN 0.7 × VDD VDD V TEN DC input low voltage V IL(DC)_TEN VSS 0.3 × VDD V TEN AC input low voltage V IL(AC)_TEN VSS 0.2 × VDD V2 TEN falling time tF_TEN – 1 0 ns 16Gb: x4, x8, x16 DDR4 SDRAM Electrical Characteristics – AC and DC Single-Ended Input Measurement Levels CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 275 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Table 94: CT Type-B Input Levels Parameter Symbol Min Max Unit Note CTipB AC input high voltage V IH(AC) VREF + 300 V DD11 V 2, 3 CTipB DC input high voltage V IH(DC) VREF + 200 V DD V 2, 3 CTipB DC input low voltage V IL(DC) VSS VREF - 200 V 2, 3 CTipB AC input low voltage V IL(AC) VSS11 VREF - 300 V 2, 3 CTipB falling time tF_CTipB – 5 ns 2 CTipB rising time tR_CTipB – 5 ns 2 Notes: 1. Refer to Overshoot and Undershoot Specifications. 2. CT Type-B inputs: DML_n/DBIL_n, DMU_n/DBIU_n and DM_n/DBI_n. 3. V REFDQ should be 0.5 × VDD Figure 214: CT Type-B Input Slew Rate Definition VIH(AC)_CTipBmin VIL(AC)_CTipBmax VIH(DC)_CTipBmin VIL(DC)_CTipBmax tR_CTipBtF_CTipB VREFDQ Table 95: CT Type-C Input Levels (CMOS) Parameter Symbol Min Max Unit Note CTipC AC input high voltage V IH(AC)_CTipC 0.8 × VDD VDD1 V2 CTipC DC input high voltage V IH(DC)_CTipC 0.7 × VDD VDD V2 CTipC DC input low voltage V IL(DC)_CTipC VSS 0.3 × VDD V2 CTipC AC input low voltage V IL(AC)_CTipC VSS1 0.2 × VDD V2 CTipC falling time tF_CTipC – 1 0 ns 2 CTipC rising time tR_CTipC – 1 0 ns 2 Notes: 1. Refer to Overshoot and Undershoot Specifications. 2. CT Type-C inputs: Alert_n. 16Gb: x4, x8, x16 DDR4 SDRAM Electrical Characteristics – AC and DC Single-Ended Input Measurement Levels CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 277 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Electrical Characteristics – AC and DC Differential Input Measurement Levels Differential Inputs Figure 217: Differential AC Swing and “Time Exceeding AC-Level” tDVAC VIH,diff(AC)min 0.0 VIL,diff,max tDVAC VIH,diff,min VIL,diff(AC)max Half cycle tDVAC CK_t, CK_c Notes: 1. Differential signal rising edge from V IL,diff,max to VIH,diff(AC)min must be monotonic slope. 2. Differential signal falling edge from IH,diff,min to VIL,diff(AC)max must be monotonic slope. Table 97: Differential Input Swing Requirements for CK_t, CK_c Parameter Sym- bol DDR4-1600 / DDR4-2400 /

2666 DDR4-2933 DDR4-3200

sMin Max Min Max Min Max Min Max Differential input high V IHdiff 150 Note 3 135 Note 3 125 Note 3 110 Note 3 mV 1 Differential input low V ILdiff Note 3 –150 Note 3 -135 Note 3 -125 Note 3 -110 mV 1 Differential input high (AC) VIH- diff(AC) 2 × (VIH(AC) - VREF) Note 3 2 × (VIH(AC) - VREF) Note 3 2 × (VIH(AC) - VREF) Note 3 2 × (VIH(AC) - VREF) Note 3 V 2 16Gb: x4, x8, x16 DDR4 SDRAM Electrical Characteristics – AC and DC Differential Input Meas- urement Levels CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 279 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Table 97: Differential Input Swing Requirements for CK_t, CK_c (Continued) Parameter Sym- bol DDR4-1600 / DDR4-2400 / sMin Max Min Max Min Max Min Max Differential input low (AC) VIL- diff(AC) Note 3 2 × (VIL(AC) - VREF) Note 3 2 × (VIL(AC) - VREF) Note 3 2 × (VIL(AC) - VREF) Note 3 2 × (VIL(AC) - VREF) Notes: 1. Used to define a differential signal slew-rate. 2. For CK_t, CK_c use V IH(AC) and VIL(AC) of ADD/CMD and VREFCA. 3. These values are not defined; however, the differential signals (CK_t, CK_c) need to be within the respective limits, VIH(DC)max and VIL(DC)min for single-ended signals as well as the limitations for overshoot and undershoot. Table 98: Minimum Time AC Time tDVAC for CK Slew Rate (V/ns) tDVAC (ps) at |VIH,diff(AC) to VIL,diff(AC)| 200mV TBDmV >4.0 120 TBD 4.0 115 TBD 3.0 110 TBD 2.0 105 TBD 1.9 100 TBD 1.6 95 TBD 1.4 90 TBD 1.2 85 TBD 1.0 80 TBD <1.0 80 TBD Note: 1. Below V IL(AC). Single-Ended Requirements for CK Differential Signals Each individual component of a differential signal (CK_t, CK_c) has to comply with cer- tain requirements for single-ended signals. CK_t and CK_c have to reach approximately V SEHmin/VSEL,max, which are approximately equal to the AC levels VIH(AC) and VIL(AC) for ADD/CMD signals in every half-cycle. The applicable AC levels for ADD/CMD might differ per speed-bin, and so on. For example, if a value other than 100mV is used for ADD/CMD V IH(AC) and VIL(AC) signals, then these AC levels also apply for the single- ended signals CK_t and CK_c. While ADD/CMD signal requirements are with respect to VREFCA, the single-ended com- ponents of differential signals have a requirement with respect to VDD/2; this is nomi- nally the same. The transition of single-ended signals through the AC levels is used to measure setup time. For single-ended components of differential signals the require- ment to reach V SEL,max/VSEH,min has no bearing on timing, but adds a restriction on the common mode characteristics of these signals. 16Gb: x4, x8, x16 DDR4 SDRAM Electrical Characteristics – AC and DC Differential Input Meas- urement Levels CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 280 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Figure 218: Single-Ended Requirements for CK VSS or VSSQ VDD or VDDQ VSEL,max VSEH,min VSEH VSEL CK VDD/2 or VDDQ/2 Table 99: Single-Ended Requirements for CK Parameter Symbol DDR4-1600 / 1866 / 2133 DDR4-2400 / 2666 DDR4-2933 / 3200 Unit NotesMin Max Min Max Single-ended high level for CK_t, CK_c VSEH VDD/2 + 0.100 Note 3 V DD/2 + 0.095 Note 3 V DD/2 + 0.085 Note 3 V 1, 2 Single-ended low level for CK_t, CK_c VSEL Note 3 V DD/2 - 0.100 Note 3 V DD/2 - 0.095 Note 3 V DD/2 - 0.085 V 1, 2 Notes: 1. For CK_t, CK_c use V IH(AC) and VIL(AC) of ADD/CMD and VREFCA. 2. ADDR/CMD V IH(AC) and VIL(AC) based on VREFCA. 3. These values are not defined; however, the differential signal (CK_t, CK_c) need to be within the respective limits, VIH(DC)max and VIL(DC)min for single-ended signals as well as the limitations for overshoot and undershoot. Slew Rate Definitions for CK Differential Input Signals Table 100: CK Differential Input Slew Rate Definition Differential input slew rate for rising edge V IL,diff,max VIH,diff,min |VIH,diff,min - VIL,diff,max_˂TRdiff Differential input slew rate for falling edge V IH,diff,min VIL,diff,max |VIH,diff,min - VIL,diff,max_˂TFdiff Note: 1. The differential signal CK_t, CK_c must be monotonic between these thresholds. 16Gb: x4, x8, x16 DDR4 SDRAM Electrical Characteristics – AC and DC Differential Input Meas- urement Levels CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 281 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Table 101: Cross Point Voltage For CK Differential Input Signals at DDR4-1600 through DDR4-2400 Parameter Sym Input Level DDR4-1600, 1866, 2133, 2400 Min Max Differential input cross point volt- age relative to V DD/2 for CK_t, CK_c VIX(CK) VSEH > VDD/2 + 145mV N/A 120mV VDD/2 + 100mV ื VSEH ื VDD/2 + 145mV N/A (V SEH - VDD/2) - 25mV VDD/2 - 145mV ื VSEL ื VDD/2 - 100mV –(V DD/2 - VSEL) + 25mV N/A VSEL < VDD/2 - 145mV –120mV N/A Table 102: Cross Point Voltage For CK Differential Input Signals at DDR4-2666 through DDR4-3200 Parameter Sym Input Level DDR4-2666, 2933, 3200 Min Max Differential input cross point volt- age relative to V DD/2 for CK_t, CK_c VIX(CK) VSEH > VDD/2 + 145mV N/A 110mV VDD/2 + 90mV ื VSEH ื VDD/2 + 145mV N/A (V SEH - VDD/2) - 30mV VDD/2 - 145mV ื VSEL ื VDD/2 - 90mV –(V DD/2 - VSEL) + 30mV N/A VSEL < VDD/2 - 145mV –110mV N/A DQS Differential Input Signal Definition and Swing Requirements Figure 221: Differential Input Signal Definition for DQS_t, DQS_c Half cycle VIL,diff,peak 0.0V DQS_t, DQS_c: Differential Input Voltage VIH,diff,peak Half cycle Table 103: DDR4-1600 through DDR4-2400 Differential Input Swing Requirements for DQS_t, DQS_c Parameter Symbol DDR4-1600, 1866,

2133 DDR4-2400

Peak differential input high voltage V IH,diff,peak 186 V DDQ 160 V DDQ mV 1 , 2 16Gb: x4, x8, x16 DDR4 SDRAM Electrical Characteristics – AC and DC Differential Input Meas- urement Levels CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 283 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Table 103: DDR4-1600 through DDR4-2400 Differential Input Swing Requirements for DQS_t, DQS_c (Continued) Parameter Symbol DDR4-1600, 1866, Peak differential input low voltage V IL,diff,peak VSSQ –186 V SSQ –160 mV 1 , 2 Notes: 1. Minimum and maximum limits are relative to single-ended portion and can be exceeded within allowed overshoot and undershoot limits. 2. Minimum value point is used to determine differential signal slew-rate. Table 104: DDR4-2633 through DDR4-3200 Differential Input Swing Requirements for DQS_t, DQS_c Parameter Symbol DDR4-2666 DDR4-2933 DDR4-3200 Unit NotesMin Max Min Max Min Max Peak differential input high volt- age VIH,diff,peak 150 V DDQ 145 V DDQ 140 V DDQ mV 1 , 2 Peak differential input low volt- age VIL,diff,peak VSSQ –150 V SSQ –145 V SSQ –140 mV 1 , 2 Notes: 1. Minimum and maximum limits are relative to single-ended portion and can be exceeded within allowed overshoot and undershoot limits. 2. Minimum value point is used to determine differential signal slew-rate. The peak voltage of the DQS signals are calculated using the following equations: VIH,dif,Peak voltage = MAX(ft) VIL,dif,Peak voltage = MIN(ft) (ft) = DQS_t, DQS_c. The MAX(f(t)) or MIN(f(t)) used to determine the midpoint from which to reference the ±35% window of the exempt non-monotonic signaling shall be the smallest peak volt- age observed in all UIs. Figure 222: DQS_t, DQS_c Input Peak Voltage Calculation and Range of Exempt non-Monotonic Sig- naling DQS_t MIN(ft) MAX(ft) DQS_c DQS_t, DQS_c: Single-Ended Input Voltages +50% –50% +35% –35% 16Gb: x4, x8, x16 DDR4 SDRAM Electrical Characteristics – AC and DC Differential Input Meas- urement Levels CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 284 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

DQS Differential Input Cross Point Voltage To achieve tight RxMask input requirements as well as output skew parameters with re- spect to strobe, the cross point voltage of differential input signals (DQS_t, DQS_c) must meet V IX_DQS,ratio in the table below. The differential input cross point voltage VIX_DQS (VIX_DQS_FR and VIX_DQS_RF) is measured from the actual cross point of DQS_t, DQS_c relative to the VDQS,mid of the DQS_t and DQS_c signals. VDQS,mid is the midpoint of the minimum levels achieved by the transitioning DQS_t and DQS_c signals, and noted by VDQS_trans. VDQS_trans is the difference between the low- est horizontal tangent above VDQS,mid of the transitioning DQS signals and the highest horizontal tangent below VDQS,mid of the transitioning DQS signals. A non-monotonic transitioning signal’s ledge is exempt or not used in determination of a horizontal tan- gent provided the said ledge occurs within ±35% of the midpoint of either V IH.DIFF .Peak voltage (DQS_t rising) or VIL.DIFF .Peak voltage (DQS_c rising), as shown in the figure be- low. A secondary horizontal tangent resulting from a ring-back transition is also exempt in determination of a horizontal tangent. That is, a falling transition’s horizontal tangent is derived from its negative slope to zero slope transition (point A in the figure below), and a ring-back’s horizontal tangent is derived from its positive slope to zero slope transi- tion (point B in the figure below) and is not a valid horizontal tangent; a rising transi- tion’s horizontal tangent is derived from its positive slope to zero slope transition (point C in the figure below), and a ring-back’s horizontal tangent derived from its negative slope to zero slope transition (point D in the figure below) and is not a valid horizontal tangent. Figure 223: V IXDQS Definition DQS_t, DQS_c: Single-Ended Input Voltages DQS_t VIX_DQS,FR VIX_DQS,FRVIX_DQS,RF VIX_DQS,RF VDQS_trans VDQS_trans/2 Lowest horizontal tanget above VDQS,mid of the transitioning signals Highest horizontal tanget below VDQS,mid of the transitioning signals VSSQ VDQS,mid DQS_c A B C D Table 105: Cross Point Voltage For Differential Input Signals DQS Parameter Symbol DDR4-1600, 1866, 2133, 2400, 2666, 2933, 3200 Unit NotesMin Max DQS_t and DQS_c crossing relative to the midpoint of the DQS_t and DQS_c signal swings VIX_DQS,ratio – 25 % 1, 2 16Gb: x4, x8, x16 DDR4 SDRAM Electrical Characteristics – AC and DC Differential Input Meas- urement Levels CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 285 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Table 105: Cross Point Voltage For Differential Input Signals DQS (Continued) Parameter Symbol DDR4-1600, 1866, 2133, 2400, 2666, 2933, 3200 Unit NotesMin Max VDQS,mid to Vcent(midpoint) offset V DQS,mid_to_Vcent – Note 3 mV 2 Notes: 1. V IX_DQS,ratio is DQS VIX crossing (VIX_DQS,FR or VIX_DQS,RF) divided by VDQS_trans. VDQS_trans is the difference between the lowest horizontal tangent above VDQS,midd of the transition- ing DQS signals and the highest horizontal tangent below VDQS,mid of the transitioning DQS signals. 2. V DQS,mid will be similar to the VREFDQ internal setting value (Vcent(midpoint) offset) ob- tained during VREF Training if the DQS and DQs drivers and paths are matched. 3. The maximum limit shall not exceed the smaller of V IH,diff,DQS minimum limit or 50mV. Slew Rate Definitions for DQS Differential Input Signals Table 106: DQS Differential Input Slew Rate Definition Differential input slew rate for rising edge V IL,diff,DQS V IH,diff,DQS |VIH,diff,DQS - VIL,diff,DQS_˂TRdiff Differential input slew rate for falling edge V IH,diff,DQS V IL,diff,DQS |VIHdiffDQS - VIL,diff,DQS_˂TFdiff Note: 1. The differential signal DQS_t, DQS_c must be monotonic between these thresholds. Figure 224: Differential Input Slew Rate and Input Level Definition for DQS_t, DQS_c TFdiff TRdiff VIL,diff,peak 0.0V DQS_t, DQS_c: Differential Input Voltage VIH,diff,peak VIH,diff,DQS VIL,diff,DQS Table 107: DDR4-1600 through DDR4-2400 Differential Input Slew Rate and Input Levels for DQS_t, DQS_c Parameter Symbol DDR4-1600, 1866, 2133 DDR4-2400 Unit NotesMin Max Min Max Peak differential input high voltage V IH,diff,peak 186 V DDQ 160 V DDQ mV 1 Differential input high voltage V IH,diff,DQS 136 – 130 – mV 2, 3 Differential input low voltage V IL,diff,DQS – –136 – –130 mV 2, 3 16Gb: x4, x8, x16 DDR4 SDRAM Electrical Characteristics – AC and DC Differential Input Meas- urement Levels CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 286 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Table 107: DDR4-1600 through DDR4-2400 Differential Input Slew Rate and Input Levels for DQS_t, DQS_c (Continued) Parameter Symbol DDR4-1600, 1866, 2133 DDR4-2400 Unit NotesMin Max Min Max Peak differential input low voltage V IL,diff,peak VSSQ –186 V SSQ –160 mV 1 DQS differential input slew rate SRIdiff 3.0 18 3.0 18 V/ns 4, 5 Notes: 1. Minimum and maximum limits are relative to single-ended portion and can be exceeded within allowed overshoot and undershoot limits. 2. Differential signal rising edge from V IL,diff,DQS to VIH,diff,DQS must be monotonic slope. 3. Differential signal falling edge from V IH,diff,DQS to VIL,diff,DQS must be monotonic slope. 4. Differential input slew rate for rising edge from V IL,diff,DQS to VIH,diff,DQS is defined by | VIL,diff,min - VIH,diff,max_˂TRdiff. 5. Differential input slew rate for falling edge from V IH,diff,DQS to VIL,diff,DQS is defined by | VIL,diff,min - VIH,diff,max_˂TFdiff. Table 108: DDR4-2666 through DDR4-3200 Differential Input Slew Rate and Input Levels for DQS_t, DQS_c Parameter Symbol DDR4-2666 DDR4-2933 DDR4-3200 Unit NotesMin Max Min Max Min Max Peak differential input high voltage VIH,diff,peak 150 V DDQ 145 V DDQ 140 V DDQ mV 1 Differential input high voltage VIH,diff,DQS 130 – 115 – 110 – mV 2, 3 Differential input low voltage VIL,diff,DQS – –130 – –115 – –110 mV 2, 3 Peak differential input low voltage VIL,diff,peak VSSQ –150 V SSQ –145 V SSQ –140 mV 1 DQS differential input slew rate SRIdiff 2.5 18 2.5 18 2.5 18 V/ns 4, 5 Notes: 1. Minimum and maximum limits are relative to single-ended portion and can be exceeded within allowed overshoot and undershoot limits. 2. Differential signal rising edge from V IL,diff,DQS to VIH,diff,DQS must be monotonic slope. 3. Differential signal falling edge from V IH,diff,DQS to VIL,diff,DQS must be monotonic slope. 4. Differential input slew rate for rising edge from V IL,diff,DQS to VIH,diff,DQS is defined by | VIL,diff,min - VIH,diff,max_˂TRdiff. 5. Differential input slew rate for falling edge from V IH,diff,DQS to VIL,diff,DQS is defined by | VIL,diff,min - VIH,diff,max_˂TFdiff. 16Gb: x4, x8, x16 DDR4 SDRAM Electrical Characteristics – AC and DC Differential Input Meas- urement Levels CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 287 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Electrical Characteristics – Overshoot and Undershoot Specifications Address, Command, and Control Overshoot and Undershoot Specifications Table 109: ADDR, CMD, CNTL Overshoot and Undershoot/Specifications Address and control pins (A[17:0], BG[1:0], BA[1:0], CS_n, RAS_n, CAS_n, WE_n, CKE, ODT, C2-0) Area A: Maximum peak amplitude above VDD absolute MAX Area B: Amplitude allowed between VDD and VDD absolute MAX Area C: Maximum peak amplitude allowed for undershoot below VSS Figure 225: ADDR, CMD, CNTL Overshoot and Undershoot Definition VDD absolute MAX Absolute MAX overshoot Overshoot area above VDD absolute MAX Overshoot area below VDD absolute MAX and above VDD MAX Undershoot area below VSS 1tCK Volts (V) VDD VSS A B C 16Gb: x4, x8, x16 DDR4 SDRAM Electrical Characteristics – Overshoot and Undershoot Specifi- cations CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 288 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Clock Overshoot and Undershoot Specifications Table 110: CK Overshoot and Undershoot/ Specifications CLK_t, CLK_n Area A: Maximum peak amplitude above VDD absolute MAX Area B: Amplitude allowed between VDD and VDD absolute MAX Area C: Maximum peak amplitude allowed for undershoot below VSS Figure 226: CK Overshoot and Undershoot Definition VDD absolute MAX Absolute MAX overshoot Overshoot area above VDD absolute MAX Overshoot area below VDD absolute MAX and above VDD MAX Undershoot area below VSS 1UI Volts (V) VDD VSS A B C 16Gb: x4, x8, x16 DDR4 SDRAM Electrical Characteristics – Overshoot and Undershoot Specifi- cations CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 289 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Data, Strobe, and Mask Overshoot and Undershoot Specifications Table 111: Data, Strobe, and Mask Overshoot and Undershoot/ Specifications DQS_t, DQS_n, LDQS_t, LDQS_n, UDQS_t, UDQS_n, DQ[0:15], DM/DBI, UDM/UDBI, LDM/LDBI, Area A: Maximum peak amplitude above VDDQ absolute MAX Area B: Amplitude allowed between VDDQ and VDDQ absolute MAX Area C: Maximum peak amplitude allowed for undershoot below VSSQ Area D: Maximum peak amplitude below VSSQ absolute MIN Figure 227: Data, Strobe, and Mask Overshoot and Undershoot Definition VDDQ absolute MAX VSSQ absolute MIN A B C Absolute MAX overshoot Absolute MAX undershoot Overshoot area above VDDQ absolute MAX Undershoot area below VSSQ absolute MIN Overshoot area below VDDQ absolute MAX and above VDDQ MAX Undershoot area below VSSQ MIN and above VSSQ absolute MIN 1UI Volts (V) VDDQ VSSQ D Electrical Characteristics – AC and DC Output Measurement Levels Single-Ended Outputs Table 112: Single-Ended Output Levels Parameter Symbol DDR4-1600 to DDR4-3200 Unit DC output high measurement level (for IV curve linearity) V OH(DC) 1.1 × VDDQ V DC output mid measurement level (for IV curve linearity) V OM(DC) 0.8 × VDDQ V DC output low measurement level (for IV curve linearity) V OL(DC) 0.5 × VDDQ V AC output high measurement level (for output slew rate) V OH(AC) (0.7 + 0.15) × VDDQ V 16Gb: x4, x8, x16 DDR4 SDRAM Electrical Characteristics – AC and DC Output Measurement Levels CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 290 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Table 112: Single-Ended Output Levels (Continued) Parameter Symbol DDR4-1600 to DDR4-3200 Unit AC output low measurement level (for output slew rate) V OL(AC) (0.7 - 0.15) × VDDQ V Note: 1. The swing of ±0.15 × V DDQ is based on approximately 50% of the static single-ended output peak-to-peak swing with a driver impedance of RZQ/7 and an effective test load of 50˖ to VTT = VDDQ. Using the same reference load used for timing measurements, output slew rate for fall- ing and rising edges is defined and measured between VOL(AC) and VOH(AC) for single- ended signals. Table 113: Single-Ended Output Slew Rate Definition Single-ended output slew rate for rising edge V OL(AC) VOH(AC) [VOH(AC) - VOL(AC)@˂TRse Single-ended output slew rate for falling edge V OH(AC) VOL(AC) [VOH(AC) - VOL(AC)@˂TFse Figure 228: Single-ended Output Slew Rate Definition TRse TFse VOH(AC) VOL(AC) Single-Ended Output Voltage (DQ) 16Gb: x4, x8, x16 DDR4 SDRAM Electrical Characteristics – AC and DC Output Measurement Levels CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 291 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Table 114: Single-Ended Output Slew Rate For RON = RZQ/7 Parameter Symbol DDR4-1600/ 1866 / 2133 /

2400 DDR4-2666 DDR4-2933 / 3200

UnitMin Max Min Max Min Max Single-ended output slew rate SRQse 4 9 4949 V/ns Notes: 1. SR = slew rate; Q = query output; se = single-ended signals. 2. In two cases a maximum slew rate of 12V/ns applies for a single DQ signal within a byte lane:

• Case 1 is defined for a single DQ signal within a byte lane that is switching into a cer- tain direction (either from HIGH-to-LOW or LOW-to-HIGH) while all remaining DQ sig- nals in the same byte lane are static (they stay at either HIGH or LOW).
• Case 2 is defined for a single DQ signal within a byte lane that is switching into a cer- tain direction (either from HIGH-to-LOW or LOW-to-HIGH) while all remaining DQ sig- nals in the same byte lane are switching into the opposite direction (from LOW-to- HIGH or HIGH-to-LOW, respectively). For the remaining DQ signal switching into the opposite direction, the standard maximum limit of 9 V/ns applies. Differential Outputs Table 115: Differential Output Levels Parameter Symbol DDR4-1600 to DDR4-3200 Unit AC differential output high measurement level (for output slew rate) VOH,diff(AC) 0.3 × VDDQ V AC differential output low measurement level (for output slew rate) VOL,diff(AC) –0.3 × VDDQ V Note: 1. The swing of ±0.3 × V DDQ is based on approximately 50% of the static single-ended out- put peak-to-peak swing with a driver impedance of RZQ/7 and an effective test load of 50˖ to VTT = VDDQ at each differential output. Using the same reference load used for timing measurements, output slew rate for fall- ing and rising edges is defined and measured between VOL,diff(AC) and VOH,diff(AC) for dif- ferential signals. Table 116: Differential Output Slew Rate Definition

Differential output slew rate for rising edge V OL,diff(AC) VOH,diff(AC) [VOH,diff(AC) - VOL,diff(AC)@˂TRdiff Differential output slew rate for falling edge V OH,diff(AC) VOL,diff(AC) [VOH,diff(AC) - VOL,diff(AC)@˂TFdiff 16Gb: x4, x8, x16 DDR4 SDRAM Electrical Characteristics – AC and DC Output Measurement Levels CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 292 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Figure 229: Differential Output Slew Rate Definition TRdiff TFdiff VOH,diff(AC) VOL,diff(AC) Differential Input Voltage (DQS_t, DQS_c) Table 117: Differential Output Slew Rate For RON = RZQ/7 Parameter Symbol DDR4-1600 / 1866 / 2133 / 2400 DDR4-2666 DDR4-2933 / 3200 UnitMin Max Min Max Min Max Differential output slew rate SRQdiff 8 18 8 18 8 18 V/ns Note: 1. SR = slew rate; Q = query output; diff = differential signals. Reference Load for AC Timing and Output Slew Rate The effective reference load of 50˖ to VTT = VDDQ and driver impedance of RZQ/7 for each output was used in defining the relevant AC timing parameters of the device as well as output slew rate measurements. R ON nominal of DQ, DQS_t and DQS_c drivers uses 34 ohms to specify the relevant AC timing parameter values of the device. The maximum DC high level of output signal = 1.0 × V DDQ, the minimum DC low level of output signal = { 34 /( 34 + 50 ) } × VDDQ = 0.4 × VDDQ. The nominal reference level of an output signal can be approximated by the following: The center of maximum DC high and minimum DC low = { ( 1 + 0.4 ) / 2 } × VDDQ = 0.7 × VDDQ. The actual reference level of output signal might vary with driver RON and refer- ence load tolerances. Thus, the actual reference level or midpoint of an output signal is at the widest part of the output signal’s eye. 16Gb: x4, x8, x16 DDR4 SDRAM Electrical Characteristics – AC and DC Output Measurement Levels CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 293 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Figure 232: Connectivity Test Mode Output Slew Rate Definition TFoutput_CT VOH(AC) VOL(AC) VTT0.5 x VDD TRoutput_CT Table 119: Connectivity Test Mode Output Slew Rate Parameter Symbol DDR4-1600 / 1866 / 2133 / 2400 DDR4-2666 DDR4-2933 / 3200 UnitMin Max Min Max Min Max Output signal falling time TF_output_CT – 10 – 10 – 10 ns/V Output signal rising time TR_output_CT – 10 – 10 – 10 ns/V Electrical Characteristics – AC and DC Output Driver Characteristics Connectivity Test Mode Output Driver Electrical Characteristics The DDR4 driver supports special values during connectivity test mode. These RON val- ues are referenced in this section. A functional representation of the output buffer is shown in the figure below. 16Gb: x4, x8, x16 DDR4 SDRAM Electrical Characteristics – AC and DC Output Driver Charac- teristics CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 295 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Figure 233: Output Driver During Connectivity Test Mode VDDQ VSSQ Chip in drive mode DQ VOUT IOUT RONPU_CT RONPD_CT Output driver To other circuitry like RCV, ... IPU_CT IPD_CT The output driver impedance, RON, is determined by the value of the external reference resistor RZQ as follows: RON = RZQ/7. This targets 34˖ with nominal RZQ ˖; however, connectivity test mode uses uncalibrated drivers and only a maximum target is defined. Mismatch between pull up and pull down is undefined. The individual pull-up and pull-down resistors (R ONPu_CT and RONPd_CT) are defined as follows: RONPu_CT when RONPd_CT is off: 52138B&7 9''49287 ,287 RONPD_CT when RONPU_CT is off: 5213'B&7 9287 ,287 16Gb: x4, x8, x16 DDR4 SDRAM Electrical Characteristics – AC and DC Output Driver Charac- teristics CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 296 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Table 120: Output Driver Electrical Characteristics During Connectivity Test Mode Assumes RZQ ˖; ZQ calibration not required RON,nom_CT Resistor VOUT Min Nom Max Unit RONPD_CT VOB(DC) = 0.2 × VDDQ N/A N/A 1.9 R ZQ/7 VOL(DC) = 0.5 × VDDQ N/A N/A 2.0 R ZQ/7 VOM(DC) = 0.8 × VDDQ N/A N/A 2.2 R ZQ/7 VOH(DC) = 1.1 × VDDQ N/A N/A 2.5 R ZQ/7 RONPU_CT VOB(DC) = 0.2 × VDDQ N/A N/A 1.9 R ZQ/7 VOL(DC) = 0.5 × VDDQ N/A N/A 2.0 R ZQ/7 VOM(DC) = 0.8 × VDDQ N/A N/A 2.2 R ZQ/7 VOH(DC) = 1.1 × VDDQ N/A N/A 2.5 R ZQ/7 Output Driver Electrical Characteristics The DDR4 driver supports two RON values. These RON values are referred to as strong mode (low RON ˖) and weak mode (high RON ˖). A functional representation of the output buffer is shown in the figure below. Figure 234: Output Driver: Definition of Voltages and Currents VDDQ VSSQ Chip in drive mode DQ VOUT IOUT RONPU RONPD Output driver To other circuitry like RCV, ... IPU IPD The output driver impedance, RON, is determined by the value of the external reference resistor RZQ as follows: RON(34) = RZQ/7, or RON(48) = RZQ/5. This provides either a nomi- nal 34.3˖±10% or 48˖±10% with nominal RZQ ˖ The individual pull-up and pull-down resistors (RONPu and RONPd) are defined as fol- lows: RONPu when RONPd is off: 16Gb: x4, x8, x16 DDR4 SDRAM Electrical Characteristics – AC and DC Output Driver Charac- teristics CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 297 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

RONPU = VDDQ - VOUT IOUT RONPD when RONPU is off: RONPD = VOUT IOUT Table 121: Strong Mode (34˖˖) Output Driver Electrical Characteristics Assumes RZQ ˖; Entire operating temperature range after proper ZQ calibration RON,nom Resistor VOUT Min Nom Max Unit Notes RON34PD VOL(DC) = 0.5 × VDDQ 0.73 1.00 1.10 R ZQ/7 1, 2, 3 VOM(DC) = 0.8 × VDDQ 0.83 1.00 1.10 R ZQ/7 1, 2, 3 VOH(DC) = 1.1 × VDDQ 0.83 1.00 1.25 R ZQ/7 1, 2, 3 RON34PU VOL(DC) = 0.5 × VDDQ 0.90 1.00 1.25 R ZQ/7 1, 2, 3 VOM(DC) = 0.8 × VDDQ 0.90 1.00 1.10 R ZQ/7 1, 2, 3 VOH(DC) = 1.1 × VDDQ 0.80 1.00 1.10 R ZQ/7 1, 2, 3 Mismatch between pull-up and pull- down, MMPUPD 6, 7 Mismatch between DQ to DQ within byte variation pull-up, MMPUdd Mismatch between DQ to DQ within byte variation pull-down, MMPDdd 6, 7 Notes: 1. The tolerance limits are specified after calibration with stable voltage and temperature. For the behavior of the tolerance limits if temperature or voltage changes after calibra- tion, see following section on voltage and temperature sensitivity. 2. The tolerance limits are specified under the condition that V DDQ = VDD and that VSSQ = VSS. 3. Micron recommends calibrating pull-down and pull-up output driver impedances at 0.8 × VDDQ. Other calibration schemes may be used to achieve the linearity specification shown above; for example, calibration at 0.5 × VDDQ and 1.1 VDDQ. 4. DQ-to-DQ mismatch within byte variation for a given component including DQS_t and DQS_c (characterized). 5. Measurement definition for mismatch between pull-up and pull-down, MM PUPD: Measure both RONPU and RONPD at 0.8 × VDDQ separately; RON,nom is the nominal RON val- ue: MMPUPD = × 100 RONPU - RONPD RON,nom 6. R ON variance range ratio to RON nominal value in a given component, including DQS_t and DQS_c: 16Gb: x4, x8, x16 DDR4 SDRAM Electrical Characteristics – AC and DC Output Driver Charac- teristics CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 298 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

MMPUDD = × 100 RONPU,max - RONPU,min RON,nom MMPDDD = × 100 RONPD,max - RONPD,min RON,nom 7. The lower and upper bytes of a x16 are each treated on a per byte basis. 8. The minimum values are derated by 9% when the device operates between –40°C and 0°C (TC). Table 122: Weak Mode (48˖˖) Output Driver Electrical Characteristics Assumes RZQ ˖; Entire operating temperature range after proper ZQ calibration RON,nom Resistor VOUT Min Nom Max Unit Notes ˖ RON48PD VOL(DC) = 0.5 × VDDQ 0.73 1.00 1.10 R ZQ/5 1, 2, 3 VOM(DC) = 0.8 × VDDQ 0.83 1.00 1.10 R ZQ/5 1, 2, 3 VOH(DC) = 1.1 × VDDQ 0.83 1.00 1.25 R ZQ/5 1, 2, 3 RON48PU VOL(DC) = 0.5 × VDDQ 0.90 1.00 1.25 R ZQ/5 1, 2, 3 VOM(DC) = 0.8 × VDDQ 0.90 1.00 1.10 R ZQ/5 1, 2, 3 VOH(DC) = 1.1 × VDDQ 0.80 1.00 1.10 R ZQ/5 1, 2, 3 Mismatch between pull-up and pull-down, MMPUPD 6, 7 Mismatch between DQ to DQ within byte variation pull-up, MMPUdd Mismatch between DQ to DQ within byte variation pull-down, MMPDdd 6, 7 Notes: 1. The tolerance limits are specified after calibration with stable voltage and temperature. For the behavior of the tolerance limits if temperature or voltage changes after calibra- tion, see following section on voltage and temperature sensitivity. 2. The tolerance limits are specified under the condition that V DDQ = VDD and that VSSQ = VSS. 3. Micron recommends calibrating pull-down and pull-up output driver impedances at 0.8 × VDDQ. Other calibration schemes may be used to achieve the linearity specification shown above; for example, calibration at 0.5 × VDDQ and 1.1 VDDQ. 4. DQ-to-DQ mismatch within byte variation for a given component including DQS_t and DQS_c (characterized). 5. Measurement definition for mismatch between pull-up and pull-down, MM PUPD: Measure both RONPU and RONPD at 0.8 × VDDQ separately; RON,nom is the nominal RON val- ue: MMPUPD = × 100 RONPU - RONPD RON,nom 6. R ON variance range ratio to RON nominal value in a given component, including DQS_t and DQS_c: 16Gb: x4, x8, x16 DDR4 SDRAM Electrical Characteristics – AC and DC Output Driver Charac- teristics CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 299 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

MMPUDD = × 100 RONPU,max - RONPU,min RON,nom MMPDDD = × 100 RONPD,max - RONPD,min RON,nom 7. The lower and upper bytes of a x16 are each treated on a per byte basis. 8. The minimum values are derated by 9% when the device operates between –40°C and 0°C (TC). Output Driver Temperature and Voltage Sensitivity If temperature and/or voltage change after calibration, the tolerance limits widen ac- cording to the equations and tables below. ˂T = T - T(@calibration); ˂V = VDDQ - VDDQ(@ calibration); VDD = VDDQ Table 123: Output Driver Sensitivity Definitions Symbol Min Max Unit RONPU@ VOH(DC) 0.6 - dRONdTH × |˂T| - dRONdVH × |˂V| 1.1 _ dR ONdTH × |˂T| + dRONdVH × |˂V| R ZQ/6 RON@ VOM(DC) 0.9 - dRONdTM × |˂T| - dRONdVM × |˂V| 1.1 + dR ONdTM × |˂T| + dRONdVM × |˂V| R ZQ/6 RONPD@ VOL(DC) 0.6 - dRONdTL × |˂T| - dRONdVL × |˂V| 1.1 + dR ONdTL × |˂T| + dRONdVL × |˂V| R ZQ/6 Table 124: Output Driver Voltage and Temperature Sensitivity Symbol Voltage and Temperature Range UnitMin Max dRONdTM 0 1.5 %/°C dRONdVM 0 0.15 %/mV dRONdTL 0 1.5 %/°C dRONdVL 0 0.15 %/mV dRONdTH 0 1.5 %/°C dRONdVM 0 0.15 %/mV Alert Driver A functional representation of the alert output buffer is shown in the figure below. Out- put driver impedance, RON, is defined as follows. 16Gb: x4, x8, x16 DDR4 SDRAM Electrical Characteristics – AC and DC Output Driver Charac- teristics CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 300 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Figure 235: Alert Driver Alert VOUTRONPD '5$0 Alert driver IPD IOUT VSSQ RONPD when RONPU is off: RONPD = VOUT IOUT Table 125: Alert Driver Voltage RON,nom Register VOUT Min Nom Max Unit N/A R ONPD VOL(DC) = 0.1 × VDDQ 0.3 N/A 1.2 R ZQ/7 VOM(DC) = 0.8 × VDDQ 0.4 N/A 1.2 R ZQ/7 VOH(DC) = 1.1 × VDDQ 0.4 N/A 1.4 R ZQ/7 Note: 1. V DDQ voltage is at VDDQ(DC). Electrical Characteristics – On-Die Termination Characteristics ODT Levels and I-V Characteristics On-die termination (ODT) effective resistance settings are defined and can be selected by any or all of the following options:

• MR1[10:8] (R TT(NOM)): Disable, 240 ohms, 120 ohms, 80 ohms, 60 ohms, 48 ohms, 40 ohms, and 34 ohms.
• MR2[11:9] (R TT(WR)): Disable, 240 ohms,120 ohms, and 80 ohms.
• MR5[8:6] (R TT(Park)): Disable, 240 ohms, 120 ohms, 80 ohms, 60 ohms, 48 ohms, 40 ohms, and 34 ohms. ODT is applied to the following inputs:
• x4: DQ, DM_n, DQS_t, and DQS_c inputs.
• x8: DQ, DM_n, DQS_t, DQS_c, TDQS_t, and TDQS_c inputs.
• x16: DQ, LDM_n, UDM_n, LDQS_t, LDQS_c, UDQS_t, and UDQS_c inputs. A functional representation of ODT is shown in the figure below. 16Gb: x4, x8, x16 DDR4 SDRAM Electrical Characteristics – On-Die Termination Characteristics CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 301 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Figure 236: ODT Definition of Voltages and Currents VDDQ VSSQ Chip in termination mode DQ VOUT IOUT RTTTo other circuitry like RCV, ... ODT Table 126: ODT DC Characteristics RTT VOUT Min Nom Max Unit Notes 240 ohm V OL(DC) = 0.5 × VDDQ 0.9 1 1.25 R ZQ 1, 2, 3 VOM(DC) = 0.8 × VDDQ 0.9 1 1.1 R ZQ 1, 2, 3 VOH(DC) = 1.1 × VDDQ 0.8 1 1.1 R ZQ 1, 2, 3 120 ohm V OL(DC) = 0.5 × VDDQ 0.9 1 1.25 R ZQ/2 1, 2, 3 VOM(DC) = 0.8 × VDDQ 0.9 1 1.1 R ZQ/2 1, 2, 3 VOH(DC) = 1.1 × VDDQ 0.8 1 1.1 R ZQ/2 1, 2, 3 80 ohm V OL(DC) = 0.5 × VDDQ 0.9 1 1.25 R ZQ/3 1, 2, 3 VOM(DC) = 0.8 × VDDQ 0.9 1 1.1 R ZQ/3 1, 2, 3 VOH(DC) = 1.1 × VDDQ 0.8 1 1.1 R ZQ/3 1, 2, 3 60 ohm V OL(DC) = 0.5 × VDDQ 0.9 1 1.25 R ZQ/4 1, 2, 3 VOM(DC) = 0.8 × VDDQ 0.9 1 1.1 R ZQ/4 1, 2, 3 VOH(DC) = 1.1 × VDDQ 0.8 1 1.1 R ZQ/4 1, 2, 3 48 ohm V OL(DC) = 0.5 × VDDQ 0.9 1 1.25 R ZQ/5 1, 2, 3 VOM(DC) = 0.8 × VDDQ 0.9 1 1.1 R ZQ/5 1, 2, 3 VOH(DC) = 1.1 × VDDQ 0.8 1 1.1 R ZQ/5 1, 2, 3 40 ohm V OL(DC) = 0.5 × VDDQ 0.9 1 1.25 R ZQ/6 1, 2, 3 VOM(DC) = 0.8 × VDDQ 0.9 1 1.1 R ZQ/6 1, 2, 3 VOH(DC) = 1.1 × VDDQ 0.8 1 1.1 R ZQ/6 1, 2, 3 34 ohm V OL(DC) = 0.5 × VDDQ 0.9 1 1.25 R ZQ/7 1, 2, 3 VOM(DC) = 0.8 × VDDQ 0.9 1 1.1 R ZQ/7 1, 2, 3 VOH(DC) = 1.1 × VDDQ 0.8 1 1.1 R ZQ/7 1, 2, 3 DQ-to-DQ mismatch within byte Notes: 1. The tolerance limits are specified after calibration to 240 ohm ±1% resistor with stable voltage and temperature. For the behavior of the tolerance limits if temperature or voltage changes after calibration, see ODT Temperature and Voltage Sensitivity. 16Gb: x4, x8, x16 DDR4 SDRAM Electrical Characteristics – On-Die Termination Characteristics CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 302 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

1. Micron recommends calibrating pull-up ODT resistors at 0.8 × V DDQ. Other calibration schemes may be used to achieve the linearity specification shown here. 3. The tolerance limits are specified under the condition that V DDQ = VDD and VSSQ = VSS. 4. The DQ-to-DQ mismatch within byte variation for a given component including DQS_t and DQS_c. 5. R TT variance range ratio to RTT nominal value in a given component, including DQS_t and DQS_c. DQ-to-DQ mismatch = RTT(MAX) - RTT(MIN) RTT(NOM) × 100 6. DQ-to-DQ mismatch for a x16 device is treated as two separate bytes. 7. For IT, AT, and UT devices, the minimum values are derated by 9% when the device op- erates between –40°C and 0°C (TC). ODT Temperature and Voltage Sensitivity If temperature and/or voltage change after calibration, the tolerance limits widen ac- cording to the following equations and tables. ˂T = T - T(@ calibration); ˂V = VDDQ - VDDQ(@ calibration); VDD = VDDQ Table 127: ODT Sensitivity Definitions Parameter Min Max Unit RTT@ 0.9 - dR TTdT × |˂T| - dRTTdV × |˂V| 1.6 + dR TTdTH × |˂T| + dRTTdVH × |˂V| R ZQ/n Table 128: ODT Voltage and Temperature Sensitivity Parameter Min Max Unit dRTTdT 0 1.5 %/°C dRTTdV 0 0.15 %/mV ODT Timing Definitions The reference load for ODT timings is different than the reference load used for timing measurements. Figure 237: ODT Timing Reference Load Timing reference point DQ, DQS_t, DQS_c, DM, TDQS_t, TDQS_c CK_t, CK_c DUT VTT VDDQ VSSQ VSSQ= RTT = 50ȍ 16Gb: x4, x8, x16 DDR4 SDRAM Electrical Characteristics – On-Die Termination Characteristics CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 303 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Definitions for tADC, tAONAS, and tAOFAS are provided in the Table 129 (page 304) and shown in Figure 238 (page 305) and Figure 240 (page 306). Measurement reference set- tings are provided in the subsequent Table 130 (page 304). The tADC for the dynamic ODT case and read disable ODT cases are represented by tADC of Direct ODT Control case. Table 129: ODT Timing Definitions Parameter Begin Point Definition End Point Definition Figure tADC Rising edge of CK_t, CK_c defined by the end point of DODTLoff Extrapolated point at VRTT,nom Figure 238 (page 305) Rising edge of CK_t, CK_c defined by the end point of DODTLon Extrapolated point at VSSQ Figure 238 (page 305) Rising edge of CK_t, CK_c defined by the end point of ODTLcnw Extrapolated point at VRTT,nom Figure 239 (page 305) Rising edge of CK_t, CK_c defined by the end point of ODTLcwn4 or ODTLcwn8 Extrapolated point at VSSQ Figure 239 (page 305) tAONAS Rising edge of CK_t, CK_c with ODT being first registered HIGH Extrapolated point at VSSQ Figure 240 (page 306) tAOFAS Rising edge of CK_t, CK_c with ODT being first registered LOW Extrapolated point at VRTT,nom Figure 240 (page 306) Table 130: Reference Settings for ODT Timing Measurements Measure Parameter RTT(Park) RTT(NOM) RTT(WR) VSW1 VSW2 Note tADC Disable R ZQ – 0.20V 0.40V 1, 2, 4 –R ZQ High-Z 0.20V 0.40V 1, 3, 5 tAONAS Disable R ZQ – 0.20V 0.40V 1, 2, 6 tAOFAS Disable R ZQ – 0.20V 0.40V 1, 2, 6 Notes: 1. MR settings are as follows: MR1 has A10 = 1, A9 = 1, A8 = 1 for R TT(NOM) setting; MR5 has A8 = 0, A7 = 0, A6 = 0 for RTT(Park) setting; and MR2 has A11 = 0, A10 = 1, A9 = 1 for RTT(WR) setting. 2. ODT state change is controlled by ODT pin. 3. ODT state change is controlled by a WRITE command. 4. Refer to Figure 238 (page 305). 5. Refer to Figure 239 (page 305). 6. Refer to Figure 240 (page 306). 16Gb: x4, x8, x16 DDR4 SDRAM Electrical Characteristics – On-Die Termination Characteristics CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 304 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Figure 240: tAOFAS and tAONAS Definitions tAOFAS tAONAS Rising edge of CK_t, CK_c with ODT being first registered LOW Rising edge of CK_t, CK_c with ODT being first registered HIGH End point: Extrapolated point at V RTT_NOM End point: Extrapolated point at VSSQ VRTT,nomVRTT,nom VSSQ VSSQ DQ, DM DQS_t, DQS_c TDQS_t, TDQS_c CK_c CK_t Vsw2 Vsw1 16Gb: x4, x8, x16 DDR4 SDRAM Electrical Characteristics – On-Die Termination Characteristics CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 306 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Table 131: DRAM Package Electrical Specifications for x4 and x8 Devices Parameter Symbol 1600/1866/2133/ 2400/2666 2933 3200 Unit NotesMin Max Min Max Min Max Input/ output Zpkg Z IO 45 85 48 85 48 85 ohm 1, 2, 4 Package delay Td IO 14 42 14 40 14 40 ps 1, 3, 4 Lpkg L IO – 3.3 – 3.3 – 3.3 nH 10 Cpkg C IO – 0.78 – 0.78 – 0.78 pF 11 DQS_t, DQS_c Zpkg Z IO DQS 45 85 48 85 48 85 ohm 1, 2 Package delay Td IO DQS 14 42 14 40 14 40 ps 1, 3 Delta Zpkg DZ IO DQS – 10 – 10 – 10 ohm 1, 2, 6 Delta delay DTd IO DQS –5–5–5 p s 1 , 3 , 6 Lpkg L IO DQS – 3.3 – 3.3 – 3.3 nH 10 Cpkg C IO DQS – 0.78 – 0.78 – 0.78 pF 11 Input CTRL pins Zpkg Z I CTRL 50 90 50 90 50 90 ohm 1, 2, 8 Package delay Td I CTRL 14 42 14 40 14 40 ps 1, 3, 8 Lpkg L I CTRL – 3.4 – 3.4 – 3.4 nH 10 Cpkg C I CTRL – 0.7 – 0.7 – 0.7 pF 11 Input CMD ADD pins Zpkg Z I ADD CMD 50 90 50 90 50 90 ohm 1, 2, 7 Package delay Td I ADD CMD 14 45 14 40 14 40 ps 1, 3, 7 Lpkg L I ADD CMD – 3.6 – 3.6 – 3.6 nH 10 Cpkg C I ADD CMD – 0.74 – 0.74 – 0.74 pF 11 CK_t, CK_c Zpkg Z CK 50 90 50 90 50 90 ohm 1, 2 Package delay Td CK 14 42 14 42 14 42 ps 1, 3 Delta Zpkg DZ DCK – 10 – 10 – 10 ohm 1, 2, 5 Delta delay DTd DCK – 5 – 5 – 5 ps 1, 3, 5 Lpkg L I CLK – 3.4 – 3.4 – 3.4 nH 10 Cpkg C I CLK – 0.7 – 0.7 – 0.7 pF 11 ZQ Zpkg Z O ZQ – 100 – 100 – 100 ohm 1, 2 ZQ delay Td O ZQ 20 90 20 90 20 90 ps 1, 3 ALERT Zpkg Z O ALERT 40 100 40 100 40 100 ohm 1, 2 ALERT delay Td O ALERT 20 55 20 55 20 55 ps 1, 3 Notes: 1. This parameter is not subject to a production test; it is verified by design and characteri- zation and are provided for reference; system signal simulations should not use these values but use the Micron package model. The package parasitic (L and C) are validated using package only samples. The capacitance is measured with V DD, VDDQ, VSS, and VSSQ shorted with all other signal pins floating. The inductance is measured with VDD, VDDQ, VSS, and VSSQ shorted and all other signal pins shorted at the die, not pin, side. 2. Package-only impedance (Zpkg) is calculated based on the Lpkg and Cpkg total for a given pin where: Zpkg (total per pin) = SQRT (Lpkg/Cpkg). 16Gb: x4, x8, x16 DDR4 SDRAM CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 307 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

1. Package-only delay (Tpkg) is calculated based on Lpkg and Cpkg total for a given pin where: Tdpkg (total per pin) = SQRT (Lpkg × Cpkg). 4. Z IO and TdIO apply to DQ, DM, TDQS_t and TDQS_c. 5. Absolute value of ZCK_t, ZCK_c for impedance (Z) or absolute value of TdCK_t, TdCK_c for delay (Td). 6. Absolute value of ZIO (DQS_t), ZIO (DQS_c) for impedance (Z) or absolute value of TdIO (DQS_t), TdIO (DQS_c) for delay (Td). 7. Z I ADD CMD and TdI ADD CMD apply to A[17:0], BA[1:0], BG[1:0], RAS_n CAS_n, WE_n, ACT_n, and PAR. 8. Z I CTRL and TdI CTRL apply to ODT, CS_n, and CKE. 9. Package implementations will meet specification if the Zpkg and package delay fall within the ranges shown, and the maximum Lpkg and Cpkg do not exceed the maxi- mum values shown. 10. It is assumed that Lpkg can be approximated as Lpkg = Z O × Td. 11. It is assumed that Cpkg can be approximated as Cpkg = Td/Z O. Table 132: DRAM Package Electrical Specifications for x16 Devices Parameter Symbol 1600/1866/2133/ 2400/2666 2933 3200 Unit NotesMin Max Min Max Min Max Input/ output Zpkg Z IO 45 85 45 85 45 85 ohm 1, 2, 4 Package delay Td IO 14 45 14 45 14 45 ps 1, 3, 4 Lpkg L IO – 3.4 – 3.4 – 3.4 nH 11 Cpkg C IO – 0.82 – 0.82 – 0.82 pF 11 LDQS_t/ LDQS_c/ UDQS_t/ UDQS_c Zpkg Z IO DQS 45 85 45 85 45 85 ohm 1, 2 Package delay Td IO DQS 14 45 14 45 14 45 ps 1, 3 Lpkg L IO DQS – 3.4 – 3.4 – 3.4 nH 11 Cpkg C IO DQS – 0.82 – 0.82 – 0.82 pF 11 LDQS_t/ LDQS_c, UDQS_t/ UDQS_c, Delta Zpkg DZ IO DQS – 10.5 – 10.5 – 10.5 ohm 1, 2, 6 Delta delay DTd IO DQS –5–5–5 p s 1 , 3 , 6 Input CTRL pins Zpkg Z I CTRL 50 90 50 90 50 90 ohm 1, 2, 8 Package delay Td I CTRL 14 42 14 42 14 42 ps 1, 3, 8 Lpkg L I CTRL – 3.4 – 3.4 – 3.4 nH 11 Cpkg C I CTRL – 0.7 – 0.7 – 0.7 pF 11 Input CMD ADD pins Zpkg Z I ADD CMD 50 90 50 90 50 90 ohm 1, 2, 7 Package delay Td I ADD CMD 14 52 14 52 14 52 ps 1, 3, 7 Lpkg L I ADD CMD – 3.9 – 3.9 – 3.9 nH 11 Cpkg C I ADD CMD – 0.86 – 0.86 – 0.86 pF 11 CK_t, CK_c Zpkg Z CK 50 90 50 90 50 90 ohm 1, 2 Package delay Td CK 14 42 14 42 14 42 ps 1, 3 Delta Zpkg DZ DCK – 10.5 – 10.5 – 10.5 ohm 1, 2, 5 Delta delay DTd DCK – 5 – 5 – 5 ps 1, 3, 5 16Gb: x4, x8, x16 DDR4 SDRAM CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 308 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Table 132: DRAM Package Electrical Specifications for x16 Devices (Continued) Parameter Symbol 1600/1866/2133/ 2400/2666 2933 3200 Unit NotesMin Max Min Max Min Max Input CLK Lpkg L I CLK – 3.4 – 3.4 – 3.4 nH 11 Cpkg C I CLK – 0.7 – 0.7 – 0.7 pF 11 ZQ Zpkg Z O ZQ – 100 – 100 – 100 ohm 1, 2 ZQ delay Td O ZQ 20 90 20 90 20 90 ps 1, 3 ALERT Zpkg Z O ALERT 40 100 40 100 40 100 ohm 1, 2 ALERT delay Td O ALERT 20 55 20 55 20 55 ps 1, 3 Notes: 1. This parameter is not subject to a production test; it is verified by design and characteri- zation and are provided for reference; system signal simulations should not use these values but use the Micron package model. The package parasitic (L and C) are validated using package only samples. The capacitance is measured with V DD, VDDQ, VSS, and VSSQ shorted with all other signal pins floating. The inductance is measured with VDD, VDDQ, VSS, and VSSQ shorted and all other signal pins shorted at the die, not pin, side. 2. Package-only impedance (Zpkg) is calculated based on the Lpkg and Cpkg total for a given pin where: Zpkg (total per pin) = SQRT (Lpkg/Cpkg). 3. Package-only delay (Tpkg) is calculated based on Lpkg and Cpkg total for a given pin where: Tdpkg (total per pin) = SQRT (Lpkg × Cpkg). 4. Z IO and TdIO apply to DQ, DM, TDQS_t and TDQS_c. 5. Absolute value of ZCK_t, ZCK_c for impedance (Z) or absolute value of TdCK_t, TdCK_c for delay (Td). 6. Absolute value of ZIO (DQS_t), ZIO (DQS_c) for impedance (Z) or absolute value of TdIO (DQS_t), TdIO (DQS_c) for delay (Td). 7. Z I ADD CMD and TdI ADD CMD apply to A[17:0], BA[1:0], BG[1:0], RAS_n CAS_n, WE_n, ACT_n, and PAR. 8. Z I CTRL and TdI CTRL apply to ODT, CS_n, and CKE. 9. Package implementations will meet specification if the Zpkg and package delay fall within the ranges shown, and the maximum Lpkg and Cpkg do not exceed the maxi- mum values shown. 10. It is assumed that Lpkg can be approximated as Lpkg = Z O × Td. 11. It is assumed that Cpkg can be approximated as Cpkg = Td/Z O. 16Gb: x4, x8, x16 DDR4 SDRAM CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 309 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Table 133: Pad Input/Output Capacitance Parameter Symbol DDR4-1600, 1866, 2133 DDR4-2400, Unit NotesMin Max Min Max Min Max Min Max Input/output capacitance: DQ, DM, DQS_t, DQS_c, TDQS_t, TDQS_c C Input capacitance: CK_t and CK_c Input capacitance delta: CK_t and CK_c CDCK - 0.05 - 0.05 - 0.05 - 0.05 pF 2, 3, 6 Input/output capacitance del- ta: DQS_t and DQS_c CDDQS - 0.05 - 0.05 - 0.05 - 0.05 pF 2, 3, 5 Input capacitance: CTRL, ADD, CMD input-only pins Input capacitance delta: All CTRL input-only pins Input capacitance delta: All ADD/CMD input-only pins CDI_ADD_CM D Input/output capacitance del- ta: DQ, DM, DQS_t, DQS_c, TDQS_t, TDQS_c C Input/output capacitance: ALERT pin Input/output capacitance: ZQ pin Input/output capacitance: TEN pin Notes: 1. Although the DM, TDQS_t, and TDQS_c pins have different functions, the loading matches DQ and DQS. 2. This parameter is not subject to a production test; it is verified by design and characteri- zation and are provided for reference; system signal simulations should not use these values but use the Micron package model. The capacitance, if and when, is measured ac- cording to the JEP147 specification, “Procedure for Measuring Input Capacitance Using a Vector Network Analyzer (VNA),” with V DD, VDDQ, VSS, and VSSQ applied and all other pins floating (except the pin under test, CKE, RESET_n and ODT, as necessary). VDD = VDDQ = 1.2V, VBIAS = VDD/2 and on-die termination off. Measured data is rounded using industry standard half-rounded up methodology to the nearest hundredth of the MSB. 3. This parameter applies to monolithic die, obtained by de-embedding the package L and C parasitics. 4. C DIO = CIO(DQ, DM) - 0.5 × (CIO(DQS_t) + CIO(DQS_c)). 5. Absolute value of C IO (DQS_t), CIO (DQS_c) 6. Absolute value of CCK_t, CCK_c 7. C I applies to ODT, CS_n, CKE, A[17:0], BA[1:0], BG[1:0], RAS_n, CAS_n, ACT_n, PAR and WE_n. 8. C DI_CTRL applies to ODT, CS_n, and CKE. 16Gb: x4, x8, x16 DDR4 SDRAM CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 310 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

1. C DI_CTRL = CI(CTRL) - 0.5 × (CI(CLK_t) + CI(CLK_c)). 10. C DI_ADD_CMD applies to A[17:0], BA1:0], BG[1:0], RAS_n, CAS_n, ACT_n, PAR and WE_n. 11. C DI_ADD_CMD = CI(ADD_CMD) - 0.5 × (CI(CLK_t) + CI(CLK_c)). 12. Maximum external load capacitance on ZQ pin: 5pF. 13. Only applicable if TEN pin does not have an internal pull-up. Thermal Characteristics Table 134: Thermal Characteristics Parameter/Condition Value Units Symbol Notes Operating case temperature: Commercial 0 to +85 °C T C 1, 2, 3 0 to +95 °C T C 1, 2, 3, 4 Operating case temperature: Industrial –40 to +85 °C T C 1, 2, 3 –40 to +95 °C T C 1, 2, 3, 4 Operating case temperature: Automotive –40 to +85 °C T C 1, 2, 3 –40 to +105 °C T C 1, 2, 3, 4 REV B 78-ball “VA” Junction-to-case (TOP) 3.6 °C/W ˆJC 5 Junction-to-board 13.6 °C/W ˆJB 96-ball “RC” Junction-to-case (TOP) 3.5 °C/W ˆJC 5 Junction-to-board 12.7 °C/W ˆJB REV E 78-ball “JC” Junction-to-case (TOP) 4.2 °C/W ˆJC 5 Junction-to-board 13 °C/W ˆJB 96-ball “KD” Junction-to-case (TOP) 4.1 °C/W ˆJC 5 Junction-to-board 12.3 °C/W ˆJB Notes: 1. MAX operating case temperature. T C is measured in the center of the package. 2. A thermal solution must be designed to ensure the DRAM device does not exceed the maximum TC during operation. 3. Device functionality is not guaranteed if the DRAM device exceeds the maximum T C dur- ing operation. 4. If T C exceeds 85°C, the DRAM must be refreshed externally at 2x refresh, which is a 3.9μs interval refresh rate. 5. The thermal resistance data is based off of a typical number. 16Gb: x4, x8, x16 DDR4 SDRAM Thermal Characteristics CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 311 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Figure 241: Thermal Measurement Point (L/2) L W (W/2) TC test point Current Specifications – Measurement Conditions IDD, IPP, and IDDQ Measurement Conditions IDD, IPP, and IDDQ measurement conditions, such as test load and patterns, are defined in this section.

• I DD currents (IDD0, IDD1, IDD2N, IDD2NT, IDD2P, IDD2Q, IDD3N, IDD3P, IDD4R, IDD4W, IDD5R, IDD6N, IDD6E, IDD6R, IDD6A, IDD7, and IDD8) are measured as time-averaged currents with all VDD balls of the device under test grouped together.
• I PP currents are IPP3N for standby cases (IDD2N, IDD2NT, IDD2P, IDD2Q, IDD3N, IDD3P, IDD8), IPP0 for active cases (IDD0,IDD1, IDD4R, IDD4W), IPP5R for the distributed refresh case (IDD5R), IPP6x for self refresh cases (IDD6N, IDD6E, IDD6R, IDD6A) and IPP7 for the operating bank interleave read case (IDD7). These have the same definitions as the IDD currents referenced but are measured on the VPP supply.
• I DDQ currents are measured as time-averaged currents with VDDQ balls of the device under test grouped together. Micron does not specify IDDQ currents.
• I PP and IDDQ currents are not included in IDD currents, IDD and IDDQ currents are not included in IPP currents, and IDD and IPP currents are not included in IDDQ currents. Note: IDDQ values cannot be directly used to calculate the I/O power of the device. They can be used to support correlation of simulated I/O power to actual I/O power. In DRAM module application, I DDQ cannot be measured separately because VDD and VDDQ are using a merged-power layer in the module PCB. The following definitions apply for IDD, IPP and IDDQ measurements.
• “0” and “LOW” are defined as V IN ืVIL(AC)max
• “1” and “HIGH” are defined as V IN ุVIH(AC)min
• “Midlevel” is defined as inputs V REF = VDD/2
• Timings used for I DD, IPP and IDDQ measurement-loop patterns are provided in the Current Test Definition and Patterns section. 16Gb: x4, x8, x16 DDR4 SDRAM Current Specifications – Measurement Conditions CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 312 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

• Basic I DD, IPP, and IDDQ measurement conditions are described in the Current Test Definition and Patterns section.
• Detailed I DD, IPP, and IDDQ measurement-loop patterns are described in the Current Test Definition and Patterns section.
• Current measurements are done after properly initializing the device. This includes, but is not limited to, setting: R ON = RZQ/7 (34 ohm in MR1); Qoff = 0B (output buffer enabled in MR1); R TT(NOM) = RZQ/6 (40 ohm in MR1); RTT(WR) = RZQ/2 (120 ohm in MR2); RTT(Park) = disabled; TDQS feature disabled in MR1; CRC disabled in MR2; CA parity feature disabled in MR3; Gear-down mode disabled in MR3; Read/Write DBI disabled in MR5; DM disa- bled in MR5
• Define D = {CS_n, RAS_n, CAS_n, WE_n}: = {HIGH, LOW, LOW, LOW}; apply BG/BA changes when directed.
• Define D_n = {CS_n, RAS_n, CAS_n, WE_n}: = {HIGH, HIGH, HIGH, HIGH}; apply in- vert of BG/BA changes when directed above. Note: The measurement-loop patterns must be executed at least once before actual cur- rent measurements can be taken. Figure 242: Measurement Setup and Test Load for I DDx, IPPx, and IDDQx IDD CK_t/CK_c CS_n CKE ODT VDD VDDQ VSS VSSQ RESET_n ACT_n, RAS_n, CAS_n, WE_n DQS_t, DQS_c DQ DM_n ZQ A, BG, BA IDDQ C IPP VPP DDR4 SDRAM 16Gb: x4, x8, x16 DDR4 SDRAM Current Specifications – Measurement Conditions CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 313 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Figure 243: Correlation: Simulated Channel I/O Power to Actual Channel I/O Power Application-specific memory channel environment Channe l I/O power simulation IDD Q test load IDD Q simulation IDD Q measurement Correlation Correction Channe l I/O power number Note: 1. Supported by I DDQ measurement. IDD Definitions Table 135: Basic IDD, IPP, and IDDQ Measurement Conditions Symbol Description IDD0 Operating One Bank Active-Precharge Current (AL = 0) CKE: HIGH; External clock: On; tCK, nRC, nRAS, CL: see the previous table; BL: 8;1 AL: 0; CS_n: HIGH between ACT and PRE; Command, address, bank group address, bank address inputs: partially toggling according to the next table; Data I/O: V DDQ; DM_n: stable at 0; Bank activity: cycling with one bank active at a time: 0, 0, 1, 1, 2, 2, ... (see the IDD0 Measurement-Loop Pattern table); Output buffer and RTT: enabled in mode registers;2 ODT signal: stable at 0; Pattern details: see the IDD0 Measurement-Loop Pattern table IPP0 Operating One Bank Active-Precharge IPP Current (AL = 0) Same conditions as IDD0 above IDD1 Operating One Bank Active-Read-Precharge Current (AL = 0) CKE: HIGH; External clock: on; tCK, nRC, nRAS, nRCD, CL: see the previous table; BL: 8;1, 5 AL: 0; CS_n: HIGH between ACT, RD, and PRE; Command, address, bank group address, bank address inputs, Data I/O: partially toggling according to the I DD1 Measurement-Loop Pattern table; DM_n: stable at 0; Bank activity: cycling with one bank active at a time: 0, 0, 1, 1, 2, 2, ... (see the following table); Output buffer and RTT: enabled in mode registers;2 ODT Signal: stable at 0; Pattern details: see the IDD1 Measurement-Loop Pattern table IDD2N Precharge Standby Current (AL = 0) CKE: HIGH; External clock: On; tCK, CL: see the previous table; BL: 8;1 AL: 0; CS_n: stable at 1; Command, ad- dress, bank group address, bank address Inputs: partially toggling according to the IDD2N and IDD3N Measure- ment-Loop Pattern table; Data I/O: VDDQ; DM_n: stable at 1; Bank activity: all banks closed; Output buffer and RTT: enabled in mode registers;2 ODT signal: stable at 0; Pattern details: see the IDD2N and IDD3N Measurement- Loop Pattern table 16Gb: x4, x8, x16 DDR4 SDRAM Current Specifications – Measurement Conditions CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 314 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Table 135: Basic IDD, IPP, and IDDQ Measurement Conditions (Continued) Symbol Description IDD2NT Precharge Standby ODT Current CKE: HIGH; External clock: on; tCK, CL: see the previous table; BL: 8;1 AL: 0; CS_n: stable at 1; Command, ad- dress, bank gropup address, bank address inputs: partially toggling according to the IDD2NT Measurement-Loop Pattern table; Data I/O: VSSQ; DM_n: stable at 1; Bank activity: all banks closed; Output buffer and RTT: enabled in mode registers;2 ODT signal: toggling according to the IDD2NT Measurement-Loop Pattern table; Pattern de- tails: see the IDD2NT Measurement-Loop Pattern table IDD2P Precharge Power-Down Current CKE: LOW; External clock: on; tCK, CL: see the previous table; BL: 8;1 AL: 0; CS_n: stable at 1; Command, ad- dress, bank group address, bank address inputs: stable at 0; Data I/O: VDDQ; DM_n: stable at 1; Bank activity: all banks closed; Output buffer and RTT: Enabled in mode registers;2 ODT signal: stable at 0 IDD2Q Precharge Quiet Standby Current CKE: HIGH; External clock: on; tCK, CL: see the previous table; BL: 8;1 AL: 0; CS_n: stable at 1; Command, ad- dress, bank group address, bank address inputs: stable at 0; Data I/O: VDDQ; DM_n: stable at 1; Bank activity: all banks closed; Output buffer and RTT: Enabled in mode registers;2 ODT signal: stable at 0 IDD3N Active Standby Current (AL = 0) CKE: HIGH; External clock: on; tCK, CL: see the previous table; BL: 8;1 AL: 0; CS_n: stable at 1; Command, ad- dress, bank group address, bank address inputs: partially toggling according to the IDD2N and IDD3N Measure- ment-Loop Pattern table; Data I/O: VDDQ; DM_n: stable at 1; Bank activity: all banks open; Output buffer and RTT: Enabled in mode registers;2 ODT signal: stable at 0; Pattern details: see the IDD2N and IDD3N Measurement- Loop Pattern table IPP3N Active Standby IPP3N Current (AL = 0) Same conditions as IDD3N above IDD3P Active Power-Down Current (AL = 0) CKE: LOW; External clock: on; tCK, CL: see the previous table; BL: 8;1 AL: 0; CS_n: stable at 1; Command, ad- dress, bank group address, bank address inputs: stable at 1; Data I/O: VDDQ; DM_n: stable at 1; Bank activity: all banks open; Output buffer and RTT: Enabled in mode registers;2 ODT signal: stable at 0 IDD4R Operating Burst Read Current (AL = 0) CKE: HIGH; External clock: on; tCK, CL: see the previous table; BL: 8;15 AL: 0; CS_n: HIGH between RD; Com- mand, address, bank group address, bank address inputs: partially toggling according to the IDD4R Measure- ment-Loop Pattern table; Data I/O: seamless read data burst with different data between one burst and the next one according to the I DD4R Measurement-Loop Pattern table; DM_n: stable at 1; Bank activity: all banks open, RD commands cycling through banks: 0, 0, 1, 1, 2, 2, ... (see the IDD4R Measurement-Loop Pattern table); Output buffer and RTT: Enabled in mode registers;2 ODT signal: stable at 0; Pattern details: see the IDD4R Meas- urement-Loop Pattern table IDD4W Operating Burst Write Current (AL = 0) CKE: HIGH; External clock: on; tCK, CL: see the previous table; BL: 8;1 AL: 0; CS_n: HIGH between WR; Com- mand, address, bank group address, bank address inputs: partially toggling according to the IDD4W Measure- ment-Loop Pattern table; Data I/O: seamless write data burst with different data between one burst and the next one according to the I DD4W Measurement-Loop Pattern table; DM: stable at 0; Bank activity: all banks open, WR commands cycling through banks: 0, 0, 1, 1, 2, 2, ... (see IDD4W Measurement-Loop Pattern table); Output buffer and RTT: enabled in mode registers (see note2); ODT signal: stable at HIGH; Pattern details: see the IDD4W Measurement-Loop Pattern table 16Gb: x4, x8, x16 DDR4 SDRAM Current Specifications – Measurement Conditions CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 315 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Table 135: Basic IDD, IPP, and IDDQ Measurement Conditions (Continued) Symbol Description IDD5R Distributed Refresh Current (1X REF) CKE: HIGH; External clock: on; tCK, CL, nREFI: see the previous table; BL: 8;1 AL: 0; CS_n: HIGH between REF; Command, address, bank group address, bank address inputs: partially toggling according to the IDD5R Meas- urement-Loop Pattern table; Data I/O: VDDQ; DM_n: stable at 1; Bank activity: REF command every nREFI (see the IDD5R Measurement-Loop Pattern table); Output buffer and RTT: enabled in mode registers2; ODT signal: stable at 0; Pattern details: see the IDD5R Measurement-Loop Pattern table IPP5R Distributed Refresh Current (1X REF) Same conditions as IDD5R above IDD6N Self Refresh Current: Normal Temperature Range TC: 0–85°C; Auto self refresh (ASR): disabled;3 Self refresh temperature range (SRT): normal;4 CKE: LOW; Exter- nal clock: off; CK_t and CK_c: LOW; CL: see the table above; BL: 8;1 AL: 0; CS_n, command, address, bank group address, bank address, data I/O: VDDQ; DM_n: stable at 1; Bank activity: SELF REFRESH operation; Output buffer and RTT: enabled in mode registers;2 ODT signal: midlevel IDD6E Self Refresh Current: Extended Temperature Range 4 TC: 0–95°C; Auto self refresh (ASR): disabled4; Self refresh temperature range (SRT): extended;4 CKE: LOW; Ex- ternal clock: off; CK_t and CK_c: LOW; CL: see the previous table; BL: 8;1 AL: 0; CS_n, command, address, group bank address, bank address, data I/O: VDDQ; DM_n: stable at 1; Bank activity: EXTENDED TEMPERATURE SELF REFRESH operation; Output buffer and RTT: enabled in mode registers;2 ODT signal: midlevel IPP6x Self Refresh IPP Current Same conditions as IDD6E above IDD6R Self Refresh Current: Reduced Temperature Range TC: 0–45°C; Auto self refresh (ASR): disabled; Self refresh temperature range (SRT): reduced;4 CKE: LOW; Exter- nal clock: off; CK_t and CK_c: LOW; CL: see the previous table; BL: 8;1 AL: 0; CS_n, command, address, bank group address, bank address, data I/O: VDDQ; DM_n: stable at 1; Bank activity: EXTENDED TEMPERATURE SELF REFRESH operation; Output buffer and RTT: enabled in mode registers;2 ODT signal: midlevel IDD7 Operating Bank Interleave Read Current CKE: HIGH; External clock: on; tCK, nRC, nRAS, nRCD, nRRD, nFAW, CL: see the previous table; BL: 8;15 AL: CL - 1; CS_n: HIGH between ACT and RDA; Command, address, group bank adress, bank address inputs: partially toggling according to the I DD7 Measurement-Loop Pattern table; Data I/O: read data bursts with different data between one burst and the next one according to the IDD7 Measurement-Loop Pattern table; DM: stable at 1; Bank activity: two times interleaved cycling through banks (0, 1, ...7) with different addressing, see the IDD7 Measurement-Loop Pattern table; Output buffer and RTT: enabled in mode registers;2 ODT signal: stable at 0; Pattern details: see the IDD7 Measurement-Loop Pattern table IPP7 Operating Bank Interleave Read IPP Current Same conditions as IDD7 above IDD8 Maximum Power Down Current Place DRAM in MPSM then CKE: HIGH; External clock: on; tCK, CL: see the previous table; BL: 8;1 AL: 0; CS_n: stable at 1; Command, address, bank group address, bank address inputs: stable at 0; Data I/O: VDDQ; DM_n: stable at 1; Bank activity: all banks closed; Output buffer and RTT: Enabled in mode registers;2 ODT signal: sta- ble at 0 Notes: 1. Burst length: BL8 fixed by MRS: set MR0[1:0] 00. 2. Output buffer enable: set MR1[12] 0 (output buffer enabled); set MR1[2:1] 00 (R ON = RZQ/7); RTT(NOM) enable: set MR1[10:8] 011 (RZQ/6); RTT(WR) enable: set MR2[11:9] 001 (RZQ/2), and RTT(Park) enable: set MR5[8:6] 000 (disabled). 3. Auto self refresh (ASR): set MR2[6] 0 to disable or MR2[6] 1 to enable feature. 16Gb: x4, x8, x16 DDR4 SDRAM Current Specifications – Measurement Conditions CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 316 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

1. Self refresh temperature range (SRT): set MR2[7] 0 for normal or MR2[7] 1 for extended temperature range. 5. READ burst type: Nibble sequential, set MR0[3] 0. 6. In the dual-rank DDP case, note the following IDD measurement considerations:

• For all IDD measurements except IDD6, the unselected rank should be in an IDD2P condition.
• For all IPP measurements except IPP6, the unselected rank should be in an IDD3N con- dition.
• For all IDD6/IPP6 measurements, both ranks should be in the same IDD6 condition. 16Gb: x4, x8, x16 DDR4 SDRAM Current Specifications – Measurement Conditions CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 317 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Current Specifications – Patterns and Test Conditions Current Test Definitions and Patterns Table 136: IDD0 and IPP0 Measurement-Loop Pattern1 CK_t, CK_c CKE Sub-Loop Cycle Number Command CS_n ACT_n RAS_n/A16 CAS_n/A15 WE_n/A14 ODT BG[1:0]2 BA[1:0] A12/BC_n A[17,13,11]] A[10]/AP A[9:7] A[6:3] A[2:0] Data3 Toggling Static High 0 0 A C T00000000000000 – 1 , 2 D , D10000000000000 – 3, 4 D_n, D_n 111110330007F0 – nR A S P R E01010000000000 – 1 1 × nRC Repeat sub-loop 0, use BG[1:0] = 1, use BA[1:0] = 1 instead 2 2 × nRC Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 2 instead 3 3 × nRC Repeat sub-loop 0, use BG[1:0] = 1, use BA[1:0] = 3 instead 4 4 × nRC Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 1 instead 5 5 × nRC Repeat sub-loop 0, use BG[1:0] = 1, use BA[1:0] = 2 instead 6 6 × nRC Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 3 instead 7 7 × nRC Repeat sub-loop 0, use BG[1:0] = 1, use BA[1:0] = 0 instead 8 8 × nRC Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 0 instead 9 9 × nRC Repeat sub-loop 0, use BG[1:0] = 3, use BA[1:0] = 1 instead 4 10 10 × nRC Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 2 instead 4 11 11 × nRC Repeat sub-loop 0, use BG[1:0] = 3, use BA[1:0] = 3 instead 4 12 12 × nRC Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 1 instead 4 13 13 × nRC Repeat sub-loop 0, use BG[1:0] = 3, use BA[1:0] = 2 instead 4 14 14 × nRC Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 3 instead 4 15 15 × nRC Repeat sub-loop 0, use BG[1:0] = 3, use BA[1:0] = 0 instead 4 Notes: 1. DQS_t, DQS_c are V DDQ. 2. BG1 is a "Don't Care" for x16 devices. 3. DQ signals are V DDQ. 4. For x4 and x8 only. 16Gb: x4, x8, x16 DDR4 SDRAM Current Specifications – Patterns and Test Conditions CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 318 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Table 137: IDD1 Measurement – Loop Pattern1 CK_c, CK_t, CKE Sub-Loop Cycle Number Command CS_n ACT_n RAS_n/A16 CAS_n/A15 WE_n/A14 ODT BG[1:0]2 BA[1:0] A12/BC_n A[17,13,11]] A[10]/AP A[9:7] A[6:3] A[2:0] Data3 Toggling Static High 0 0 A C T 00000000000000 – 1 , 2 D , D 10000000000000 – 3, 4 D_n, D_n 1 1 1 1 1 0 3 3 0 0 0 7 F 0 – nRCD - AL RD 0 1 1 0 1 0 0 0 0 0 0 0 0 0 D0 = 00, D1 = FF, D2 = FF, D3 = 00, D4 = FF, D5 = 00, D5 = 00, D7 = FF nR A S P R E 01010000000000 1 1 × nR C + 0 A C T 00011011000000 – 1 × nRC + 1, D , D 10000000000000 – 1 × nRC + 3, D_n, D_n 1 1 1 1 1 0 3 3 0 0 0 7 F 0 – 1 × nRC +nRCD - AL RD 0 1 1 0 1 0 1 1 0 0 0 0 0 0 D0 = FF, D1 = 00, D2 = 00, D3 = FF, D4 = 00, D5 = FF, D5 = FF, D7 = 00 1 × nRC + nRAS P R E 01010011000000 2 2 × nRC Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 2 instead 3 3 × nRC Repeat sub-loop 0, use BG[1:0] = 1, use BA[1:0] = 3 instead 4 4 × nRC Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 1 instead 5 5 × nRC Repeat sub-loop 0, use BG[1:0] = 1, use BA[1:0] = 2 instead 6 6 × nRC Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 3 instead 7 7 × nRC Repeat sub-loop 0, use BG[1:0] = 1, use BA[1:0] = 0 instead 8 9 × nRC Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 0 instead 9 10 × nRC Repeat sub-loop 0, use BG[1:0] = 3, use BA[1:0] = 1 instead 4 10 11 × nRC Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 2 instead 4 11 12 × nRC Repeat sub-loop 0, use BG[1:0] = 3, use BA[1:0] = 3 instead 4 12 13 × nRC Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 1 instead 4 13 14 × nRC Repeat sub-loop 0, use BG[1:0] = 3, use BA[1:0] = 2 instead 4 14 15 × nRC Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 3 instead 4 15 16 × nRC Repeat sub-loop 0, use BG[1:0] = 3, use BA[1:0] = 0 instead 4 Notes: 1. DQS_t, DQS_c are V DDQ when not toggling. 16Gb: x4, x8, x16 DDR4 SDRAM Current Specifications – Patterns and Test Conditions CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 319 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

1. BG1 is a "Don't Care" for x16 devices. 3. DQ signals are V DDQ except when burst sequence drives each DQ signal by a READ com- mand. 4. For x4 and x8 only. Table 138: IDD2N, IDD3N, and IPP3P Measurement – Loop Pattern1 CK_c, CK_t, CKE Sub-Loop Cycle Number Command CS_n ACT_n RAS_n/A16 CAS_n/A15 WE_n/A14 ODT BG[1:0]2 BA[1:0] A12/BC_n A[17,13,11]] A[10]/AP A[9:7] A[6:3] A[2:0] Data3 Toggling Static High 0 0 D 10000000000000 –

1 D 10000000000000 –

2 D _ n111110330007F0 –

3 D _ n111110330007F0 –

1 4–7 Repeat sub-loop 0, use BG[1:0] = 1, use BA[1:0] = 1 instead 2 8–11 Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 2 instead 3 12–15 Repeat sub-loop 0, use BG[1:0] = 1, use BA[1:0] = 3 instead 4 16–19 Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 1 instead 5 20–23 Repeat sub-loop 0, use BG[1:0] = 1, use BA[1:0] = 2 instead 6 24–27 Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 3 instead 7 28–31 Repeat sub-loop 0, use BG[1:0] = 1, use BA[1:0] = 0 instead 8 32–35 Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 0 instead 9 36–39 Repeat sub-loop 0, use BG[1:0] = 3, use BA[1:0] = 1 instead 4 10 40–43 Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 2 instead 4 11 44–47 Repeat sub-loop 0, use BG[1:0] = 3, use BA[1:0] = 3 instead 4 12 48–51 Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 1 instead 4 13 52–55 Repeat sub-loop 0, use BG[1:0] = 3, use BA[1:0] = 2 instead 4 14 56–59 Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 3 instead 4 15 60–63 Repeat sub-loop 0, use BG[1:0] = 3, use BA[1:0] = 0 instead 4 Notes: 1. DQS_t, DQS_c are V DDQ. 2. BG1 is a "Don't Care" for x16 devices. 3. DQ signals are V DDQ. 4. For x4 and x8 only. 16Gb: x4, x8, x16 DDR4 SDRAM Current Specifications – Patterns and Test Conditions CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 320 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Table 139: IDD2NT Measurement – Loop Pattern1 CK_c, CK_t, CKE Sub-Loop Cycle Number Command CS_n ACT_n RAS_n/A16 CAS_n/A15 WE_n/A14 ODT BG[1:0]2 BA[1:0] A12/BC_n A[17,13,11]] A[10]/AP A[9:7] A[6:3] A[2:0] Data3 Toggling Static High 0 0 D 10000000000000 – 1 4–7 Repeat sub-loop 0 with ODT = 1, use BG[1:0] = 1, use BA[1:0] = 1 instead 2 8–11 Repeat sub-loop 0 with ODT = 0, use BG[1:0] = 0, use BA[1:0] = 2 instead 3 12–15 Repeat sub-loop 0 with ODT = 1, use BG[1:0] = 1, use BA[1:0] = 3 instead 4 16–19 Repeat sub-loop 0 with ODT = 0, use BG[1:0] = 0, use BA[1:0] = 1 instead 5 20–23 Repeat sub-loop 0 with ODT = 1, use BG[1:0] = 1, use BA[1:0] = 2 instead 6 24–27 Repeat sub-loop 0 with ODT = 0, use BG[1:0] = 0, use BA[1:0] = 3 instead 7 28–31 Repeat sub-loop 0 with ODT = 1, use BG[1:0] = 1, use BA[1:0] = 0 instead 8 32–35 Repeat sub-loop 0 with ODT = 0, use BG[1:0] = 2, use BA[1:0] = 0 instead 9 36–39 Repeat sub-loop 0 with ODT = 1, use BG[1:0] = 3, use BA[1:0] = 1 instead 4 10 40–43 Repeat sub-loop 0 with ODT = 0, use BG[1:0] = 2, use BA[1:0] = 2 instead 4 11 44–47 Repeat sub-loop 0 with ODT = 1, use BG[1:0] = 3, use BA[1:0] = 3 instead 4 12 48–51 Repeat sub-loop 0 with ODT = 0, use BG[1:0] = 2, use BA[1:0] = 1 instead 4 13 52–55 Repeat sub-loop 0 with ODT = 1, use BG[1:0] = 3, use BA[1:0] = 2 instead 4 14 56–59 Repeat sub-loop 0 with ODT = 0, use BG[1:0] = 2, use BA[1:0] = 3 instead 4 15 60–63 Repeat sub-loop 0 with ODT = 1, use BG[1:0] = 3, use BA[1:0] = 0 instead 4 Notes: 1. DQS_t, DQS_c are V SSQ. 2. BG1 is a "Don't Care" for x16 devices. 3. DQ signals are V SSQ. 4. For x4 and x8 only. 16Gb: x4, x8, x16 DDR4 SDRAM Current Specifications – Patterns and Test Conditions CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 321 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Table 140: IDD4R Measurement – Loop Pattern1 CK_c, CK_t, CKE Sub-Loop Cycle Number Command CS_n ACT_n RAS_n/A16 CAS_n/A15 WE_n/A14 ODT BG[1:0]2 BA[1:0] A12/BC_n A[17,13,11]] A[10]/AP A[9:7] A[6:3] A[2:0] Data3 Toggling Static High 0 0 RD 0 1 1 0 1 0 0 0 0 0 0 0 0 0 D0 = 00, D1 = FF, D2 = FF, D3 = 00, D4 = FF, D5 = 00, D5 = 00, D7 = FF

1 D 10000000000000

2, 3 D_n, D_n 111110330007F0 1 4 RD 0 1 1 0 1 0 1 1 0 0 0 7 F 0 D0 = FF, D1 = 00 D2 = 00, D3 = FF D4 = 00, D5 = FF D5 = FF, D7 = 00

5 D 10000000000000

6, 7 D_n, D_n 111110330007F0 2 8–11 Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 2 instead 3 12–15 Repeat sub-loop 1, use BG[1:0] = 1, use BA[1:0] = 3 instead 4 16–19 Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 1 instead 5 20–23 Repeat sub-loop 1, use BG[1:0] = 1, use BA[1:0] = 2 instead 6 24–27 Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 3 instead 7 28–31 Repeat sub-loop 1, use BG[1:0] = 1, use BA[1:0] = 0 instead 8 32–35 Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 0 instead 9 36–39 Repeat sub-loop 1, use BG[1:0] = 3, use BA[1:0] = 1 instead 4 10 40–43 Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 2 instead 4 11 44–47 Repeat sub-loop 1, use BG[1:0] = 3, use BA[1:0] = 3 instead 4 12 48–51 Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 1 instead 4 13 52–55 Repeat sub-loop 1, use BG[1:0] = 3, use BA[1:0] = 2 instead 4 14 56–59 Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 3 instead 4 15 60–63 Repeat sub-loop 1, use BG[1:0] = 3, use BA[1:0] = 0 instead 4 Notes: 1. DQS_t, DQS_c are V DDQ when not toggling. 2. BG1 is a "Don't Care" for x16 devices. 3. Burst sequence driven on each DQ signal by a READ command. Outside burst operation, DQ signals are V DDQ. 4. For x4 and x8 only. 16Gb: x4, x8, x16 DDR4 SDRAM Current Specifications – Patterns and Test Conditions CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 322 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Table 141: IDD4W Measurement – Loop Pattern1 CK_c, CK_t, CKE Sub-Loop Cycle Number Com- mand CS_n ACT_n RAS_n/A1 CAS_n/A1 WE_n/A14 ODT BG[1:0]2 BA[1:0] A12/BC_n A[17,13,1 1]] A[10]/AP A[9:7] A[6:3] A[2:0] Data3 Toggling Static High 0 0 W R01100100000000 D 0 = 00, D1 = FF, D2 = FF, D3 = 00, D4 = FF, D5 = 00, D5 = 00, D7 = FF

1 D 10000100000000

2, 3 D_n, D_n 111101330007F0 1 4 W R011001110007F0 D 0 = F F , D 1 = 0 0 D2 = 00, D3 = FF D4 = 00, D5 = FF D5 = FF, D7 = 00

5 D 10000100000000

6, 7 D_n, D_n 111101330007F0 2 8–11 Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 2 instead 3 12–15 Repeat sub-loop 1, use BG[1:0] = 1, use BA[1:0] = 3 instead 4 16–19 Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 1 instead 5 20–23 Repeat sub-loop 1, use BG[1:0] = 1, use BA[1:0] = 2 instead 6 24–27 Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 3 instead 7 28–31 Repeat sub-loop 1, use BG[1:0] = 1, use BA[1:0] = 0 instead 8 32–35 Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 0 instead 9 36–39 Repeat sub-loop 1, use BG[1:0] = 3, use BA[1:0] = 1 instead 4 10 40–43 Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 2 instead 4 11 44–47 Repeat sub-loop 1, use BG[1:0] = 3, use BA[1:0] = 3 instead 4 12 48–51 Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 1 instead 4 13 52–55 Repeat sub-loop 1, use BG[1:0] = 3, use BA[1:0] = 2 instead 4 14 56–59 Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 3 instead 4 15 60–63 Repeat sub-loop 1, use BG[1:0] = 3, use BA[1:0] = 0 instead 4 Notes: 1. DQS_t, DQS_c are V DDQ when not toggling. 2. BG1 is a "Don't Care" for x16 devices. 3. Burst sequence driven on each DQ signal by WRITE command. Outside burst operation, DQ signals are V DDQ. 4. For x4 and x8 only. 16Gb: x4, x8, x16 DDR4 SDRAM Current Specifications – Patterns and Test Conditions CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 323 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Table 142: IDD4Wc Measurement – Loop Pattern1 CK_c, CK_t, CKE Sub-Loop Cycle Number Command CS_n ACT_n RAS_n/A16 CAS_n/A15 WE_n/A14 ODT BG[1:0]3 BA[1:0] A12/BC_n A[17,13,11]] A[10]/AP A[9:7] A[6:3] A[2:0] Data4 Toggling Static High 0 0 W R01100100000000 D 0 = 00, D1 = FF, D2 = FF, D3 = 00, D4 = FF, D5 = 00, D8 = CRC 1 , 2 D , D10000100000000 3, 4 D_n, D_n 111101330007F0 1 5 W R011001110007F0 D 0 = F F , D 1 = 0 0 , D2 = 00, D3 = FF, D4 = 00, D5 = FF, D5 = FF, D7 = 00 D8 = CRC 6 , 7 D , D10000100000000 8, 9 D_n, D_n 111101330007F0 2 10–14 Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 2 instead 3 15–19 Repeat sub-loop 1, use BG[1:0] = 1, use BA[1:0] = 3 instead 4 20–24 Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 1 instead 5 25–29 Repeat sub-loop 1, use BG[1:0] = 1, use BA[1:0] = 2 instead 6 30–34 Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 3 instead 7 35–39 Repeat sub-loop 1, use BG[1:0] = 1, use BA[1:0] = 0 instead 8 40–44 Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 0 instead 9 45–49 Repeat sub-loop 1, use BG[1:0] = 3, use BA[1:0] = 1 instead 4 10 50–54 Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 2 instead 4 11 55–59 Repeat sub-loop 1, use BG[1:0] = 3, use BA[1:0] = 3 instead 4 12 60–64 Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 1 instead 4 13 65–69 Repeat sub-loop 1, use BG[1:0] = 3, use BA[1:0] = 2 instead 4 14 70–74 Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 3 instead 4 15 75–79 Repeat sub-loop 1, use BG[1:0] = 3, use BA[1:0] = 0 instead 4 Notes: 1. Pattern provided for reference only. 2. DQS_t, DQS_c are V DDQ when not toggling. 3. BG1 is a "Don't Care" for x16 devices. 4. Burst sequence driven on each DQ signal by WRITE command. Outside burst operation, DQ signals are V DDQ. 5. For x4 and x8 only. 16Gb: x4, x8, x16 DDR4 SDRAM Current Specifications – Patterns and Test Conditions CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 324 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Table 143: IDD5R Measurement – Loop Pattern1 CK_c, CK_t, CKE Sub-Loop Cycle Number Command CS_n ACT_n RAS_n/A16 CAS_n/A15 WE_n/A14 ODT BG[1:0]2 BA[1:0] A12/BC_n A[17,13,11]] A[10]/AP A[9:7] A[6:3] A[2:0] Data3 Toggling Static High 0 0 R E F01001000000000 – 1 1 D 10000000000000 –

2 D 10000000000000 –

4 D _ n111110330007F0 –

5–8 Repeat pattern 1...4, use BG[1:0] = 1, use BA[1:0] = 1 instead 9–12 Repeat pattern 1...4, use BG[1:0] = 0, use BA[1:0] = 2 instead 13–16 Repeat pattern 1...4, use BG[1:0] = 1, use BA[1:0] = 3 instead 17–20 Repeat pattern 1...4, use BG[1:0] = 0, use BA[1:0] = 1 instead 21–24 Repeat pattern 1...4, use BG[1:0] = 1, use BA[1:0] = 2 instead 25–28 Repeat pattern 1...4, use BG[1:0] = 0, use BA[1:0] = 3 instead 29–32 Repeat pattern 1...4, use BG[1:0] = 1, use BA[1:0] = 0 instead 33–36 Repeat pattern 1...4, use BG[1:0] = 2, use BA[1:0] = 0 instead 37–40 Repeat pattern 1...4, use BG[1:0] = 3, use BA[1:0] = 1 instead 4 41–44 Repeat pattern 1...4, use BG[1:0] = 2, use BA[1:0] = 2 instead 4 45–48 Repeat pattern 1...4, use BG[1:0] = 3, use BA[1:0] = 3 instead 4 49–52 Repeat pattern 1...4, use BG[1:0] = 2, use BA[1:0] = 1 instead 4 53–56 Repeat pattern 1...4, use BG[1:0] = 3, use BA[1:0] = 2 instead 4 57–60 Repeat pattern 1...4, use BG[1:0] = 2, use BA[1:0] = 3 instead 4 61–64 Repeat pattern 1...4, use BG[1:0] = 3, use BA[1:0] = 0 instead 4 2 65... nREFI - Repeat sub-loop 1; truncate if necessary Notes: 1. DQS_t, DQS_c are V DDQ. 2. BG1 is a "Don't Care" for x16 devices. 3. DQ signals are V DDQ. 4. For x4 and x8 only. 16Gb: x4, x8, x16 DDR4 SDRAM Current Specifications – Patterns and Test Conditions CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 325 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Table 144: IDD7 Measurement – Loop Pattern1 CK_t, CK_c CKE Sub-Loop Cycle Number Command CS_n ACT_n RAS_n/A16 CAS_n/A15 WE_n/A14 ODT BG[1:0]2 BA[1:0] A12/BC_n A[17,13,11]] A[10]/AP A[9:7] A[6:3] A[2:0] Data3 Toggling Static High 0 0 A C T00000000000000 –

1 R D A 01101000001000

1 nR R D A C T00000011000000 – nRRD+1 RDA 0 1 1 0 1 0 1 1 0 0 1 0 0 0 2 2 × nRRD Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 2 instead 3 3 × nRRD Repeat sub-loop 1, use BG[1:0] = 1, use BA[1:0] = 3 instead 4 4 × nRRD Repeat pattern 2...3 until nFAW - 1, if nFAW > 4 × nRRD. Truncate if necessary 5 nFAW Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 1 instead 6 nFAW + nRRD Repeat sub-loop 1, use BG[1:0] = 1, use BA[1:0] = 2 instead 7 nFAW + 2 × nRRD Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 3 instead 8 nFAW + 3 × nRRD Repeat sub-loop 1, use BG[1:0] = 1, use BA[1:0] = 0 instead 9 nFAW + 4 × nRRD Repeat sub-loop 4 10 2 × nFAW Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 0 instead 11 2 × nFAW + nRRD Repeat sub-loop 1, use BG[1:0] = 3, use BA[1:0] = 1 instead 12 2 × nFAW + 2 × nRRD Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 2 instead 13 2 × nFAW + 3 × nRRD Repeat sub-loop 1, use BG[1:0] = 3, use BA[1:0] = 3 instead 14 2 × nFAW + 4 × nRRD Repeat sub-loop 4 15 3 × nFAW Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 1 instead 16 3 × nFAW + nRRD Repeat sub-loop 1, use BG[1:0] = 3, use BA[1:0] = 2 instead 17 3 × nFAW + 2 × nRRD Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 3 instead 18 3 × nFAW + 3 × nRRD Repeat sub-loop 1, use BG[1:0] = 3, use BA[1:0] = 0 instead 19 3 × nFAW + 4 × nRRD Repeat sub-loop 4 20 4 × nFAW Repeat pattern 2...3 until nRC - 1, if nRC > 4 × nFAW. Truncate if necessary Notes: 1. DQS_t, DQS_c are V DDQ. 2. BG1 is a "Don't Care" for x16 devices. 3. DQ signals are V DDQ except when burst sequence drives each DQ signal by a READ com- mand. 16Gb: x4, x8, x16 DDR4 SDRAM Current Specifications – Patterns and Test Conditions CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 326 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

1. For x4 and x8 only. IDD Specifications Table 145: Timings used for IDD, IPP, and IDDQ Measurement – Loop Patterns Symbol DDR4-1600 DDR4-1866 DDR4-2133 DDR4-2400 DDR4-2666 DDR4-2933 DDR4-3200 Uni t 10-10-10 11-11-11 12-12-12 12-12-12 13-13-13 14-14-14 14-14-14 15-15-15 16-16-16 16-16-16 17-17-17 18-18-18 18-18-18 19-19-19 20-20-20 20-20-20 21-21-21 22-22-22 20-20-20 22-22-22 24-24-24 CL 10 11 12 12 13 14 14 15 16 16 17 18 18 19 20 20 21 22 20 22 24 CK C W L 9 1 11 11 01 21 21 11 41 41 61 61 61 81 81 8 1 4 1 8 1 8 1 62 02 0C K nRCD 10 11 12 12 13 14 14 15 16 16 17 18 18 19 20 19 20 21 20 22 24 CK nRC 38 39 40 44 45 46 50 51 52 55 56 57 61 62 63 66 67 68 72 74 76 CK nRP 10 11 12 12 13 14 14 15 16 16 17 18 18 19 20 19 20 21 20 22 24 CK nRAS 28 32 36 39 43 47 52 CK nFA W x41 16 16 16 16 16 16 16 CK x8 20 22 23 26 28 31 34 CK 28 28 32 36 40 44 48 CK nRRD x4 4 4 4 4 4 4 4 CK x8 4 4 4 4 4 4 4 CK 5667 8 8 9 C K nRRD x4 5 5 6 6 7 8 8 CK x8 5 5 6 6 7 8 8 CK 6678 9 1 01 1 C K nCCD_S 4 4 4 4 4 4 4 CK nCCD_L 5 5 6 6 7 8 8 CK nWTR_S 2 3 3 3 4 4 4 CK nWTR_L 6 7 8 9 10 11 12 CK nREFI 6,240 7,283 8,325 9,364 10,400 11,437 12,480 CK nRFC 2Gb 128 150 171 193 214 235 256 CK nRFC 4Gb 208 243 278 313 347 382 416 CK nRFC 8Gb 280 327 374 421 467 514 560 CK nRFC 16Gb 280 327 374 421 467 514 560 CK Note: 1. 1KB based x4 use same numbers of clocks for nFAW as the x8. 16Gb: x4, x8, x16 DDR4 SDRAM Current Specifications – Patterns and Test Conditions CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 327 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Current Specifications – Limits Table 146: IDD and IPP Current Limits; Die Rev. B (-40° ืื TC ื 85°C) Symbol Width DDR4-2133 DDR4-2400 DDR4-2666 DDR4-2933 DDR4-3200 Unit IDD0: One bank ACTIVATE-to- PRECHARGE current x4 56 57 58 59 60 mA x8 59 60 61 62 63 mA x16 74 75 76 77 78 mA IPP0: One bank ACTIVATE-to- PRECHARGE IPP current x4, x8 4 4 4 4 4 mA x16 5 5 5 5 5 mA IDD1: One bank ACTIVATE-to- READ-to- PRECHARGE cur- rent x4 66 67 68 69 70 mA x8 70 71 72 73 74 mA x16 95 96 97 98 99 mA I DD2N: Precharge standby current ALL 48 49 50 51 52 mA IDD2NT: Precharge standby ODT current x4, x8 52 53 54 55 56 mA x16 61 62 63 64 65 mA IDD2P: Precharge power- down current ALL 43 43 43 43 43 mA IDD2Q: Precharge quiet standby current ALL 47 47 47 47 47 mA IDD3N: Active standby current x4 74 75 76 77 78 mA x8 76 77 78 79 80 mA x16 77 78 79 80 81 mA IPP3N: Active standby IPP cur- rent ALL 3 3 3 3 3 mA IDD3P: Active power-down current x4 65 66 67 68 69 mA x8 66 67 68 69 69 mA x16 68 69 70 71 72 mA IDD4R: Burst read current x4 138 147 155 164 172 mA x8 162 172 182 192 202 mA x16 242 262 284 305 326 mA IDD4W: Burst write current x4 135 142 149 157 164 mA x8 150 158 166 175 183 mA x16 209 223 240 257 274 mA IDD5R: Distributed refresh current (1X REF) ALL 81 81 81 81 81 mA IPP5R: Distributed refresh IPP current (1X REF) ALL 5 5 5 5 5 mA IDD6N: Self refresh current; -40–85°C 1 ALL 74 74 74 74 74 mA IDD6E: Self refresh current; -40–95°C 2,4 ALL 129 129 129 129 129 mA 16Gb: x4, x8, x16 DDR4 SDRAM Current Specifications – Limits CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 328 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Table 146: IDD and IPP Current Limits; Die Rev. B (-40° ืื TC ื 85°C) (Continued) Symbol Width DDR4-2133 DDR4-2400 DDR4-2666 DDR4-2933 DDR4-3200 Unit IDD6R: Self refresh current; -40–45C 3,4 ALL 26 26 26 26 26 mA IDD6A: Auto self refresh cur- rent (25°C)4 ALL 15 15 15 15 15 mA IDD6A: Auto self refresh cur- rent (45°C)4 ALL 26 26 26 26 26 mA IDD6A: Auto self refresh cur- rent (75°C)4 ALL 73 73 73 73 73 mA IDD6A: Auto self refresh cur- rent (95°C)4 ALL 129 129 129 129 129 mA IPP6x: Auto self refresh IPP current; -40–95°C27 ALL 9 9 9 9 9 mA IDD7: Bank interleave read current x4 187 196 208 220 234 mA x8 183 185 190 193 196 mA x16 255 260 260 267 268 mA IPP7: Bank interleave read IPP current x4 11 11 11 11 11 mA x8 10 10 10 10 10 mA x16 11 11 11 11 11 mA IDD8: Maximum power-down current ALL 40 40 40 40 40 mA Notes: 1. Applicable for MR2 settings A7 = 0 and A6 = 0; manual mode with normal temperature range of operation (-40–85°C). 2. Applicable for MR2 settings A7 = 1 and A6 = 0; manual mode with extended tempera- ture range of operation (-40–95°C). 3. Applicable for MR2 settings A7 = 0 and A6 = 1; manual mode with reduced temperature range of operation (-40–45°C). 4. I DD6R, IDD6A, and IDD6E values are verified by design and characterization, and may not be subject to production test. 5. When additive latency is enabled for I DD0, current changes by approximately +1%. 6. When additive latency is enabled for I DD1, current changes by approximately +8%. 7. When additive latency is enabled for I DD2N, current changes by approximately +1%. 8. When DLL is disabled for I DD2N, current changes by approximately –6%. 9. When CAL is enabled for I DD2N, current changes by approximately –20%. 10. When gear-down is enabled for I DD2N, current changes by approximately 0%. 11. When CA parity is enabled for I DD2N, current changes by approximately +13%. 12. When additive latency is enabled for I DD3N, current changes by approximately +1%. 13. When additive latency is enabled for I DD4R, current changes by approximately +4%(x4/ x8), +3%(X16). 14. When read DBI is enabled for I DD4R, current changes by approximately -12%(x4/x8), -20%(x16). 15. When additive latency is enabled for I DD4W, current changes by approximately +4%(x4/ x8), +3%(x16). 16. When write DBI is enabled for I DD4W, current changes by approximately 0%. 17. When write CRC is enabled for I DD4W, current changes by approximately -5%. 16Gb: x4, x8, x16 DDR4 SDRAM Current Specifications – Limits CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 329 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

1. When CA parity is enabled for I DD4W, current changes by approximately +12%. 19. When 2X REF is enabled for I DD5R, current changes by approximately 0%. 20. When 4X REF is enabled for I DD5R, current changes by approximately 0%. 21. When 2X REF is enabled for I PP5R, current changes by approximately 0%. 22. When 4X REF is enabled for I PP5R, current changes by approximately 0%. 23. I PP0 test and limit is applicable for IDD0 and IDD1 conditions. 24. I PP3N test and limit is applicable for all IDD2x, IDD3x, IDD4x and IDD8 conditions; that is, test- ing IPP3N should satisfy the IPPs for the noted IDD tests. 25. DDR4-1600 and DDR4-1866 use the same I DD limits as DDR4-2133. 26. The I DD values must be derated (increased) when operated between 85°C < TC ื 95°C: When TC > 85°C: IDD0 and IDD1 must be derated by 10%; IDD2N, IDD2NT, IDD2P, IDD2Q, IDD3N and IDD3P must be derated by 15%; IDD4R, IDD4W and IDD7 must be derated by 4%; IDD5R must be derated by 56%; IPP5R must be derated by 81%; IPP0, IPP3N and IPP7 must be de- rated by 3%. These values are verified by design and characterization, and may not be subject to production test. 27. I PP6x is applicable to IDD6N, IDD6E, IDD6R and IDD6A conditions. Table 147: IDD and IPP Current Limits; Die Rev. E (-40° ืื TC ื 85°C) Symbol Width DDR4-2133 DDR4-2400 DDR4-2666 DDR4-2933 DDR4-3200 Unit IDD0: One bank ACTIVATE-to- PRECHARGE current x4 51 52 53 54 55 mA x8 56 57 58 59 60 mA x16 66 67 68 69 70 mA IPP0: One bank ACTIVATE-to- PRECHARGE IPP current x4, x8 3 3 3 3 3 mA x16 4 4 4 4 4 mA IDD1: One bank ACTIVATE-to- READ-to- PRECHARGE cur- rent x4 62 63 64 65 66 mA x8 67 68 69 70 71 mA x16 80 81 82 83 84 mA I DD2N: Precharge standby current ALL 41 42 43 44 45 mA IDD2NT: Precharge standby ODT current x4, x8 47 48 49 50 51 mA x16 54 55 56 57 58 mA IDD2P: Precharge power- down current ALL 38 38 38 38 38 mA IDD2Q: Precharge quiet standby current ALL 42 42 42 42 42 mA IDD3N: Active standby current x4 56 57 58 59 60 mA x8 57 58 59 60 61 mA x16 58 59 60 61 62 mA IPP3N: Active standby IPP cur- rent ALL 2 2 2 2 2 mA IDD3P: Active power-down current x4 44 45 46 47 48 mA x8 46 47 48 49 50 mA x16 47 48 49 50 51 mA 16Gb: x4, x8, x16 DDR4 SDRAM Current Specifications – Limits CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 330 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Table 147: IDD and IPP Current Limits; Die Rev. E (-40° ืื TC ื 85°C) (Continued) Symbol Width DDR4-2133 DDR4-2400 DDR4-2666 DDR4-2933 DDR4-3200 Unit IDD4R: Burst read current x4 101 106 112 119 127 mA x8 131 138 146 154 162 mA x16 231 243 263 282 299 mA IDD4W: Burst write current x4 89 93 97 101 105 mA x8 107 112 117 123 128 mA x16 189 200 213 226 236 mA IDD5R: Distributed refresh current (1X REF) ALL 68 68 68 68 68 mA IPP5R: Distributed refresh IPP current (1X REF) ALL 4 4 4 4 4 mA IDD6N: Self refresh current; -40–85°C 1 ALL 53 53 53 53 53 mA IDD6E: Self refresh current; -40–95°C 2,4 ALL 113 113 113 113 113 mA IDD6R: Self refresh current; -40–45C 3,4 ALL 20 20 20 20 20 mA IDD6A: Auto self refresh cur- rent (25°C)4 ALL 11 11 11 11 11 mA IDD6A: Auto self refresh cur- rent (45°C)4 ALL 20 20 20 20 20 mA IDD6A: Auto self refresh cur- rent (75°C)4 ALL 51 51 51 51 51 mA IDD6A: Auto self refresh cur- rent (95°C)4 ALL 113 113 113 113 113 mA IPP6x: Auto self refresh IPP current; -40–95°C27 ALL 6 6 6 6 6 mA IDD7: Bank interleave read current x4 189 191 193 195 197 mA x8 177 179 181 183 185 mA x16 234 240 236 242 245 mA IPP7: Bank interleave read IPP current x4 9 9 9 9 9 mA x8 8 8 8 8 8 mA x16 9 9 9 9 9 mA IDD8: Maximum power-down current ALL 36 36 36 36 36 mA Notes: 1. Applicable for MR2 settings A7 = 0 and A6 = 0; manual mode with normal temperature range of operation (-40–85°C). 2. Applicable for MR2 settings A7 = 1 and A6 = 0; manual mode with extended tempera- ture range of operation (-40–95°C). 3. Applicable for MR2 settings A7 = 0 and A6 = 1; manual mode with reduced temperature range of operation (-40–45°C). 4. I DD6R, IDD6A, and IDD6E values are verified by design and characterization, and may not be subject to production test. 16Gb: x4, x8, x16 DDR4 SDRAM Current Specifications – Limits CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 331 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

1. When additive latency is enabled for I DD0, current changes by approximately +1%. 6. When additive latency is enabled for I DD1, current changes by approximately +3%(x4/x8), + 2%(x16). 7. When additive latency is enabled for I DD2N, current changes by approximately +1%. 8. When DLL is disabled for I DD2N, current changes by approximately -4%. 9. When CAL is enabled for I DD2N, current changes by approximately -18%. 10. When gear-down is enabled for I DD2N, current changes by approximately 0%. 11. When CA parity is enabled for I DD2N, current changes by approximately +8%. 12. When additive latency is enabled for I DD3N, current changes by approximately +1%. 13. When additive latency is enabled for I DD4R, current changes by approximately +4%(x4/ x8), +1%(x16). 14. When read DBI is enabled for I DD4R, current changes by approximately -9%. 15. When additive latency is enabled for I DD4W, current changes by approximately +5%(x4/ x8), +2%(x16). 16. When write DBI is enabled for I DD4W, current changes by approximately +1%. 17. When write CRC is enabled for I DD4W, current changes by approximately -5%(x4/x8), -8% (x16). 18. When CA parity is enabled for I DD4W, current changes by approximately +13%(x4/x8), +6%(x16). 19. When 2X REF is enabled for I DD5R, current changes by approximately 0%. 20. When 4X REF is enabled for I DD5R, current changes by approximately 0%. 21. When 2X REF is enabled for I PP5R, current changes by approximately 0%. 22. When 4X REF is enabled for I PP5R, current changes by approximately 0%. 23. I PP0 test and limit is applicable for IDD0 and IDD1 conditions. 24. I PP3N test and limit is applicable for all IDD2x, IDD3x, IDD4x and IDD8 conditions; that is, test- ing IPP3N should satisfy the IPPs for the noted IDD tests. 25. DDR4-1600 and DDR4-1866 use the same I DD limits as DDR4-2133. 26. The I DD values must be derated (increased) when operated between 85°C < TC ื 95°C: IDD0 and IDD1must be derated by 10%; IDD2N, IDD2NT, IDD2Q, and IDD3N must be derated by 18%; IDD2P and IDD3P must be derated by 23%; IDD4R and IDD4W must be derated by 6%; IDD5R must be derated by 58%; IDD7, IPP7 and IPP0 must be derated by 3%; IDD8 must be derated by 28%; IPP5R must be derated by 97% 27. I PP6x is applicable to IDD6N, IDD6E, IDD6R and IDD6A conditions. 16Gb: x4, x8, x16 DDR4 SDRAM Current Specifications – Limits CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 332 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

DDR4 DRAM timing is primarily covered by two types of tables: the Speed Bin tables in this section and the tables found in the Electrical Characteristics and AC Timing Param- eters section. The timing parameter tables define the applicable timing specifications based on the speed rating. The Speed Bin tables on the following pages list the tAA, tRCD, tRP , tRAS, and tRC limits of a given speed mark and are applicable to the CL set- tings in the lower half of the table provided they are applied in the correct clock range, which is noted. Backward Compatibility Although the speed bin tables list the slower data rates, tAA, CL, and CWL, it is difficult to determine whether a faster speed bin supports all of the tAA, CL, and CWL combina- tions across all the data rates of a slower speed bin. To assist in this process, please refer to the Backward Compatibility table. 16Gb: x4, x8, x16 DDR4 SDRAM Speed Bin Tables CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 333 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Table 148: Backward Compatibility Note 1 applies to the entire table. Component Speed Bin Speed Bin Supported -125 -125E -107 -107E -093 -093E -083D -083 -083E -075D -075 -075E -068D -068 -068E -062 -062E -062Y -125 yes -125E yes 2 y e s -107 yes yes -107E yes 2 yes yes 2 y e s -093 yes yes yes -093E yes 2 yes yes 2 yes yes 2 y e s -083D yes yes yes yes -083 yes yes yes yes yes -083E yes 2 yes yes 2 yes yes 2 yes yes 2 yes2 y e s -075D yes yes yes yes yes -075 yes yes yes yes yes yes yes -075E yes yes yes yes yes yes yes yes yes yes yes -068D yes yes yes yes yes yes -068 yes yes yes yes yes yes yes yes yes -068E yes yes yes yes yes yes yes yes yes yes -062 yes yes yes yes yes yes yes -062E yes yes yes yes yes yes yes yes yes yes yes -062Y yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes 16Gb: x4, x8, x16 DDR4 SDRAM Speed Bin Tables CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 334 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Notes: 1. The backward compatibility table is not meant to guarantee that any new device will be a drop in replacement for an existing part number. Customers should review the operat- ing conditions for any device to determine its suitability for use in their design. 2. This condition exceeds the JEDEC requirement in order to allow additional flexibility for components. However, JEDEC SPD compliance may force modules to only support the JE- DEC-defined value. Refer to the SPD documentation for further clarification. 16Gb: x4, x8, x16 DDR4 SDRAM Speed Bin Tables CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 335 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Table 149: DDR4-1600 Speed Bins and Operating Conditions Notes 1–3 apply to the entire table DDR4-1600 Speed Bin -125E -125 Unit CL-nRCD-nRP 11-11-11 12-12-12 Parameter Symbol Min Max Min Max Internal READ command to first data tAA 13.75 (13.50)4 19.006 15.00 19.00 6 ns Internal READ command to first data with read DBI enabled tAA_DBI tAA (MIN) + 2nCK tAA (MAX) + 2nCK tAA (MIN) + 2nCK tAA (MAX) + 2nCK ns ACTIVATE-to-internal READ or WRITE delay time tRCD 13.75 (13.50)4 – 15.00 – ns PRECHARGE command period tRP 13.75 (13.50)4 – 15.00 – ns ACTIVATE-to-PRECHARGE command period tRAS 35 9 × tREFI 35 9 × tREFI ns ACTIVATE-to-ACTIVATE or REFRESH command period tRC5t RAS + tRP – tRAS + tRP –n s Data Rate Max (MT/s) Equivalent Speed Bin tAAmin(ns): non-DB READ CL: nonDBI READ CL: DBI WRITE CWL Symbol Min Max Min Max Unit 1333 - 13.50 9 11 9 tCK (AVG) 1.500 1.900 6 Reserved ns 1600 -125E 13.75 11 13 9, 11 tCK (AVG) 1.250 <1.500 Reserved ns -125 15.00 12 14 tCK (AVG) 1.250 <1.500 ns Supported CL settings 9, 106, 11-12 10, 12 nCK Supported CL settings with read DBI 11, 12 6, 13-14 12, 14 nCK Supported CWL settings 9, 11 9, 11 nCK 16Gb: x4, x8, x16 DDR4 SDRAM Speed Bin Tables CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 336 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Notes: 1. Speed Bin table is only valid with DLL enabled. 2. When operating in 2 tCK WRITE preamble mode, CWL must be programmed to a value at least 1 clock greater than the lowest CWL setting supported in the applicable tCK range. 3. The programmed value of CWL must be less than or equal to the programmed value of CL. 4. This value applies to non-native tCK-CL-nRCD-nRP combinations. 5. When calculating tRC in clocks, values may not be used in a combination that violate tRAS or tRP. 6. This value exceeds the JEDEC requirement in order to allow additional flexibility, espe- cially for components. However, JEDEC SPD compliance may force modules to only sup- port the JEDEC defined value, please refer to the SPD documentation. 16Gb: x4, x8, x16 DDR4 SDRAM Speed Bin Tables CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 337 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Table 150: DDR4-1866 Speed Bins and Operating Conditions Notes 1–3 apply to the entire table DDR4-1866 Speed Bin -107E -107 Unit CL-nRCD-nRP 13-13-13 14-14-14 Parameter Symbol Min Max Min Max Internal READ command to first data tAA 13.92 (13.50)4 19.006 15.00 19.00 6 ns Internal READ command to first data with read DBI enabled tAA_DBI tAA (MIN) + 2nCK tAA (MAX) + 2nCK tAA (MIN) + 2nCK tAA (MAX) + 2nCK ns ACTIVATE to internal READ or WRITE delay time tRCD 13.92 (13.50)4 – 15.00 – ns PRECHARGE command period tRP 13.92 (13.50)4 – 15.00 – ns ACTIVATE-to-PRECHARGE command period tRAS 34 9 × tREFI 34 9 × tREFI ns ACTIVATE-to-ACTIVATE or REFRESH command period tRC5t RAS + tRP – tRAS + tRP –n s Data Rate Max (MT/s) Equivalent Speed Bin tAAmin: non- DBI READ CL: nonDBI READ CL: DBI WRITE CWL Symbol Min Max Min Max Unit 1333 – 13.50 9 11 9 tCK (AVG) 1.500 1.900 6 Reserved ns 1600 -125E 13.75 11 13 9, 11 tCK (AVG) 1.250 <1.500 Reserved ns -125 15.00 12 14 tCK (AVG) 1.250 <1.500 ns 1866 -107E 13.92 13 15 10, 12 tCK (AVG) 1.071 <1.250 Reserved ns -107 15.00 14 16 tCK (AVG) 1.071 <1.250 ns Supported CL settings 9, 106 , 11–14 10, 12, 14 nCK Supported CL settings with read DBI 11, 12 6 , 13–16 12, 14, 16 nCK Supported CWL settings 9–12 9–12 nCK 16Gb: x4, x8, x16 DDR4 SDRAM Speed Bin Tables CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 338 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Notes: 1. Speed Bin table is only valid with DLL enabled. 2. When operating in 2 tCK WRITE preamble mode, CWL must be programmed to a value at least 1 clock greater than the lowest CWL setting supported in the applicable tCK range. 3. The programmed value of CWL must be less than or equal to the programmed value of CL. 4. This value applies to non-native tCK-CL-nRCD-nRP combinations. 5. When calculating tRC in clocks, values may not be used in a combination that violate tRAS or tRP. 6. This value exceeds the JEDEC requirement in order to allow additional flexibility, espe- cially for components. However, JEDEC SPD compliance may force modules to only sup- port the JEDEC defined value, please refer to the SPD documentation. 16Gb: x4, x8, x16 DDR4 SDRAM Speed Bin Tables CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 339 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Table 151: DDR4-2133 Speed Bins and Operating Conditions Notes 1–3 apply to the entire table DDR4-2133 Speed Bin -093E -093 Unit CL-nRCD-nRP 15-15-15 16-16-16 Parameter Symbol Min Max Min Max Internal READ command to first data tAA 14.06 (13.50)4 19.006 15.00 19.00 6 ns Internal READ command to first data with read DBI enabled tAA_DBI tAA (MIN) + 3nCK tAA (MAX) + 3nCK tAA (MIN) + 3nCK tAA (MAX) + 3nCK ns ACTIVATE to internal READ or WRITE delay time tRCD 14.06 (13.50)4 – 15.00 – ns PRECHARGE command period tRP 14.06 (13.50)4 – 15.00 – ns ACTIVATE-to-PRECHARGE command period tRAS 33 9 × tREFI 33 9 × tREFI ns ACTIVATE-to-ACTIVATE or REFRESH command period tRC5t RAS + tRP – tRAS + tRP –n s Data Rate Max (MT/s) Equivalent Speed Bin tAAmin (ns): non-DBI READ CL: non-DBI READ CL: DBI WRITE CWL Symbol Min Max Min Max Unit 1333 – 13.50 9 11 9 tCK (AVG) 1.500 1.900 6 Reserved ns 1600 -125E 13.75 11 13 9 , 11 tCK (AVG) 1.250 <1.500 Reserved ns -125 15.00 12 14 tCK (AVG) 1.250 <1.500 ns 1866 -107E 13.92 13 15 10, 12 tCK (AVG) 1.071 <1.250 Reserved ns -107 15.00 14 16 tCK (AVG) 1.071 <1.250 ns 2133 -093E 14.06 15 18 11, 14 tCK (AVG) 0.937 <1.071 Reserved ns -093 15.00 16 19 tCK (AVG) 0.937 <1.071 ns Supported CL settings 9, 106 , 11–16 10, 12, 14, 16 nCK Supported CL settings with read DBI 11, 12 6 , 13–16, 18-19 12, 14, 16, 19 nCK Supported CWL settings 9, 10, 11, 12, 14 9, 10, 11, 12, 14 nCK 16Gb: x4, x8, x16 DDR4 SDRAM Speed Bin Tables CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 340 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Notes: 1. Speed Bin table is only valid with DLL enabled. 2. When operating in 2 tCK WRITE preamble mode, CWL must be programmed to a value at least 1 clock greater than the lowest CWL setting supported in the applicable tCK range. 3. The programmed value of CWL must be less than or equal to the programmed value of CL. 4. This value applies to non-native tCK-CL-nRCD-nRP combinations. 5. When calculating tRC in clocks, values may not be used in a combination that violate tRAS or tRP. 6. This value exceeds the JEDEC requirement in order to allow additional flexibility, espe- cially for components. However, JEDEC SPD compliance may force modules to only sup- port the JEDEC defined value, please refer to the SPD documentation. 16Gb: x4, x8, x16 DDR4 SDRAM Speed Bin Tables CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 341 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Table 152: DDR4-2400 Speed Bins and Operating Conditions Notes 1–3 apply to the entire table DDR4-2400 Speed Bin -083E -083 -083D Unit CL-nRCD-nRP 16-16-16 17-17-17 18-18-18 Parameter Symbol Min Max Min Max Min Max Internal READ command to first data tAA 13.32 19.00 6 14.16 (13.75)4 19.006 15.00 19.00 6 ns Internal READ command to first data with read DBI enabled tAA_DBI tAA (MIN) + 3nCK tAA (MAX) + 3nCK tAA (MIN) + 3nCK tAA (MAX) + 3nCK tAA (MIN) + 3nCK tAA (MAX) + 3nCK ns ACTIVATE to internal READ or WRITE delay time tRCD 13.32 – 14.16 (13.75)4 – 15.00 19.00 ns PRECHARGE command period tRP 13.32 – 14.16 (13.75)4 – 15.00 19.00 ns ACTIVATE-to-PRECHARGE command period tRAS 32 9 × tREFI 32 9 × tREFI 32 9 × tREFI ns ACTIVATE-to-ACTIVATE or REFRESH command period tRC5t RAS + tRP – tRAS + tRP – tRAS + tRP –n s Data Rate Max (MT/s) Equivalent Speed Bin tAAmin (ns): non-DBI READ CL: non-DBI READ CL: DBI WRITE CWL Symbol Min Max Min Max Min Max Unit 1333 – 13.50 9 11 9 tCK (AVG) 1.500 1.900 6 Reserved Reserved ns -125 15.00 12 14 tCK (AVG) 1.250 <1.500 ns -107 15.00 14 16 tCK (AVG) 1.071 <1.250 ns -093 15.00 16 19 tCK (AVG) 0.937 <1.071 ns 2400 -083E 13.32 16 19 12, 16 tCK (AVG) 0.833 <0.937 Reserved Reserved ns -083 14.16 17 20 tCK (AVG) 0.833 <0.937 ns -083D 15.00 18 21 tCK (AVG) 0.833 <0.937 ns Supported CL settings 9, 10 6 , 11–18 10–18 10, 12, 14, 16, 18 nCK Supported CL settings with read DBI 11, 12 6 , 13–16, 18–21 12–16, 18–21 12, 14, 16, 19, 21 nCK Supported CWL settings 9–12, 14, 16 9-12, 14, 16 9–12, 14, 16 nCK 16Gb: x4, x8, x16 DDR4 SDRAM Speed Bin Tables CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 342 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Notes: 1. Speed Bin table is only valid with DLL enabled. 2. When operating in 2 tCK WRITE preamble mode, CWL must be programmed to a value at least 1 clock greater than the lowest CWL setting supported in the applicable tCK range. 3. The programmed value of CWL must be less than or equal to the programmed value of CL. 4. This value applies to non-native tCK-CL-nRCD-nRP combinations. 5. When calculating tRC in clocks, values may not be used in a combination that violate tRAS or tRP. 6. This value exceeds the JEDEC requirement in order to allow additional flexibility, espe- cially for components. However, JEDEC SPD compliance may force modules to only sup- port the JEDEC defined value, please refer to the SPD documentation. 16Gb: x4, x8, x16 DDR4 SDRAM Speed Bin Tables CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 343 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Table 153: DDR4-2666 Speed Bins and Operating Conditions Notes 1–3 apply to the entire table DDR4-2666 Speed Bin -075E -075 -075D Unit CL-nRCD-nRP 18-18-18 19-19-19 20-20-20 Parameter Symbol Min Max Min Max Min Max Internal READ command to first data tAA 13.50 19.00 6 14.25 (13.75)4 19.006 15.00 19.00 6 ns Internal READ command to first data with read DBI enabled tAA_DBI tAA (MIN) + 3nCK tAA (MAX) + 3nCK tAA (MIN) + 3nCK tAA (MAX) + 3nCK tAA (MIN) + 3nCK tAA (MAX) + 3nCK ns ACTIVATE to internal READ or WRITE delay time tRCD 13.50 – 14.25 PRECHARGE command period tRP 13.50 – 14.25 ACTIVATE-to-PRECHARGE command period tRAS 32 9 × tREFI 32 9 × tREFI 32 9 × tREFI ns ACTIVATE-to-ACTIVATE or REFRESH command period tRC5 tRAS + tRP – tRAS + tRP – tRAS + tRP –n s Data Rate Max (MT/s) Equivalent Speed Bin tAAmin (ns): non-DBI READ CL: non-DBI READ CL: DBI WRITE CWL Symbol Min Max Min Max Min Max Unit 1333 - 13.50 9 11 tCK (AVG) 1.500 1.900 6 Reserved Reserved ns 1600 -125E 13.75 11 13 9, 11 tCK (AVG) 1.250 <1.500 1.250 <1.500 Reserved ns -125 15.00 12 14 tCK (AVG) 1.250 <1.500 ns 1866 -107E 13.92 13 15 10, 12 tCK (AVG) 1.071 <1.250 1.071 <1.250 Reserved ns -107 15.00 14 16 tCK (AVG) 1.071 <1.250 ns 2133 -093E 14.06 15 18 11, 14 tCK (AVG) 0.937 <1.071 0.937 <1.071 Reserved ns -093 15.00 16 19 tCK (AVG) 0.937 <1.071 ns 2400 -083E 13.32 16 19 12, 16 tCK (AVG) Reserved Reserved Reserved ns -083 14.16 17 20 tCK (AVG) 0.833 <0.937 0.833 <0.937 ns -083D 15.00 18 21 tCK (AVG) 0.833 <0.937 ns 2666 -075E 13.50 18 21 14, 18 tCK (AVG) 0.750 <0.833 Reserved Reserved ns -075 14.25 19 22 tCK (AVG) 0.750 <0.833 ns -075D 15.00 20 23 tCK (AVG) 0.750 <0.833 ns Supported CL settings 9–20 10-20 10, 12, 14, 16, 18, nCK 16Gb: x4, x8, x16 DDR4 SDRAM Speed Bin Tables CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 344 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Table 153: DDR4-2666 Speed Bins and Operating Conditions (Continued) Notes 1–3 apply to the entire table DDR4-2666 Speed Bin -075E -075 -075D Unit CL-nRCD-nRP 18-18-18 19-19-19 20-20-20 Parameter Symbol Min Max Min Max Min Max Supported CL settings with read DBI 11–16, 18–23 12–16, 18–23 12, 14, 16, 19, 21, nCK Supported CWL settings 9–12, 14, 16, 18 9–12, 14, 16, 18 9–12, 14, 16, 18 nCK 16Gb: x4, x8, x16 DDR4 SDRAM Speed Bin Tables CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 345 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Notes: 1. Speed Bin table is only valid with DLL enabled. 2. When operating in 2 tCK WRITE preamble mode, CWL must be programmed to a value at least 1 clock greater than the lowest CWL setting supported in the applicable tCK range. 3. The programmed value of CWL must be less than or equal to the programmed value of CL. 4. This value applies to non-native tCK-CL-nRCD-nRP combinations. 5. When calculating tRC in clocks, values may not be used in a combination that violate tRAS or tRP. 6. This value exceeds the JEDEC requirement in order to allow additional flexibility, espe- cially for components. However, JEDEC SPD compliance may force modules to only sup- port the JEDEC defined value, please refer to the SPD documentation. 16Gb: x4, x8, x16 DDR4 SDRAM Speed Bin Tables CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 346 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Table 154: DDR4-2933 Speed Bins and Operating Conditions Notes 1–3 apply to the entire table DDR4-2933 Speed Bin -068E -068 -068D Unit CL-nRCD-nRP 20-20-20 21-21-21 22-22-22 Parameter Symbol Min Max Min Max Min Max Internal READ command to first data tAA 13.64 19.00 6 14.32 (13.75)4 19.006 15.00 19.00 6 ns Internal READ command to first data with read DBI enabled tAA_DBI tAA (MIN) + 4nCK tAA (MAX) + 4nCK tAA (MIN) + 4nCK tAA (MAX) + 4nCK tAA (MIN) + 4nCK tAA (MAX) + 4nCK ns ACTIVATE-to-internal READ or WRITE delay time tRCD 13.64 – 14.32 (13.75)4 – 15.00 – ns PRECHARGE command period tRP 13.64 – 14.32 (13.75)4 – 15.00 – ns ACTIVATE-to-PRECHARGE command period tRAS 32 9 × tREFI 32 9 × tREFI 32 9 × tREFI ns ACTIVATE-to-ACTIVATE or REFRESH command period tRC5t RAS + tRP – tRAS + tRP – tRAS + tRP –n s Data Rate Max (MT/s) Equivalent Speed Bin tAAmin(ns): non-DBI READ CL: non-DBI READ CL: DBI WRITE CWL Symbol Min Max Min Max Min Max Unit 1333 – 13.50 9 11 9 tCK (AVG) Reserved Reserved Reserved ns -125 15.00 12 14 tCK (AVG) 1.250 <1.500 ns -107 15.00 14 16 tCK (AVG) 1.071 <1.250 ns -093 15.00 16 19 tCK (AVG) 0.937 <1.071 ns 2400 -083E 13.32 16 19 12, 16 tCK (AVG) Reserved Reserved Reserved ns 083D 15.00 18 21 tCK (AVG) 0.833 <0.937 ns 2666 -075E 13.50 18 21 14, 18 tCK (AVG) Reserved Reserved Reserved ns -075D 15.00 20 23 tCK (AVG) 0.750 <0.833 ns 16Gb: x4, x8, x16 DDR4 SDRAM Speed Bin Tables CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 347 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Table 154: DDR4-2933 Speed Bins and Operating Conditions (Continued) Notes 1–3 apply to the entire table DDR4-2933 Speed Bin -068E -068 -068D Unit CL-nRCD-nRP 20-20-20 21-21-21 22-22-22 Parameter Symbol Min Max Min Max Min Max 2933 -068E 13.64 20 24 16, 20 tCK (AVG) 0.682 <0.750 Reserved Reserved ns -068 14.32 21 25 tCK (AVG) 0.682 <0.750 ns -068D 15.00 22 26 tCK (AVG) 0.682 <0.750 ns – 16.37 24 28 tCK (AVG) Reserved Reserved Reserved ns Supported CL settings 10–22 10–22 10, 12, 14, 16, 18, 20, 22 nCK Supported CL settings with read DBI 12–16, 18–26 12–16,18–23, 25-26 23, 26 nCK Supported CWL settings 9–12, 14, 16, 18, 9–12, 14, 16, 18, 9–12, 14, 16, 18, nCK 16Gb: x4, x8, x16 DDR4 SDRAM Speed Bin Tables CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 348 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Notes: 1. Speed Bin table is only valid with DLL enabled. 2. When operating in 2 tCK WRITE preamble mode, CWL must be programmed to a value at least 1 clock greater than the lowest CWL setting supported in the applicable tCK range. 3. The programmed value of CWL must be less than or equal to the programmed value of CL. 4. This value applies to non-native tCK-CL-nRCD-nRP combinations. 5. When calculating tRC in clocks, values may not be used in a combination that violate tRAS or tRP. 6. This value exceeds the JEDEC requirement in order to allow additional flexibility, espe- cially for components. However, JEDEC SPD compliance may force modules to only sup- port the JEDEC defined value, please refer to the SPD documentation. 16Gb: x4, x8, x16 DDR4 SDRAM Speed Bin Tables CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 349 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Table 155: DDR4-3200 Speed Bins and Operating Conditions Notes 1–3 apply to the entire table DDR4-3200 Speed Bin -062Y6 -062E -062 Unit CL-nRCD-nRP 22-22-22 22-22-22 24-24-24 Parameter Symbol Min Max Min Max Min Max Internal READ command to first data tAA 13.75 (13.32)4 Internal READ command to first data with read DBI enabled tAA_DBI tAA (MIN) + 4nCK tAA (MAX) + 4nCK tAA (MIN) + 4nCK tAA (MAX) + 4nCK tAA (MIN) + 4nCK tAA (MAX) + 4nCK ns ACTIVATE-to-internal READ or WRITE delay time tRCD 13.75 (13.32)4 – 13.75 – 15.00 – ns PRECHARGE command period tRP 13.75 (13.32)4 – 13.75 – 15.00 – ns ACTIVATE-to-PRECHARGE command period tRAS 32 9 × tREFI 32 9 × tREFI 32 9 × tREFI ns ACTIVATE-to-ACTIVATE or REFRESH command period tRC5t RAS + tRP – tRAS + tRP – tRAS + tRP –n s Data Rate Max (MT/s) Equivalent Speed Bin tAAmin (ns): non-DBI READ CL: non-DBI READ CL: DBI WRITE CWL Symbol Min Max Min Max Min Max Unit 1333 - 13.50 9 11 9 tCK (AVG) 1.500 1.900 6 Reserved Reserved ns -125 15.00 12 14 tCK (AVG) 1.250 <1.500 ns -107 15.00 14 16 tCK (AVG) 1.071 <1.250 ns -093 15.00 16 19 tCK (AVG) 0.937 <1.071 ns 2400 -083E 13.32 16 19 12, 16 tCK (AVG) 0.833 <0.937 Reserved Reserved ns -083 14.16 17 20 tCK (AVG) 0.833 <0.937 ns -083D 15.00 18 21 tCK (AVG) 0.833 <0.937 ns 2666 -075E 13.50 18 21 14, 18 tCK (AVG) 0.750 <0.833 Reserved Reserved ns -075 14.25 19 22 tCK (AVG) 0.750 <0.833 ns -075D 15.00 20 23 tCK (AVG) 0.750 <0.833 ns 16Gb: x4, x8, x16 DDR4 SDRAM Speed Bin Tables CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 350 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Table 155: DDR4-3200 Speed Bins and Operating Conditions (Continued) Notes 1–3 apply to the entire table DDR4-3200 Speed Bin -062Y6 -062E -062 Unit CL-nRCD-nRP 22-22-22 22-22-22 24-24-24 Parameter Symbol Min Max Min Max Min Max 2933 -068E 13.64 20 24 16, 20 tCK (AVG) Reserved Reserved Reserved ns – 16.37 24 28 tCK (AVG) 0.682 <0.750 ns -062 15.00 24 28 tCK (AVG) 0.625 <0.682 ns Supported CL settings 9–22, 24 10–22, 24 10, 12, 14, 16, 18, 20, 22, 24 nCK Supported CL settings with read DBI 11–16, 18–23, 25-26, 28 12–16, 18–23, 25-26, 28 23, 26, 28 nCK Supported CWL settings 9–12, 14, 16, 18, 9–12, 14, 16, 18, 9–12, 14, 16, 18, nCK 16Gb: x4, x8, x16 DDR4 SDRAM Speed Bin Tables CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 351 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Notes: 1. Speed Bin table is only valid with DLL enabled. 2. When operating in 2 tCK WRITE preamble mode, CWL must be programmed to a value at least 1 clock greater than the lowest CWL setting supported in the applicable tCK range. 3. The programmed value of CWL must be less than or equal to the programmed value of CL. 4. This value applies to non-native tCK-CL-nRCD-nRP combinations. 5. When calculating tRC in clocks, values may not be used in a combination that violate tRAS or tRP. 6. This value exceeds the JEDEC requirement in order to allow additional flexibility, espe- cially for components. However, JEDEC SPD compliance may force modules to only sup- port the JEDEC defined value, please refer to the SPD documentation. Refresh Parameters By Device Density Table 156: Refresh Parameters by Device Density Parameter Symbol 2Gb 4Gb 8Gb 16Gb Unit Notes REF command to ACT or REF com- mand time tRFC (All bank groups) 160 260 350 350 ns Average periodic refresh interval tREFI -40°C ื TC ื 85°C 7.8 7.8 7.8 7.8 μs 85°C < TC ื 95°C 3.9 3.9 3.9 3.9 μs 1 95°C < TC ื 105°C 1.95 1.95 1.95 1.95 μs 1 Note: 1. Users should refer to the DRAM supplier data sheet and/or the DIMM SPD to determine if the devices support these options or requirements. 16Gb: x4, x8, x16 DDR4 SDRAM Refresh Parameters By Device Density CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 352 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Electrical Characteristics and AC Timing Parameters Table 157: Electrical Characteristics and AC Timing Parameters: DDR4-1600 through DDR4-2400 Parameter Symbol DDR4-1600 DDR4-1866 DDR4-2133 DDR4-2400 Unit NotesMin Max Min Max Min Max Min Max Clock Timing Clock period average (DLL off mode) tCK (DLL_OFF) 8 20 8 20 8 20 8 20 ns Clock period average tCK (AVG, DLL_ON) 0) , (AVG) (AVG) Clock period jitter Total tJITper_tot –63 63 –54 54 –47 47 –42 42 ps 17 , 18 Deterministic tJITper_dj –31 31 –27 27 –23 23 –21 21 ps 17 DLL locking tJITper,lck –50 50 –43 43 –38 38 -33 33 ps Clock absolute period tCK (ABS) MIN = tCK (AVG) MIN + tJITper_tot MIN; MAX = tCK (AVG) MAX + tJITper_tot MAX ps Clock absolute high pulse width (includes duty cycle jitter) tCH (ABS) 0.45 – 0.45 – 0.45 – 0.45 – tCK (AVG) Clock absolute low pulse width (includes duty cycle jitter) tCL (ABS) 0.45 – 0.45 – 0.45 – 0.45 – tCK (AVG) Cycle-to-cycle jitter Total tJITcc _tot – 125 – 107 – 94 – 83 ps DLL locking tJITcc,lck – 100 – 86 – 75 – 67 ps 16Gb: x4, x8, x16 DDR4 SDRAM Electrical Characteristics and AC Timing Parameters CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 353 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Table 157: Electrical Characteristics and AC Timing Parameters: DDR4-1600 through DDR4-2400 (Continued) Parameter Symbol DDR4-1600 DDR4-1866 DDR4-2133 DDR4-2400 Unit NotesMin Max Min Max Min Max Min Max Cumulative error across 2 cycles tERR2per –92 92 –79 79 –69 69 –61 61 ps 3 cycles tERR3per –109 109 –94 94 –82 82 –73 73 ps 4 cycles tERR4per –121 121 –104 104 –91 91 –81 81 ps 5 cycles tERR5per –131 131 –112 112 –98 98 –87 87 ps 6 cycles tERR6per –139 139 –119 119 –104 104 –92 92 ps 7 cycles tERR7per –145 145 –124 124 –109 109 –97 97 ps 8 cycles tERR8per –151 151 –129 129 –113 113 –101 101 ps 9 cycles tERR9per –156 156 –134 134 –117 117 –104 104 ps 10 cycles tERR10per –160 160 –137 137 –120 120 –107 107 ps 11 cycles tERR11per –164 164 –141 141 –123 123 –110 110 ps 12 cycles tERR12per –168 168 –144 144 –126 126 –112 112 ps 50 cycles tERRnper tERRnper MIN = (1 + 0.68ln[n]) × tJITper_tot MIN tERRnper MAX = (1 + 0.68ln[n]) × tJITper_tot MAX ps DQ Input Timing Data setup time to DQS_t, DQS_c Base (calibrated VREF) tDS Refer to DQ Input Receiver Specification section (approximately 0.15tCK to 0.28tCK ) Noncalibrated VREF tPDA_S minimum of 0.5UI UI 22 Data hold time from DQS_t, DQS_c Base (calibrated VREF) tDH Refer to DQ Input Receiver Specification section (approximately 0.15tCK to 0.28tCK ) Noncalibrated VREF tPDA_H minimum of 0.5UI UI 22 DQ and DM minimum data pulse width for each input tDIPW 0.58 – 0.58 – 0.58 – 0.58 – UI DQ Output Timing (DLL enabled) DQS_t, DQS_c to DQ skew, per group, per access tDQSQ – 0.16 – 0.16 – 0.16 – 0.17 UI DQ output hold time from DQS_t, DQS_c tQH 0.76 – 0.76 – 0.76 – 0.74 – UI Data Valid Window per device: tQH - tDQSQ each device’s output per UI tDVWd 0.63 0.63 0.64 0.64 UI Data Valid Window per device, per pin: tQH - tDQSQ each device’s output per UI tDVWp 0.66 – 0.66 – 0.69 – 0.72 – UI 16Gb: x4, x8, x16 DDR4 SDRAM Electrical Characteristics and AC Timing Parameters CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 354 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Table 157: Electrical Characteristics and AC Timing Parameters: DDR4-1600 through DDR4-2400 (Continued) Parameter Symbol DDR4-1600 DDR4-1866 DDR4-2133 DDR4-2400 Unit NotesMin Max Min Max Min Max Min Max DQ Low-Z time from CK_t, CK_c tLZDQ –450 225 –390 195 –360 180 –330 175 ps DQ High-Z time from CK_t, CK_c tHZDQ – 225 – 195 – 180 – 175 ps DQ Strobe Input Timing DQS_t, DQS_c rising edge to CK_t, CK_c rising edge for 1tCKpreamble DQS_t, DQS_c rising edge to CK_t, CK_c rising edge for 2tCKpreamble DQS_t, DQS_c differential input low pulse width DQS_t, DQS_c differential input high pulse width DQS_t, DQS_c falling edge setup to CK_t, CK_c rising edge tDSS 0.18 – 0.18 – 0.18 – 0.18 – CK DQS_t, DQS_c falling edge hold from CK_t, CK_c rising edge tDSH 0.18 – 0.18 – 0.18 – 0.18 – CK DQS_t, DQS_c differential WRITE pream- ble for 1tCKpreamble tWPRE1ck 0.9 – 0.9 – 0.9 – 0.9 – CK DQS_t, DQS_c differential WRITE pream- ble for 2tCKpreamble tWPRE2ck 1.8 – 1.8 – 1.8 – 1.8 – CK DQS_t, DQS_c differential WRITE postam- ble tWPST 0.33 – 0.33 – 0.33 – 0.33 – CK DQS Strobe Output Timing (DLL enabled) DQS_t, DQS_c rising edge output access time from rising CK_t, CK_c tDQSCK –225 225 –195 195 –180 180 –175 175 ps DQS_t, DQS_c rising edge output var- iance window per DRAM tDQSCKi – 370 – 330 – 310 – 290 ps DQS_t, DQS_c differential output high time DQS_t, DQS_c differential output low time DQS_t, DQS_c Low-Z time (RL - 1) tLZDQS –450 225 –390 195 –360 180 –330 175 ps DQS_t, DQS_c High-Z time (RL + BL/2) tHZDQS – 225 – 195 – 180 – 175 ps 16Gb: x4, x8, x16 DDR4 SDRAM Electrical Characteristics and AC Timing Parameters CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 355 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Table 157: Electrical Characteristics and AC Timing Parameters: DDR4-1600 through DDR4-2400 (Continued) Parameter Symbol DDR4-1600 DDR4-1866 DDR4-2133 DDR4-2400 Unit NotesMin Max Min Max Min Max Min Max DQS_t, DQS_c differential READ pream- ble for 1tCKpreamble tRPRE1ck 0.9 – 0.9 – 0.9 – 0.9 – CK 20 DQS_t, DQS_c differential READ pream- ble for 2tCK preamble tRPRE2ck 1.8 – 1.8 – 1.8 – 1.8 – CK 20 DQS_t, DQS_c differential READ postam- ble tRPST 0.33 – 0.33 – 0.33 – 0.33 – CK 21 Command and Address Timing DLL locking time tDLLK 597 – 597 – 768 – 768 – CK 2, 4 CMD, ADDR setup time to CK_t, CK_c Base ref- erenced to V IH(AC) and VIL(AC) levels Base tIS 115 – 100 – 80 – 62 – ps VREFCA tISVREF 215 – 200 – 180 – 162 – ps CMD, ADDR hold time to CK_t, CK_c Base ref- erenced to V IH(DC) and VIL(DC) levels Base tIH 140 – 125 – 105 – 87 – ps VREFCA tIHVREF 215 – 200 – 180 – 162 – ps CTRL, ADDR pulse width for each input tIPW 600 – 525 – 460 – 410 – ps ACTIVATE to internal READ or WRITE de- lay tRCD See Speed Bin Tables for tRCD ns PRECHARGE command period tRP See Speed Bin Tables for tRP ns ACTIVATE-to-PRECHARGE command peri- od tRAS See Speed Bin Tables for tRAS ns 12 ACTIVATE-to-ACTIVATE or REF command period tRC See Speed Bin Tables for tRC ns 12 ACTIVATE-to-ACTIVATE command period to different bank groups for 1/2KB page size tRRD_S (1/2KB) MIN = greater of 4CK or 5ns MIN = greater of 4CK or 4.2ns MIN = greater of 4CK or 3.7ns MIN = greater of 4CK or 3.3ns CK 1 ACTIVATE-to-ACTIVATE command period to different bank groups for 1KB page size tRRD_S (1KB) MIN = greater of 4CK or 5ns MIN = greater of 4CK or 4.2ns MIN = greater of 4CK or 3.7ns MIN = greater of 4CK or 3.3ns CK 1 ACTIVATE-to-ACTIVATE command period to different bank groups for 2KB page size tRRD_S (2KB) MIN = greater of 4CK or 6ns MIN = greater of 4CK or 5.3ns MIN = greater of 4CK or 5.3ns MIN = greater of 4CK or 5.3ns CK 1 16Gb: x4, x8, x16 DDR4 SDRAM Electrical Characteristics and AC Timing Parameters CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 356 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Table 157: Electrical Characteristics and AC Timing Parameters: DDR4-1600 through DDR4-2400 (Continued) Parameter Symbol DDR4-1600 DDR4-1866 DDR4-2133 DDR4-2400 Unit NotesMin Max Min Max Min Max Min Max ACTIVATE-to-ACTIVATE command period to same bank groups for 1/2KB page size tRRD_L (1/2KB) MIN = greater of 4CK or 6ns MIN = greater of 4CK or 5.3ns MIN = greater of 4CK or 5.3ns MIN = greater of 4CK or 4.9ns CK 1 ACTIVATE-to-ACTIVATE command period to same bank groups for 1KB page size tRRD_L (1KB) MIN = greater of 4CK or 6ns MIN = greater of 4CK or 5.3ns MIN = greater of 4CK or 5.3ns MIN = greater of 4CK or 4.9ns CK 1 ACTIVATE-to-ACTIVATE command period to same bank groups for 2KB page size tRRD_L (2KB) MIN = greater of 4CK or 7.5ns MIN = greater of 4CK or 6.4ns MIN = greater of 4CK or 6.4ns MIN = greater of 4CK or 6.4ns CK 1 Four ACTIVATE windows for 1/2KB page size tFAW (1/2KB) MIN = greater of 16CK or 20ns MIN = greater of 16CK or 17ns MIN = greater of 16CK or 15ns MIN = greater of 16CK or 13ns ns Four ACTIVATE windows for 1KB page size tFAW (1KB) MIN = greater of 20CK or 25ns MIN = greater of 20CK or 23ns MIN = greater of 20CK or 21ns MIN = greater of 20CK or 21ns ns Four ACTIVATE windows for 2KB page size tFAW (2KB) MIN = greater of 28CK or 35ns MIN = greater of 28CK or 30ns MIN = greater of 28CK or 30ns MIN = greater of 28CK or 30ns ns WRITE recovery time tWR MIN = 15ns ns 5, 9, 1 tWR2 MIN = 1CK + tWR CK 5, 10, 1 WRITE recovery time when CRC and DM are both enabled tWR_CRC_DM MIN = tWR + greater of (4CK or 3.75ns) MIN = tWR + greater of (5CK or 3.75ns) CK 6, 9, 1 tWR_CRC_DM2 MIN = 1CK + tWR_CRC_DM CK 6, 10, 1 Delay from start of internal WRITE trans- action to internal READ command – Same bank group tWTR_L MIN = greater of 4CK or 7.5ns CK 5, 9, 1 tWTR_L2 MIN = 1CK + tWTR_L CK 5, 10, 1 Delay from start of internal WRITE trans- action to internal READ command – Same bank group when CRC and DM are both enabled tWTR_L_CRC_D M MIN = tWTR_L + greater of (4CK or 3.75ns) MIN = tWTR_L + greater of (5CK or 3.75ns) CK 6, 9, 1 tWTR_L_CRC_D MIN = 1CK + tWTR_L_CRC_DM CK 6, 10, 1 Delay from start of internal WRITE trans- action to internal READ command – Dif- ferent bank group tWTR_S MIN = greater of (2CK or 2.5ns) CK 5, 7, 8, 9, 1 tWTR_S2 MIN = 1CK + tWTR_S CK 5, 7, 8, 10, 1 16Gb: x4, x8, x16 DDR4 SDRAM Electrical Characteristics and AC Timing Parameters CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 357 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Table 157: Electrical Characteristics and AC Timing Parameters: DDR4-1600 through DDR4-2400 (Continued) Parameter Symbol DDR4-1600 DDR4-1866 DDR4-2133 DDR4-2400 Unit NotesMin Max Min Max Min Max Min Max Delay from start of internal WRITE trans- action to internal READ command – Dif- ferent bank group when CRC and DM are both enabled tWTR_S_CRC_D M MIN = tWTR_S + greater of (4CK or 3.75ns) MIN = tWTR_S + greater of (5CK or 3.75ns) CK 6, 7, 8, 9, 1 tWTR_S_CRC_D MIN = 1CK + tWTR_S_CRC_DM CK 6, 7, 8, 10, 1 READ-to-PRECHARGE time tRTP MIN = greater of 4CK or 7.5ns CK 1 CAS_n-to-CAS_n command delay to dif- ferent bank group tCCD_S 4 – 4 – 4 – 4 – CK CAS_n-to-CAS_n command delay to same bank group tCCD_L MIN = greater of 4CK or 6.25ns – MIN = greater of 4CK or 5.355ns – MIN = greater of 4CK or 5.355ns – MIN = greater of 4CK or 5ns –C K1 4 Auto precharge write recovery + pre- charge time tDAL (MIN) MIN = WR + ROUND tRP/tCK (AVG); MAX = N/A CK 8 MRS Command Timing MRS command cycle time tMRD 8 – 8 – 8 – 8 – CK MRS command cycle time in PDA mode tMRD_PDA MIN = greater of (16nCK, 10ns) CK 1 MRS command cycle time in CAL mode tMRD_CAL MIN = tMOD + tCAL CK MRS command update delay tMOD MIN = greater of (24nCK, 15ns) CK 1 MRS command update delay in PDA mode tMOD_PDA MIN = tMOD CK MRS command update delay in CAL mode tMOD_CAL MIN = tMOD + tCAL CK MRS command to DQS drive in preamble training tSDO MIN = tMOD + 9ns MPR Command Timing Multipurpose register recovery time tMPRR MIN = 1CK CK Multipurpose register write recovery time tWR_MPR MIN = tMOD + AL + PL CRC Error Reporting Timing CRC error to ALERT_n latency tCRC_ALERT 3 13 3 13 3 13 3 13 ns CRC ALERT_n pulse width tCRC_ALERT_P W 6 10 6 10 6 10 6 10 CK 16Gb: x4, x8, x16 DDR4 SDRAM Electrical Characteristics and AC Timing Parameters CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 358 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Table 157: Electrical Characteristics and AC Timing Parameters: DDR4-1600 through DDR4-2400 (Continued) Parameter Symbol DDR4-1600 DDR4-1866 DDR4-2133 DDR4-2400 Unit NotesMin Max Min Max Min Max Min Max CA Parity Timing Parity latency PL 4 – 4 – 4 – 5 – CK Commands uncertain to be executed dur- ing this time tPAR_UN- KNOWN – PL – PL – PL – PL CK Delay from errant command to ALERT_n assertion tPAR_ALERT_O N – PL + 6ns – P L + 6ns – PL + 6ns – PL + 6ns CK Pulse width of ALERT_n signal when as- serted tPAR_ALERT_P W 48 96 56 112 64 128 72 144 CK Time from alert asserted until DES com- mands required in persistent CA parity mode tPAR_ALERT_RS P – 43 – 50 – 57 – 64 CK CAL Timing CS_n to command address latency tCAL 3 – 4 – 4 – 5 – CK 19 CS_n to command address latency in gear-down mode tCALg N/A – N/A – N/A – N/A – CK MPSM Timing Command path disable delay upopn MPSM entry tMPED MIN = tMOD (MIN) + tCPDED (MIN) CK 1 Valid clock requirement after MPSM entry tCKMPE MIN = tMOD (MIN) + tCPDED (MIN) CK 1 Valid clock requirement before MPSM exit tCKMPX MIN = tCKSRX (MIN) CK 1 Exit MPSM to commands not requiring a locked DLL tXMP tXS (MIN) CK Exit MPSM to commands requiring a locked DLL tXMPDLL MIN = tXMP (MIN) + tXSDLL (MIN) CK 1 CS setup time to CKE tMPX_S MIN = tIS (MIN) + tIH (MIN) ns CS_n HIGH hold time to CKE rising edge tMPX_HH MIN = tXP ns CS_n LOW hold time to CKE rising edge tMPX_LH 12 tXMP-1 0ns 12 tXMP-1 0ns 12 tXMP-1 0ns 12 tXMP-1 0ns ns Connectivity Test Timing TEN pin HIGH to CS_n LOW – Enter CT mode tCT_Enable 200 – 200 – 200 – 200 – ns 16Gb: x4, x8, x16 DDR4 SDRAM Electrical Characteristics and AC Timing Parameters CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 359 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Table 157: Electrical Characteristics and AC Timing Parameters: DDR4-1600 through DDR4-2400 (Continued) Parameter Symbol DDR4-1600 DDR4-1866 DDR4-2133 DDR4-2400 Unit NotesMin Max Min Max Min Max Min Max CS_n LOW and valid input to valid output tCT_Valid – 200 – 200 – 200 – 200 ns CK_t, CK_c valid and CKE HIGH after TEN goes HIGH tCTCKE_Valid 10 – 10 – 10 – 10 – ns Calibration and VREFDQ Train Timing ZQCL command: Long calibration time POWER-UP and RESET operation tZQinit 1024 – 1024 – 1024 – 1024 – CK Normal opera- tion tZQoper 512 – 512 – 512 – 512 – CK ZQCS command: Short calibration time tZQCS 128 – 128 – 128 – 128 – CK The VREF increment/decrement step time V REF_time MIN = 150ns Enter VREFDQ training mode to the first write or VREFDQ MRS command delay tVREFDQE MIN = 150ns ns 1 Exit VREFDQ training mode to the first WRITE command delay tVREFDQX MIN = 150ns ns 1 Initialization and Reset Timing Exit reset from CKE HIGH to a valid com- mand tXPR MIN = greater of 5CK or tRFC (MIN) + 10ns CK 1 RESET_L pulse low after power stable tPW_RESET_S 1.0 – 1.0 – 1.0 – 1.0 – μs RESET_L pulse low at power-up tPW_RESET_L 200 – 200 – 200 – 200 – μs Begin power supply ramp to power sup- plies stable tVDDPR MIN = N/A; MAX = 200 ms RESET_n LOW to power supplies stable tRPS MIN = 0; MAX = 0 ns Refresh Timing REFRESH-to-ACTIVATE or REFRESH command period (all bank groups) 4Gb tRFC1 MIN = 260 ns 1, 11 tRFC2 MIN = 160 ns 1, 11 tRFC4 MIN = 110 ns 1, 11 8Gb tRFC1 MIN = 350 ns 1, 11 tRFC2 MIN = 260 ns 1, 11 tRFC4 MIN = 160 ns 1, 11 16Gb tRFC1 MIN = 350 ns 1, 11 tRFC2 MIN = 260 ns 1, 11 tRFC4 MIN = 160 ns 1, 11 16Gb: x4, x8, x16 DDR4 SDRAM Electrical Characteristics and AC Timing Parameters CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 360 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Table 157: Electrical Characteristics and AC Timing Parameters: DDR4-1600 through DDR4-2400 (Continued) Parameter Symbol DDR4-1600 DDR4-1866 DDR4-2133 DDR4-2400 Unit NotesMin Max Min Max Min Max Min Max Average periodic re- fresh interval -40°C ื TC ื 85°C tREFI MIN = N/A; MAX = 7.8 μs 11 85°C < TC ื 95°C tREFI MIN = N/A; MAX = 3.9 μs 11 95°C < TC ื 105°C tREFI MIN = N/A; MAX = 1.95 μs 11 105°C < TC ื 125°C tREFI MIN = N/A; MAX = 0.975 μs 11 Self Refresh Timing Exit self refresh to commands not requir- ing a locked DLL tXS MIN = tRFC + 10ns ns 1 Exit self refresh to commands not requir- ing a locked DLL in self refresh abort tXS_ABORT MIN = tRFC4 + 10ns ns 1 Exit self refresh to ZQCL, ZQCS and MRS (CL, CWL, WR, RTP and gear-down) tXS_FAST MIN = tRFC4 + 10ns ns Exit self refresh to commands requiring a locked DLL tXSDLL MIN = tDLLK (MIN) CK 1 Minimum CKE low pulse width for self re- fresh entry to self refresh exit timing tCKESR MIN = tCKE (MIN) + 1nCK CK 1 Minimum CKE low pulse width for self re- fresh entry to self refresh exit timing when CA parity is enabled tCKESR_PAR MIN = tCKE (MIN) + 1nCK + PL CK 1 Valid clocks after self refresh entry (SRE) or power-down entry (PDE) tCKSRE MIN = greater of (5CK, 10ns) CK 1 Valid clock requirement after self refresh entry or power-down when CA parity is enabled tCKSRE_PAR MIN = greater of (5CK, 10ns) + PL CK 1 Valid clocks before self refresh exit (SRX) or power-down exit (PDX), or reset exit tCKSRX MIN = greater of (5CK, 10ns) CK 1 Power-Down Timing Exit power-down with DLL on to any val- id command tXP MIN = greater of 4CK or 6ns CK 1 Exit power-down with DLL on to any val- id command when CA Parity is enabled. tXP _PAR MIN = (greater of 4CK or 6ns) + PL CK 1 CKE MIN pulse width tCKE (MIN) MIN = greater of 3CK or 5ns CK 1 Command pass disable delay tCPDED 4 – 4 – 4 – 4 – CK 16Gb: x4, x8, x16 DDR4 SDRAM Electrical Characteristics and AC Timing Parameters CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 361 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Table 157: Electrical Characteristics and AC Timing Parameters: DDR4-1600 through DDR4-2400 (Continued) Parameter Symbol DDR4-1600 DDR4-1866 DDR4-2133 DDR4-2400 Unit NotesMin Max Min Max Min Max Min Max Power-down entry to power-down exit timing tPD MIN = tCKE (MIN); MAX = 9 × tREFI CK Begin power-down period prior to CKE registered HIGH tANPD WL - 1CK CK Power-down entry period: ODT either synchronous or asynchronous PDE Greater of tANPD or tRFC - REFRESH command to CKE LOW time CK Power-down exit period: ODT either syn- chronous or asynchronous PDX tANPD + tXSDLL CK Power-Down Entry Minimum Timing ACTIVATE command to power-down en- try tACTPDEN 1 – 1 – 2 – 2 – CK PRECHARGE/PRECHARGE ALL command to power-down entry tPRPDEN 1 – 1 – 2 – 2 – CK REFRESH command to power-down entry tREFPDEN 1 – 1 – 2 – 2 – CK MRS command to power-down entry tMRSPDEN MIN = tMOD (MIN) CK 1 READ/READ with auto precharge com- mand to power-down entry tRDPDEN MIN = RL + 4 + 1 CK 1 WRITE command to power-down entry (BL8OTF, BL8MRS, BC4OTF) tWRPDEN MIN = WL + 4 + tWR/tCK (AVG) CK 1 WRITE command to power-down entry (BC4MRS) tWRPBC4DEN MIN = WL + 2 + tWR/tCK (AVG) CK 1 WRITE with auto precharge command to power-down entry (BL8OTF, BL8MRS,BC4OTF) tWRAPDEN MIN = WL + 4 + WR + 1 CK 1 WRITE with auto precharge command to power-down entry (BC4MRS) tWRAPBC4DEN MIN = WL + 2 + WR + 1 CK 1 ODT Timing Direct ODT turn-on latency DODTLon WL - 2 = CWL + AL + PL - 2 CK Direct ODT turn-off latency DODTLoff WL - 2 = CWL + AL + PL - 2 CK R Asynchronous RTT(NOM) turn-on delay (DLL off) tAONAS 1 9 1 9 1 9 1 9 ns 16Gb: x4, x8, x16 DDR4 SDRAM Electrical Characteristics and AC Timing Parameters CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 362 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Table 157: Electrical Characteristics and AC Timing Parameters: DDR4-1600 through DDR4-2400 (Continued) Parameter Symbol DDR4-1600 DDR4-1866 DDR4-2133 DDR4-2400 Unit NotesMin Max Min Max Min Max Min Max Asynchronous RTT(NOM) turn-off delay (DLL off) tAOFAS 1 9 1 9 1 9 1 9 ns ODT HIGH time with WRITE command and BL8 ODTH8 1tCK 6 – 6 – 6 – 6 – CK ODTH8 2tC K 7–7–7–7– ODT HIGH time without WRITE command or with WRITE command and BC4 ODTH4 1tCK 4 – 4 – 4 – 4 – CK ODTH4 2tC K 5–5–5–5– Write Leveling Timing First DQS_t, DQS_c rising edge after write leveling mode is programmed tWLMRD 40 – 40 – 40 – 40 – CK DQS_t, DQS_c delay after write leveling mode is programmed tWLDQSEN 25 – 25 – 25 – 25 – CK Write leveling setup from rising CK_t, CK_c crossing to rising DQS_t, DQS_c crossing tWLS 0.13 – 0.13 – 0.13 – 0.13 – tCK (AVG) Write leveling hold from rising DQS_t, DQS_c crossing to rising CK_t, CK_c cross- ing tWLH 0.13 – 0.13 – 0.13 – 0.13 – tCK (AVG) Write leveling output delay tWLO 0 9.5 0 9.5 0 9.5 0 9.5 ns Write leveling output error tWLOE 0 2 0 2 0 2 0 2 ns Gear-Down Timing (Not Supported Below DDR4-2666) Exit reset from CKE HIGH to a valid MRS gear-down tXPR_GEAR N/A N/A N/A N/A CK CKE HIGH assert to gear-down enable time) tXS_GEAR N/A N/A N/A N/A CK MRS command to sync pulse time tSYNC_GEAR N/A N/A N/A N/A CK Sync pulse to first valid command tCMD_GEAR N/A N/A N/A N/A CK Gear-down setup time tGEAR_setup N/A – N/A – N/A – N/A – CK Gear-down hold time tGEAR_hold N/A – N/A – N/A – N/A – CK 16Gb: x4, x8, x16 DDR4 SDRAM Electrical Characteristics and AC Timing Parameters CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 363 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Notes: 1. Maximum limit not applicable. 2. Micron tDLLK values support the legacy JEDEC tDLLK specifications. 3. DDR4-1600 AC timing parameters apply if DRAM operates at lower than 1600 MT/s data rate. 4. Data rate is greater than or equal to 1066 Mb/s. 5. WRITE-to-READ when CRC and DM are both not enabled. 6. WRITE-to-READ delay when CRC and DM are both enabled. 7. The start of internal write transactions is defined as follows:

• For BL8 (fixed by MRS and on-the-fly): rising clock edge four clock cycles after WL
• For BC4 (on-the-fly): rising clock edge four clock cycles after WL
• For BC4 (fixed by MRS): rising clock edge two clock cycles after WL 8. For these parameters, the device supports tnPARAM [nCK] = ROUND{tPARAM [ns]/tCK (AVG) [ns]} according to the rounding algorithms found in the Converting Time-Based Specifications to Clock-Based Requirements section, in clock cycles, assuming all input clock jitter specifications are satisfied. 9. When operating in 1 tCK WRITE preamble mode. 10. When operating in 2 tCK WRITE preamble mode. 11. When CA parity mode is selected and the DLLoff mode is used, each REF command re- quires an additional "PL" added to tRFC refresh time. 12. DRAM devices should be evenly addressed when being accessed. Disproportionate ac- cesses to a particular row address may result in reduction of the product lifetime and/or reduction in data retention ability. 13. Applicable from tCK (AVG) MIN to tCK (AVG) MAX as stated in the Speed Bin tables. 14. JEDEC specifies a minimum of five clocks. 15. The maximum read postamble is bound by tDQSCK (MIN) plus tQSH (MIN) on the left side and tHZ(DQS) MAX on the right side. 16. The reference level of DQ output signal is specified with a midpoint as a widest part of output signal eye, which should be approximately 0.7 × VDDQ as a center level of the static single-ended output peak-to-peak swing with a driver impedance of 34 ohms and an effective test load of 50 ohms to V TT = VDDQ. 17. JEDEC hasn't agreed upon the definition of the deterministic jitter; the user should fo- cus on meeting the total limit. 18. Spread spectrum is not included in the jitter specification values. However, the input clock can accommodate spread-spectrum at a sweep rate in the range of 20–60 kHz with an additional 1% of tCK (AVG) as a long-term jitter component; however, the spread spectrum may not use a clock rate below tCK (AVG) MIN. 19. The actual tCAL minimum is the larger of 3 clocks or 3.748ns/tCK; the table lists the ap- plicable clocks required at targeted speed bin. 20. The maximum READ preamble is bounded by tLZ(DQS) MIN on the left side and tDQSCK (MAX) on the right side. See figure in the Clock to Data Strobe Relationship section. Boundary of DQS Low-Z occurs one cycle earlier in 2 tCK toggle mode, as illustrated in the READ Preamble section. 21. DQ falling signal middle-point of transferring from HIGH to LOW to first rising edge of DQS differential signal cross-point. 22. The tPDA_S/tPDA_H parameters may use the tDS/tDH limits, respectively, if the signal is LOW the entire BL8. 16Gb: x4, x8, x16 DDR4 SDRAM Electrical Characteristics and AC Timing Parameters CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 364 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Electrical Characteristics and AC Timing Parameters: 2666 Through 3200 Table 158: Electrical Characteristics and AC Timing Parameters Parameter Symbol DDR4-2666 DDR4-2933 DDR4-3200 Reserved Unit NotesMin Max Min Max Min Max Min Max Clock Timing Clock period average (DLL off mode) tCK (DLL_OFF) 8 20 8 20 8 20 ns Clock period average tCK (AVG, DLL_ON) 0 ), 13 (AVG) (AVG) Clock period jitter Total tJITper_tot –38 38 -34 34 –32 32 ps 17 , 18 Deterministic tJITper_dj –19 19 -17 17 –16 16 ps 17 DLL locking tJITper,lck –30 30 -27 27 –25 25 ps Clock absolute period tCK (ABS) MIN = tCK (AVG) MIN + tJITper_tot MIN; MAX = tCK (AVG) MAX + tJITper_tot MAX ps Clock absolute high pulse width (includes duty cycle jitter) tCH (ABS) 0.45 – 0.45 – 0.45 – tCK (AVG) Clock absolute low pulse width (includes duty cycle jitter) tCL (ABS) 0.45 – 0.45 – 0.45 – tCK (AVG) Cycle-to-cycle jitter Total tJITcc _tot – 75 – 68 – 62 ps DLL locking tJITcc,lck – 60 – 55 – 62 ps 16Gb: x4, x8, x16 DDR4 SDRAM Electrical Characteristics and AC Timing Parameters: 2666 Through 3200 CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 365 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Table 158: Electrical Characteristics and AC Timing Parameters (Continued) Parameter Symbol DDR4-2666 DDR4-2933 DDR4-3200 Reserved Unit NotesMin Max Min Max Min Max Min Max Cumulative error across 2 cycles tERR2per –55 55 -50 50 –46 46 ps 3 cycles tERR3per –66 66 -60 60 –55 55 ps 4 cycles tERR4per –73 73 -66 66 –61 61 ps 5 cycles tERR5per –78 78 -71 71 –65 65 ps 6 cycles tERR6per –83 83 -75 75 –69 69 ps 7 cycles tERR7per –87 87 -79 79 –73 73 ps 8 cycles tERR8per –91 91 -83 83 –76 76 ps 9 cycles tERR9per –94 94 -85 85 –78 78 ps 10 cycles tERR10per –96 96 -88 88 –80 80 ps 11 cycles tERR11per –99 99 -90 90 –83 83 ps 12 cycles tERR12per –101 101 -92 92 –84 84 ps 50 cycles tERRnper tERRnper MIN = (1 + 0.68ln[n]) × tJITper_tot MIN tERRnper MAX = (1 + 0.68ln[n]) × tJITper_tot MAX ps DQ Input Timing Data setup time to DQS_t, DQS_c Base (calibrated VREF) tDS Refer to DQ Input Receiver Specification section (approximately 0.15tCK to 0.28tCK ) Non-calibrated VREF tPDA_S minimum of 0.5ui UI 22 Data hold time from DQS_t, DQS_c Base (calibrated VREF) tDH Refer to DQ Input Receiver Specification section (approximately 0.15tCK to 0.28tCK ) Non-calibrated VREF tPDA_H minimum of 0.5UI UI 22 DQ and DM minimum data pulse width for each input tDIPW 0.58 – 0.58 – 0.58 – UI DQ Output Timing (DLL enabled) DQS_t, DQS_c to DQ skew, per group, per access tDQSQ – 0.18 – 0.19 – 0.20 UI DQ output hold time from DQS_t, DQS_c tQH 0.74 – 0.72 – 0.70 – UI Data Valid Window per device: tQH - tDQSQ each device’s output per UI tDVWd 0.64 – 0.64 – 0.64 – UI Data Valid Window per device, per pin: tQH - tDQSQ each device’s output per UI tDVWp 0.72 – 0.72 – 0.72 – UI 16Gb: x4, x8, x16 DDR4 SDRAM Electrical Characteristics and AC Timing Parameters: 2666 Through 3200 CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 366 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Table 158: Electrical Characteristics and AC Timing Parameters (Continued) Parameter Symbol DDR4-2666 DDR4-2933 DDR4-3200 Reserved Unit NotesMin Max Min Max Min Max Min Max DQ Low-Z time from CK_t, CK_c tLZDQ –310 170 –280 165 –250 160 ps DQ High-Z time from CK_t, CK_c tHZDQ – 170 – 165 – 160 ps DQ Strobe Input Timing DQS_t, DQS_c rising edge to CK_t, CK_c rising edge for 1tCKpreamble DQS_t, DQS_c rising edge to CK_t, CK_c rising edge for 2tCKpreamble DQS_t, DQS_c differential input low pulse width DQS_t, DQS_c differential input high pulse width DQS_t, DQS_c falling edge setup to CK_t, CK_c rising edge tDSS 0.18 – 0.18 – 0.18 – CK DQS_t, DQS_c falling edge hold from CK_t, CK_c rising edge tDSH 0.18 – 0.18 – 0.18 – CK DQS_t, DQS_c differential WRITE pream- ble for 1tCKpreamble tWPRE1ck 0.9 – 0.9 – 0.9 – CK DQS_t, DQS_c differential WRITE pream- ble for 2tCKpreamble tWPRE2ck 1.8 – 1.8 – 1.8 – CK DQS_t, DQS_c differential WRITE postam- ble tWPST 0.33 – 0.33 – 0.33 – CK DQS Strobe Output Timing (DLL enabled) DQS_t, DQS_c rising edge output access time from rising CK_t, CK_c tDQSCK –170 170 –165 165 –160 160 ps DQS_t, DQS_c rising edge output var- iance window per DRAM tDQSCKi – 270 – 265 – 260 ps DQS_t, DQS_c differential output high time tQSH 0.40 – 0.40 – 0.40 – CK DQS_t, DQS_c differential output low time tQSL 0.40 – 0.40 – 0.40 – CK DQS_t, DQS_c Low-Z time (RL - 1) tLZDQS –310 170 –280 165 –250 160 ps DQS_t, DQS_c High-Z time (RL + BL/2) tHZDQS – 170 – 165 – 160 ps 16Gb: x4, x8, x16 DDR4 SDRAM Electrical Characteristics and AC Timing Parameters: 2666 Through 3200 CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 367 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Table 158: Electrical Characteristics and AC Timing Parameters (Continued) Parameter Symbol DDR4-2666 DDR4-2933 DDR4-3200 Reserved Unit NotesMin Max Min Max Min Max Min Max DQS_t, DQS_c differential READ pream- ble for 1tCKpreamble tRPRE1ck 0.9 – 0.9 – 0.9 – CK 20 DQS_t, DQS_c differential READ pream- ble for 2tCKpreamble tRPRE2ck 1.8 – 1.8 – 1.8 – CK 20 DQS_t, DQS_c differential READ postam- ble tRPST 0.33 – 0.33 – 0.33 – CK 21 Command and Address Timing DLL locking time tDLLK 854 – 940 – 1024 – CK 2, 4 CMD, ADDR setup time to CK_t, CK_c refer- enced to V IH(AC) and VIL(AC) levels Base tIS 55 – 48 – 40 – ps VREFCA tISVREF 145 – 138 – 130 – ps CMD, ADDR hold time to CK_t, CK_c refer- enced to V IH(DC) and VIL(DC) levels Base tIH 80 – 73 – 65 – ps VREFCA tIHVREF 145 – 138 – 130 – ps CTRL, ADDR pulse width for each input tIPW 385 – 365 – 340 – ps ACTIVATE to internal READ or WRITE de- lay tRCD See Speed Bin Tables for tRCD ns PRECHARGE command period tRP See Speed Bin Tables for tRP ns ACTIVATE-to-PRECHARGE command peri- od tRAS See Speed Bin Tables for tRAS ns 12 ACTIVATE-to-ACTIVATE or REF command period tRC See Speed Bin Tables for tRC ns 12 ACTIVATE-to-ACTIVATE command period to different bank groups for 1/2KB page size tRRD_S (1/2KB) MIN = greater of 4CK or 3.0ns MIN = greater of 4CK or 2.7ns MIN = greater of 4CK or 2.5ns CK 1 ACTIVATE-to-ACTIVATE command period to different bank groups for 1KB page size tRRD_S (1KB) MIN = greater of 4CK or 3.0ns MIN = greater of 4CK or 2.7ns MIN = greater of 4CK or 2.5ns CK 1 ACTIVATE-to-ACTIVATE command period to different bank groups for 2KB page size tRRD_S (2KB) MIN = greater of 4CK or 5.3ns MIN = greater of 4CK or 5.3ns MIN = greater of 4CK or 5.3ns CK 1 16Gb: x4, x8, x16 DDR4 SDRAM Electrical Characteristics and AC Timing Parameters: 2666 Through 3200 CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 368 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Table 158: Electrical Characteristics and AC Timing Parameters (Continued) Parameter Symbol DDR4-2666 DDR4-2933 DDR4-3200 Reserved Unit NotesMin Max Min Max Min Max Min Max ACTIVATE-to-ACTIVATE command period to same bank groups for 1/2KB page size tRRD_L (1/2KB) MIN = greater of 4CK or 4.9ns MIN = greater of 4CK or 4.9ns MIN = greater of 4CK or 4.9ns CK 1 ACTIVATE-to-ACTIVATE command period to same bank groups for 1KB page size tRRD_L (1KB) MIN = greater of 4CK or 4.9ns MIN = greater of 4CK or 4.9ns MIN = greater of 4CK or 4.9ns CK 1 ACTIVATE-to-ACTIVATE command period to same bank groups for 2KB page size tRRD_L (2KB) MIN = greater of 4CK or 6.4ns MIN = greater of 4CK or 6.4ns MIN = greater of 4CK or 6.4ns CK 1 Four ACTIVATE windows for 1/2KB page size tFAW (1/2KB) MIN = greater of 16CK or 12ns MIN = greater of 16CK or 10.875ns MIN = greater of 16CK or 10ns ns Four ACTIVATE windows for 1KB page size tFAW (1KB) MIN = greater of 20CK or 21ns MIN = greater of 20CK or 21ns MIN = greater of 20CK or 21ns ns Four ACTIVATE windows for 2KB page size tFAW (2KB) MIN = greater of 28CK or 30ns MIN = greater of 28CK or 30ns MIN = greater of 28CK or 30ns ns WRITE recovery time tWR MIN = 15ns ns 5, 9, 1 tWR2 MIN = 1CK + tWR CK 5, 10, 1 WRITE recovery time when CRC and DM are both enabled tWR_CRC_DM MIN = tWR + greater of (5CK or 3.75ns) CK 6, 9, 1 WRITE recovery time when CRC and DM are both enabled tWR_CRC_DM2 MIN = 1CK + tWR_CRC_DM CK 6, 10, 1 Delay from start of internal WRITE trans- action to internal READ command – Same bank group tWTR_L MIN = greater of 4CK or 7.5ns CK 5, 9, 1 tWTR_L2 MIN = 1CK + tWTR_L CK 5, 10, 1 Delay from start of internal WRITE trans- action to internal READ command – Same bank group when CRC and DM are both enabled tWTR_L_CRC_D M MIN = tWTR_L + greater of (5CK or 3.75ns) CK 6, 9, 1 tWTR_L_CRC_D MIN = 1CK + tWTR_L_CRC_DM CK 6, 10, 1 Delay from start of internal WRITE trans- action to internal READ command – Dif- ferent bank group tWTR_S MIN = greater of (2CK or 2.5ns) CK 5, 7, 8, 9, 1 tWTR_S2 MIN = 1CK + tWTR_S CK 5, 7, 8, 10, 1 Delay from start of internal WRITE trans- action to internal READ command – Dif- ferent bank group when CRC and DM are both enabled tWTR_S_CRC_D M MIN = tWTR_S + greater of (5CK or 3.75ns) CK 6, 7, 8, 9, 1 tWTR_S_CRC_D MIN = 1CK + tWTR_S_CRC_DM CK 6, 7, 8, 10, 1 16Gb: x4, x8, x16 DDR4 SDRAM Electrical Characteristics and AC Timing Parameters: 2666 Through 3200 CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 369 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Table 158: Electrical Characteristics and AC Timing Parameters (Continued) Parameter Symbol DDR4-2666 DDR4-2933 DDR4-3200 Reserved Unit NotesMin Max Min Max Min Max Min Max READ-to-PRECHARGE time tRTP MIN = greater of 4CK or 7.5ns CK 1 CAS_n-to-CAS_n command delay to dif- ferent bank group tCCD_S 4 – 4 – 4 – CK CAS_n-to-CAS_n command delay to same bank group tCCD_L MIN = greater of 4CK or 5ns – MIN = greater of 4CK or 5ns – MIN = greater of 4CK or 5ns – CK 14 Auto precharge write recovery + pre- charge time tDAL (MIN) MIN = WR + ROUND tRP/tCK (AVG); MAX = N/A CK 8 MRS Command Timing MRS command cycle time tMRD 8 – 8 – 8 – CK MRS command cycle time in PDA mode tMRD_PDA MIN = greater of (16nCK, 10ns) 1 MRS command cycle time in CAL mode tMRD_CAL MIN = tMOD + tCAL CK MRS command update delay tMOD MIN = greater of (24nCK, 15ns) CK 1 MRS command update delay in PDA mode tMOD_PDA MIN = tMOD CK MRS command update delay in CAL mode tMOD_CAL MIN = tMOD + tCAL CK MRS command to DQS drive in preamble training tSDO MIN = tMOD + 9ns MPR Command Timing Multipurpose register recovery time tMPRR MIN = 1nCK CK Multipurpose register write recovery time tWR_MPR MIN = tMOD + AL + PL CRC Error Reporting Timing CRC error to ALERT_n latency tCRC_ALERT 3 13 3 13 3 13 ns CRC ALERT_n pulse width tCRC_ALERT_P W 6 10 6 10 6 10 CK CA Parity Timing Parity latency PL 5 – 6 – 6 – CK Commands uncertain to be executed dur- ing this time tPAR_UN- KNOWN – PL – PL – PL CK Delay from errant command to ALERT_n assertion tPAR_ALERT_O N – PL + 6ns – PL + 6ns – PL + 6ns CK 16Gb: x4, x8, x16 DDR4 SDRAM Electrical Characteristics and AC Timing Parameters: 2666 Through 3200 CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 370 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Table 158: Electrical Characteristics and AC Timing Parameters (Continued) Parameter Symbol DDR4-2666 DDR4-2933 DDR4-3200 Reserved Unit NotesMin Max Min Max Min Max Min Max Pulse width of ALERT_n signal when as- serted tPAR_ALERT_P W 80 160 88 176 96 192 CK Time from alert asserted until DES com- mands required in persistent CA parity mode tPAR_ALERT_RS P – 71 – 78 – 85 CK CAL Timing CS_n to command address latency tCAL 5 – 6 – 6 – CK 19 CS_n to command address latency in gear-down mode tCALg 6 – 8 – 8 – CK MPSM Timing Command path disable delay upopn MPSM entry tMPED MIN = tMOD (MIN) + tCPDED (MIN) CK 1 Valid clock requirement after MPSM entry tCKMPE MIN = tMOD (MIN) + tCPDED (MIN) CK 1 Valid clock requirement before MPSM exit tCKMPX MIN = tCKSRX (MIN) CK 1 Exit MPSM to commands not requiring a locked DLL tXMP tXS (MIN) CK Exit MPSM to commands requiring a locked DLL tXMPDLL MIN = tXMP (MIN) + tXSDLL (MIN) CK 1 CS setup time to CKE tMPX_S MIN = tIS (MIN) + tIH (MIN) ns CS_n HIGH hold time to CKE rising edge tMPX_HH MIN = tXP ns CS_n LOW hold time to CKE rising edge tMPX_LH 12 tXMP-1 0ns 12 tXMP-1 0ns 12 tXMP-1 0ns ns Connectivity Test Timing TEN pin HIGH to CS_n LOW – Enter CT mode tCT_Enable 200 – 200 – 200 – ns CS_n LOW and valid input to valid output tCT_Valid – 200 – 200 – 200 ns CK_t, CK_c valid and CKE HIGH after TEN goes HIGH tCTCKE_Valid 10 – 10 – 10 – ns Calibration and VREFDQ Train Timing 16Gb: x4, x8, x16 DDR4 SDRAM Electrical Characteristics and AC Timing Parameters: 2666 Through 3200 CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 371 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Table 158: Electrical Characteristics and AC Timing Parameters (Continued) Parameter Symbol DDR4-2666 DDR4-2933 DDR4-3200 Reserved Unit NotesMin Max Min Max Min Max Min Max ZQCL command: Long calibration time POWER-UP and RESET operation tZQinit 1024 – 1024 – 1024 – CK Normal opera- tion tZQoper 512 – 512 – 512 – CK ZQCS command: Short calibration time tZQCS 128 – 128 – 128 – CK The VREF increment/decrement step time V REF_time MIN = 150ns Enter VREFDQ training mode to the first write or VREFDQ MRS command delay tVREFDQE MIN = 150ns ns 1 Exit VREFDQ training mode to the first WRITE command delay tVREFDQX MIN = 150ns ns 1 Initialization and Reset Timing Exit reset from CKE HIGH to a valid com- mand tXPR MIN = tRFC1 + 10ns ns 1 RESET_L pulse low after power stable tPW_RESET_S 1.0 – 1.0 – 1.0 – μs RESET_L pulse low at power-up tPW_RESET_L 200 – 200 – 200 – μs Begin power supply ramp to power sup- plies stable tVDDPR MIN = N/A; MAX = 200 ms RESET_n LOW to power supplies stable tRPS MIN = 0; MAX = 0 ns Refresh Timing REFRESH-to-ACTIVATE or REFRESH command period (all bank groups) 4Gb tRFC1 MIN = 260 ns 1, 11 tRFC2 MIN = 160 ns 1, 11 tRFC4 MIN = 110 ns 1, 11 8Gb tRFC1 MIN = 350 ns 1, 11 tRFC2 MIN = 260 ns 1, 11 tRFC4 MIN = 160 ns 1, 11 16Gb tRFC1 MIN = 350 ns 1, 11 tRFC2 MIN = 260 ns 1, 11 tRFC4 MIN = 160 ns 1, 11 16Gb: x4, x8, x16 DDR4 SDRAM Electrical Characteristics and AC Timing Parameters: 2666 Through 3200 CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 372 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Table 158: Electrical Characteristics and AC Timing Parameters (Continued) Parameter Symbol DDR4-2666 DDR4-2933 DDR4-3200 Reserved Unit NotesMin Max Min Max Min Max Min Max Average periodic re- fresh interval -40°C ื TC ื 85°C tREFI MIN = N/A; MAX = 7.8 μs 11 85°C < TC ื 95°C tREFI MIN = N/A; MAX = 3.9 μs 11 95°C < TC ื 105°C tREFI MIN = N/A; MAX = 1.95 μs 11 105°C < TC ื 125°C tREFI MIN = N/A; MAX = 0.975 μs 11 Self Refresh Timing Exit self refresh to commands not requir- ing a locked DLL tXS MIN = tRFC1 + 10ns ns 1 Exit self refresh to commands not requir- ing a locked DLL in self refresh abort tXS_ABORT MIN = tRFC4 + 10ns ns 1 Exit self refresh to ZQCL, ZQCS and MRS (CL, CWL, WR, RTP and gear-down) tXS_FAST MIN = tRFC4 + 10ns ns Exit self refresh to commands requiring a locked DLL tXSDLL MIN = tDLLK (MIN) CK 1 Minimum CKE low pulse width for self re- fresh entry to self refresh exit timing tCKESR MIN = tCKE (MIN) + 1nCK CK 1 Minimum CKE low pulse width for self re- fresh entry to self refresh exit timing when CA parity is enabled tCKESR_par MIN = tCKE (MIN) + 1nCK + PL CK 1 Valid clocks after self refresh entry (SRE) or power-down entry (PDE) tCKSRE MIN = greater of (5CK, 10ns) CK 1 Valid clock requirement after self refresh entry or power-down when CA parity is enabled tCKSRE_par MIN = greater of (5CK, 10ns) + PL CK 1 Valid clocks before self refresh exit (SRX) or power-down exit (PDX), or reset exit tCKSRX MIN = greater of (5CK, 10ns) CK 1 Power-Down Timing Exit power-down with DLL on to any val- id command tXP MIN = greater of 4CK or 6ns CK 1 Exit precharge power-down with DLL fro- zen to commands not requiring a locked DLL when CA Parity is enabled. tXP _PAR MIN = (greater of 4CK or 6ns) + PL CK 1 CKE MIN pulse width tCKE (MIN) MIN = greater of 3CK or 5ns CK 1 16Gb: x4, x8, x16 DDR4 SDRAM Electrical Characteristics and AC Timing Parameters: 2666 Through 3200 CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 373 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Table 158: Electrical Characteristics and AC Timing Parameters (Continued) Parameter Symbol DDR4-2666 DDR4-2933 DDR4-3200 Reserved Unit NotesMin Max Min Max Min Max Min Max Command pass disable delay tCPDED 4 – 4 – 4 – CK Power-down entry to power-down exit timing tPD MIN = tCKE (MIN); MAX = 9 × tREFI CK Begin power-down period prior to CKE registered HIGH tANPD WL - 1CK CK Power-down entry period: ODT either synchronous or asynchronous PDE Greater of tANPD or tRFC - REFRESH command to CKE LOW time CK Power-down exit period: ODT either syn- chronous or asynchronous PDX tANPD + tXSDLL CK Power-Down Entry Minimum Timing ACTIVATE command to power-down en- try tACTPDEN 2 – 2 – 2 – CK PRECHARGE/PRECHARGE ALL command to power-down entry tPRPDEN 2 – 2 – 2 – CK REFRESH command to power-down entry tREFPDEN 2 – 2 – 2 – CK MRS command to power-down entry tMRSPDEN MIN = tMOD (MIN) CK 1 READ/READ with auto precharge com- mand to power-down entry tRDPDEN MIN = RL + 4 + 1 CK 1 WRITE command to power-down entry (BL8OTF, BL8MRS, BC4OTF) tWRPDEN MIN = WL + 4 + tWR/tCK (AVG) CK 1 WRITE command to power-down entry (BC4MRS) tWRPBC4DEN MIN = WL + 2 + tWR/tCK (AVG) CK 1 WRITE with auto precharge command to power-down entry (BL8OTF, BL8MRS,BC4OTF) tWRAPDEN MIN = WL + 4 + WR + 1 CK 1 WRITE with auto precharge command to power-down entry (BC4MRS) tWRAPBC4DEN MIN = WL + 2 + WR + 1 CK 1 ODT Timing Direct ODT turn-on latency DODTLon WL - 2 = CWL + AL + PL - 2 CK Direct ODT turn-off latency DODTLoff WL - 2 = CWL + AL + PL - 2 CK R Asynchronous RTT(NOM) turn-on delay (DLL off) tAONAS 1 9 1 9 1 9 ns 16Gb: x4, x8, x16 DDR4 SDRAM Electrical Characteristics and AC Timing Parameters: 2666 Through 3200 CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 374 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Table 158: Electrical Characteristics and AC Timing Parameters (Continued) Parameter Symbol DDR4-2666 DDR4-2933 DDR4-3200 Reserved Unit NotesMin Max Min Max Min Max Min Max Asynchronous RTT(NOM) turn-off delay (DLL off) tAOFAS 1 9 1 9 1 9 ns ODT HIGH time with WRITE command and BL8 ODTH8 1tCK 6 – 6 – 6 – CK ODTH8 2tCK 7 – 7 – 7 – ODT HIGH time without WRITE command or with WRITE command and BC4 ODTH4 1tCK 4 – 4 – 4 – CK ODTH4 2tCK 5 – 5 – 5 – Write Leveling Timing First DQS_t, DQS_c rising edge after write leveling mode is programmed tWLMRD 40 – 40 – 40 – CK DQS_t, DQS_c delay after write leveling mode is programmed tWLDQSEN 25 – 25 – 25 – CK Write leveling setup from rising CK_t, CK_c crossing to rising DQS_t, DQS_c crossing tWLS 0.13 – 0.13 – 0.13 – CK Write leveling hold from rising DQS_t, DQS_c crossing to rising CK_t, CK_c cross- ing tWLH 0.13 – 0.13 – 0.13 – CK Write leveling output delay tWLO 0 9.5 0 9.5 0 9.5 ns Write leveling output error tWLOE 0 2 0 2 0 2 ns Gear-Down Timing Exit reset from CKE HIGH to a valid MRS gear-down tXPR_GEAR tXPR tXPR tXPR CK CKE HIGH assert to gear-down enable time) tXS_GEAR tXS tXS tXS CK MRS command to sync pulse time tSYNC_GEAR tMOD + 4CK tMOD + 4CK tMOD + 4CK CK Sync pulse to first valid command tCMD_GEAR tMOD tMOD tMOD CK Gear-down setup time tGEAR_setup 2CK – 2CK – 2CK – CK Gear-down hold time tGEAR_hold 2CK – 2CK – 2CK – CK 16Gb: x4, x8, x16 DDR4 SDRAM Electrical Characteristics and AC Timing Parameters: 2666 Through 3200 CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 375 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Notes: 1. Maximum limit not applicable. 2. Micron tDLLK values support the legacy JEDEC tDLLK specifications. 3. DDR4-1600 AC timing parameters apply if DRAM operates at lower than 1600 MT/s data rate. 4. Data rate is greater than or equal to 1066 Mb/s. 5. WRITE-to-READ when CRC and DM are both not enabled. 6. WRITE-to-READ delay when CRC and DM are both enabled. 7. The start of internal write transactions is defined as follows:

• For BL8 (fixed by MRS and on-the-fly): rising clock edge four clock cycles after WL
• For BC4 (on-the-fly): rising clock edge four clock cycles after WL
• For BC4 (fixed by MRS): rising clock edge two clock cycles after WL 8. For these parameters, the device supports tnPARAM [nCK] = ROUND{tPARAM [ns]/tCK (AVG) [ns]} according to the rounding algorithms found in the Converting Time-Based Specifications to Clock-Based Requirements section, in clock cycles, assuming all input clock jitter specifications are satisfied. 9. When operating in 1 tCK WRITE preamble mode. 10. When operating in 2 tCK WRITE preamble mode. 11. When CA parity mode is selected and the DLLoff mode is used, each REF command re- quires an additional "PL" added to tRFC refresh time. 12. DRAM devices should be evenly addressed when being accessed. Disproportionate ac- cesses to a particular row address may result in reduction of the product lifetime and/or reduction in data retention ability. 13. Applicable from tCK (AVG) MIN to tCK (AVG) MAX as stated in the Speed Bin tables. 14. JEDEC specifies a minimum of five clocks. 15. The maximum read postamble is bound by tDQSCK (MIN) plus tQSH (MIN) on the left side and tHZ(DQS) MAX on the right side. 16. The reference level of DQ output signal is specified with a midpoint as a widest part of output signal eye, which should be approximately 0.7 × VDDQ as a center level of the static single-ended output peak-to-peak swing with a driver impedance of 34 ohms and an effective test load of 50 ohms to V TT = VDDQ. 17. JEDEC hasn't agreed upon the definition of the deterministic jitter; the user should fo- cus on meeting the total limit. 18. Spread spectrum is not included in the jitter specification values. However, the input clock can accommodate spread-spectrum at a sweep rate in the range of 20–60 kHz with an additional 1% of tCK (AVG) as a long-term jitter component; however, the spread spectrum may not use a clock rate below tCK (AVG) MIN. 19. The actual tCAL minimum is the larger of 3 clocks or 3.748ns/tCK; the table lists the ap- plicable clocks required at targeted speed bin. 20. The maximum READ preamble is bounded by tLZ(DQS) MIN on the left side and tDQSCK (MAX) on the right side. See figure in the Clock to Data Strobe Relationship section. Boundary of DQS Low-Z occurs one cycle earlier in 2 tCK toggle mode, as illustrated in the READ Preamble section. 21. DQ falling signal middle-point of transferring from HIGH to LOW to first rising edge of DQS differential signal cross-point. 22. The tPDA_S/tPDA_H parameters may use the tDS/tDH limits, respectively, if the signal is LOW the entire BL8. Converting Time-Based Specifications to Clock-Based Requirements Software algorithms for calculation of timing parameters are subject to potential round- ing errors when converting DRAM timing requirements to system clocks; for example, a 16Gb: x4, x8, x16 DDR4 SDRAM Converting Time-Based Specifications to Clock-Based Require- ments CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 376 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

memory clock with a nominal frequency of 933.33...3MHz which yields a clock period of ly and some sort of rounding needs to be done. DDR4 SDRAM SPD-based specifications use a minimum granularity for SPD-associated timing parameters of 1ps. Clock periods such as tCK (AVG) MIN are defined to the near- as tAA MIN are specified in units of time (nanoseconds) and require mathematical com- putation to convert to system clocks (nCK). Rules for rounding allow optimization of device performance without violating device parameters. These SPD algorithms rely on results that are within nCK adjustment factors on device testing and specification to avoid losing performance due to rounding errors when using SPD-based parameters. Note that JEDEC also defines an nCK adjustment factor, but mandates the inverse nCK adjustment factor be used in case of conflicting results, so only the inverse nCK adjust- ment factor is discussed here. Guidance converting SPD associated timing parameters to system clock requirements:

• Round the application clock period up to the nearest picosecond.
• Express the timing specification and application clock period in picoseconds; scaling a nanosecond-based parameter value by 1000 allows programmers to use integer math instead of real math by expressing timing in ps.
• Divide the picosecond-based parameter by the picoseconds based application clock period.
• Add an inverse nCK adjustment factor of 97.4%.
• Truncate down to the next lower integer value.
• nCK = Truncate[(parameter in ps)/(application tCK in ps) + (974/1000)]. Guidance converting nonSPD associated timing parameters to system clock require- ments:
• Divide the time base specification (in ns) and divided by the clock period (in ns).
• The resultant is set to the next higher integer number of clocks.
• nCK = Ceiling[(parameter in ns/application tCK in ns)]. 16Gb: x4, x8, x16 DDR4 SDRAM Converting Time-Based Specifications to Clock-Based Require- ments CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 377 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Table 159: Options – Speed Based Function Acronym Data Rate 1600 1866 2133 2400 2666 2933 3200 Write leveling WL Yes Yes Yes Yes Yes Yes Yes Temperature controlled refresh TCR Yes Yes Yes Yes Yes Yes Yes Low-power auto self refresh LPASR Yes Yes Yes Yes Yes Yes Yes Fine granularity refresh FGR Yes Yes Yes Yes Yes Yes Yes Multipurpose register MR Yes Yes Yes Yes Yes Yes Yes Data mask DM Yes Yes Yes Yes Yes Yes Yes Data bus inversion DBI Yes Yes Yes Yes Yes Yes Yes TDQS – Yes Yes Yes Yes Yes Yes Yes ZQ calibration ZQ CAL Yes Yes Yes Yes Yes Yes Yes V REFDQ calibration – Yes Yes Yes Yes Yes Yes Yes Per-DRAM addressability Per DRAM Yes Yes Yes Yes Yes Yes Yes Mode register readout – Yes Yes Yes Yes Yes Yes Yes Command/Address latency CAL Yes Yes Yes Yes Yes Yes Yes Write CRC CRC Yes Yes Yes Yes Yes Yes Yes CA parity – Yes Yes Yes Yes Yes Yes Yes Gear-down mode – No No No No Yes Yes Yes Programmable preamble – No No No Yes Yes Yes Yes Maximum power saving mode MPSM Yes Yes Yes Yes Yes Yes Yes Additive latency AL Yes Yes Yes Yes Yes Yes Yes Connectivity test mode CT Yes Yes Yes Yes Yes Yes Yes Hard post package repair mode hPPR Yes Yes Yes Yes Yes Yes Yes Soft post package repair mode sPPR Yes Yes Yes Yes Yes Yes Yes 16Gb: x4, x8, x16 DDR4 SDRAM Options Tables CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 378 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.

Table 160: Options – Width Based Function Acronym Width x4 x8 x16 Write leveling WL Yes Yes Yes Temperature controlled refresh TCR Yes Yes Yes Low-power auto self refresh LPASR Yes Yes Yes Fine granularity refresh FGR Yes Yes Yes Multipurpose register MR Yes Yes Yes Data mask DM No Yes Yes Data bus inversion DBI No Yes Yes TDQS – No Yes No ZQ calibration ZQ CAL Yes Yes Yes V REFDQ calibration – Yes Yes Yes Per-DRAM addressability Per DRAM Yes Yes Yes Mode regsiter readout – Yes Yes Yes Command/Address latency CAL Yes Yes Yes Write CRC CRC Yes Yes Yes CA parity – Yes Yes Yes Gear-down mode – Yes Yes Yes Programmable preamble – Yes Yes Yes Maximum power-down mode MPSM Yes Yes Yes Additive latency AL Yes Yes Yes Connectivity test mode CT JEDEC optional on 8Gb and larger densities Micron supports on all densities Yes Hard post package repair mode hPPR JEDEC optional on 4Gb Micron supports on all densities Soft post package repair mode sPPR JEDEC optional on 4Gb and 8Gb Micron supports on all densities 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-4000 www.micron.com/products/support Sales inquiries: 800-932-4992 Micron and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered final, these specifications are subject to change, as further product development and data characterization some- times occur. 16Gb: x4, x8, x16 DDR4 SDRAM Options Tables CCM005-1406124318-10453 16gb_ddr4_dram.pdf - Rev. G 08/2020 EN 379 Micron Technology, Inc. reserves the right to change products or specifications without notice. ‹ 2018 Micron Technology, Inc. All rights reserved.