MT28F004B5-1

MT28F004B5-1 MICRON | Alldatasheet

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PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE . 4Mb Smart 5 Boot Block Flash Memory ©2002, Micron Technology Inc. MT28F004B5_3.fm - Rev. 3, Pub. 8/2002 1 4Mb SMART 5 BOOT BLOCK FLASH MEMORY FLASH MEMORY MT28F004B5 MT28F400B5 5V Only, Dual Supply (Smart 5) 0.18µm Process Technology

FEATURES

• Seven erase blocks: 16KB/8K-word boot block (protected) Two 8KB/4K-word parameter blocks Four main memory blocks  Smart 5 technology (B5): 5V ±10% VCC 5V ±10% VPP application/production programming1  Advanced 0.18µm CMOS floating-gate process  Compatible with 0.3µm Smart 5 device  Address access time: 80ns  100,000 ERASE cycles  Industry-standard pinouts  Inputs and outputs are fully TTL-compatible  Automated write and erase algorithm  T wo-cycle WRITE/ERASE sequence  Byte- or word-wide READ and WRITE (MT28F400B5, 256K x 16/512K x 8) B y t e - w i d e R E A D a n d W R I T E o n l y (MT28F004B5, 512K x 8)  TSOP and SOP packaging options Notes: 1. This generation of devices does not support 12V V PP compatibility production programming; however, 5V VPP application production programming can be used with no loss of performance. 2. Contact factory for availability. Part Number Example: MT28F400B5WG-8 T GENERAL DESCRIPTION The MT28F004B5 (x8) and MT28F400B5 (x16, x8) are nonvolatile, electrically block-erasable (Flash), programmable, read-only memories containing 4,194,304 bits organized as 262,144 words (16 bits) or 524,288 bytes (8 bits). Writing or erasing the device is d o n e w i t h a 5 V V PP voltage, while all operations are performed with a 5V V CC. Due to process technology advances, 5V V PP is optimal for application and pro- duction programming. These devices are fabricated w i t h M i c r o n ’ s a d v a n c e d 0 . 1 8 µ m C M O S f l o a t i n g - g a t e process. The MT28F004B5 and MT28F400B5 are organized into seven separately erasable blocks. T o ensure that critical firmware is protected from accidental erasure or overwrite, the devices feature a hardware-protected boot block. Writing or erasing the boot block requires either applying a super-voltage to the RP# pin or driv- ing WP# HIGH in addition to executing the normal write or erase sequences. This block may be used to store code implemented in low-level system recovery. The remaining blocks vary in density and are written and erased with no additional security measures. Please refer to Micron’s Web site (www.micron.com/ flash) for the latest data sheet. OPTIONS MARKING  Timing 80ns access -8  Configurations 512K x 8 MT28F004B5 256K x 16/512K x 8 MT28F400B5  Boot Block Starting Word Address Top (3FFFFh) T Bottom (00000h) B O p e r a t i n g T e m p e r a t u r e R a n g e Commercial (0ºC to +70ºC) None Extended (-40ºC to +85ºC) ET P a c k a g e s MT28F400B5 Plastic 44-pin SOP (600 mil) SG Plastic 48-pin TSOP Type I WG MT28F004B5 Plastic 40-pin TSOP Type I VG 40-Pin TSOP Type I 44-Pin SOP2 48-Pin TSOP Type I

SMART 5 BOOT BLOCK FLASH MEMORY 4Mb Smart 5 Boot Block Flash Memory ©2002, Micron Technology Inc. MT28F004B5_3.fm - Rev. 3, Pub. 8/2002 2 Pin Assignment (Top View) 48-Pin TSOP Type I Order Number and Part Marking MT28F400B5WG-8 B MT28F400B5WG-8 T MT28F400B5WG-8 BET MT28F400B5WG-8 TET 44-PIN SOP1 Order Number and Part Marking MT28F400B5SG-8 B MT28F400B5SG-8 T MT28F400B5SG-8 BET MT28F400B5SG-8 TET 40-Pin TSOP Type I Order Number and Part Marking MT28F004B5VG-8 B MT28F004B5VG-8 T MT28F004B5VG-8 BET MT28F004B5VG-8 TET Notes: 1. Contact factory for availability. A15 A14 A13 A12 A11 A10 NC NC WE# RP# V PP WP# NC NC A17 A16 BYTE# V SS DQ15/(A-1) DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 V CC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE# V SS CE# VPP WP# A17 CE# V SS OE# DQ0 DQ8 DQ1 DQ9 DQ2 DQ10 DQ3 DQ11 RP# WE# A10 A11 A12 A13 A14 A15 A16 BYTE# V SS DQ15/(A-1) DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 V CC A16 A15 A14 A13 A12 A11 WE# RP# V PP WP# A18 A17 V SS NC NC A10 DQ7 DQ6 DQ5 DQ4 V CC VCC NC DQ3 DQ2 DQ1 DQ0 OE# V SS CE#

SMART 5 BOOT BLOCK FLASH MEMORY 4Mb Smart 5 Boot Block Flash Memory ©2002, Micron Technology Inc. MT28F004B5_3.fm - Rev. 3, Pub. 8/2002 3 Functional Block Diagram Notes: 1. Does not apply to MT28F004B5. 16KB Boot Block 8KB Parameter Block 8KB Parameter Block 96KB Main Block 128KB Main Block 128KB Main Block Y - Select Gates Sense Amplifiers Write/Erase-Bit Compare and Verify Addr. Buffer/ Latch Power (Current) Control Addr. Counter Command Execution Logic I/O Control Logic VPP Switch/ Pump Status Register Identification Register Y - Decoder 128KB Main Block X - Decoder/Block Erase Control Output Buffer Input Buffer State Machine BYTE#1 A0–A17/(18) CE# OE# WE# RP# VPP DQ15/(A - 1)1 MUX DQ15 DQ8–DQ141 DQ0–DQ7 18 (19) A-1 (10) Output Buffer Output Buffer Input Buffer Input Buffer Input Data Latch/Mux VCC WP#

SMART 5 BOOT BLOCK FLASH MEMORY 4Mb Smart 5 Boot Block Flash Memory ©2002, Micron Technology Inc. MT28F004B5_3.fm - Rev. 3, Pub. 8/2002 4 PIN DESCRIPTIONS 44-PIN SOP NUMBERS 40-PIN TSOP NUMBERS 48-PIN TSOP NUMBERS SYMBOL TYPE DESCRIPTION 43 9 11 WE# Input Write Enable: Determines if a given cycle is a WRITE cycle. If WE# is LOW, the cycle is either a WRITE to the command execution logic (CEL) or to the memory array. 2 12 14 WP# Input Write Protect: Unlocks the boot block when HIGH if VPP = 5V and RP# = VIH during a WRITE or ERASE. Does not affect WRITE or ERASE operation on other blocks. 12 22 26 CE# Input Chip Enable: Activates the device when LOW. When CE# is HIGH, the device is disabled and goes into standby power mode. 44 10 12 RP# Input Reset/Power-Down: When LOW, RP# clears the status register, sets the internal state machine (ISM) to the array read mode and places the device in deep power-down mode. All inputs, including CE#, are “Don’t Care,” and all outputs are High-Z. RP# unlocks the boot block and overrides the condition of WP# when at V HH, and must be held at VIH during all other modes of operation. 14 24 28 OE# Input Output Enable: Enables data output buffers when LOW. When OE# is HIGH, the output buffers are disabled. 33 – 47 BYTE# Input Byte Enable: If BYTE# = HIGH, the upper byte is active through DQ8–DQ15. If BYTE# = LOW, DQ8–DQ14 are High-Z, and all data is accessed through DQ0–DQ7. DQ15/ (A-1) becomes the least significant address input. 11, 10, 9, 8, 7, 6, 5, 4, 42, 41, 40, 39, 38, 37, 36, 35, 34, 3 21, 20, 19, 18, 17, 16,15, 14, 8, 7, 36, 6, 5, 4, 3, 2, 1, 40, 13 25, 24, 23, 22, 21, 20, 19, 18, 8, 7, 6, 5, 4, 3, 2, 1, 48, 17 A0–A17/ (A18) Input Address Inputs: Select a unique, 16-bit word or 8-bit byte. The Q15/(A-1) input becomes the lowest order address when BYTE# = LOW (MT28F400B5) to allow for a selection of an 8-bit byte from the 524,288 available. 31 – 45 DQ15 (A-1) Input/ Output Data I/O: MSB of data when BYTE# = HIGH. Address Input: LSB of address input when BYTE# = LOW during READ or WRITE operation. 15, 17, 19, 21, 24, 26, 28, 30 25-28, 32-35 29, 31, 33, 35, 38, 40, 42, 44 DQ0–DQ7 Input/ Output Data I/Os: Data output pins during any READ operation or data input pins during a WRITE. These pins are used to input commands to the CEL. 16, 18, 20, 22, 25, 27, – 30, 32, 34, 36, 39, 41, DQ8– DQ14 Input/ Output Data I/Os: Data output pins during any READ operation or data input pins during a WRITE when BYTE# = HIGH. These pins are High-Z when BYTE# is LOW. 11 1 1 3 V PP Supply Write/Erase Supply Voltage: From a WRITE or ERASE CONFIRM until completion of the WRITE or ERASE, VPP must be at VPPH (5V). VPP = “Don’t Care” during all other operations. 23 30, 31 37 V CC Supply Power Supply: +5V ±10%. 13, 32 23, 39 27, 46 V SS Supply Ground. – 29, 37, 38 9, 10, 15, 16 NC – No Connect: These pins may be driven or left unconnected.

SMART 5 BOOT BLOCK FLASH MEMORY 4Mb Smart 5 Boot Block Flash Memory ©2002, Micron Technology Inc. MT28F004B5_3.fm - Rev. 3, Pub. 8/2002 5 Notes: 1. L = VIL (LOW), H = VIH (HIGH), X = VIL or VIH (“Don’t Care”). 2. VPPH = 5V. 3. Operation must be preceded by ERASE SETUP command. 4. Operation must be preceded by WRITE SETUP command. 5. The READ ARRAY command must be issued before reading the array after writing or erasing. 6. When WP# = VIH, RP# may be at VIH or VHH. 7. A1–A8, A10–A17 = VIL. 8. Value reflects DQ8–DQ15. TRUTH TABLE (MT28F400B5)1 FUNCTION RP# CE# OE# WE# WP# BYTE# A0 A9 VPP DQ0– DQ7 DQ8– DQ14 DQ15/ A - 1 Standby H H X X X X X X X High-Z High-Z High-Z Reset L X X X X X X X X High-Z High-Z High-Z READ READ (word mode) H L L H X H X X X Data-Out Data-Out Data-Out READ (byte mode) H L L H X L X X X Data-Out High-Z A-1 Output Disable H L H H X X X X X High-Z High-Z High-Z WRITE/ERASE (EXCEPT BOOT BLOCK)2 ERASE SETUP HLHLX X XXX 2 0 h X X ERASE CONFIRM3 HLHLX X XX V PPH D0h X X WRITE SETUP H L H L X X X X X 10h/40h X X WRITE (word mode)4 HLHLX H XX V PPH Data-In Data-In Data-In WRITE (byte mode)4 HLHLX L XX V PPH Data-In X A-1 READ ARRAY5 HLHLX X XXX F F h X X WRITE/ERASE (BOOT BLOCK)2 ERASE SETUP HLHLX X XXX 2 0 h X X ERASE CONFIRM3 VHH L H L XXX X V PPH D0h X X ERASE CONFIRM3, 6 HLHLH X XX V PPH D0h X X WRITE SETUP H L H L X X X X X 10h/40h X X WRITE (word mode)4 VHH LHLX H XX V PPH Data-In Data-In Data-In WRITE (word mode)4, 6 HLHLH H XX V PPH Data-In Data-In Data-In WRITE (byte mode)4 VHH LHLX L XX V PPH Data-In X A-1 WRITE (byte mode)4, 6 HLHLH L XX V PPH Data-In X A-1 READ ARRAY5 HLHLX X XXX F F h X X DEVICE IDENTIFICATION7 Manufacturer Compatibility (word mode)8 HLLHX H L V ID X 89hX 00h – Manufacturer Compatibility (byte mode) HLLHX L L V ID X 89h High-Z X Device (word mode, top boot)8 HLLHX H H V ID X 70h 44h – Device (byte mode, top boot) HLLHX L H V ID X 70h High-Z X Device (word mode, bottom boot)8 HLLHX H H V ID X 71h 44h – Device (byte mode, bottom boot) HLLHX L H V ID X 71h High-Z X

SMART 5 BOOT BLOCK FLASH MEMORY 4Mb Smart 5 Boot Block Flash Memory ©2002, Micron Technology Inc. MT28F004B5_3.fm - Rev. 3, Pub. 8/2002 6 Notes: 1. L = VIL, H = VIH, X = VIL or VIH. 2. VPPH = 5V. 3. Operation must be preceded by ERASE SETUP command. 4. Operation must be preceded by WRITE SETUP command. 5. The READ ARRAY command must be issued before reading the array after writing or erasing. 6. When WP# = VIH, RP# may be at VIH or VHH. 7. A1–A8, A10–A18 = VIL. TRUTH TABLE (MT28F004B5)1 FUNCTION RP# CE# OE# WE# WP# A0 A9 VPP DQ0–DQ7 Standby HHXXXXXX H i g h - Z RESET LXXXXXXX H i g h - Z READ READ HL LHXXXX D a t a - O u t Output Disable HLHHXXXX H i g h - Z WRITE/ERASE (EXCEPT BOOT BLOCK)2 ERASE SETUP HLHLXXXX 2 0 h ERASE CONFIRM3 HLHLXXX V PPH D0h WRITE SETUP HLHLXXXX 1 0 h / 4 0 h WRITE4 HLHLXXX V PPH Data-In READ ARRAY5 HLHLXXXX F F h WRITE/ERASE (BOOT BLOCK)2 ERASE SETUP HLHLXXXX 2 0 h ERASE CONFIRM3 VHH LHLXXX V PPH D0h ERASE CONFIRM3, 6 HLHLHXX V PPH D0h WRITE SETUP HLHLXXXX 1 0 h / 4 0 h WRITE4 VHH LHLXXX V PPH Data-In WRITE4, 6 HLHLHXX V PPH Data-In READ ARRAY5 HLHLXXXX F F h DEVICE IDENTIFICATION7 Manufacturer Compatibility HLLHXL V ID X 89h Device (top boot) HLLHXH V ID X 78h Device (bottom boot) HLLHXH V ID X 79h

SMART 5 BOOT BLOCK FLASH MEMORY 4Mb Smart 5 Boot Block Flash Memory ©2002, Micron Technology Inc. MT28F004B5_3.fm - Rev. 3, Pub. 8/2002 7 FUNCTIONAL DESCRIPTION The MT28F004B5 and MT28F400B5 Flash memo- ries incorporate a number of features ideally suited for system firmware. The memory array is segmented into individual erase blocks. Each block may be erased without affecting data stored in other blocks. These memory blocks are read, written and erased with com- mands to the command execution logic (CEL). The CEL controls the operation of the internal state machine (ISM), which completely controls all WRITE, BLOCK ERASE, and VERIFY operations. The ISM pro- t e c t s e a c h m e m o r y l o c a t i o n f r o m o v e r - e r a s u r e a n d optimizes each memory location for maximum data retention. In addition, the ISM greatly simplifies the control necessary for writing the device in-system or in an external programmer. The Functional Description provides detailed infor- mation on the operation of the MT28F004B5 and MT28F400B5 and is organized into these sections: O v e r v i e w  Memory Architecture  Output (READ) operations I n p u t O p e r a t i o n s  Command Set I S M S t a t u s R e g i s t e r  Command Execution  Error Handling W R I T E / E R A S E C y c l e E n d u r a n c e P o w e r U s a g e P o w e r - U p OVERVIEW Smart 5 Technology (B5) Smart 5 technology allows maximum flexibility for in-system READ, WRITE and ERASE operations. For 5V-only systems, WRITE and ERASE operations may be executed with a V PP voltage of 5V . Due to process tech- nology advances, 5V VPP is optimal for application and production programming. Seven Independently Erasable Memory Blocks The MT28F004B5 and MT28F400B5 are organized into seven independently erasable memory blocks that allow portions of the memory to be erased without affecting the rest of the memory data. A special boot block is hardware-protected against inadvertent era- sure or writing by requiring either a super-voltage on the RP# pin or driving the WP# pin HIGH. One of these two conditions must exist, along with the V PP voltage (5V) on the V PP pin, before a WRITE or ERASE will be performed on the boot block. The remaining blocks require that only the V PP voltage be present on the V PP pin before writing or erasing. Hardware-Protected Boot This block of the memory array can be erased or written only when the RP# pin is taken to V HH or when the WP# pin is brought HIGH. This provides additional security for the core firmware during in-system firm- ware updates should an unintentional power fluctua- tion or system reset occur. The MT28F004B5 and MT28F400B5 are available with the boot block starting at the bottom of the address space (“B” suffix) or the top of the address space (“T” suffix). Selectable Bus Size (MT28F400B5 only) The MT28F400B5 allows selection of an 8-bit (512K x 8) or 16-bit (256K x 16) data bus for reading and writ- ing the memory. The BYTE# pin is used to select the bus width. In the x16 configuration, control data is read or written only on the lower eight bits (DQ0– DQ7). Data written to the memory array utilizes all active data pins for the selected configuration. When the x8 configuration is selected, data is written in byte form; when the x16 configuration is selected, data is written in word form. Internal State Machine (ISM) Block erase and byte/word write timing are simpli- fied with an ISM that controls all erase and write algo- rithms in the memory array. The ISM ensures protection against overerasure and optimizes write margin to each cell. During WRITE operations, the ISM automatically increments and monitors WRITE attempts, verifies write margin on each memory cell and updates the ISM status register. When BLOCK ERASE is performed, the ISM automatically overwrites the entire addressed block (eliminates overerasure), increments and moni- tors ERASE attempts, and sets bits in the ISM status register. ISM Status Register The ISM status register enables an external proces- sor to monitor the status of the ISM during WRITE and ERASE operations. Two bits of the 8-bit status register are set and cleared entirely by the ISM. These bits indi- cate whether the ISM is busy with a WRITE or ERASE task and when an ERASE has been suspended. Addi-

SMART 5 BOOT BLOCK FLASH MEMORY 4Mb Smart 5 Boot Block Flash Memory ©2002, Micron Technology Inc. MT28F004B5_3.fm - Rev. 3, Pub. 8/2002 8 tional error information is set in three other bits: V PP status, write status, and erase status. Command Execution Logic (CEL) The CEL receives and interprets commands to the device. These commands control the operation of the ISM and the read path (i.e., memory array, ID register or status register). Commands may be issued to the CEL while the ISM is active. However, there are restric- tions on what commands are allowed in this condition. See the Command Execution section for more detail. Deep Power-down Mode T o allow for maximum power conservation, the MT28F004B5 and MT28F400B5 feature a very low cur- rent, deep power-down mode. To enter this mode, the RP# pin is taken to V SS ±0.2V . In this mode, the current draw is a maximum of 20µA at 5V V CC. Entering deep power-down also clears the status register and sets the ISM to the read array mode. MEMORY ARCHITECTURE The MT28F004B5 and MT28F400B5 memory array architecture is designed to allow sections to be erased without disturbing the rest of the array. The array is divided into seven addressable blocks that vary in size and are independently erasable. When blocks rather than the entire array are erased, total device endur- ance is enhanced, as is system flexibility. Only the ERASE function is block- oriented. All READ and WRITE operations are done on a random-access basis. The boot block is protected from unintentional ERASE or WRITE operations with a hardware protec- tion circuit that requires a super-voltage be applied to RP# or that the WP# pin be driven HIGH before erasure is commenced. The boot block is intended for the core firmware required for basic system functionality. The remaining six blocks do not require that either of these two conditions be met before WRITE or ERASE opera- tions. Boot Block The hardware-protected boot block provides extra security for the most sensitive portions of the firm- ware. This 16KB block may only be erased or written when the RP# pin is at the specified boot block unlock voltage (V HH) or when the WP# pin is V IH. During a WRITE or ERASE of the boot block, the RP# pin must b e h e l d a t V HH or the WP# pin held HIGH until the ERASE or WRITE is completed. The V PP pin must be at VPPH (5V) when the boot block is written to or erased. The MT28F004B5 and MT28F400B5 are available in two configurations and top or bottom boot block. The top boot block version supports processors of the x86 variety. The bottom boot block version is intended for 680X0 and RISC applications. Figure 1 illustrates the memory address maps associated with these two ver- sions. Parameter Blocks The two 8KB parameter blocks store less sensitive and more frequently changing system parameters and also may store configuration or diagnostic coding. These blocks are enabled for erasure when the V PP pin is at V PPH. No super-voltage unlock or WP# control is required. Main Memory Blocks The four remaining blocks are general-purpose memory blocks and do not require a super-voltage on R P # o r W P # c o n t r o l t o b e e r a s e d o r w r i t t e n . T h e s e blocks are intended for code storage, ROM-resident applications or operating systems that require in-sys- tem update capability.

SMART 5 BOOT BLOCK FLASH MEMORY 4Mb Smart 5 Boot Block Flash Memory ©2002, Micron Technology Inc. MT28F004B5_3.fm - Rev. 3, Pub. 8/2002 9 Figure 1 Memory Address Maps Bottom Boot MT28F004B5/400B5xx-xxB Top Boot MT28F004B5/400B5xx-xxT 3FFFFh 30000h 2FFFFh 20000h 1FFFFh 10000h 0FFFFh 04000h 03FFFh 03000h 02FFFh 02000h 01FFFh 00000h 128KB Main Block 128KB Main Block 128KB Main Block 96KB Main Block 8KB Parameter Block 8KB Parameter Block 16KB Boot Block WORD ADDRESS 7FFFFh 60000h 5FFFFh 40000h 3FFFFh 20000h 1FFFFh 08000h 07FFFh 06000h 05FFFh 04000h 03FFFh 00000h BYTE ADDRESS 3FFFFh 3E000h 3DFFFh 3D000h 3CFFFh 3C000h 3BFFFh 30000h 2FFFFh 20000h 1FFFFh 10000h 0FFFFh 00000h 16KB Boot Block 8KB Parameter Block 8KB Parameter Block 96KB Main Block 128KB Main Block 128KB Main Block 128KB Main Block WORD ADDRESS 7FFFFh 7C000h 7BFFFh 7A000h 79FFFh 78000h 77FFFh 60000h 5FFFFh 40000h 3FFFFh 20000h 1FFFFh 00000h BYTE ADDRESS

SMART 5 BOOT BLOCK FLASH MEMORY 4Mb Smart 5 Boot Block Flash Memory ©2002, Micron Technology Inc. MT28F004B5_3.fm - Rev. 3, Pub. 8/2002 10 OUTPUT (READ) OPERATIONS The MT28F004B5 and MT28F400B5 feature three different types of READS. Depending on the current mode of the device, a READ operation produces data from the memory array , status register or device iden- tification register. In each of these three cases, the WE#, CE# and OE# inputs are controlled in a similar manner. Moving between modes to perform a specific read is described in the Command Execution section. Memory Array To read the memory array, WE# must be HIGH, and OE# and CE# must be LOW . Valid data is output on the DQ pins when these conditions have been met and a valid address is given. Valid data remains on the DQ pins until the address changes, or until OE# or CE# goes HIGH, whiche ver occurs first. The D Q pins con- tinue to output new data after each address transition as long as OE# and CE# remain LOW. The MT28F400B5 features selectable bus widths. When the memory array is accessed as a 256K x 16, BYTE# is HIGH, and data will be output on DQ0– DQ15. To access the memory array as a 512K x 8, BYTE# must be LOW, DQ8–DQ14 are High-Z, and all data is output on DQ0–DQ7. The DQ15/(A - 1) pin becomes the lowest order address input so that 524,288 locations can be read. After power-up or RESET , the device is automati- cally in the array read mode. All commands and their operations are described in the Command Set and Command Execution sections. Status Register P e r f o r m i n g a R E A D o f t h e s t a t u s r e g i s t e r r e q u i r e s the same input sequencing as a READ of the array except that the address inputs are “Don’t Care.” The status register contents are always output on DQ0– DQ7, regardless of the condition of BYTE# on the MT28F400B5. DQ8–DQ15 are LOW when BYTE# is HIGH, and DQ8–DQ14 are High-Z when BYTE# is L O W . D a t a f r o m t h e s t a t u s r e g i s t e r i s l a t c h e d o n t h e falling edge of OE# or CE#, whichever occurs last. If the contents of the status register change during a READ of the status register, either OE# or CE# may be toggled while the other is held LOW to update the output. Following a WRITE or ERASE, the device automati- cally enters the status register read mode. In addition, a READ during a WRITE or ERASE produces the status register contents on DQ0–DQ7. When the device is in the erase suspend mode, a READ operation produces the status register contents until another command is issued, while in certain other modes, READ STATUS REGISTER may be given to return to the status register read mode. All commands and their operations are described in the Command Set and Command Execu- tion sections. Identification Registers A READ of the two 8-bit device identification regis- ters requires the same input sequencing as a READ of the array. WE# must be HIGH, and OE# and CE# must b e L O W . H o w e v e r , I D r e g i s t e r d a t a i s o u t p u t o n l y o n DQ0–DQ7, regardless of the condition of BYTE# on the MT28F400B5. A0 is used to decode between the two bytes of the device ID register; all other address inputs are “Don’t Care.” When A0 is LOW, the manufacturer compatibility ID is output, and when A0 is HIGH, the device ID is output. DQ8–DQ15 are High-Z when BYTE# is LOW. When BYTE# is HIGH, DQ8–DQ15 are 00h when the manufacturer compatibility ID is read and 44h when the device ID is read. T o get to the identification register read mode, READ IDENTIFICATION may be issued while the device is in certain other modes. In addition, the iden- tification register read mode can be reached by apply- ing a super-voltage (V ID) to the A9 pin. Using this method, the ID register can be read while the device is i n a n y m o d e . W h e n A 9 i s r e t u r n e d t o V IL or V IH, the device returns to the previous mode. INPUT OPERATIONS The DQ pins are used either to input data to the array or to input a command to the CEL. A command input issues an 8-bit command to the CEL to control the mode of operation of the device. A WRITE is used to input data to the memory array. The following sec- tion describes both types of inputs. More information describing how to use the two types of inputs to write or erase the device is provided in the Command Execu- tion section. Commands T o perform a command input, OE# must be HIGH, and CE# and WE# must be LOW . Addresses are “Don’t Care” but must be held stable, except during an ERASE CONFIRM (described in a later section). The 8-bit command is input on DQ0–DQ7, while DQ8–DQ15 are “Don’t Care” on the MT28F400B5. The command is latched on the rising edge of CE# (CE#-controlled) or WE# (WE#-controlled), whichever occurs first. The condition of BYTE# on the MT28F400B5 has no effect on a command input.

SMART 5 BOOT BLOCK FLASH MEMORY 4Mb Smart 5 Boot Block Flash Memory ©2002, Micron Technology Inc. MT28F004B5_3.fm - Rev. 3, Pub. 8/2002 11 Memory Array A WRITE to the memory array sets the desired bits to logic 0s but cannot change a given bit to a logic 1 from a logic 0. Setting any bits to a logic 1 requires that the entire block be erased. To perform a WRITE, OE# must be HIGH, CE# and WE# must be LOW, and V PP must be set to V PPH. Writing to the boot block also requires that the RP# pin be at V HH or WP# be HIGH. A0–A17/(A18) provide the address to be written, while the data to be written to the array is input on the DQ pins. The data and addresses are latched on the rising edge of CE# (CE#-controlled) or WE# (WE#-con- trolled), whichever occurs first. A WRITE must be pre- ceded by a WRITE SETUP command. Details on how to input data to the array are described in the Write Sequence section. Selectable bus sizing applies to WRITEs as it does to READs on the MT28F400B5. When BYTE# is LOW (byte mode), data is input on DQ0–DQ7, DQ8–DQ14 are High-Z and DQ15 becomes the lowest order address input. When BYTE# is HIGH (word mode), data is input on DQ0–DQ15. COMMAND SET To simplify writing of the memory blocks, the MT28F004B5 and MT28F400B5 incorporate an ISM that controls all internal algorithms for the WRITE and ERASE cycles. An 8-bit command set is used to control the device. Details on how to sequence commands are provided in the Command Execution section. Table 1 lists the valid commands. Table 1: Command Set COMMAND HEX CODE DESCRIPTION RESERVED 00h This command and all unlisted commands are invalid and should not be called. These commands are reserved to allow for future feature enhancements. READ ARRAY FFh Must be issued after any other command cycle before the array can be read. It is not necessary to issue this command after power-up or RESET. IDENTIFY DEVICE 90h Allows the device ID and manufacturer compatibility ID to be read. A0 is used to decode between the manufacturer compatibility ID (A0 = LOW) and device ID (A0 = HIGH). READ STATUS REGISTER 70h Allows the status register to be read. Please refer to Table 2 for more information on the status register bits. CLEAR STATUS REGISTER 50h Clears status register bits 3–5, which cannot be cleared by the ISM. ERASE SETUP 20h The first command given in the two-cycle ERASE sequence. The ERASE is not completed unless followed by ERASE CONFIRM. ERASE CONFIRM/RESUME D0h The second command given in the two-cycle ERASE sequence. Must follow an ERASE SETUP command to be valid. Also used during an ERASE SUSPEND to resume the ERASE. WRITE SETUP 40h or 10h The first command given in the two-cycle WRITE sequence. The write data and address are given in the following cycle to complete the WRITE. ERASE SUSPEND B0h Requests a halt of the ERASE and puts the device into the erase suspend mode. When the device is in this mode, only READ STATUS REGISTER, READ ARRAY and ERASE RESUME commands may be executed.

SMART 5 BOOT BLOCK FLASH MEMORY 4Mb Smart 5 Boot Block Flash Memory ©2002, Micron Technology Inc. MT28F004B5_3.fm - Rev. 3, Pub. 8/2002 12 ISM STATUS REGISTER The 8-bit ISM status register (see Table 2) is polled to check for WRITE or ERASE completion or any related errors. During or following a WRITE, ERASE or ERASE SUSPEND, a READ operation outputs the sta- tus register contents on DQ0–DQ7 without prior com- mand. While the status register contents are read, the outputs are not updated if there is a change in the ISM status unless OE# or CE# is toggled. If the device is not in the write, erase, erase suspend or status register read mode, READ STATUS REGISTER (70h) can be issued to view the status register contents. All of the defined bits are set by the ISM, but only the ISM and erase suspend status bits are reset by the ISM. The erase, write and V PP status bits must be cleared using CLEAR STATUS REGISTER. If the Vpp status bit (SR3) is set, the CEL does not allow further WRITE or ERASE operations until the status register is cleared. This enables the user to choose when to poll and clear the status register. For example, the host sys- tem may perform multiple BYTE WRITE operations before checking the status register instead of checking after each individual WRITE. Asserting the RP# signal or powering down the device also clears the status register. Table 2: Status Register STATUS BIT # STATUS REGISTER BIT DESCRIPTION SR7 ISM STATUS 1 = Ready 0 = Busy The ISMS bit displays the active status of the state machine during WRITE or BLOCK ERASE operations. The controlling logic polls this bit to determine when the erase and write status bits are valid. SR6 ERASE SUSPEND STATUS 1 = ERASE suspended 0 = ERASE in progress/completed Issuing an ERASE SUSPEND places the ISM in the suspend mode and sets this and the ISMS bit to “1.” The ESS bit remains “1” until an ERASE RESUME is issued. SR5 ERASE STATUS 1 = BLOCK ERASE error 0 = Successful BLOCK ERASE ES is set to “1” after the maximum number of ERASE cycles is executed by the ISM without a successful verify. ES is only cleared by a CLEAR STATUS REGISTER command or after a RESET. SR4 WRITE STATUS 1 = WORD/BYTE WRITE error 0 = Successful WORD/BYTE WRITE WS is set to “1” after the maximum number of WRITE cycles is executed by the ISM without a successful verify. WS is only cleared by a CLEAR STATUS REGISTER command or after a RESET. SR3 V PP STATUS 1 = No VPP voltage detected 0 = VPP present VPPS detects the presence of a VPP voltage. It does not monitor VPP continuously, nor does it indicate a valid VPP voltage. The VPP pin is sampled for 5V after WRITE or ERASE CONFIRM is given. VPPS must be cleared by CLEAR STATUS REGISTER or by a RESET. SR0-2 RESERVED Reserved for future use.

SMART 5 BOOT BLOCK FLASH MEMORY 4Mb Smart 5 Boot Block Flash Memory ©2002, Micron Technology Inc. MT28F004B5_3.fm - Rev. 3, Pub. 8/2002 13 COMMAND EXECUTION Commands are issued to bring the device into dif- ferent operational modes. Each mode allows specific operations to be performed. Several modes require a s e q u e n c e o f c o m m a n d s t o b e w r i t t e n b e f o r e t h e y a r e reached. The following section describes the proper- ties of each mode, and Table 3 lists all command sequences required to perform the desired operation. Read Array The array read mode is the initial state of the device upon power-up and after a RESET . If the device is in any other mode, READ ARRAY (FFh) must be given to return to the array read mode. Unlike the WRITE SETUP command (40h), READ ARRAY does not need to be given before each individual read access. Identify Device IDENTIFY DEVICE (90h) may be written to the CEL to enter the identify device mode. While the device is in this mode, any READ produces the device ID when A0 is HIGH and manufacturer compatibility ID when A 0 i s L O W . T h e d e v i c e r e m a i n s i n t h i s m o d e u n t i l another command is given. WRITE Sequence T wo consecutive cycles are needed to write data to the array. WRITE SETUP (40h or 10h) is given in the first cycle. The next cycle is the WRITE, during which the write address and data are issued and V PP is brought to V PPH. Writing to the boot block also requires that the RP# pin be brought to VHH or that the WP# pin be brought HIGH at the same time V PP IS brought to V PPH. The ISM will now begin to write the word or byte. V PP must be held at V PPH until the write is completed (SR7 = 1). While the ISM executes the WRITE, the ISM status bit (SR7) is at “0,” and the device does not respond to any commands. Any READ operation produces the s t a t u s r e g i s t e r c o n t e n t s o n D Q 0 – D Q 7 . W h e n t h e I S M status bit (SR7) is set to a logic 1, the write is complete, and the device goes into the status register read mode until another command is given. After the ISM has initiated the WRITE, it cannot be aborted except by a RESET or by powering down the part. Doing either during a WRITE corrupts the data being written. If only the WRITE SETUP command has been given, the WRITE may be nullified by performing a null WRITE. T o execute a null WRITE, FFh must be written when BYTE# is LOW , or FFFFh must be written when BYTE# is HIGH. When the ISM status bit (SR7) is set, the device is in the status register read mode until another command is issued. Notes: 1. Must follow WRITE or ERASE CONFIRM commands to the CEL to enable Flash array READ cycles. 2. IA = Identify Address: 00h for manufacturer compatibility ID; 01h for device ID. 3. ID = Identify Data. 4. SRD = Status Register Data. 5. On x16 (X00) devices BA = Block Address (A12–A17), on x8 (00X) devices BA = Block Address (A13–A18). 6. Addresses are “Don’t Care” in first cycle but must be held stable. 7. WA = Address to be written; WD = Data to be written to WA. Table 3: Command Sequences COMMANDS BUS CYCLES REQ’D FIRST CYCLE SECOND CYCLE NOTESOPERATION ADDRESS DATA OPERATION ADDRESS DATA READ ARRAY 1 WRITE X FFh 1 IDENTIFY DEVICE 3 WRITE X 90h READ IA ID 2, 3 READ STATUS REGISTER 2 WRITE X 70h READ X SRD 4 CLEAR STATUS REGISTER 1 WRITE X 50h ERASE SETUP/CONFIRM 2 WRITE X 20h WRITE BA D0h 5, 6 ERASE SUSPEND/RESUME 2 WRITE X B0h WRITE X D0h WRITE SETUP/WRITE 2 WRITE X 40h WRITE WA WD 6, 7 ALTERNATE WORD/BYTE WRITE

2 WRITE X 10h WRITE WA WD 6, 7

SMART 5 BOOT BLOCK FLASH MEMORY 4Mb Smart 5 Boot Block Flash Memory ©2002, Micron Technology Inc. MT28F004B5_3.fm - Rev. 3, Pub. 8/2002 14 ERASE Sequence Executing an ERASE sequence sets all bits within a block to logic 1. The command sequence necessary to execute an ERASE is similar to that of a WRITE. To pro- vide added security against accidental block erasure, two consecutive command cycles are required to ini- tiate an ERASE of a block. In the first cycle , addr esses ar e “ Don ’ t C ar e , ” and ERASE SETUP (20h) is giv en. I n the second cycle, V PP must be brought to V PPH, an address within the block to be erased must be issued, and ERASE CONFIRM (D0 H) must be given. If a com- mand other than ERASE CONFIRM is given, the write and erase status bits (SR4 and SR5) are set, and the device is in the status register read mode. After the ERASE CONFIRM (D0h) is issued, the ISM starts the ERASE of the addressed block. Any READ operation outputs the status register contents on DQ0–DQ7. V PP must be held at VPPH until the ERASE is completed (SR7 = 1). When the ERASE is completed, the device is in the status register read mode until another command is issued. Erasing the boot block also requires that either the RP# pin be set to V HH or the WP# pin be held HIGH at the same time V PP is set to VPPH. ERASE Suspension The only command that may be issued while an ERASE is in progress is ERASE SUSPEND. This com- mand enables other commands to be executed while pausing the ERASE in progress. When the device has reached the erase suspend mode, the erase suspend status bit (SR6) and ISM status bit (SR7) is set. The device may now be given a READ ARRAY, ERASE RESUME or READ STATUS REGISTER command. After READ ARRAY has been issued, any location not within the block being erased may be read. If ERASE RESUME is issued before SR6 has been set, the device immedi- ately proceeds with the ERASE in progress. ERROR HANDLING After the ISM status bit (SR7) has been set, the V PP (SR3), write (SR4) and erase (SR5) status bits may be checked. If one or a combination of these three bits has been set, an error has occurred. The ISM cannot reset these three bits. To clear these bits, CLEAR STA- TUS REGISTER (50 H) must be giv en. If the V PP status bit (SR3) is set, further WRITE or ERASE operations cannot resume until the status register is cleared. Table 4 lists the combination of errors. Notes: 1. SR3–SR5 must be cleared using CLEAR STATUS REGISTER. Table 4: Status Register Error Decode 1 STATUS BITS ERROR DESCRIPTION SR5 SR4 SR3

000 No errors

001 VPP voltage error

010 WRITE error

011 WRITE error, VPP voltage not valid at time of WRITE

100 ERASE error

101 ERASE error, VPP voltage not valid at time of ERASE CONFIRM

110 Command sequencing error or WRITE/ERASE error

111 Command sequencing error, VPP voltage error, with WRITE and ERASE errors

SMART 5 BOOT BLOCK FLASH MEMORY 4Mb Smart 5 Boot Block Flash Memory ©2002, Micron Technology Inc. MT28F004B5_3.fm - Rev. 3, Pub. 8/2002 15 WRITE/ERASE CYCLE ENDURANCE The MT28F004B5 and MT28F400B5 are designed and fabricated to meet advanced firmware storage requirements. To ensure this level of reliability, V PP m u s t b e a t 5 V ± 1 0 % d u r i n g W R I T E o r E R A S E c y c l e s . Due to process technology advances, 5V V PP is optimal for application and production programming. POWER USAGE The MT28F004B5 and MT28F400B5 offer several power-saving features that may be utilized in the array read mode to conserve power. Deep power-down mode is enabled by bringing RP# LOW . Current draw CC) in this mode is a maximum of 20µA at 5V V CC. When CE# is HIGH, the device enters standby mode. In this mode, maximum I CC current is 130µA at 5V . If CE# is brought HIGH during a WRITE or ERASE, the ISM continues to operate, and the device consumes the respective active power until the WRITE or ERASE is completed. POWER-UP The likelihood of unwanted WRITE or ERASE opera- tions is minimized because two consecutive cycles are required to execute either operation. However, to reset the ISM and to provide additional protection while V CC is ramping, one of the following conditions must be met: R P # m u s t b e h e l d L O W u n t i l V CC is at valid func- tional level; or  CE# or WE# may be held HIGH and RP# must be toggled from VCC-GND-VCC. After a power-up or RESET , the status register is reset, and the device enters the array read mode. Figure 2: Power-Up/Reset Timing Diagram VALID VALID VCC (5V) Data Address UNDEFINED t Note 1 RP# RWH tAA NOTE: 1. VCC must be within the valid operating range before RP# goes HIGH.

SMART 5 BOOT BLOCK FLASH MEMORY 4Mb Smart 5 Boot Block Flash Memory ©2002, Micron Technology Inc. MT28F004B5_3.fm - Rev. 3, Pub. 8/2002 16 Self-Timed WRITE Sequence (WORD or BYTE WRITE)1 Complete WRITE STATUS-CHECK Sequence Notes: 1. Sequence may be repeated for additional BYTE or WORD WRITEs. 2. Complete status check is not required. However, if SR3 = 1, further WRITEs are inhibited until the status register is cleared. 3. Device will be in status register read mode. To return to the array read mode, the FFh command must be issued. 4. If SR3 is set during a WRITE or BLOCK ERASE attempt, CLEAR STATUS REGISTER must be issued before further WRITE or ERASE operations are allowed by the CEL. 5. Status register bits 3-5 must be cleared using CLEAR STATUS REGISTER. YES NO WRITE 40h or 10h VPP = 5V Start WRITE Word or Byte Address/Data STATUS REGISTER READ SR7 = 1? Complete Status Check (optional) WRITE Complete 3 NO Start (WRITE completed) YES SR4 = 0? SR3 = 0? NO YES BYTE/WORD WRITE Error5 WRITE Successful V ErrorPP 4, 5

SMART 5 BOOT BLOCK FLASH MEMORY 4Mb Smart 5 Boot Block Flash Memory ©2002, Micron Technology Inc. MT28F004B5_3.fm - Rev. 3, Pub. 8/2002 17 Self-Timed BLOCK ERASE Sequence1 Complete BLOCK ERASE STATUS-CHECK Sequence Notes: 1. Sequence may be repeated to erase additional blocks. 2. Complete status check is not required. However, if SR3 = 1, further ERASEs are inhibited until the status register is cleared. 3. To return to the array read mode, the FFh command must be issued. 4. Refer to the ERASE SUSPEND flowchart for more information. 5. If SR3 is set during a WRITE or BLOCK ERASE attempt, CLEAR STATUS REGISTER must be issued before further WRITE or ERASE operations are allowed by the CEL. 6. Status register bits 3-5 must be cleared using CLEAR STATUS REGISTER. YES NO VPP = 5V Complete Status Check (optional) ERASE Complete NO YES Suspend ERASE? STATUS REGISTER READ SR7 = 1? WRITE 20h Start WRITE D0h, Block Address Suspend Sequence ERASE Resumed ERASE Busy NO Start (ERASE completed) YES SR4, 5 = 1? SR3 = 0? YES YES Command Sequence Error SR5 = 0? NO NO V ErrorPP BLOCK ERASE Error 5, 6 ERASE Successful

SMART 5 BOOT BLOCK FLASH MEMORY 4Mb Smart 5 Boot Block Flash Memory ©2002, Micron Technology Inc. MT28F004B5_3.fm - Rev. 3, Pub. 8/2002 18 ERASE SUSPEND/RESUME Sequence NO WRITE B0h (ERASE SUSPEND) Start (ERASE in progress) WRITE FFh (READ ARRAY) STATUS REGISTER READ YES SR6 = 1? SR7 = 1? NO YES NO YES Done Reading? WRITE D0h (ERASE RESUME) Resume ERASE ERASE Completed VPP = 5V

SMART 5 BOOT BLOCK FLASH MEMORY 4Mb Smart 5 Boot Block Flash Memory ©2002, Micron Technology Inc. MT28F004B5_3.fm - Rev. 3, Pub. 8/2002 19 ABSOLUTE MAXIMUM RATINGS* RP# or A9 Pin Voltage *Stresses greater than those listed under “ Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other condi- tions above those indicated in the operational sections of this specification is not implied. Exposure to abso- lute maximum rating conditions for extended periods may affect reliability. **V CC, input and I/O pins may transition to -2V for <20ns and VCC + 2V for <20ns. †Voltage may pulse to -2V for <20ns and 14V for <20ns. Notes: 1. All voltages referenced to VSS. ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC READ OPERATING CONDITIONS Commercial Temperature (0ºC /g163 TA /g163 +70ºC) and Extended Temperature (-40ºC /g163 TA /g163 +85ºC) PARAMETER/CONDITION SYMBOL MIN MAX UNITS NOTES 5V Supply Voltage VCC 4.5 5.5 V 1 Input High (Logic 1) Voltage, all inputs VIH 2V CC + 0.5 V 1 Input Low (Logic 0) Voltage, all inputs VIL -0.5 0.8 V 1 Device Identification Voltage, A9 VID 10 12.6 V 1 VPP Supply Voltage VPP -0.5 5.5 V 1 DC OPERATING CHARACTERISTICS Commercial Temperature (0ºC /g163 TA /g163 +70ºC) and Extended Temperature (-40ºC /g163 TA /g163 +85ºC) PARAMETER/CONDITION SYMBOL MIN MAX UNITS NOTES OUTPUT VOLTAGE LEVELS (TTL) Output High Voltage (IOH = -2.5mA) Output Low Voltage (IOL = 5.8mA) VOH1 2.4 – V VOL –0 . 5 0 V 1 OUTPUT VOLTAGE LEVELS (CMOS) Output High Voltage (IOH = -100µA) VOH2 VCC - 0.4 – V 1 INPUT LEAKAGE CURRENT Any input (0V /g163 VIN /g163 VCC); All other pins not under test = 0V IL -1 1 µA INPUT LEAKAGE CURRENT: VHH INPUT (10V /g163 VHH /g163 12.6V = VID) IID – 500 µA INPUT LEAKAGE CURRENT: RP# INPUT (10V /g163 RP# /g163 12.6V = VHH) IHH – 500 µA OUTPUT LEAKAGE CURRENT (DOUT is disabled; 0V /g163 VOUT /g163 VCC) IOZ -10 10 µA

SMART 5 BOOT BLOCK FLASH MEMORY 4Mb Smart 5 Boot Block Flash Memory ©2002, Micron Technology Inc. MT28F004B5_3.fm - Rev. 3, Pub. 8/2002 20 Notes: 1. Vcc = MAX during Icc tests. 2. Icc is dependent on cycle rates. 3. Icc is dependent on output loading. Specified values are obtained with the outputs open. CAPACITANCE (TA = +25ºC; f = 1 MHz) PARAMETER/CONDITION SYMBOL MAX UNITS Input Capacitance C I 9p F Output Capacitance C O 12 pF READ AND STANDBY CURRENT DRAIN (Note: 1) Commercial Temperature (0ºC /g163 TA /g163 +70ºC) and Extended Temperature (-40ºC /g163 TA /g163 +85ºC) PARAMETER/CONDITION SYMBOL MAX UNITS NOTES READ CURRENT: WORD-WIDE, TTL INPUT LEVELS (CE# = VIL; OE# = VIH; f = 10 MHz; Other inputs = VIL or VIH; RP# = VIH) ICC1 55 mA 2, 3 READ CURRENT: WORD-WIDE, CMOS INPUT LEVELS (CE# /g163 0.2V; OE# /g179 VCC - 0.2V; f = 10 MHz; Other inputs /g163 0.2V or /g179 VCC - 0.2V; RP# /g179 VCC - 0.2V) ICC2 50 mA 2, 3 READ CURRENT: BYTE-WIDE, TTL INPUT LEVELS (CE# = VIL; OE# = VIH; f = 10 MHz; Other inputs = VIL or VIH; RP# = VIH) ICC3 55 mA 2, 3 READ CURRENT: BYTE-WIDE, CMOS INPUT LEVELS (CE# /g163 0.2V; OE# /g179 VCC - 0.2V; f = 10 MHz; Other inputs /g163 0.2V or /g179 VCC - 0.2V; RP# = VCC - 0.2V) ICC4 50 mA 2, 3 STANDBY CURRENT: TTL INPUT LEVELS VCC power supply standby current (CE# = RP# = VIH; Other inputs = VIL or VIH) ICC5 2m A STANDBY CURRENT: CMOS INPUT LEVELS VCC power supply standby current (CE# = RP# = VCC - 0.2V) ICC6 130 µA DEEP POWER-DOWN CURRENT: VCC SUPPLY (RP# = VSS ±0.2V) ICC8 20 µA STANDBY OR READ CURRENT: VPP SUPPLY (VPP /g163 5.5V) IPP1 ±15 µA DEEP POWER-DOWN CURRENT: VPP SUPPLY (RP# = VSS ±0.2V) IPP2 5µ A

SMART 5 BOOT BLOCK FLASH MEMORY 4Mb Smart 5 Boot Block Flash Memory ©2002, Micron Technology Inc. MT28F004B5_3.fm - Rev. 3, Pub. 8/2002 21 Notes: 1. OE# may be delayed by tACE - tAOE after CE# falls before tACE is affected. READ TIMING PARAMETERS ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS Commercial Temperature (0ºC /g163 TA /g163 +70ºC) and Extended Temperature (-40ºC /g163 TA /g163 +85ºC); VCC = +5V ±10% AC CHARACTERISTICS -8/-8 ET PARAMETER SYMBOL MIN MAX UNITS NOTES Read cycle time tRC 80 ns Access time from CE# tACE 80 ns 1 Access time from OE# tAOE 40 ns 1 Access time from address tAA 80 ns RP# HIGH to output valid delay tRWH 1,000 ns OE# or CE# HIGH to output in High-Z tOD 20 ns Output hold time from OE#, CE# or address change tOH 0 ns RP# LOW pulse width tRP 60 ns

SMART 5 BOOT BLOCK FLASH MEMORY 4Mb Smart 5 Boot Block Flash Memory ©2002, Micron Technology Inc. MT28F004B5_3.fm - Rev. 3, Pub. 8/2002 22 AC TEST CONDITIONS L = 100pF WORD-WIDE READ CYCLE1 TIMING PARAMETERS Commercial Temperature (0ºC /g163 TA /g163 +70ºC) Extended Temperature (-40ºC /g163 TA /g163 +85ºC) Notes: 1. BYTE# = HIGH (MT28F400B5 only). SYMBOL -8/-8 ET UNITS SYMBOL -8/-8 ET UNITSMIN MAX MIN MAX tRC 80 ns tRWH 1,000 ns tACE 80 ns tOD 20 ns tAOE 40 ns tOH 0n s tAA 80 ns VALID DATA VALID ADDRESS CE# A0–A17/(A18) OE# DQ0–DQ15 tRC tACE tAOE tOD tOH tAA WE# RP# VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL tRWH DON’T CARE UNDEFINED

SMART 5 BOOT BLOCK FLASH MEMORY 4Mb Smart 5 Boot Block Flash Memory ©2002, Micron Technology Inc. MT28F004B5_3.fm - Rev. 3, Pub. 8/2002 23 BYTE-WIDE READ CYCLE1 TIMING PARAMETERS Commercial Temperature (0ºC /g163 TA /g163 +70ºC) Extended Temperature (-40ºC /g163 TA/g163 +85ºC) Notes: 1. BYTE# = LOW (MT28F400B5 only). SYMBOL -8/-8 ET UNITS SYMBOL -8/-8 ET UNITSMIN MAX MIN MAX tRC 80 ns tRWH 1,000 ns tACE 80 ns tOD 20 ns tAOE 40 ns tOH 0n s tAA 80 ns VALID DATA VALID ADDRESS CE# (A - 1)-A17/(A18) OE# DQ0-DQ7 DON’T CARE UNDEFINED tRC tACE tAOE tOD tOH tAA WE# RP# VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL tRWH DQ8-DQ14 VIH VIL HIGH-Z

SMART 5 BOOT BLOCK FLASH MEMORY 4Mb Smart 5 Boot Block Flash Memory ©2002, Micron Technology Inc. MT28F004B5_3.fm - Rev. 3, Pub. 8/2002 24 Notes: 1. WRITE operations are tested at VCC/VPP voltages equal to or less than the previous ERASE, and READ operations are tested at VCC voltages equal to or less than the previous WRITE. 2. Absolute WRITE/ERASE protection when VPP /g163 VPPLK. 3. When 5V VCC and VPP are used, VCC cannot exceed VPP by more than 500mV during WRITE and ERASE operations. 4. Applies to MT28F400B5 only. 5. Applies to MT28F004B5 and MT28F400B5 with BYTE = LOW. 6. Parameter is specified when device is not accessed. Actual current draw will be ICC12 (5V VCC) plus read current if a READ is executed while the device is in erase suspend mode. RECOMMENDED DC WRITE/ERASE CONDITIONS1 Commercial Temperature (0ºC /g163 TA /g163 +70ºC) and Extended Temperature (-40ºC /g163 TA /g163 +85ºC); VCC = +5V ±10% PARAMETER/CONDITION SYMBOL MIN MAX UNITS NOTES VPP WRITE/ERASE lockout voltage VPPLK –1 . 5V 2 VPP voltage during WRITE/ERASE operation VPPH 4.5 5.5 V 3 Boot block unlock voltage VHH 10 12.6 V VCC WRITE/ERASE lockout voltage VLKO 2–V WRITE/ERASE CURRENT DRAIN Commercial Temperature (0ºC /g163 TA /g163 +70ºC) and Extended Temperature (-40ºC /g163 TA /g163 +85ºC); VCC = +5V ±10% PARAMETER/CONDITION SYMBOL MAX UNITS NOTES WORD WRITE CURRENT: VCC SUPPLY ICC9 25 mA 4 WORD WRITE CURRENT: VPP SUPPLY IPP4 20 mA 4 BYTE WRITE CURRENT: VCC SUPPLY ICC10 25 mA 5 BYTE WRITE CURRENT: VPP SUPPLY IPP5 20 mA 5 ERASE CURRENT: VCC SUPPLY ICC11 30 mA ERASE CURRENT: VPP SUPPLY IPP6 40 mA ERASE SUSPEND CURRENT: VCC SUPPLY (ERASE suspended) ICC12 10 mA 6 ERASE SUSPEND CURRENT: VPP SUPPLY (ERASE suspended) IPP7 200 µA

SMART 5 BOOT BLOCK FLASH MEMORY 4Mb Smart 5 Boot Block Flash Memory ©2002, Micron Technology Inc. MT28F004B5_3.fm - Rev. 3, Pub. 8/2002 25 Notes: 1. Measured with VPP = VPPH = 5V. 2. RP# should be held at VHH or WP# held HIGH until boot block WRITE or ERASE is complete. 3. WRITE/ERASE times are measured to valid status register data (SR7 = 1). 4. Polling status register before tWB is met may falsely indicate WRITE or ERASE completion. 5. tREL is required to relock boot block after WRITE or ERASE to boot block. 6. Typical values measured at TA = +25ºC. 7. Assumes no system overhead. 8. Typical WRITE times use checkerboard data pattern. SPEED-DEPENDENT WRITE/ERASE AC TIMING CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS: WE#- (CE#-)CONTROLLED WRITES Commercial Temperature (0ºC /g163 TA /g163 +70ºC) and Extended Temperature (-40ºC /g163 TA /g163 +85ºC); VCC = +5V ±10% or +5V ±5% AC CHARACTERISTICS -8/-8 ET PARAMETER SYMBOL MIN MAX UNITS NOTES WRITE cycle time tWC 80 ns WE# HIGH pulse width tWPH (tCPH) 30 ns WE# pulse width tWP (tCP) 50 ns Address setup time to WE# HIGH tAS 50 ns Address hold time from WE# HIGH tAH 0n s Data setup time to WE# HIGH tDS 50 ns Data hold time from WE# HIGH tDH 0n s CE# setup time to WE# LOW tCS (tWS) 0n s CE# hold time from WE# HIGH tCH (tWH) 0n s VPP setup time to WE# HIGH tVPS1 200 ns 1 RP# HIGH to WE# LOW delay tRS 1,000 ns RP# at VHH or WP# HIGH setup time to WE# HIGH tRHS 100 ns 2 WRITE duration (WORD or BYTE WRITE) tWED1 4.5 µs 3 Boot BLOCK ERASE duration tWED2 100 ms 2, 3 Parameter BLOCK ERASE duration tWED3 100 ms 3 Main BLOCK ERASE duration tWED4 500 ms 3 WE# HIGH to busy status (SR7 = 0) tWB 200 ns 4 VPP hold time from status data valid tVPH 0n s 3 RP# at VHH or WP# HIGH hold time from status data valid tRHH 0n s 2 Boot block relock delay time tREL 100 ns 5 WORD/BYTE WRITE AND ERASE DURATION CHARACTERISTICS PARAMETER TYP MAX UNITS NOTES Boot/parameter BLOCK ERASE time 0.5 7 s 6 Main BLOCK ERASE time 1.5 14 s 6 Main BLOCK WRITE time (byte mode) 1–s 6 , 7 , 8 Main BLOCK WRITE time (word mode) 1–s 6 , 7 , 8

SMART 5 BOOT BLOCK FLASH MEMORY 4Mb Smart 5 Boot Block Flash Memory ©2002, Micron Technology Inc. MT28F004B5_3.fm - Rev. 3, Pub. 8/2002 26 WRITE/ERASE CYCLE WE#-CONTROLLED WRITE/ERASE TIMING PARAMETERS Commercial Temperature (0ºC /g163 TA /g163 +70ºC) Extended Temperature (-40ºC /g163 TA/g163 +85ºC) Notes: 1. Address inputs are “Don’t Care” but must be held stable. 2. If BYTE# is LOW, data and command are 8-bit. If BYTE# is HIGH, data is 16-bit and command is 8-bit (MT28F400B5 only). SYMBOL -8/-8 ET UNITS SYMBOL -8/-8 ET UNITSMIN MAX MIN MAX tWC4 80 ns tRS 1,000 ns tWPH4 30 ns tRHS 100 ns tWP4 50 ns tWED1 4.5 µs tAS 50 ns tWED2 100 ms tAH 0n s tWED3 100 ms tDS 50 ns tWED4 500 ms tDH 0n s tWB 200 ns tCS 0n s tVPH 0n s tCH 0n s tRHH 0n s tVPS1 200 ns DON’T CARE tWC tWED1/2/3/4 tRS AIN Status (SR7=1) tCHtCS [Unlock boot block] tRHS tVPH tAS tAH tWP tWPH tDS tDH CMD in tRHH CMD/ Data-in CMD in WRITE SETUP or ERASE SETUP input WRITE or ERASE (block) address asserted, and WRITE data or ERASE CONFIRM issued WRITE or ERASE executed, status register checked for completion Command for next operation issued tDH tDS [Unlock boot block] tVPS1 Note 1 tAS tAH Status (SR7=0) tWB CE# A0–A17/(A18) OE# DQ0–DQ7/ DQ0–DQ15 2 WE# RP# 3 VIH VIL VPP VHH VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL WP# 3 VIH VIL VIL VPPH VPPLK [5V VPP]

SMART 5 BOOT BLOCK FLASH MEMORY 4Mb Smart 5 Boot Block Flash Memory ©2002, Micron Technology Inc. MT28F004B5_3.fm - Rev. 3, Pub. 8/2002 27 3. Either RP# at VHH or WP# HIGH unlocks the boot block. 4. Measurements tested under AC Test Condition 1, VCC = 5V ±10%.

SMART 5 BOOT BLOCK FLASH MEMORY 4Mb Smart 5 Boot Block Flash Memory ©2002, Micron Technology Inc. MT28F004B5_3.fm - Rev. 3, Pub. 8/2002 28 WRITE/ERASE CYCLE CE#-CONTROLLED WRITE/ERASE TIMING PARAMETERS Commercial Temperature (0ºC /g163 TA /g163 +70ºC) Extended Temperature (-40ºC /g163 TA/g163 +85ºC) Notes: 1. Address inputs are “Don’t Care” but must be held stable. 2. If BYTE# is LOW, data and command are 8-bit. If BYTE# is HIGH, data is 16-bit and command is 8-bit (MT28F400B5 only). 3. Either RP# at VHH or WP# HIGH unlocks the boot block. SYMBOL -8/-8 ET UNITS SYMBOL -8/-8 ET UNITSMIN MAX MIN MAX tWC4 80 ns tRS 1,000 ns tWPH4 30 ns tRHS 100 ns tWP4 50 ns tWED1 4.5 µs tAS 50 ns tWED2 100 ms tAH 0n s tWED3 100 ms tDS 50 ns tWED4 500 ms tDH 0n s tWB 200 ns tCS 0n s tVPH 0n s tCH 0n s tRHH 0n s tVPS1 200 ns DON’T CARE tWC tWED1/2/3/4 tRS AIN Status (SR7=1) tWHtWS [Unlock boot block] tRHS tVPH tAS tAH tCP tCPH tDS tDH CMD in tRHH CMD/ Data-in CMD in WRITE SETUP or ERASE SETUP input WRITE or ERASE (block) address asserted, and WRITE data or ERASE CONFIRM issued WRITE or ERASE executed, status register checked for completion Command for next operation issued tDHtDS [5V VPP] [Unlock boot block] tVPS1 Note 1 tAS tAH Status (SR7=0) tWB WE# A0–A17/(A18) OE# DQ0–DQ7/ DQ0–DQ15 2 CE# RP# 3 VIH VIL VPP VIH VIL VHH VIH VIL VIH VIL VIH VIL VIH VIL WP# 3 VIH VIL VIL VPPH VPPLK

SMART 5 BOOT BLOCK FLASH MEMORY 4Mb Smart 5 Boot Block Flash Memory ©2002, Micron Technology Inc. MT28F004B5_3.fm - Rev. 3, Pub. 8/2002 29 4. Measurements tested under AC Test Condition 1, VCC = 5V ±10%. 44-PIN PLASTIC SOP1 (600 mil) Notes: 1. Contact factory for availability 2. All dimensions in millimeters MAX/MIN or typical where noted. 3. Package width and length do not include mold protrusion; allowable mold protrusion is 0.1" per side. .016 (0.40) .010 (0.25) .066 (1.72) .020 (0.50) .015 (0.38) .007 (0.18) .005 (0.13) .004 (0.10) .643 (16.34) .620 (15.74) DETAIL A PIN #1 INDEX (ROTATED 90 CW) SEE DETAIL A GAGE PLANE .0315 (0.80) 1.113 (28.27) 1.107 (28.12) .010 (0.25) .499 (12.68) .493 (12.52) .030 (0.76) .106 (2.70) MAX .050 (1.27) TYP

SMART 5 BOOT BLOCK FLASH MEMORY 4Mb Smart 5 Boot Block Flash Memory ©2002, Micron Technology Inc. MT28F004B5_3.fm - Rev. 3, Pub. 8/2002 30 40-PIN PLASTIC TSOP I (10mm x 20mm) Notes: 1. All dimensions in millimeters MAX/MIN or typical where noted. 2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.1" per side. DETAIL A .721 (18.31) .780 (19.80) .397 (10.08) .010 (0.25) .0197 (0.50) .010 (0.25) .007 (0.18) SEE DETAIL A .795 (20.20) .727 (18.47) .006 (0.15) TYP .005 (0.13) .391 (9.93) .024 (0.60) .016 (0.40) .008 (0.20) .004 (0.10) .002 (0.05) .0315 (0.80) .047 (1.20) MAX 401 20 21 .010 (0.25) PLANE GAGE PIN #1 INDEX

SMART 5 BOOT BLOCK FLASH MEMORY 4Mb Smart 5 Boot Block Flash Memory ©2002, Micron Technology Inc. MT28F004B5_3.fm - Rev. 3, Pub. 8/2002 31 48-PIN PLASTIC TSOP I1 (12mm x 20mm) Notes: 1. All dimensions in millimeters MAX/MIN or typical where noted. 2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.1" per side. DATA SHEET DESIGNATIONS No Mark This data sheet contains minimum and maximum limits specified over the complete power supply and temperature range for production devices. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur .047 (1.20) MAX .005 (0.12) .007 (0.18) .006 (0.15) .010 (0.25) SEE DETAIL A .0197 (0.50) TYP .780 (19.80) .727 (18.47) .721 (18.31) .795 (20.20) .475 (12.07) .002 (0.05) DETAIL A .016 (0.40) .024 (0.60) .0315 (0.80) .008 (0.20) .004 (0.10) .469 (11.91) .010 (0.25) PLANE GAGE .010 (0.25) PIN #1 INDEX

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992 Micron and the Micron and M logos are trademarks and/or service marks of Micron Technology, Inc. 4Mb SMART 5 BOOT BLOCK FLASH MEMORY 4Mb Smart 5 Boot Block Flash Memory ©2002, Micron Technology Inc. MT28F004B5_3.fm - Rev. 3, Pub. 8/2002 32

REVISION HISTORY

 Removed PRELIMINARY designation C h a n g e d tRS (MIN) from 600ns to 1,000ns C h a n g e d VOL (MAX)from 0.45V to 0.50V  Updated input capacitance specification U p d a t e d tRWH specification