Memory

MT28C3212P2FL

Micron Technology

FLASH AND SRAM COMBO MEMORY

Manufacturer: Micron Technology

Document: 47 Pages / 564Kb

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PDF pages: 47

Technical content

2 MEG x 16 PAGE FLASH

128K x 16 SRAM COMBO MEMORY PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. FLASH AND SRAM COMBO MEMORY MT28C3212P2FL MT28C3212P2NFL Low Voltage, Extended Temperature

FEATURES

Flexible dual-bank architecture
Support for true concurrent operations with no latency: Read bank b during program bank a and vice versa Read bank b during erase bank a and vice versa
Organization: 2,048K x 16 (Flash) 128K x 16 (SRAM)
Basic configuration: Flash Bank a (4Mb Flash for data storage) – Eight 4K-word parameter blocks – Seven 32K-word blocks Bank b (28Mb Flash for program storage) – Fifty-six 32K-word main blocks SRAM 2Mb SRAM for data storage – 128K-words
F_V CC, VCCQ, F_V PP, S_V CC voltages 1 1.65V (MIN)/1.95V (MAX) F_V CC read voltage or 1.80V (MIN)/2.20V (MAX) F_V CC read voltage 1.65V (MIN)/1.95V (MAX) S_V CC read voltage or 1.80V (MIN)/2.20V (MAX) S_V CC read voltage 1.65V (MIN)/1.95V (MAX) V CCQ or 1.80V (MIN)/2.20V (MAX) V CCQ 1.80V (TYP) F_V PP (in-system PROGRAM/ERASE) 0.0V (MIN)/2.20V (MAX) F_V PP (in-system PROGRAM/ERASE) 2 12V ±5% (HV) F_V PP (production programming compatibility)
Asynchronous access time 1 Flash access time: 100ns or 110ns @ 1.65V F_V CC SRAM access time: 100ns @ 1.65V S_V CC
Page Mode read access 1 Interpage read access: 100ns/110ns @ 1.65V F_V CC Intrapage read access: 35ns/45ns @ 1.65V F_V CC
Low power consumption
Enhanced suspend options ERASE-SUSPEND-to-READ within same bank PROGRAM-SUSPEND-to-READ within same bank ERASE-SUSPEND-to-PROGRAM within same bank
Read/Write SRAM during program/erase of Flash
Dual 64-bit chip protection registers for security purposes
PROGRAM/ERASE cycles 100,000 WRITE/ERASE cycles per block
Cross-compatible command set support Extended command set Common Flash interface (CFI) compliant NOTE: 1. These specifications are guaranteed for operation within either one of two voltage ranges, 1.65V–1.95V or 1.80V–2.20V. Use only one of the two voltage ranges for PROGRAM and ERASE operations. 2. MT28C3212P2NFL only. OPTIONS MARKING
Timing 100ns -10 110ns -11
Boot Block Top T Bottom B PP1 Range 0.9V–2.2V None 0.0V–2.2V N
Operating Temperature Range Commercial Temperature (0 oC to +70 oC) None Extended Temperature (-40 oC to +85 oC) ET
Package 66-ball FBGA (8 x 8 grid) FL Part Number Example: MT28C3212P2FL-10 TET BALL ASSIGNMENT 66-Ball FBGA (Top View) A B C D E F G H 1 2 3 4 5 6 7 8 9 10 11 12 Top View (Ball Down) NC NC A14 DQ11 A15 A10 A19 S_OE# A20 A16 F_WE# S_V SS F_WP# S_LB# A18 F_VCC A12 S_WE# DQ6 S_CE2 DQ10 DQ8 F_VSS F_VSS DQ14 DQ4 S_VCC DQ2 DQ0 F_OE# V ccQ DQ7 DQ5 F_V CC DQ3 DQ1 S_CE1# NC NC NC NC NC A13 DQ15 DQ13 DQ12 DQ9 F_CE# NC NC A11 NC F_RP# F_V PP S_UB# A17

2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory Micron Technology, Inc., reserves the right to change products or specifications without notice. MT28C3212P2FL_2.p65 – Rev. 2, Pub. 4/02 ©2002, Micron Technology, Inc. 128K x 16 SRAM COMBO MEMORY Table 2 Cross Reference for Abbreviated Device Marks PRODUCT SAMPLE MECHANICAL PART NUMBER MARKING MARKING SAMPLE MARKING MT28C3212P2FL-10 BET FW443 FX443 FY443 MT28C3212P2FL-10 TET FW442 FX442 FY442 MT28C3212P2FL-11 BET FW444 FX444 FY444 MT28C3212P2FL-11 TET FW433 FX433 FY433 MT28C3212P2NFL-11 TET FW445 FX445 FY445 GENERAL DESCRIPTION The MT28C3212P2FL and MT28C3212P2NFL com- bination Flash and SRAM memory devices provide a compact, low-power solution for systems where PCB real estate is at a premium. The dual-bank Flash is a high-performance, high-density, nonvolatile memory device with a revolutionary architecture that can sig- nificantly improve system performance. This new architecture features:

A two-memory-bank configuration supporting dual-bank burst operation;
A high-performance bus interface providing a fast page data transfer; and
A conventional asynchronous bus interface. The device also provides soft protection for blocks by configuring soft protection registers with dedicated command sequences. For security purposes, dual 64- bit chip protection registers are provided. The embedded WORD WRITE and BLOCK ERASE functions are fully automated by an on-chip write state machine (WSM). The WSM simplifies these operations and relieves the system processor of secondary tasks. An on-chip status register, one for each bank, can be used to monitor the WSM status to determine the progress of a PROGRAM/ERASE command. The erase/program suspend functionality allows compatibility with existing EEPROM emulation soft- ware packages. The device takes advantage of a dedicated power source for the Flash device (F_V CC) and a dedicated power source for the SRAM device (S_V CC), both at 1.65V–1.95V or 1.80V–2.20V for optimized power con- sumption and improved noise immunity. The MT28C3212P2FL and MT28C3212P2NFL devices sup- port two VPP voltage ranges, V PP1 and VPP2. VPP1 is an in- circuit voltage of 0.9V–2.2V (MT28C3212P2FL) or 0.0V– 2.2V (MT28C3212P2NFL). V PP2 is the production com- patibility voltage of 12V ±5%. The 12V ±5% V PP2 is sup- ported for a maximum of 100 cycles and 10 cumulative hours. See Table 1. The MT28C3212P2FL and MT28C3212P2NFL de- vices contain an asynchronous 2Mb SRAM organized as 128K-words by 16 bits. These devices are fabricated using an advanced CMOS process and high-speed/ ultra-low-power circuit technology. The MT28C3212P2FL and MT28C3212P2NFL de- vices are packaged in a 66-ball FBGA package with 0.80mm pitch. DEVICE MARKING Due to the size of the package, Micron’s standard part number is not printed on the top of each device. Instead, an abbreviated device mark comprised of a five-digit alphanumeric code is used. The abbreviated device marks are cross referenced to Micron part num- bers in Table 2. Table 1 VPP Voltage Ranges VOLTAGE RANGE DEVICE V PP1 VPP2 MT28C3212P2FL 0.9V–2.2V 11.4V–12.6V MT28C3212P2NFL 0.0V–2.2V 11.4V–12.6V

2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory Micron Technology, Inc., reserves the right to change products or specifications without notice. MT28C3212P2FL_2.p65 – Rev. 2, Pub. 4/02 ©2002, Micron Technology, Inc. 128K x 16 SRAM COMBO MEMORY PART NUMBERING INFORMATION Micron’s low-power devices are available with sev- eral different combinations of features (see Figure 1). Table 3 Valid Part Number Combinations BOOT BLOCK OPERATING VPP1 ACCESS STARTING TEMPERATURE PART NUMBER RANGE TIME (ns) ADDRESS RANGE MT28C3212P2FL-10 BET 0.9V–2.2V 100 Bottom -40 oC to +85oC MT28C3212P2FL-10 TET 0.9V–2.2V 100 Top -40 oC to +85oC MT28C3212P2FL-11 BET 0.9V–2.2V 110 Bottom -40 oC to +85oC MT28C3212P2FL-11 TET 0.9V–2.2V 110 Top -40 oC to +85oC MT28C3212P2NFL-11 TET 0.0V–2.2V 110 Top -40 oC to +85oC MT 28C 321 2 P 2 N FL-11 T ET Micron Technology Flash Family 28C = Dual-Supply Flash/SRAM Combo Density/Organization/Banks 321 = 32Mb (2,048K x 16) bank a = 1/8; bank b = 7/8 SRAM Density 2 = 2Mb SRAM (128K x 16) Access Time -10 = 100ns -11 = 110ns Read Mode Operation P = Asynchronous/Page Read Package Code FL = 66-ball FBGA (8 x 8 grid) Operating Temperature Range None = Commercial (0ºC to +70ºC) ET = Extended (-40ºC to +85ºC) VPP1 Range None = 0.9V–2.2V N = 0.0V–2.2V Boot Block Starting Address B = Bottom boot T = Top boot Operating Voltage Range 2 = 1.65V–1.95V or 1.80V–2.20V Figure 1 Part Number Chart Valid combinations of features and their correspond- ing part numbers are listed in Table 3.

2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory Micron Technology, Inc., reserves the right to change products or specifications without notice. MT28C3212P2FL_2.p65 – Rev. 2, Pub. 4/02 ©2002, Micron Technology, Inc. 128K x 16 SRAM COMBO MEMORY BLOCK DIAGRAM F_VPP S_OE# S_CE2 S_CE1# S_WE# DQ0–DQ15 A17–A20 A0–A16 F_RP# F_CE# F_OE# F_WE# F_VCC F_WP# F_VSS FLASH SRAM S_VSS S_UB# S_LB# 2,048K x 16 128K x 16 Bank a Bank b S_VCC VCCQ FLASH FUNCTIONAL BLOCK DIAGRAM Address Input Buffer X DEC Y/Z DEC Data Input Buffer Output Multiplexer Address CNT/WSM Output Buffer Status Reg. WSM Program/ Erase Pump Voltage Generators Address Latch DQ0-DQ15 DQ0–DQ15 CSM F_RST# F_CE# X DEC Y/Z DEC F_WE# F_OE# I/O Logic A0–A20 Address Multiplexer Bank 2 Blocks Y/Z Gating/Sensing Data Register Bank 1 Blocks Y/Z Gating/Sensing ID Reg. RCR Block Lock Device ID Manufacturer’s ID OTP Query PR Lock Query/OTP PR Lock

2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory Micron Technology, Inc., reserves the right to change products or specifications without notice. MT28C3212P2FL_2.p65 – Rev. 2, Pub. 4/02 ©2002, Micron Technology, Inc. 128K x 16 SRAM COMBO MEMORY BALL DESCRIPTIONS 66-BALL FBGA NUMBERS SYMBOL TYPE DESCRIPTION A3, A4, A5, A6, A0–A20 Input Address Inputs: Inputs for the addresses during READ and WRITE A7, A8, B3, B4, operations. Addresses are internally latched during READ and WRITE B5, B6, E5, G3, cycles. Flash: A0–A20; SRAM: A0–A16. G4, G5, G6, G7, G8, G9, H4, H5, H7 F_CE# Input Flash Chip Enable: Activates the device when LOW. When CE# is HIGH, the device is disabled and goes into standby power mode. H9 F_OE# Input Flash Output Enable: Enables Flash output buffers when LOW. When F_OE# is HIGH, the output buffers are disabled. C3 F_WE# Input Flash Write Enable: Determines if a given cycle is a Flash WRITE cycle. F_WE# is active LOW. D4 F_RP# Input Reset. When F_RP# is a logic LOW, the device is in reset, which drives the outputs to High-Z and resets the WSM. When F_RP# is a logic HIGH, the device is in standard operation. When F_RP# transitions from logic LOW to logic HIGH, the device resets all blocks to locked and defaults to the read array mode. E3 F_WP# Input Flash Write Protect. Controls the lock down function of the flexible locking feature. G10 S_CE1# Input SRAM Chip Enable1: Activates the SRAM when it is LOW. HIGH level deselects the SRAM and reduces the power consumption to standby levels. D8 S_CE2 Input SRAM Chip Enable2: Activates the SRAM when it is HIGH. LOW level deselects the SRAM and reduces the power consumption to standby levels. F5 S_OE# Input SRAM Output Enable: Enables SRAM output buffers when LOW. When S_OE# is HIGH, the output buffers are disabled. B8 S_WE# Input SRAM Write Enable: Determines if a given cycle is an SRAM WRITE cycle. S_WE# is active LOW. F3 S_LB# Input SRAM Lower Byte: When LOW, it selects the SRAM address lower byte (DQ0–DQ7). F4 S_UB# Input SRAM Upper Byte: When LOW, it selects the SRAM address upper byte (DQ8–DQ15). B7, B9, B10, DQ 0–DQ15 Input/ Data Inputs/Outputs: Input array data on the second CE# and WE# C7, C8, C9, Output cycle during PROGRAM command. Input commands to the command C10, D7, E6, user interface when CE# and WE# are active. Output data when CE# E8, E9, E10, and OE# are active. F7, F8, F9, F10 (continued on next page)

2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory Micron Technology, Inc., reserves the right to change products or specifications without notice. MT28C3212P2FL_2.p65 – Rev. 2, Pub. 4/02 ©2002, Micron Technology, Inc. 128K x 16 SRAM COMBO MEMORY BALL DESCRIPTIONS (continued) 66-BALL FBGA NUMBERS SYMBOL TYPE DESCRIPTION Supply Operates as input at logic levels to control complete device protection. Provides backward compatibility for factory programming when driven to 11.4V–12.6V. A lower F_V PP voltage range (0.0V–2.2V) is available on the MT28C3212P2NFL device. device operation. A9, H8 F_V SS Supply Flash Specific Ground: Do not float any ground pin. device operation. D3 S_V SS Supply SRAM Specific Ground: Do not float any ground pin. directly to VCC. A1, A2, A11, NC – No Connect: Lead is not internally connected; it may be driven or A12, C4, H1, floated. H2, H10, H11, H12

2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory Micron Technology, Inc., reserves the right to change products or specifications without notice. MT28C3212P2FL_2.p65 – Rev. 2, Pub. 4/02 ©2002, Micron Technology, Inc. 128K x 16 SRAM COMBO MEMORY NOTE: 1. Two devices may not drive the memory bus at the same time. 2. Allowable flash read modes include read array, read query, read configuration, and read status. 3. Outputs are dependent on a separate device controlling bus outputs. 4. Modes of the Flash and SRAM can be interleaved so that while one is disabled, the other controls outputs. 5. SRAM is enabled and/or disabled with the logical function: S_CE1# or S_CE2. 6. Simultaneous operations can exist, as long as the operations are interleaved such that only one device attempts to control the bus outputs at a time. 7. Data output on lower byte only; upper byte High-Z. 8. Data output on upper byte only; lower byte High-Z. 9. Data input on lower byte only. 10. Data input on upper byte only. TRUTH TABLE – FLASH FLASH SIGNALS SRAM SIGNALS MEMORY OUPUT BUS CONTROL Read H L L H SRAM must be High-Z Flash D OUT 1, 2, 3 Write H L H L Flash D IN 1 Standby H H X X Other High-Z 4 Output Disable H L H H SRAM any mode allowable Other High-Z 4, 5 Reset L X X X Other High-Z 4, 6 TRUTH TABLE – SRAM FLASH SIGNALS SRAM SIGNALS MEMORY OUPUT BUS CONTROL Read DQ0–DQ15 L H L H L L SRAM D OUT 1, 3 DQ0–DQ7 L H L H H L SRAM D OUT LB 7 DQ8–DQ15 Flash must be High-Z L H L H L H SRAM D OUT UB 8 Write DQ0–DQ15 L H H L L L SRAM D IN 1, 3 DQ0–DQ7 L H H L H L SRAM D IN LB 9 DQ8–DQ15 L H H L L H SRAM D IN UB 10 Standby H X X X X X Other High-Z 4 Flash any mode allowable X L X X X X Other High-Z 4 Output Disable L H X X X X Other High-Z 4

2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory Micron Technology, Inc., reserves the right to change products or specifications without notice. MT28C3212P2FL_2.p65 – Rev. 2, Pub. 4/02 ©2002, Micron Technology, Inc. 128K x 16 SRAM COMBO MEMORY ARCHITECTURE AND MEMORY ORGANIZATION The Flash memory device contains two separate memory banks (bank a and bank b) for simultaneous READ and WRITE operations. Bank a is 2Mb deep and contains 8 x 4K-word parameter blocks and seven 32K- word blocks. Bank b is 28Mb deep, is equally sectored, and contains fifty-six 32K-word blocks. Figures 2 and 3 show the top and bottom memory organizations.

2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory Micron Technology, Inc., reserves the right to change products or specifications without notice. MT28C3212P2FL_2.p65 – Rev. 2, Pub. 4/02 ©2002, Micron Technology, Inc. 128K x 16 SRAM COMBO MEMORY Figure 2 Bottom Boot Block Device Bank b = 28Mb Block Block Size Address Range (K-bytes/K-words) (x16) 70 64/32 1F8000h-1FFFFFh 69 64/32 1F0000h-1F7FFFh 68 64/32 1E8000h-1EFFFFh 67 64/32 1E0000h-1E7FFFh 66 64/32 1D8000h-1DFFFFh 65 64/32 1D0000h-1D7FFFh 64 64/32 1C8000h-1CFFFFh 63 64/32 1C0000h-1C7FFFh 62 64/32 1B8000h-1BFFFFh 61 64/32 1B0000h-1B7FFFh 60 64/32 1A8000h-1AFFFFh 59 64/32 1A0000h-1A7FFFh 58 64/32 198000h-19FFFFh 57 64/32 190000h-197FFFh 56 64/32 188000h-18FFFFh 55 64/32 180000h-187FFFh 54 64/32 178000h-17FFFFh 53 64/32 170000h-177FFFh 52 64/32 168000h-16FFFFh 51 64/32 160000h-167FFFh 50 64/32 158000h-15FFFFh 49 64/32 150000h-157FFFh 48 64/32 148000h-14FFFFh 47 64/32 140000h-147FFFh 46 64/32 138000h-13FFFFh 45 64/32 130000h-137FFFh 44 64/32 128000h-12FFFFh 43 64/32 120000h-127FFFh 42 64/32 118000h-11FFFFh 41 64/32 110000h-117FFFh 40 64/32 108000h-10FFFFh 39 64/32 100000h-107FFFh 38 64/32 0F8000h-0FFFFFh 37 64/32 0F0000h-0F7FFFh 36 64/32 0E8000h-0EFFFFh 35 64/32 0E0000h-0E7FFFh 34 64/32 0D800h-0DFFFFh 33 64/32 0D0000h-0D7FFFh 32 64/32 0C8000h-0CFFFFh 31 64/32 0C0000h-0C7FFFh 30 64/32 0B8000h-0BFFFFh 29 64/32 0B0000h-0B7FFFh 28 64/32 0A8000h-0AFFFFh 27 64/32 0A0000h-0A7FFFh 26 64/32 098000h-097FFFh 25 64/32 090000h-097FFFh 24 64/32 088000h-087FFFh 23 64/32 080000h-087FFFh 22 64/32 078000h-07FFFFh 21 64/32 070000h-077FFFh 20 64/32 068000h-067FFFh 19 64/32 060000h-067FFFh 18 64/32 058000h-05FFFFh 17 64/32 050000h-057FFFh 16 64/32 048000h-04FFFFh 15 64/32 040000h-047FFFh Bank a = 4Mb Block Block Size Address Range (K-bytes/K-words) (x16) 14 64/32 038000h-03FFFFh 13 64/32 030000h-037FFFh 12 64/32 028000h-02FFFFh 11 64/32 020000h-027FFFh 10 64/32 018000h-01FFFFh 9 64/32 010000h-017FFFh 8 64/32 008000h-00FFFFh 7 8/4 007000h-007FFFh 6 8/4 006000h-006FFFh 5 8/4 005000h-005FFFh 4 8/4 004000h-004FFFh 3 8/4 003000h-003FFFh 2 8/4 002000h-002FFFh 1 8/4 001000h-001FFFh 0 8/4 000000h-000FFFh

2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory Micron Technology, Inc., reserves the right to change products or specifications without notice. MT28C3212P2FL_2.p65 – Rev. 2, Pub. 4/02 ©2002, Micron Technology, Inc. 128K x 16 SRAM COMBO MEMORY Figure 3 Top Boot Block Device Bank b = 28Mb Block Block Size Address Range (K-bytes/K-words) (x16) 55 64/32 1B8000h-1BFFFFh 54 64/32 1B0000h-1B7FFFh 53 64/32 1A8000h-1AFFFFh 52 64/32 1A0000h-1A7FFFh 51 64/32 198000h-19FFFFh 50 64/32 190000h-197FFFh 49 64/32 188000h-18FFFFh 48 64/32 180000h-187FFFh 47 64/32 178000h-17FFFFh 46 64/32 170000h-177FFFh 45 64/32 168000h-16FFFFh 44 64/32 160000h-167FFFh 43 64/32 158000h-15FFFFh 42 64/32 150000h-157FFFh 41 64/32 148000h-14FFFFh 40 64/32 140000h-147FFFh 39 64/32 138000h-13FFFFh 38 64/32 130000h-137FFFh 37 64/32 128000h-12FFFFh 36 64/32 120000h-127FFFh 35 64/32 118000h-11FFFFh 34 64/32 110000h-117FFFh 33 64/32 108000h-10FFFFh 32 64/32 100000h-107FFFh 31 64/32 0F8000h-0FFFFFh 30 64/32 0F0000h-0F7FFFh 29 64/32 0E8000h-0EFFFFh 28 64/32 0E0000h-0E7FFFh 27 64/32 0D8000h-0DFFFFh 26 64/32 0D0000h-0D7FFFh 25 64/32 0C8000h-0CFFFFh 24 64/32 0C0000h-0C7FFFh 23 64/32 0B8000h-0BFFFFh 22 64/32 0B0000h-0B7FFFh 21 64/32 0A8000h-0AFFFFh 20 64/32 0A0000h-0A7FFFh 19 64/32 098000h-09FFFFh 18 64/32 090000h-097FFFh 17 64/32 088000h-08FFFFh 16 64/32 080000h-087FFFh 15 64/32 078000h-07FFFFh 14 64/32 070000h-077FFFh 13 64/32 068000h-06FFFFh 12 64/32 060000h-067FFFh 11 64/32 058000h-05FFFFh 10 64/32 050000h-057FFFh 9 64/32 048000h-04FFFFh 8 64/32 040000h-047FFFh 7 64/32 038000h-03FFFFh 6 64/32 030000h-037FFFh 5 64/32 028000h-02FFFFh 4 64/32 020000h-027FFFh 3 64/32 018000h-01FFFFh 2 64/32 010000h-017FFFh 1 64/32 008000h-00FFFFh 0 64/32 000000h-007FFFh Bank a = 4Mb Block Block Size Address Range (K-bytes/K-words) (x16) 70 8/4 1FF000h-1FFFFFh 69 8/4 1FE000h-1FEFFFh 68 8/4 1FD000h-1FDFFFh 67 8/4 1FC000h-1FCFFFh 66 8/4 1FB000h-1FBFFFh 65 8/4 1FA000h-1FAFFFh 64 8/4 1F9000h-1F9FFFh 63 8/4 1F8000h-1F8FFFh 62 64/32 1F0000h-1F7FFFh 61 64/32 1E8000h-1EFFFFh 60 64/32 1E0000h-1E7FFFh 59 64/32 1D8000h-1DFFFFh 58 64/32 1D0000h-1D7FFFh 57 64/32 1C8000h-1CFFFFh 56 64/32 1C0000h-1C7FFFh

2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory Micron Technology, Inc., reserves the right to change products or specifications without notice. MT28C3212P2FL_2.p65 – Rev. 2, Pub. 4/02 ©2002, Micron Technology, Inc. 128K x 16 SRAM COMBO MEMORY FLASH MEMORY OPERATING MODES COMMAND STATE MACHINE Commands are issued to the command state ma- chine (CSM) using standard microprocessor write tim- ings. The CSM acts as an interface between external microprocessors and the internal write state machine (WSM). The available commands are listed in Table 4, their definitions are given in Table 5 and their descrip- tions in Table 6. Program and erase algorithms are au- tomated by the on-chip WSM. Table 7 shows the CSM transition states. Once a valid PROGRAM/ERASE com- mand is entered, the WSM executes the appropriate algorithm, which generates the necessary timing sig- nals to control the device internally. A command is valid only if the exact sequence of WRITEs is completed. After the WSM completes its task, the write state ma- chine status (WSMS) bit (SR7) (see Table 9) is set to a logic HIGH level (V IH), allowing the CSM to respond to the full command set again. OPERATIONS Device operations are selected by entering a stan- dard JEDEC 8-bit command code with conventional microprocessor timings into an on-chip CSM through I/O pins DQ0–DQ7. The number of bus cycles required to activate a command is typically one or two. The first operation is always a WRITE. Control pins F_CE# and F_WE# must be at a logic LOW level (V IL), and F_OE# and F_RP# must be at logic HIGH (V IH). The second operation, when needed, can be a WRITE or a READ depending upon the command. During a READ opera- tion, control pins F_CE# and F_OE# must be at a logic LOW level (V IL), and F_WE# and F_RP# must be at logic HIGH (V IH). Table 8 illustrates the bus operations for all the modes: write, read, reset, standby, and output disable. When the device is powered up, internal reset cir- cuitry initializes the chip to a read array mode of opera- tion. Changing the mode of operation requires that a command code be entered into the CSM. For each one of the two flash memory partitions, an on-chip status register is available. These two registers allow the moni- toring of the progress of various operations that can take place on a memory bank. One of the two status registers is interrogated by entering a READ STATUS REGISTER command onto the CSM (cycle 1), specify- ing an address within the memory partition boundary, and reading the register data on I/O pins DQ0–DQ7 (cycle 2). Status register bits SR0-SR7 correspond to DQ0–DQ7 (see Table 9). COMMAND DEFINITION Once a specific command code has been entered, the WSM executes an internal algorithm, generating the necessary timing signals to program, erase, and verify data. See Table 5 for the CSM command defini- tions and data for each of the bus cycles. STATUS REGISTER The status register allows the user to determine whether the state of a PROGRAM/ERASE operation is pending or complete. The status register is monitored by toggling F_OE# and F_CE# and reading the result- ing status code on I/O pins DQ0–DQ7. The high-order I/Os (DQ8–DQ15) are set to 00h internally, so only the Table 4 Command State Machine Codes For Device Mode Selection COMMAND DQ0–DQ7 CODE ON DEVICE MODE 10h/40h Program setup/alternate program setup 20h Block erase setup 50h Clear status register 60h Protection configuration setup 70h Read status register 90h Read protection configuration register 98h Read query B0h Program/erase suspend C0h Protection register program/lock D0h Program/erase resume - erase confirm FFh Read array

2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory Micron Technology, Inc., reserves the right to change products or specifications without notice. MT28C3212P2FL_2.p65 – Rev. 2, Pub. 4/02 ©2002, Micron Technology, Inc. 128K x 16 SRAM COMBO MEMORY low-order I/O pins (DQ0–DQ7) need to be interpreted. Address lines select the status register pertinent to the selected memory partition. Register data is updated and latched on the rising edge of F_OE# or F_CE#, whichever occurs first. The latest falling edge of either of these two signals up- dates the latch within a given READ cycle. Latching the data prevents errors from occurring if the register input changes during a status register read. The status register provides the internal state of the WSM to the external microprocessor. During periods when the WSM is active, the status register can be polled to determine the WSM status. Table 9 defines the sta- tus register bits. After monitoring the status register during a PROGRAM/ERASE operation, the data appearing on DQ0–DQ7 remains as status register data until a new command is issued to the CSM. To return the device to other modes of operation, a new command must be issued to the CSM. COMMAND STATE MACHINE OPERATIONS The CSM decodes instructions for the commands listed in Table 4. The 8-bit command code is input to the device on DQ0–DQ7 (see Table 5 for command definitions). During a PROGRAM or ERASE cycle, the CSM informs the WSM that a PROGRAM or ERASE cycle has been requested. During a PROGRAM cycle, the WSM controls the program sequences and the CSM responds to a PRO- GRAM SUSPEND command only. During an ERASE cycle, the CSM responds to an ERASE SUSPEND command only. When the WSM has completed its task, the WSMS bit (SR7) is set to a logic HIGH level and the CSM responds to the full command set. The CSM stays in the current command state until the microprocessor issues another command. The WSM successfully initiates an ERASE or PRO- GRAM operation only when V PP is within its correct volt- age range. Table 5 Command Definitions FIRST BUS CYCLE SECOND BUS CYCLE COMMAND OPERATION ADDRESS DATA OPERATION ADDRESS DATA READ ARRAY WRITE WA FFh READ PROTECTION CONFIGURATION REGISTER WRITE IA 90h READ IA ID READ STATUS REGISTER WRITE BA 70h READ BA SRD CLEAR STATUS REGISTER WRITE BA 50h READ QUERY WRITE QA 98h READ QA QD BLOCK ERASE SETUP WRITE BA 20h WRITE BA D0h PROGRAM SETUP/ALTERNATE PROGRAM SETUP WRITE WA 40h/10h WRITE WA WD PROGRAM/ERASE SUSPEND WRITE BA B0h PROGRAM/ERASE RESUME - ERASE CONFIRM WRITE BA D0h LOCK BLOCK WRITE BA 60h WRITE BA 01h UNLOCK BLOCK WRITE BA 60h WRITE BA D0h LOCK DOWN BLOCK WRITE BA 60h WRITE BA 2Fh PROTECTION REGISTER PROGRAM WRITE PA C0h WRITE PA PD PROTECTION REGISTER LOCK WRITE LPA C0h WRITE LPA FFFDh NOTE: 1. WA: Word address of memory location to be written, or read 2. IA: Identification code address 3. BA: Address within the block 4. ID: Identification code data 5. SRD: Data read from the status register 6. QA: Query code address 7. QD: Query code data 8. WD: Data to be written at the location WA 9. PA: Protection register address 10. LPA: Lock protection register address 11. PD: Protection register data

2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory Micron Technology, Inc., reserves the right to change products or specifications without notice. MT28C3212P2FL_2.p65 – Rev. 2, Pub. 4/02 ©2002, Micron Technology, Inc. 128K x 16 SRAM COMBO MEMORY Table 6 Command Descriptions CODE DEVICE MODE BUS CYCLE DESCRIPTION 10h Alt. Program Setup First Operates the same as a PROGRAM SETUP command. 20h Erase Setup First Prepares the CSM for an ERASE CONFIRM command. If the next command is not ERASE CONFIRM, the CSM sets both SR4 and SR5 of the status register to a “1,” places the device into read status register mode, and waits for another command. 40h Program Setup First A two-cycle command: The first cycle prepares for a PROGRAM operation, the second cycle latches addresses and data and initiates the WSM to execute the program algorithm. The Flash outputs status register data on the falling edge of F_OE# or F_CE#, whichever occurs first. 50h Clear Status First The WSM can set the program status (SR4), and erase status (SR5) bits Register in the status register to “1,” but it cannot clear them to “0.” Issuing this command clears those bits to “0.” 60h Protection First Prepares the CSM for changes to the block locking status. If the next Configuration command is not BLOCK UNLOCK, BLOCK LOCK or BLOCK LOCK Setup DOWN, then the CSM sets both the program and erase status register bits to indicate a command sequence error. 70h Read Status First Places the device into read status register mode. Reading the device Register outputs the contents of the status register, regardless of the address presented to the device. The device automatically enters this mode after a PROGRAM or ERASE operation has been initiated. 90h Read Protection First Puts the device into the read protection configuration mode so that Configuration reading the device outputs the manufacturer/device codes or block lock status. 98h Read Query First Puts the device into the read query mode so that reading the device outputs common Flash interface information. B0h Program Suspend First Suspends the currently executing PROGRAM/ERASE operation. The status register indicates when the operation has been successfully Erase Suspend First suspended by setting either the program suspend (SR2) or erase suspend (SR6) and the WSMS bit (SR7) to a “1” (ready). The WSM continues to idle in the suspend state, regardless of the state of all input control pins except F_RP#, which immediately shuts down the WSM and the remainder of the chip if F_RP# is driven to V IL. C0h Program Device First Writes a specific code into the device protection register. Protection Register Lock Device First Locks the device protection register; data can no longer be changed. Protection register (continued on the next page)

2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory Micron Technology, Inc., reserves the right to change products or specifications without notice. MT28C3212P2FL_2.p65 – Rev. 2, Pub. 4/02 ©2002, Micron Technology, Inc. 128K x 16 SRAM COMBO MEMORY Table 6 Command Descriptions (continued) CODE DEVICE MODE BUS CYCLE DESCRIPTION D0h Erase Confirm First If the previous command was an ERASE SETUP command, then the CSM closes the address and data latches, and it begins erasing the block indicated on the address pins. During programming/erase, the device responds only to the READ STATUS REGISTER, PROGRAM SUSPEND, or ERASE SUSPEND commands and outputs status register data on the falling edge of F_OE# or F_CE#, whichever occurs last. Program/Erase First If a PROGRAM or ERASE operation was previously suspended, this Resume command resumes the operation. FFh Read Array First During the array mode, array data is output on the data bus. 01h Lock Block Second If the previous command was PROTECTION CONFIGURATION SETUP, the CSM latches the address and locks the block indicated on the address bus. 2Fh Lock Down Second If the previous command was PROTECTION CONFIGURATION SETUP, the CSM latches the address and locks down the block indicated on the address bus. D0h Unlock Block Second If the previous command was PROTECTION CONFIGURATION SETUP, the CSM latches the address and unlocks the block indicated on the address bus. If the block had been previously set to lock down, this operation has no effect. 00h Invalid/Reserved Unassigned command that should not be used.

2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory Micron Technology, Inc., reserves the right to change products or specifications without notice. MT28C3212P2FL_2.p65 – Rev. 2, Pub. 4/02 ©2002, Micron Technology, Inc. 128K x 16 SRAM COMBO MEMORY CLEAR STATUS REGISTER The internal circuitry can set, but not clear, the block lock status bit (SR1), the V PP status bit (SR3), the pro- gram status bit (SR4), and the erase status bit (SR5) of the status register. The CLEAR STATUS REGISTER com- mand (50h) allows the external microprocessor to clear these status bits and synchronize to the internal op- erations. When the status bits are cleared, the device returns to the read array mode. READ OPERATIONS The following READ operations are available: READ ARRAY, READ PROTECTION CONFIGURATION REG- ISTER, READ QUERY and READ STATUS REGISTER. READ ARRAY The array is read by entering the command code FFh on DQ0–DQ7. Control pins F_CE# and F_OE# must be at a logic LOW level (V IL), and F_WE# and F_RP# must be at a logic HIGH level (V IH) to read data from the array. Data is available on DQ0–DQ15. Any valid ad- dress within any of the blocks selects that address and allows data to be read from that address. Upon initial power-up, the device defaults to the read array mode. READ CHIP PROTECTION IDENTIFICATION DATA The chip identification mode outputs three types of information: the manufacturer/device identifier, the block locking status, and the protection register. Two bus cycles are required for this operation: the chip iden- tification data is read by entering the command code 90h on DQ0–DQ7 to the bank containing address 00h and the identification code address on the address lines. Control pins F_CE# and F_OE# must be at a logic LOW level (V IL), and F_WE# and F_RP# must be at a logic HIGH level (V IH) to read data from the protection configuration register. Data is available on DQ0–DQ15. After data is read from the protection configuration register, the READ ARRAY command, FFh, must be is- sued to the bank containing address 00h prior to issu- ing other commands. See Table 11 for further details. READ QUERY The read query mode outputs common Flash inter- face (CFI) data when the device is read (see Table 15). Two bus cycles are required for this operation. It is possible to access the query by writing the read query command code 98h on DQ0–DQ7. Control pins F_CE# and F_OE# must be at a logic LOW level (V IL), and F_WE# and F_RP# must be at a logic HIGH level (V IH) to read data from the query. The CFI data structure contains information such as block size, density, command set, and electrical specifications. To return to read array mode, write the read array command code FFh on DQ0– DQ7. READ STATUS REGISTER The status register is read by entering the command code 70h on DQ0–DQ7. Two bus cycles are required for this operation: one to enter the command code and a second to read the status register. In a READ cycle, the address is latched and register data is updated on the falling edge of F_OE# or F_CE#, whichever occurs last.

2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory Micron Technology, Inc., reserves the right to change products or specifications without notice. MT28C3212P2FL_2.p65 – Rev. 2, Pub. 4/02 ©2002, Micron Technology, Inc. 128K x 16 SRAM COMBO MEMORY Table 7 Command State Machine Transition Table )noititraptneserpehtfoetatstxendna(noititraptneserpehtottupnidnammoC tneserpehtfoetatstneserP noititrap etatstneserP rehtoehtfo noititrap hF2 kcoL nwod mrifnoc h10 kcoL mrifnoc h0C PTO putes h06 kcolnU/kcoL nwodkcoL/ h89 daeR yreuq h09 daeR ecived DI h05 raelC sutats retsiger h07 daeR sutats h0B margorP esarE/ dnepsus h0D ,mrifnocEB ,emuserE/P mrifnocBLU h02 esarE putes h04/h01 margorP putes hFF daeR yarra 7RS ataD nehw daer etatSe doM yarradaeR kcoL daeR yreuq daeR DI daeR yarra daeR sutats yarradaeR 1y arrAy arrA daeR 1p uteS 2y suB yarradaeR PTO putes yarradaeR esarE putes margorP putes daeR yarra 3e ldI yarradaeR yarradaeR 4 esarE dnepsus yarradaeR5 .gorP dnepsus yarradaeR kcoL daeR yreuq daeR DI daeR yarra daeR sutats yarradaeR 1I FCy reuQ 6p uteS 7y suB yarradaeR PTO putes yarradaeR esarE putes margorP putes daeR yarra 8e ldI yarradaeR yarradaeR 9 esarE dnepsus yarradaeR0 1 .gorP dnepsus yarradaeR kcoL daeR yreuq daeR DI daeR yarra daeR sutats yarradaeR 1D I eciveD DI 11p uteS 21y suB yarradaeR PTO putes yarradaeR esarE putes margorP putes daeR yarra 31e ldI yarradaeR yarradaeR 41 esarE dnepsus yarradaeR5 1 .gorP dnepsus yarradaeR kcoL daeR yreuq daeR DI daeR yarra daeR sutats yarradaeR 1s utatSs utatS 61p uteS 71y suB yarradaeR PTO putes yarradaeR esarE putes margorP putes daeR yarra 81e ldI yarradaeR yarradaeR 91 esarE dnepsus yarradaeR0 2 .gorP dnepsus ysubretsigernoitcetorP 1s utatSp uteS P r o t e c t i o n r e g i s t e r 12e ldI ysubretsigernoitcetorP 0s utatSy suB2 2e ldI yarradaeRk coL daeR yreuq daeR DI daeR yarra daeR sutats yarradaeR1 s utatSe noD 32p uteS 42y suB yarradaeR PTO putes kcoL daeR yreuq daeR DI daeR yarra daeR sutats yarradaeR esarE putes margorP putes daeR yarra 1s utatSe noD 52e ldI yarradaeR yarradaeR 62 esarE dnepsus yarradaeR7 2 .gorP dnepsus (continued on next page)

2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory Micron Technology, Inc., reserves the right to change products or specifications without notice. MT28C3212P2FL_2.p65 – Rev. 2, Pub. 4/02 ©2002, Micron Technology, Inc. 128K x 16 SRAM COMBO MEMORY Table 7 Command State Machine Transition Table (continued) )noititraptneserpehtfoetatstxendna(noititraptneserpehtottupnidnammoC tneserpehtfoetatstneserP noititrap foetatstneserP rehtoeht noititrap hF2 kcoL nwod mrifnoc h10 kcoL mrifnoc H0C PTO putes h06 kcolnU/kcoL nwodkcoL/ h89 daeR yreuq h09 daeR DIecived h05 raelC sutats retsiger h07 daeR sutats h0B margorP esarE/ dnepsus h0D ,mrifnocEB ,emuserE/P mrifnocBLU h02 esarE putes h04/h01 margorP putes hFF daeR yarra 7RS ataD nehw daer etatSe doM BLU/BLk coLL B LU/BLk coL1 s utatSp uteS kcoL 82 ynA etats yarradaeR kcoL daeR yreuq DIdaeR daeR yarra daeR sutats yarradaeR 1s utatSr orrE 92p uteS 03y suB yarradaeR PTO putes yarradaeR esarE putes margorP putes daeR yarra 13e ldI yarradaeR yarradaeR 23 esarE dnepsus yarradaeR3 3 .gorP dnepsus yarradaeR kcoL daeR yreuq DIdaeR daeR yarra daeR sutats yarradaeR 1s utatS /kcoL kcolnU 43p uteS 53y suB yarradaeR PTO putes yarradaeR esarE putes margorP putes daeR yarra 63e ldI yarradaeR yarradaeR 73 esarE dnepsus yarradaeR8 3 .gorP dnepsus ysuBmargorP 1s utatSp uteS margorP 93 ynA etats ysuBmargorPd aerSPy submargorP0 s utatSy suB0 4e ldI yarradaeR kcoL daeR yreuq DIdaeR daeR yarra daeR sutats yarradaeR 1s utatSe noD 14p uteS 24y suB yarradaeR PTO putes yarradaeR esarE putes margorP putes daeR yarra 34e ldI yarradaeR yarradaeR 44 esarE dnepsus yarradaeR5 4 .gorP dnepsus daerdnepsusmargorP yarra kcoL margorP dnepsus daer yreuq margorP dnepsus DIdaer margorP dnepsus daer yarra margorP dnepsus daer sutats margorP dnepsus daer yarra ysubmargorP daerdnepsusmargorP yarra 1s utatS daeR sutats margorP dnepsus 64p uteS 74e ldI 84 esarE dnepsus (continued on next page)

2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory Micron Technology, Inc., reserves the right to change products or specifications without notice. MT28C3212P2FL_2.p65 – Rev. 2, Pub. 4/02 ©2002, Micron Technology, Inc. 128K x 16 SRAM COMBO MEMORY Table 7 Command State Machine Transition Table (continued) )noititraptneserpehtfoetatstxendna(noititraptneserpehtottupnidnammoC tneserpehtfoetatstneserP noititrap etatstneserP rehtoehtfo noititrap hF2 kcoL nwod mrifnoc h10 kcoL mrifnoc h0C PTO putes h06 kcolnU/kcoL nwodkcoL/ h89 daeR yreuq h09 daeR DIecived h05 raelC sutats retsiger h07 daeR sutats h0B margorP esarE/ dnepsus h0D ,mrifnocEB ,emuserE/P mrifnocBLU h02 esarE putes h04/h01 margorP putes hFF daeR yarra 7RS ataD nehw daer etatSe doM daerdnepsusmargorP yarra kcoL margorP dnepsus daer yreuq margorP dnepsus DIdaer margorP dnepsus daer yarra margorP dnepsus daer sutats margorP dnepsus daer yarra ysubmargorP daerdnepsusmargorP yarra 1y arrA daeR yarra margorP dnepsus 94p uteS 05e ldI 15 esarE dnepsus daerdnepsusmargorP yarra kcoL margorP dnepsus daer yreuq margorP dnepsus DIdaer margorP dnepsus daer yarra margorP dnepsus daer sutats margorP dnepsus daer yarra ysubmargorP daerdnepsusmargorP yarra 1 DI DIdaeR 25p uteS 35e ldI 45 esarE dnepsus daerdnepsusmargorP yarra kcoL margorP dnepsus daer yreuq margorP dnepsus DIdaer margorP dnepsus daer yarra margorP dnepsus daer sutats margorP dnepsus daer yarra ysubmargorP daerdnepsusmargorP yarra 1I FC daeR yreuQ 55p uteS 65e ldI 75 esarE dnepsus BLU/BLr orreesarE esarE rorre ysubesarEr orreesarE 1s utatSp uteS esarE 85e ldI yarradaeR kcoL daeR yreuq DIdaeR daeR yarra daeR sutats yarradaeR 1 sutatS rorrE 95p uteS 06y suB yarradaeR PTO putes yarradaeR esarE putes margorP putes daeR yarra 16e ldI yarradaeR yarradaeR 26 esarE dnepsus yarradaeR3 6 .gorP dnepsus yarradaeR kcoL daeR yreuq DIdaeR daeR yarra daeR sutats yarradaeR 1 sutatS enoD 46p uteS 56y suB yarradaeR PTO putes yarradaeRe sarE margorP putes daeR yarra 66e ldI yarradaeR yarradaeR 76 esarE dnepsus yarradaeR8 6 .gorP dnepsus ysubesarekcolB daerSE sutats ysubesarE0 s utatSy suB9 6e ldI (continued on next page)

2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory Micron Technology, Inc., reserves the right to change products or specifications without notice. MT28C3212P2FL_2.p65 – Rev. 2, Pub. 4/02 ©2002, Micron Technology, Inc. 128K x 16 SRAM COMBO MEMORY Table 7 Command State Machine Transition Table )noititraptneserpehtfoetatstxendna(noititraptneserpehtottupnidnammoC tneserpehtfoetatstneserP noititrap etatstneserP rehtoehtfo noititrap hF2 kcoL nwod mrifnoc h10 kcoL mrifnoc h0C PTO putes h06 kcolnU/kcoL nwodkcoL/ h89 daeR yreuq h09 daeR DIecived h05 raelC sutats retsiger h07 daeR sutats h0B margorP esarE/ dnepsus h0D ,mrifnocEB ,emuserE/P mrifnocBLU h02 esarE putes h04/h01 margorP putes hFF daeR yarra 7RS ataD nehw daer etatSe doM yarradaerdnepsusesarEk coL esarE dnepsus daer yreuq esarE dnepsus DIdaer esarE dnepsus daer yarra esarE dnepsus daer sutats daerSE yarra ysubesarE daerdnepsusesarE yarra 1 sutatS daeR sutats esarE dnepsus 07p uteS yarradaerdnepsusesarE 17y suB daerSE yarra ysubesarE SE daer yarra .gorP putes SE daer yarra 27e ldI yarradaerdnepsusesarE 37 .gorP dnepsus yarradaerdnepsusesarEk coL esarE dnepsus daer yreuq esarE dnepsus DIdaer esarE dnepsus daer yarra esarE dnepsus daer sutats daerSE yarra ysubesarE daerdnepsusesarE yarra 1y arrA daeR arra y 47p uteS yarradaerdnepsusesarE 57y suB daerSE yarra ysubesarE SE daer yarra .gorP putes SE daer yarra 67e ldI yarradaerdnepsusesarE 77 .gorP dnepsus yarradaerdnepsusesarEk coL esarE dnepsus daer yreuq esarE dnepsus DIdaer esarE dnepsus daer yarra esarE dnepsus daer sutats daerSE yarra ysubesarE daerdnepsusesarE yarra

1 DI daeR

yarradaerdnepsusesarE 97y suB daerSE yarra ysubesarE SE daer yarra .gorP putes SE daer yarra 08e ldI yarradaerdnepsusesarE 18 .gorP dnepsus yarradaerdnepsusesarEk coL esarE dnepsus daer yreuq esarE dnepsus DIdaer esarE dnepsus daer yarra esarE dnepsus daer sutats daerSE yarra ysubesarE daerdnepsusesarE yarra 1I FC daeR yreuq 28p uteS yarradaerdnepsusesarE 38y suB daerSE yarra ysubesarE SE daer yarra .gorP putes SE daer yarra 48e ldI yarradaerdnepsusesarE 58 .gorP dnepsus

2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory Micron Technology, Inc., reserves the right to change products or specifications without notice. MT28C3212P2FL_2.p65 – Rev. 2, Pub. 4/02 ©2002, Micron Technology, Inc. 128K x 16 SRAM COMBO MEMORY plished only by blocks; data at single address locations within the array cannot be erased individually. The block to be erased is selected by using any valid ad- dress within that block. Block erasure is initiated by a command sequence to the CSM: BLOCK ERASE setup (20h) followed by BLOCK ERASE CONFIRM (D0h) (see Table 5). A two-command erase sequence protects against accidental erasure of memory contents. When the BLOCK ERASE CONFIRM command is complete, the WSM automatically executes a sequence of events to complete the block erasure. During this sequence, the block is programmed with logic 0s, data is verified, all bits in the block are erased, and finally verification is performed to ensure that all bits are cor- rectly erased. Monitoring of the ERASE operation is possible through the status register (see the Status Register section). During the execution of an ERASE operation, the ERASE SUSPEND command (B0h) can be entered to direct the WSM to suspend the ERASE operation. Once the WSM has reached the suspend state, it allows the CSM to respond only to the READ ARRAY, READ STA- TUS REGISTER, READ QUERY, READ CHIP PROTEC- TION CONFIGURATION, PROGRAM SETUP, PRO- GRAM RESUME, ERASE RESUME and LOCK SETUP (see the Block Locking section). During the ERASE SUS- PEND operation, array data must be read from a block other than the one being erased. To resume the ERASE operation, an ERASE RESUME command (D0h) must be issued to cause the CSM to clear the suspend state previously set (see Figure 7). It is also possible that an ERASE in any bank can be suspended and a WRITE to another block in the same bank can be initiated. After the completion of a WRITE, an ERASE can be resumed by writing an ERASE RESUME command. PROGRAMMING OPERATIONS There are two CSM commands for programming: PROGRAM SETUP and ALTERNATE PROGRAM SETUP (see Table 4). After the desired command code is entered (10h or 40h command code on DQ0–DQ7), the WSM takes over and correctly sequences the device to complete the PROGRAM operation. The WRITE operation may be monitored through the status register (see the Status Register section). During this time, the CSM only re- sponds to a PROGRAM SUSPEND command until the PROGRAM operation has been completed, after which time all commands to the CSM become valid again. The PROGRAM operation can be suspended by issuing a PROGRAM SUSPEND command (B0h). Once the WSM reaches the suspend state, it allows the CSM to re- spond only to READ ARRAY, READ STATUS REGISTER, READ PROTECTION CONFIGURATION, READ QUERY, PROGRAM SETUP, or PROGRAM RESUME. During the PROGRAM SUSPEND operation, array data should be read from an address other than the one being pro- grammed. To resume the PROGRAM operation, a PRO- GRAM RESUME command (D0h) must be issued to cause the CSM to clear the suspend state previously set (see Figure 4 for programming operation and Figure 5 for program suspend and program resume). Taking F_RP# to V IL during programming aborts the PROGRAM operation. ERASE OPERATIONS An ERASE operation must be used to initialize all bits in an array block to “1s.” After BLOCK ERASE con- firm is issued, the CSM responds only to an ERASE SUSPEND command until the WSM completes its task. Block erasure inside the memory array sets all bits within the address block to logic 1s. Erase is accom- Table 8 Bus Operations MODE F_RP# F_CE# F_OE# F_WE# ADDRESS DQ0–DQ15 Read (array, status registers, V IH VIL VIL VIH XD OUT device identification register, or query) Standby V IH VIH X X X High-Z Output Disable V IH VIH X X X High-Z Reset V IL X X X X High-Z Write V IH VIL VIH VIL XD IN

2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory Micron Technology, Inc., reserves the right to change products or specifications without notice. MT28C3212P2FL_2.p65 – Rev. 2, Pub. 4/02 ©2002, Micron Technology, Inc. 128K x 16 SRAM COMBO MEMORY STATUS BIT # STATUS REGISTER BIT DESCRIPTION SR7 WRITE STATE MACHINE STATUS (WSMS) Check write state machine bit first to determine word 1 = Ready program or block erase completion, before checking 0 = Busy program or erase status bits. SR6 ERASE SUSPEND STATUS (ESS) When ERASE SUSPEND is issued, WSM halts execution and 1 = BLOCK ERASE Suspended sets both WSMS and ESS bits to “1.” ESS bit remains set to 0 = BLOCK ERASE in “1” until an ERASE RESUME command is issued. Progress/Completed SR5 ERASE STATUS (ES) When this bit is set to “1,” WSM has applied the maximum 1 = Error in Block Erasure number of erase pulses to the block and is still unable to 0 = Successful BLOCK ERASE verify successful block erasure. SR4 PROGRAM STATUS (PS) When this bit is set to “1,” WSM has attempted but failed to 1 = Error in PROGRAM program a word. 0 = Successful PROGRAM SR3 V PP STATUS (V PPS) The V PP status bit does not provide continuous indication 1 = V PP Low Detect, Operation Abort of the V PP level. The WSM interrogates the V PP level only 0 = V PP = OK after the program or erase command sequences have been entered and informs the system if V PP has not been switched on. The V PP level is also checked before the PROGRAM/ERASE operation is verified by the WSM. The MT28C3212P2NFL device allows PROGRAM or ERASE at 0V, in which case SR3 is held at “0.” SR2 PROGRAM SUSPEND STATUS (PSS) When PROGRAM SUSPEND is issued, WSM halts execution 1 = PROGRAM Suspended and sets both WSM and PSS bits to “1.” PSS bit remains set to 0 = PROGRAM in Progress/Completed “1” until a PROGRAM RESUME command is issued. SR1 BLOCK LOCK STATUS (BLS) If a PROGRAM or ERASE operation is attempted to one of 1 = PROGRAM/ERASE Attempted on a the locked blocks, this is set by the WSM. The operation Locked Block; Operation Aborted specified is aborted, and the device is returned to read status 0 = No Operation to Locked Blocks mode. SR0 RESERVED FOR FUTURE This bit is reserved for future. ENHANCEMENT Table 9 Status Register Bit Definition WSMS ESS ES PS V PPS PSS BLS R 7654 3210

2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory Micron Technology, Inc., reserves the right to change products or specifications without notice. MT28C3212P2FL_2.p65 – Rev. 2, Pub. 4/02 ©2002, Micron Technology, Inc. 128K x 16 SRAM COMBO MEMORY Figure 4 Automated Word Programming Flowchart NOTE: 1. Full status register check can be done after each word or after a sequence of words. 2. SR3 must be cleared before attempting additional PROGRAM/ERASE operations. 3. SR4 is cleared only by the CLEAR STATUS REGISTER command, but it does not prevent additional program operation attempts. BUS OPERATION COMMAND COMMENTS WRITE WRITE Data = 40h or 10h PROGRAM Addr = Address of word to be SETUP programmed WRITE WRITE Data = Word to be DATA programmed Addr = Address of word to be programmed READ Status register data; toggle OE# or CE# to update status register. Standby Check SR7 1 = Ready, 0 = Busy Repeat for subsequent words. Write FFh after the last word programming operation to reset the device to read array mode. BUS OPERATION COMMAND COMMENTS Standby Check SR1 1 = Detect locked block Standby Check SR3 2 1 = Detect V PP low Standby Check SR4 3 1 = Word program error YES NO Full Status Register Check (optional) NO YES PROGRAM SUSPEND?SR7 = 1? Issue PROGRAM SETUP Command and Word Address Start Word Program Passed VPP Range Error Word Program Failed FULL STATUS REGISTER CHECK FLOW Read Status Register Bits Issue Word Address and Word Data PROGRAM SUSPEND Loop YES NO SR1 = 0? YES NO SR3 = 0? YES NO SR4 = 0? Word Program Completed Read Status Register Bits PROGRAM Attempted on a Locked Block

2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory Micron Technology, Inc., reserves the right to change products or specifications without notice. MT28C3212P2FL_2.p65 – Rev. 2, Pub. 4/02 ©2002, Micron Technology, Inc. 128K x 16 SRAM COMBO MEMORY Issue READ ARRAY Command PROGRAM Complete Finished Reading Issue PROGRAM RESUME Command YES YES NO NO SR2 = 1? Start PROGRAM Resumed Read Status Register Bits Issue PROGRAM SUSPEND Command YES NO SR7 = 1? Figure 5 PROGRAM SUSPEND/ PROGRAM RESUME Flowchart BUS OPERATION COMMAND COMMENTS WRITE PROGRAM Data = B0h SUSPEND READ Status register data; toggle OE# or CE# to update status register. Standby Check SR7 1 = Ready Standby Check SR2 1 = Suspended WRITE READ Data = FFh MEMORY READ Read data from block other than that being programmed. WRITE PROGRAM Data = D0h RESUME

2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory Micron Technology, Inc., reserves the right to change products or specifications without notice. MT28C3212P2FL_2.p65 – Rev. 2, Pub. 4/02 ©2002, Micron Technology, Inc. 128K x 16 SRAM COMBO MEMORY YES NO Full Status Register Check (optional) NO YES ERASE SUSPEND?SR 7 = 1? Start BLOCK ERASE Passed VPP Range Error BLOCK ERASE Failed FULL STATUS REGISTER CHECK FLOW Read Status Register Bits ERASE SUSPEND Loop YES NO SR1 = 0? YES NO YES NO BLOCK ERASE Completed Read Status Register Bits ERASE Attempted on a Locked Block SR3 = 0? SR5 = 0? Issue ERASE SETUP Command and Block Address Issue BLOCK ERASE CONFIRM Command and Block Address Figure 6 BLOCK ERASE Flowchart NOTE: 1. Full status register check can be done after each block or after a sequence of blocks. 2. SR3 must be cleared before attempting additional PROGRAM/ERASE operations. 3. SR5 is cleared only by the CLEAR STATUS REGISTER command in cases where multiple blocks are erased before full status is checked. BUS OPERATION COMMAND COMMENTS WRITE WRITE Data = 20h ERASE Block Addr = Address SETUP within block to be erased WRITE ERASE Data = D0h Block Addr = Address within block to be erased READ Status register data; toggle OE# or CE# to update status register. Standby Check SR7 1 = Ready, 0 = Busy Repeat for subsequent blocks. Write FFh after the last BLOCK ERASE operation to reset the device to read array mode. BUS OPERATION COMMAND COMMENTS Standby Check SR1 1 = Detect locked block Standby Check SR3 2 1 = Detect VPP block Standby Check SR4 and SR5 1 = BLOCK ERASE command error Standby Check SR5 3 1 = BLOCK ERASE error

2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory Micron Technology, Inc., reserves the right to change products or specifications without notice. MT28C3212P2FL_2.p65 – Rev. 2, Pub. 4/02 ©2002, Micron Technology, Inc. 128K x 16 SRAM COMBO MEMORY READ PROGRAM Issue READ ARRAY Command PROGRAM Loop ERASE Complete READ or PROGRAM? YES NO Issue ERASE RESUME Command READ or PROGRAM Complete? YES NO SR6 = 1? Start ERASE Continued Read Status Register Bits Issue ERASE SUSPEND Command (Note 1) YES NO SR7 = 1? Figure 7 ERASE SUSPEND/ERASE RESUME Flowchart NOTE: 1. See BLOCK ERASE Flowchart for complete erasure procedure. 2. See Word Programming Flowchart for complete programming procedure. BUS OPERATION COMMAND COMMENTS WRITE ERASE Data = B0h SUSPEND READ Status register data; toggle OE# or CE# to update status register. Standby Check SR7 1 = Ready Standby Check SR6 1 = Suspended WRITE READ Data = FFh MEMORY READ Read data from block other than that being erased. WRITE ERASE Data = D0h RESUME

2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory Micron Technology, Inc., reserves the right to change products or specifications without notice. MT28C3212P2FL_2.p65 – Rev. 2, Pub. 4/02 ©2002, Micron Technology, Inc. 128K x 16 SRAM COMBO MEMORY READ-WHILE-WRITE/ERASE CONCURRENCY It is possible for the device to read from one bank while erasing/writing to another bank. Once a bank enters the WRITE/ERASE operation, the other bank automatically enters read array mode. For example, during a READ CONCURRENCY operation, if a PRO- GRAM/ERASE command is issued in bank a, then bank a changes to the read status mode and bank b defaults to the read array mode. The device reads from bank b if the latched address resides in bank b (see Figure 8). Similarly, if a PROGRAM/ERASE command is issued in bank b, then bank b changes to read status mode and bank a defaults to read array mode. When returning to bank a, the device reads program/erase status if the latched address resides in bank a. A correct bank ad- dress must be specified to read status register after returning from concurrent read in the other bank. When reading the CFI area, or the chip protection register, the possible concurrent operations are re- ported in Figures 9a and 9b. Figure 8 READ-While-WRITE Concurrency Bank a 1 - Erasing/writing to bank a 2 - Erasing in bank a can be suspended, and a WRITE to another block in bank a can be initiated. 3 - After the WRITE in that block is complete, an ERASE can be resumed by writing an ERASE RESUME command. 1 - Reading bank a Bank b 1 - Reading from bank b 1 - Erasing/writing to bank b 2 - Erasing in bank b can be suspended, and a WRITE to another block in bank b can be initiated. 3 - After the WRITE in that block is complete, an ERASE can be resumed by writing an ERASE RESUME command. Figure 9a Top Boot Block Device Figure 9b Bottom Boot Block Device BANK a BANK b Reading the READ Not Not CFI or Chip Supported Supported Protection WRITE Not NotRegister ERASE Supported Supported BANK a BANK b Reading the READ Not Supported CFI or Chip Supported Protection WRITE Not SupportedRegister ERASE Supported BLOCK LOCKING The Flash memory of the MT28C3212P2FL or MT28C3212P2NFL device provides a flexible locking scheme which allows each block to be individually locked or unlocked with no latency. The device offers two-level protection for the blocks. The first level allows software-only control of block lock- ing (for data which needs to be changed frequently), while the second level requires hardware interaction before locking can be changed (code which does not require frequent updates). Control pins F_WP#, DQ0, and DQ1 define the state of a block; for example, state [001] means F_WP# = 0, DQ0 = 0 and DQ1 = 1. Table 10 defines all of the possible locking states. NOTE: All blocks are software-locked upon comple- tion of the power-up sequence. LOCKED STATE After a power-up sequence completion, or after a reset sequence, all blocks are locked (states [001] or [101]). This means full protection from alteration. Any PROGRAM or ERASE operations attempted on a locked block will return an error on bit SR1 of the status regis- ter. The status of a locked block can be changed to unlocked or lock down using the appropriate software commands. Writing the lock command sequence, 60h followed by 01h, can lock an unlocked block. UNLOCKED STATE Unlocked blocks (states [000], [100], [110]) can be programmed or erased. All unlocked blocks return to the locked state when the device is reset or powered down. An unlocked block can be locked or locked down using the appropriate software command sequence, 60h followed by D0h. (See Table 5.) LOCKED DOWN STATE Blocks locked down (state [011]) are protected from PROGRAM and ERASE operations, but their protection status cannot be changed using software commands

Top boot configuration 44A2h
Bottom boot configuration 44A3h Block Lock Configuration 2 XX002h Lock
Block is unlocked DQ0 = 0
Block is locked DQ0 = 1
Block is locked down DQ1 = 1 Chip Protection Register Lock 80h PR Lock Chip Protection Register 1 81h–84h Factory Data Chip Protection Register 2 85h–88h User Data NOTE: 1. Other locations within the configuration address space are reserved by Micron for future use. 2. “XX” specifies the block address of lock configuration. Table 11 Chip Protection Configuration Addressing 1

2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory Micron Technology, Inc., reserves the right to change products or specifications without notice. MT28C3212P2FL_2.p65 – Rev. 2, Pub. 4/02 ©2002, Micron Technology, Inc. 128K x 16 SRAM COMBO MEMORY DOWN command. It can only be cleared by reset or power-down, not by software. Table 10 shows the block locking state transition scheme. The READ ARRAY com- mand, FFh, must be issued to the bank containing ad- dress 00h prior to issuing other commands. LOCKING OPERATIONS DURING ERASE SUSPEND Changes to block lock status can be performed dur- ing an ERASE SUSPEND by using the standard locking command sequences to unlock, lock, or lock down. This is useful in the case when another block needs to be updated while an ERASE operation is in progress. To change block locking during an ERASE opera- tion, first write the ERASE SUSPEND command (B0h), then check the status register until it indicates that the ERASE operation has been suspended. Next, write the desired lock command sequence to block lock, and the lock status will be changed. After completing any de- sired LOCK, READ, or PROGRAM operations, resume the ERASE operation with the ERASE RESUME com- mand (D0h). If a block is locked or locked down during an ERASE SUSPEND on the same block, the locking status bits are changed immediately. When the ERASE is resumed, the ERASE operation completes. A locking operation cannot be performed during a PROGRAM SUSPEND. STATUS REGISTER ERROR CHECKING Using nested locking or program command se- quences during ERASE SUSPEND can introduce ambi- guity into status register results. Following protection configuration setup (60h), an invalid command produces a lock command error (SR4 and SR5 are set to “1”) in the status register. If a lock command error occurs during an ERASE SUSPEND, SR4 and SR5 are set to “1” and remain at “1” after the ERASE SUSPEND command is issued. When the ERASE is complete, any possible error during the ERASE can- not be detected via the status register because of the previous locking command error. A similar situation happens if an error occurs during a program operation error nested within an ERASE SUSPEND. CHIP PROTECTION REGISTER A 128-bit protection register can be used to fullfill the security considerations in the system (preventing device substitution). The 128-bit security area is divided into two 64-bit segments. The first 64 bits are programmed at the manufacturing site with a unique 64-bit number. The other segment is left blank for customers to program as desired. (See Figure 10). READING THE CHIP PROTECTION REGISTER The chip protection register is read in the device identification mode. To enter this mode, load the 90h command to the bank containing address 00h. Once in this mode, READ cycles from addresses shown in Table 11 retrieve the specified information. To return to the read array mode, write the READ ARRAY command (FFh). The read array command, FFh, must be issued to the bank containing address 00h prior to issuing other commands. PAGE READ MODE The initial portion of the page mode cycle is the same as the asynchronous access cycle. Holding CE# LOW and toggling addresses A0–A1 allows random ac- cess of other words in the page. The page size can be customized at the factory to four or eight words as required; but if no specification is made, the normal size is four words. ASYNCHRONOUS READ CYCLE When accessing addresses in a random order or when switching between pages, the access time is given by tAA. When F_CE# and F_OE# are LOW, the data is placed on the data bus and the processor can read the data. Figure 10 Protection Register Memory Map

4 Words

2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory Micron Technology, Inc., reserves the right to change products or specifications without notice. MT28C3212P2FL_2.p65 – Rev. 2, Pub. 4/02 ©2002, Micron Technology, Inc. 128K x 16 SRAM COMBO MEMORY STANDBY MODE Icc supply current is reduced by applying a logic HIGH level on F_CE# and F_RP# to enter the standby mode. In the standby mode, the outputs are placed in High-Z. Applying a CMOS logic HIGH level on F_CE# and F_RP# reduces the current to I CC2 (MAX). If the device is deselected during an ERASE operation or dur- ing programming, the device continues to draw cur- rent until the operation is complete. AUTOMATIC POWER SAVE MODE (APS) Substantial power savings are realized during peri- ods when the Flash array is not being read and the device is in the active mode. During this time the de- vice switches to the automatic power save (APS) mode. When the device switches to this mode, I CC is reduced to I CC2. The low level of power is maintained until an- other operation is initiated. In this mode, the I/O pins retain the data from the last memory address read un- til a new address is read. This mode is entered auto- matically if no address or control pins toggle. VPP/VCC PROGRAM AND ERASE VOLTAGES The MT28C3212P2FL Flash memory provides in- system programming and erase with V PP in the 0.9V– 2.2V range (V PP1). In addition to the flexible block lock- ing, the V PP programming voltage can be held LOW for absolute hardware write protection of all blocks in the Flash device. When V PP is below VPPLK, any PROGRAM or ERASE operation results in an error, prompting the cor- responding status register bit (SR3) to be set. The MT28C3212P2NFL Flash memory provides in- system programming and erase with V PP in the 0.0V– 2.2V range (V PP1). VPP at 12V ±5% (V PP2) is supported for a maximum of 100 cycles and 10 cumulative hours. The device can withstand 100,000 WRITE/ERASE operations when V PP = VCC. During WRITE and ERASE operations, the WSM monitors the V PP voltage level. WRITE/ERASE opera- tions are allowed only when V PP is within the ranges specified in Table 12. When V CC is below V LKO or V PP is below V PPLK, any WRITE/ERASE operation is prevented. DEVICE RESET To correctly reset the device, the RST# signal must be asserted (RST# = V IL) for a minimum of tRP. After reset, the device can be accessed for a READ operation with a delayed access time of tRWH from the rising edge of RST#. The circuitry used for generating the RST# signal needs to be common with the rest of the system reset to ensure that correct system initialization occurs. Please refer to the timing diagram for further details. POWER-UP SEQUENCE The following power-up sequence must be observed to properly initialize the device:

RST# must be at V IL.
Power on V CC/VCCQ (VCC VCCQ at all times).
Wait 2µS after V CC reaches V CC (MIN).
Take RST# from V IL to VIH.
The RST# transition from V IL to V IH must be less than 10µS. Table 12 VPP Ranges (V) IN-SYSTEM IN-FACTORY DEVICE MIN MAX MIN MAX MT28C3212P2FL 0.9 2.2 11.4 12.6 MT28C3212P2NFL 0.0 2.2 11.4 12.6

2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory Micron Technology, Inc., reserves the right to change products or specifications without notice. MT28C3212P2FL_2.p65 – Rev. 2, Pub. 4/02 ©2002, Micron Technology, Inc. 128K x 16 SRAM COMBO MEMORY ABSOLUTE MAXIMUM RATINGS* Voltage to Any Pin Except V CC and V PP VPP Voltage (for BLOCK ERASE and PROGRAM with Respect to V VCC and V CCQ Supply Voltage *Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. **Maximum DC voltage on V PP may overshoot to +13.5V for periods <20ns. RECOMMENDED OPERATING CONDITIONS PARAMETER SYMBOL MIN MAX UNITS NOTES Operating temperature tA -40 +85 oC VCC supply voltage F_V CC, S_VCC 1.65 2.2 V I/O supply voltage (V CC = 1.65V–1.95V) V CCQ 1.65 1.95 V 1 I/O supply voltage (V CC = 1.80V–2.20V) V CCQ 1.80 2.20 V 1 VPP voltage V PP1 0.9 2.2 V (MT28C3212P2FL only) V PP voltage V PP1 0.0 2.2 V (MT28C3212P2NFL only) VPP in-factory programming voltage V PP2 11.4 12.6 V 2 Data retention supply voltage S_V DR 1.0 – V Block erase cycling – 100,000 Cycles Figure 11 Output Load Circuit I/O 14.5K 30pF VCC VSS 14.5K FLASH ELECTRICAL SPECIFICATIONS 2. 12V V PP is supported for a maximum of 100 cycles and may be connected for up to 10 cumulative hours.

2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory Micron Technology, Inc., reserves the right to change products or specifications without notice. MT28C3212P2FL_2.p65 – Rev. 2, Pub. 4/02 ©2002, Micron Technology, Inc. 128K x 16 SRAM COMBO MEMORY COMBINED DC CHARACTERISTICS1 VCC = 1.65V–1.95V or 1.80V–2.20V VCCQ = 1.65V–1.95V or 1.80V–2.20V DESCRIPTION CONDITIONS SYMBOL MIN TYP MAX UNITS NOTES Input low voltage V IL -0.4 – 0.4 V Input high voltage V IH VCCQ - – V CCQ + V 0.4V 0.3V Output low voltage V OL – – 0.10 V IOL = 100µA Output high voltage V OH VCCQ - – – V IOH = 100µA 0.1V VPP lock out voltage V PPLK – – 0.4 V VPP during PROGRAM/ERASE V PP1 0.9 – 2.2 V operations (MT28C3212P2FL only) V PP2 11.4 – 12.6 V 2 VPP during PROGRAM/ERASE V PP1 0.0 – 2.2 V operations (MT28C3212P2NFL only) V PP2 11.4 – 12.6 V 2 VCC PROGRAM/ERASE lock voltage V LKO 1.0 – – V Input leakage current I L ––1 mA Output leakage current I OZ ––1 mA F_VCC asynchronous I CC1 –– 1 5 m A read current at 95ns F_V CC page mode I CC2 ––5m A read current at 35ns F_VCC plus S_V CC standby current I CC3 –2 5 6 0 mA F_VCC program current I CC4+IPP3 –– 5 5 m A F_VCC erase current I CC5+IPP4 –– 6 5 m A F_VCC/S_VCC erase suspend current I CC6 –– 6 0 mA F_VCC/S_VCC program suspend I CC7 –– 6 0 mA current Read-while-write current I CC8 –– 8 0 m A S_VCC read/write operating V IN = VIH or VIL ICC9 –1 2 2 5m A3 supply current – page access chip enabled, I OL = 0 mode NOTE: 1. All currents are in RMS unless otherwise noted. 2. 12V V PP is supported for a maximum of 100 cycles and may be connected for up to 10 cumulative hours. 3. Operating current is a linear function of operating frequency and voltage. Operating current can be calculated using the formula shown with operating frequency (f) expressed in MHz and operating voltage (V) in volts. Example: When operating at 2 MHz at 2V, the device will draw a typical active current of 0.8*2* = 3.2mA in the page access mode. This parameter is specified with the outputs disabled to avoid external loading effects. The user must add current required to drive output capacitance expected in the actual system. (continued on the next page)

2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory Micron Technology, Inc., reserves the right to change products or specifications without notice. MT28C3212P2FL_2.p65 – Rev. 2, Pub. 4/02 ©2002, Micron Technology, Inc. 128K x 16 SRAM COMBO MEMORY COMBINED DC CHARACTERISTICS1 (continued) VCC = 1.65V–1.95V or 1.80V–2.20V VCCQ = 1.65V–1.95V or 1.80V–2.20V DESCRIPTION CONDITIONS SYMBOL MIN TYP MAX UNITS NOTES S_VCC read/write operating V IN = VIH or VIL ICC10 –38m A 3 supply current – word access chip enabled, I OL = 0 mode VPP read current V PP ≤ VCC IPP1 ––1 mA VPP ‡ VCC – – 200 mA VPP standby current V PP ≤ VCC IPP2 ––1 mA VPP ‡ VCC – – 200 mA VPP erase suspend current V PP = VPP1 IPP5 ––1 mA VPP = VPP2 – – 200 mA VPP program suspend current V PP = VPP1 IPP6 ––1 mA VPP = VPP2 – – 200 mA NOTE: 1. All currents are in RMS unless otherwise noted. 2. 12V V PP is supported for a maximum of 100 cycles and may be connected for up to 10 cumulative hours. 3. Operating current is a linear function of operating frequency and voltage. Operating current can be calculated using the formula shown with operating frequency (f) expressed in MHz and operating voltage (V) in volts. Example: When operating at 2 MHz at 2V, the device will draw a typical active current of 0.8*2* = 3.2mA in the page access mode. This parameter is specified with the outputs disabled to avoid external loading effects. The user must add current required to drive output capacitance expected in the actual system.

2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory Micron Technology, Inc., reserves the right to change products or specifications without notice. MT28C3212P2FL_2.p65 – Rev. 2, Pub. 4/02 ©2002, Micron Technology, Inc. 128K x 16 SRAM COMBO MEMORY FLASH READ CYCLE TIMING REQUIREMENT VCC = 1.65V–1.95V -10 -11 VCC = 1.65V–1.95V V CC = 1.65V–1.95V PARAMETER SYMBOL MIN MAX MIN MAX UNITS Address to output delay tAA 100 110 ns CE# LOW to output delay tACE 100 110 ns Page address access tAPA 35 45 ns OE# LOW to output delay tAOE 30 30 ns F_RP# HIGH to output delay tRWH 200 200 ns F_RP# LOW pulse width tRP 125 125 ns CE# or OE# HIGH to output High-Z tOD 25 25 ns Output hold from address, CE# or OE# change tOH 0 0 ns READ cycle time tRC 100 110 ns FLASH READ CYCLE TIMING REQUIREMENT VCC = 1.80V–2.20V -10 -11 VCC = 1.80V–2.20V V CC = 1.80V–2.20V PARAMETER SYMBOL MIN MAX MIN MAX UNITS Address to output delay tAA 95 100 ns CE# LOW to output delay tACE 95 100 ns Page address access tAPA 35 45 ns OE# LOW to output delay tAOE 30 30 ns F_RP# HIGH to output delay tRWH 150 150 ns F_RP# LOW pulse width tRP 100 100 ns CE# or OE# HIGH to output High-Z tOD 25 25 ns Output hold from address, CE# or OE# change tOH 0 0 ns READ cycle time tRC 95 100 ns

2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory Micron Technology, Inc., reserves the right to change products or specifications without notice. MT28C3212P2FL_2.p65 – Rev. 2, Pub. 4/02 ©2002, Micron Technology, Inc. 128K x 16 SRAM COMBO MEMORY FLASH WRITE CYCLE TIMING REQUIREMENTS -10/-11 VCC = 1.65V–1.95V or 1.80V–2.20V PARAMETER SYMBOL MIN MAX UNITS Reset HIGH recovery to WE# going LOW tRS 150 ns CE# setup to WE# going LOW tCS 0 ns Write pulse width tWP 50 ns Data setup to WE# going HIGH tDS 50 ns Address setup to WE# going HIGH tAS 50 ns CE# hold from WE# HIGH tCH 0 ns Data hold from WE# HIGH tDH 0 ns Address hold from WE# HIGH tAH 9 ns Write pulse width HIGH tWPH 30 ns WP# setup to WE# going HIGH tRHS 200 ns VPP setup to WE# going HIGH tVPS 200 ns Write recovery before READ tWOS 50 ns WP# hold from valid SRD tRHH 0 ns VPP hold from valid SRD tVPH 0 ns WE# HIGH to data valid tWB tAA+50 ns FLASH ERASE AND PROGRAM CYCLE TIMING REQUIREMENTS -10/-11 VCC = 1.65V–1.95V or 1.80V–2.20V PARAMETER TYP MAX UNITS 4KW parameter block program time 0.1 0.3 s 32KW parameter block program time 0.8 2.4 s Word program time 8 185 µs 4KW parameter block erase time 1 4 s 32KW parameter block erase time 1.5 5 s Program suspend latency 51 0 µ s Erase suspend latency 52 0 µ s

2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory Micron Technology, Inc., reserves the right to change products or specifications without notice. MT28C3212P2FL_2.p65 – Rev. 2, Pub. 4/02 ©2002, Micron Technology, Inc. 128K x 16 SRAM COMBO MEMORY TWO-CYCLE PROGRAMMING/ERASE OPERATION VALID ADDRESS VALID ADDRESS VALID ADDRESS UNDEFINED tCH tDH tRHS tDS A0–A20 OE# CE# WE# VPP RP# WP# VIH VIH VIL VIL VIH VIL VIH VIL VIH VIL VIH VIL VIPPLK VIL VIPPH tAS tAH tWPH tRS tWP tWOStCS tWB CMD CMD/ DATADQ0–DQ15 VOH VOL tRHH tVPS tVPPH STATUSHigh-Z NOTE: 1. The WRITE cycles for the WORD PROGRAMMING command are followed by a READ ARRAY DATA cycle. -10/-11 VCC = 1.65V–1.95V or 1.80V–2.20V SYMBOL MIN MAX UNITS WRITE TIMING PARAMETERS -10/-11 VCC = 1.65V–1.95V or 1.80V–2.20V SYMBOL MIN MAX UNITS tRS 150 ns tCS 0 ns tWP 50 ns tDS 50 ns tAS 50 ns tCH 0 ns tDH 0 ns tAH 9 ns tRHS 200 ns tVPS 200 ns tWOS 50 ns tRHH 0 ns tVPH 0 ns tWB tAA+50 ns

2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory Micron Technology, Inc., reserves the right to change products or specifications without notice. MT28C3212P2FL_2.p65 – Rev. 2, Pub. 4/02 ©2002, Micron Technology, Inc. 128K x 16 SRAM COMBO MEMORY SINGLE ASYNCHRONOUS READ OPERATION READ TIMING PARAMETERS (VCC = 1.65V–1.95V) -10 -11 VCC = 1.65V–1.95V V CC = 1.65V–1.95V SYMBOL MIN MAX MIN MAX UNITS tAA 100 110 ns tACE 100 110 ns tAOE 30 30 ns tRWH 200 200 ns tOD 25 25 ns tOH 0 0 ns tRC 100 110 ns VALID ADDRESS UNDEFINED tOD tAA tACE tOH A0–A20 OE# CE# WE# VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL tRC tRWH DQ0–DQ15 RP# VOH VOL VALID OUTPUTHigh-Z tAOE READ TIMING PARAMETERS (VCC = 1.80V–2.20V) -10 -11 VCC = 1.80V–2.20V V CC = 1.80V–2.20V SYMBOL MIN MAX MIN MAX UNITS tAA 95 100 ns tACE 95 100 ns tAOE 30 30 ns tRWH 150 150 ns tOD 25 25 ns tOH 0 0 ns tRC 95 100 ns

2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory Micron Technology, Inc., reserves the right to change products or specifications without notice. MT28C3212P2FL_2.p65 – Rev. 2, Pub. 4/02 ©2002, Micron Technology, Inc. 128K x 16 SRAM COMBO MEMORY ASYNCHRONOUS PAGE MODE READ OPERATION VALID ADDRESS VALID ADDRESS VALID ADDRESS VALID ADDRESS VALID OUTPUT VALID OUTPUT VALID OUTPUT VALID OUTPUT UNDEFINED tOD tAA tACE tOHtAPAtAOE tRMH A0–A1 F_OE# F_CE# F_WE# VIH VIL VIH VIL VIH VIL VIH VIL VALID ADDRESSA2–A20 VIH VIL F_RP# VIH VIL DQ0–DQ15 VOH VOL High-Z READ TIMING PARAMETERS (VCC = 1.65V–1.95V) -10 -11 VCC = 1.65V–1.95V V CC = 1.65V–1.95V SYMBOL MIN MAX MIN MAX UNITS tAA 100 110 ns tACE 100 110 ns tAPA 35 45 ns tAOE 30 30 ns tRWH 200 200 ns tOD 25 25 ns tOH 0 0 ns READ TIMING PARAMETERS (VCC = 1.80V–2.20V) -10 -11 VCC = 1.80V–2.20V V CC = 1.80V–2.20V SYMBOL MIN MAX MIN MAX UNITS tAA 95 100 ns tACE 95 100 ns tAPA 35 45 ns tAOE 30 30 ns tRWH 150 150 ns tOD 25 25 ns tOH 0 0 ns

2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory Micron Technology, Inc., reserves the right to change products or specifications without notice. MT28C3212P2FL_2.p65 – Rev. 2, Pub. 4/02 ©2002, Micron Technology, Inc. 128K x 16 SRAM COMBO MEMORY RESET OPERATION F_OE# DQ0–DQ15 VIH VIL F_RST# VIH VIL F_CE# VIH VIL VOH VOL tRWH tRP READ TIMING PARAMETERS (VCC = 1.65V–1.95V) -10 -11 VCC = 1.65V–1.95V V CC = 1.65V–1.95V SYMBOL MIN MAX MIN MAX UNITS tRWH 200 200 ns tRP 125 125 ns READ TIMING PARAMETERS (VCC = 1.80V–2.20V) -10 -11 VCC = 1.80V–2.20V V CC = 1.80V–2.20V SYMBOL MIN MAX MIN MAX UNITS tRWH 150 150 ns tRP 100 100 ns

01 A2h Top Boot Block Device Code

A3h Bottom Boot Block Device Code 02–0F reserved Reserved 10, 11 0051,0052 “QR” 12 0059 “Y” 13, 14 0003, 0000 Primary OEM Command Set 15, 16 0039, 0000 Address for Primary Extended Table 17, 18 0000, 0000 Alternate OEM Command Set 19, 1A 0000, 0000 Address for OEM Extended Table 1B 0017 V CC MIN for Erase/Write; Bit7–Bit4 Volts in BCD; Bit3–Bit0 100mV in BCD 1C 0022 V CC MAX for Erase/Write; Bit7–Bit4 Volts in BCD; Bit3–Bit0 100mV in BCD 1D 00B4 V PP MIN for Erase/Write; Bit7–Bit4 Volts in Hex; Bit3–Bit0 100mV in BCD 1E 00C6 V PP MAX for Erase/Write; Bit7–Bit4 Volts in Hex; Bit3–Bit0 100mV in BCD 1F 0003 Typical timeout for single byte/word program, 2 n µs, 0000 = not supported 20 0000 Typical timeout for maximum size multiple byte/word program, 2 n µs, 0000 = not supported 21 0009 Typical timeout for individual block erase, 2 n ms, 0000 = not supported 22 0000 Typical timeout for full chip erase, 2 n ms, 0000 = not supported 23 000C Maximum timeout for single byte/word program, 2 n µs, 0000 = not supported 24 0000 Maximum timeout for maximum size multiple byte/word program, 2 n µs, 0000 = not supported 25 0003 Maximum timeout for individual block erase, 2 n ms, 0000 = not supported 26 0000 Maximum timeout for full chip erase, 2 n ms, 0000 = not supported 27 0016 Device size, 2 n bytes 28 0001 Bus Interface x8 = 0, x16 = 1, x8/x16 = 2 29 0000 Flash device interface description 0000 = async 2A, 2B 0000, 0000 Maximum number of bytes in multi-byte program or page, 2 n 2C 0003 Number of erase block regions within device (4K words and 32K words) 2D, 2E 0037, 0000 Top boot block device erase block region information 1, 8 blocks … 0007, 0000 Bottom boot block device erase block region information 1, 8 blocks … 2F, 30 0000, 0001 Top boot block device ...of 8KB 0020, 0000 Bottom boot block device ...of 8KB 31, 32 0006, 0000 7 blocks of … 33, 34 0000, 0001 ……64KB 35, 36 0007, 0000 Top boot block device 56 blocks of 0037, 0000 Bottom boot block device 56 blocks of (continued on the next page)

2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory Micron Technology, Inc., reserves the right to change products or specifications without notice. MT28C3212P2FL_2.p65 – Rev. 2, Pub. 4/02 ©2002, Micron Technology, Inc. 128K x 16 SRAM COMBO MEMORY Table 15 CFI (continued) OFFSET DATA DESCRIPTION 37, 38 0020, 0000 Top boot block device……64KB 0000, 0001 Bottom boot block device……64KB 39, 3A 0050, 0052 “PR” 3B 0049 “I” 3C 0030 Major version number, ASCII 3D 0031 Minor Version Number, ASCII 3E 00E6 Optional Feature and Command Support 3F 0002 Bit 0 Chip erase supported no = 0 40 0000 Bit 1 Suspend erase supported = yes = 1 41 0000 Bit 2 Suspend program supported = yes = 1 Bit 3 Chip lock/unlock supported = no = 0 Bit 4 Queued erase supported = no = 0 Bit 5 Instant individual block locking supported = yes = 1 Bit 6 Protection bits supported = yes = 1 Bit 7 Page mode read supported = yes = 1 Bit 8 Synchronous read supported = yes = 1 Bit 9 Simultaneous operation supported = yes = 1 42 0001 Program supported after erase suspend = yes 43, 44 0003, 0000 Bit 0 Block Lock Status active = yes; Bit 1 Block Lock Down active = yes 45 0018 V CC supply optimum; Bit7–Bit4 Volts in BCD; Bit3–Bit0 100mV in BCD 46 00C0 V PP supply optimum; Bit7–Bit4 Volts in Hex; Bit3–Bit0 100mV in BCD 47 0001 Number of protection register fields in JEDEC ID space 48, 49 0080, 0000 Lock bytes LOW address, lock bytes HIGH address 4A, 4B 0003, 0003 2 n factory programmed bytes, 2 n user programmable bytes 4C 0002 Background Operation 0000 = Not used 0001 = 4% block split 0002 = 12% block split 0003 = 25% block split 0004 = 50% block split 4D 0000 Burst Mode Type 0000 = No burst mode 00x1 = 4 words max 00x2 = 8 words max 00x3 = 16 words max 001x = Linear burst, and/or 002x = Interleaved burst, and/or 004x = Continuous burst 4E 0002 Page Mode Type 0000 = No page mode 0001 = 4-word page 0002 = 8-word page 0003 = 16-word page 0004 = 32-word page 4F 0002 SRAM density, 2Mb (128K x 16)

2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory Micron Technology, Inc., reserves the right to change products or specifications without notice. MT28C3212P2FL_2.p65 – Rev. 2, Pub. 4/02 ©2002, Micron Technology, Inc. 128K x 16 SRAM COMBO MEMORY SRAM OPERATING MODES SRAM READ ARRAY The operational state of the SRAM is determined by indicated in the Truth Table. To perform an SRAM READ operation, S_CE1#, and S_OE#, must be at V IL, and S_CE2 and S_WE# must be at V IH. When in this state, S_UB# and S_LB# control whether the lower byte is read (S_UB# V IH, S_LB# V IL), the upper byte is read (S_UB# VIL, S_LB# V IH), both upper and lower bytes are read (S_UB# V IL, S_LB# V IL), or neither are read (S_UB# VIH, S_LB# V IH) and the device is in a standby state. While performing an SRAM READ operation, cur- rent consumption may be reduced by reading within a 16-word page. This is done by holding S_CE1# and SRAM FUNCTIONAL BLOCK DIAGRAM DQ0–DQ7 WORD ADDRESS DECODE LOGIC PAGE ADDRESS DECODE LOGIC CONTROL LOGIC 8K-PAGE x16 WORD x16 BIT RAM ARRAY WORD MUX DQ8–DQ15 INPUT/ OUTPUT MUX AND BUFFERS S_CE1# A4–A16 A0–A3 S_OE# S_UB# S_LB# S_CE2 S_WE# S_OE# at V IL, S_WE# and S_CE2 at V IH, and toggling addresses A0-A3. S_UB# and S_LB# control the data width as described above. SRAM WRITE ARRAY In order to perform an SRAM WRITE operation, S_CE1# and S_WE# must be at V IL, and S_CE2 and S_OE# must be at V IH. When in this state, S_UB# and S_LB# control whether the lower byte is written (S_UB# V IH, S_LB# V IL), the upper byte is written (S_UB# V IL, S_LB# V IH), both upper and lower bytes are written (S_UB# V IL, S_LB# V IL), or neither are written (S_UB# VIH, S_LB# V IH) and the device is in a standby state.

2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory Micron Technology, Inc., reserves the right to change products or specifications without notice. MT28C3212P2FL_2.p65 – Rev. 2, Pub. 4/02 ©2002, Micron Technology, Inc. 128K x 16 SRAM COMBO MEMORY TIMING TEST CONDITIONS oC to +85 oC SRAM READ CYCLE TIMING -10/-11 VCC = 1.65V–1.95V V CC = 1.80V–2.20V DESCRIPTION SYMBOL MIN MAX MIN MAX UNITS Read cycle time tRC 100 85 ns Address access time tAA 100 85 ns Chip enable to valid output tCO 100 85 ns Output enable to valid output tOE 35 35 ns Byte select to valid output tLB, tUB 100 85 ns Chip enable to Low-Z output tLZ 0 0 ns Output enable to Low-Z output tOLZ 0 0 ns Byte select to Low-Z output tLBZ, tUBZ 0 0 ns Chip enable to High-Z output tHZ 0 15 0 15 ns Output disable to High-Z output tOHZ 0 15 0 15 ns Byte select disable to High-Z output tLBHZ, tUBHZ 0 15 0 15 ns Output hold from address change tOH 5 5 ns SRAM WRITE CYCLE TIMING -10/-11 VCC = 1.65V–1.95V V CC = 1.80V–2.20V DESCRIPTION SYMBOL MIN MAX MIN MAX UNITS Write cycle time tWC 100 85 ns Chip enable to end of write tCW 100 85 ns Address valid to end of write tAW 100 85 ns Byte select to end of write tLBW, tUBW 100 85 ns Address setup time tAS 0 0 ns Write pulse width tWP 50 50 ns Write recovery time tWR 0 0 ns Write to High-Z output tWHZ 0 15 0 15 ns Data to write time overlap tDW 50 50 ns Data hold from write time tDH 0 0 ns End write to Low-Z output tOW 0 0 ns

2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory Micron Technology, Inc., reserves the right to change products or specifications without notice. MT28C3212P2FL_2.p65 – Rev. 2, Pub. 4/02 ©2002, Micron Technology, Inc. 128K x 16 SRAM COMBO MEMORY DON’T CARE ADDRESS S_CE1# S_CE2 S_OE# S_LB#, S_UB# DATA-OUT tRC tAA tHZ (1, 2) tCO tLBLZ, tUBLZ tLBHZ, tUBHZ DATA VALIDHigh-Z tOE tLZ(2) tOLZ tOHZ (1) tLB, tUB READ CYCLE 1 (S_CE1# = S_OE# = VIL; S_CE2, S_WE# = VIH) ADDRESS DATA-OUT tRC tAA tOH PREVIOUS DATA VALID DATA VALID READ CYCLE 2 (S_WE# = VIH) READ TIMING PARAMETERS -10/-11 VCC = 1.65V–1.95V V CC = 1.80V–2.20V SYMBOL MIN MAX MIN MAX UNITS tRC 100 85 ns tAA 100 85 ns tCO 100 85 ns tOE 35 35 ns tLB, tUB 100 85 ns tLZ 0 0 ns -10/-11 VCC = 1.65V–1.95V V CC = 1.80V–2.20V SYMBOL MIN MAX MIN MAX UNITS tOLZ 0 0 ns tHZ 0 15 0 15 ns tOHZ 0 15 0 15 ns tLBHZ, tUBHZ 0 15 0 15 ns tOH 5 5 ns

2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory Micron Technology, Inc., reserves the right to change products or specifications without notice. MT28C3212P2FL_2.p65 – Rev. 2, Pub. 4/02 ©2002, Micron Technology, Inc. 128K x 16 SRAM COMBO MEMORY WRITE CYCLE (S_WE# CONTROL) DON’T CARE ADDRESS S_CE1# S_CE2 DATA-OUT tWC tAW tWR tCW tWHZ tOW High-Z S_LB#, S_UB# tLBW, tUBW S_WE# DATA-IN tAS tWP tDHtDW DATA VALIDHigh-Z WRITE TIMING PARAMETERS -10/-11 VCC = 1.65V–1.95V V CC = 1.80V–2.20V SYMBOL MIN MAX MIN MAX UNITS tWC 100 85 ns tCW 100 85 ns tAW 100 85 ns tLBW, tUBW 100 85 ns tAS 0 0 ns tWP 50 50 ns -10/-11 VCC = 1.65V–1.95V V CC = 1.80V–2.20V SYMBOL MIN MAX MIN MAX UNITS tWR 0 0 ns tWHZ 0 15 0 15 ns tDW 50 50 ns tDH 0 0 ns tOW 0 0 ns

2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory Micron Technology, Inc., reserves the right to change products or specifications without notice. MT28C3212P2FL_2.p65 – Rev. 2, Pub. 4/02 ©2002, Micron Technology, Inc. 128K x 16 SRAM COMBO MEMORY WRITE CYCLE 2 (S_CE1# CONTROL) DON’T CARE ADDRESS S_CE1# DATA-OUT tWC tAW tWR tCW tWHZtLZ High-Z S_LB#, S_UB# S_WE# DATA-IN tAS tWP tLBW, tUBW tDHtDW DATA VALID WRITE TIMING PARAMETERS -10/-11 VCC = 1.65V–1.95V V CC = 1.80V–2.20V SYMBOL MIN MAX MIN MAX UNITS tWC 100 85 ns tCW 100 85 ns tAW 100 85 ns tLBW, tUBW 100 85 ns tAS 0 0 ns tWP 50 50 ns -10/-11 VCC = 1.65V–1.95V V CC = 1.80V–2.20V SYMBOL MIN MAX MIN MAX UNITS tWR 0 0 ns tWHZ 0 15 0 15 ns tDW 50 50 ns tDH 0 0 ns tOW 0 0 ns

2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory Micron Technology, Inc., reserves the right to change products or specifications without notice. MT28C3212P2FL_2.p65 – Rev. 2, Pub. 4/02 ©2002, Micron Technology, Inc. 128K x 16 SRAM COMBO MEMORY 66-BALL FBGA 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992 Micron is a registered trademark and the Micron logo and M logo are trademarks of Micron Technology, Inc. SOLDER BALL MATERIAL: EUTECTIC 63% Sn, 37% Pb or 62% Sn, 36% Pb, 2%Ag SOLDER BALL PAD: Ø .27mm MOLD COMPOUND: EPOXY NOVOLAC SUBSTRATE: PLASTIC LAMINATE

1.40 MAX

0.80 (TYP) 8.80 0.80 (TYP) 8.00 ±0.10 12.00 ±0.10 66X Ø 0.35 BALL A12 BALL A1 BALL A1BALL #1 ID 5.60 2.80 ±0.05 4.00 ±0.05 0.10 1.05 ±0.075 C C SEATING PLANE SOLDER BALL DIAMETER REFERS TO POST REFLOW CONDITION. THE PRE- REFLOW DIAMETER IS Ø 0.33 C L C L NOTE: 1. All dimensions in millimeters MAX or typical where noted. MIN 2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.27mm per side. DATA SHEET DESIGNATION This data sheet contains minimum and maximum limits specified over the complete power supply and temperature range for production devices. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur.

REVISION HISTORY

Updated the chip protection mode and register information.
Updated the block locking information.
Removed the tCBPH parameter.
Data sheet designation change (removed “Advance”)

Product Information

MT28C3212P2FL specifications and overview.

Summary

FLASH AND SRAM COMBO MEMORY

Description

FLASH AND SRAM COMBO MEMORY

Source title MT28C3212P2FL Datasheet(PDF) - Micron Technology

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