MT250QL01GABA8ESE0SITES

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Technical content

Datasheet sections

Features

• SPI-compatible serial bus interface
• Single and double transfer rate (STR/DTR)
• Clock frequency – 133 MHz (MAX) for all protocols in STR – 90 MHz (MAX) for all protocols in DTR
• Dual/quad I/O commands for increased through- put up to 90 MB/s
• Supported protocols: Extended, Dual and Quad I/O both STR and DTR
• Execute-in-place (XIP)
• PROGRAM/ERASE SUSPEND operations
• Volatile and nonvolatile configuration settings
• Software reset
• Additional reset pin for selected part numbers
• 3-byte and 4-byte address modes – enable memory access beyond 128Mb
• Dedicated 64-byte OTP area outside main memory – Readable and user-lockable – Permanent lock with PROGRAM OTP command
• Erase capability – Bulk erase – Sector erase 64KB uniform granularity – Subsector erase 4KB, 32KB granularity
• Erase performance: 400KB/sec (64KB sector)
• Erase performance: 80KB/sec (4KB sub-sector)
• Program performance: 2MB/sec
• Security and write protection – Volatile and nonvolatile locking and software write protection for each 64KB sector – Nonvolatile configuration locking – Password protection – Hardware write protection: nonvolatile bits (BP[3:0] and TB) define protected area size – Program/erase protection during power-up – CRC detects accidental changes to raw data
• Electronic signature – JEDEC-standard 3-byte signature (BA19h) – Extended device ID: two additional bytes identify device factory options
• JESD47H-compliant – Minimum 100,000 ERASE cycles per sector – Data retention: 20 years (TYP) Options Marking
• Voltage – 2.7–3.6V L
• Density – 256Mb 256
• Device stacking – Monolithic A
• Device generation B
• Die revision A
• Pin configuration – RESET# and HOLD# 8
• Sector size – 64KB E
• Packages – JEDEC-standard, RoHS- compliant – 24-ball T-PBGA 05/6mm × 8mm (5 × 5 array) – 24-ball T-PBGA 05/6mm × 8mm (4 × 6 array) – 16-pin SOP2, 300 mils (SO16W, SO16-Wide, SOIC-16) SF – W-PDFN-8 6mm × 5mm (MLP8 6mm × 5mm) – W-PDFN-8 8mm × 6mm (MLP8 8mm × 6mm)
• Security features – Standard security 0
• Special options – Standard S – Automotive A
• Operating temperature range – From –40°C to +85°C IT – From –40°C to +105°C AT – From –40°C to +125°C UT 256Mb, 3V Multiple I/O Serial Flash Memory

mt25q-qljs-L256-ABA-xxT.pdf - Rev. K 07/18 EN 1 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice.

Micron Serial NOR Flash devices are available in different configurations and densities. Verify valid part numbers by using Micron’s part catalog search at www.micron.com. To compare features and specifications by device type, visit www.micron.com/products. Contact the factory for devices not found. Figure 1: Part Number Ordering Information Production Status Blank = Production ES = Engineering samples QS = Qualification samples Operating Temperature IT = –40°C to +85°C AT = –40°C to +105°C UT = –40°C to +125°C Special Options S = Standard A = Automotive grade AEC-Q100 Security Features 0 = Standard default security Package Codes 12 = 24-ball T-PBGA, 05/6 x 8mm (5 x 5 array) 14 = 24-ball T-PBGA, 05/6 x 8mm (4 x 6 array) SC = 8-pin SOP2, 150 mils SE = 8-pin SOP2, 208 mils SF = 16-pin SOP2, 300 mils W7 = 8-pin W-PDFN, 6 x 5mm W9 = 8-pin W-PDFN, 8 x 6mm 5x = WLCSP package 1 Sector size E = 64KB sectors, 4KB and 32KB subsectors Micron Technology Part Family 25Q = SPI NOR Voltage L = 2.7–3.6V U = 1.7–2.0V Density 064 = 64Mb (8MB) 128 = 128Mb (16MB) 256 = 256Mb (32MB) 512 = 512Mb (64MB) 01G = 1Gb (128MB) 02G = 2Gb (256MB) Stack A = 1 die/1 S# B = 2 die/1 S# C = 4 die/1 S# Device Generation B = 2nd generation Die Revision A = Rev. A B = Rev. B Pin Configuration Option 1 = HOLD# pin 3 = RESET# pin 8 = RESET# and HOLD# pin MT 25Q L xxx A BA 1 E SF IT0- S ES Note: 1. WLCSP package codes, package size, and availability are density-specific. Contact the factory for availability. 256Mb, 3V Multiple I/O Serial Flash Memory mt25q-qljs-L256-ABA-xxT.pdf - Rev. K 07/18 EN 2 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

256Mb, 3V Multiple I/O Serial Flash Memory mt25q-qljs-L256-ABA-xxT.pdf - Rev. K 07/18 EN 4 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

256Mb, 3V Multiple I/O Serial Flash Memory mt25q-qljs-L256-ABA-xxT.pdf - Rev. K 07/18 EN 7 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Important Notes and Warnings Micron Technology, Inc. ("Micron") reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions. This document supersedes and replaces all information supplied prior to the publication hereof. You may not rely on any information set forth in this docu- ment if you obtain the product described herein from any unauthorized distributor or other source not authorized by Micron. Automotive Applications. Products are not designed or intended for use in automotive applications unless specifi- cally designated by Micron as automotive-grade by their respective data sheets. Distributor and customer/distrib- utor shall assume the sole risk and liability for and shall indemnify and hold Micron harmless against all claims, costs, damages, and expenses and reasonable attorneys' fees arising out of, directly or indirectly, any claim of product liability, personal injury, death, or property damage resulting directly or indirectly from any use of non- automotive-grade products in automotive applications. Customer/distributor shall ensure that the terms and con- ditions of sale between customer/distributor and any customer of distributor/customer (1) state that Micron products are not designed or intended for use in automotive applications unless specifically designated by Micron as automotive-grade by their respective data sheets and (2) require such customer of distributor/customer to in- demnify and hold Micron harmless against all claims, costs, damages, and expenses and reasonable attorneys' fees arising out of, directly or indirectly, any claim of product liability, personal injury, death, or property damage resulting from any use of non-automotive-grade products in automotive applications. Critical Applications. Products are not authorized for use in applications in which failure of the Micron compo- nent could result, directly or indirectly in death, personal injury, or severe property or environmental damage ("Critical Applications"). Customer must protect against death, personal injury, and severe property and environ- mental damage by incorporating safety design measures into customer's applications to ensure that failure of the Micron component will not result in such harms. Should customer or distributor purchase, use, or sell any Micron component for any critical application, customer and distributor shall indemnify and hold harmless Micron and its subsidiaries, subcontractors, and affiliates and the directors, officers, and employees of each against all claims, costs, damages, and expenses and reasonable attorneys' fees arising out of, directly or indirectly, any claim of product liability, personal injury, or death arising in any way out of such critical application, whether or not Mi- cron or its subsidiaries, subcontractors, or affiliates were negligent in the design, manufacture, or warning of the Micron product. Customer Responsibility. Customers are responsible for the design, manufacture, and operation of their systems, applications, and products using Micron products. ALL SEMICONDUCTOR PRODUCTS HAVE INHERENT FAIL- URE RATES AND LIMITED USEFUL LIVES. IT IS THE CUSTOMER'S SOLE RESPONSIBILITY TO DETERMINE WHETHER THE MICRON PRODUCT IS SUITABLE AND FIT FOR THE CUSTOMER'S SYSTEM, APPLICATION, OR PRODUCT . Customers must ensure that adequate design, manufacturing, and operating safeguards are included in customer's applications and products to eliminate the risk that personal injury, death, or severe property or en- vironmental damages will result from failure of any semiconductor component. Limited Warranty. In no event shall Micron be liable for any indirect, incidental, punitive, special or consequential damages (including without limitation lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort, warranty, breach of contract or other legal theory, unless explicitly stated in a written agreement executed by Micron's duly authorized representative. 256Mb, 3V Multiple I/O Serial Flash Memory Important Notes and Warnings CCMTD-1725822587-3368 mt25q-qljs-L256-ABA-xxT.pdf - Rev. K 07/18 EN 8 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

The MT25Q is a high-performance multiple input/output serial Flash memory device. It features a high-speed SPI-compatible bus interface, execute-in-place (XIP) functionali- ty, advanced write protection mechanisms, and extended address access. Innovative, high-performance, dual and quad input/output commands enable double or quadru- ple the transfer bandwidth for READ and PROGRAM operations. Figure 2: Block Diagram HOLD# Control logic High voltage generator Memory Address register and counter 256 byte data buffer 256 bytes (page size) X decoder Y decoder C Status register

64 OTP bytes

RESET# Note: 1. Each page of memory can be individually programmed, but the device is not page-eras- able. 256Mb, 3V Multiple I/O Serial Flash Memory Device Description CCMTD-1725822587-3368 mt25q-qljs-L256-ABA-xxT.pdf - Rev. K 07/18 EN 9 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Figure 3: Logic Diagram DQ[3:0] V CC C V SS RESET# HOLD# Notes: 1. Depending on the selected device (see Part Numbering Ordering Information), DQ3 = DQ3/RESET# or DQ3/HOLD#. 2. A separate RESET pin is available on dedicated part numbers (see Part Numbering Order- ing Information). Advanced Security Protection The device offers an advanced security protection scheme where each sector can be in- dependently locked, by either volatile or nonvolatile locking features. The nonvolatile locking configuration can also be locked, as well password-protected. See Block Protec- tion Settings and Sector and Password Protection for more details. 256Mb, 3V Multiple I/O Serial Flash Memory Device Description CCMTD-1725822587-3368 mt25q-qljs-L256-ABA-xxT.pdf - Rev. K 07/18 EN 10 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Signal Assignments – Package Code: 12 Figure 4: 24-Ball T-BGA, 5 x 5 (Balls Down) A B C D E 1 2 3 4 5 MT25QXXXXXXX 8E12-XXXX RESET# V CC W#/DQ2 DQ3/HOLD# RFU NC C DQ1 RFU RFU V SS RFU DQ0 RFU RFU RFU RFU RFU RFU RFU RFU RFU RFU A B C D E 1 2 3 4 5 MT25QXXXXXXX 1E12-XXXX DNU V CC W#/DQ2 DQ3/HOLD# RFU NC C DQ1 RFU RFU V SS RFU DQ0 RFU RFU RFU RFU RFU RFU RFU RFU RFU RFU A B C D E 1 2 3 4 5 MT25QXXXXXXX 3E12-XXXX DNU V CC W#/DQ2 DQ3/RESET# RFU NC C DQ1 RFU RFU V SS RFU DQ0 RFU RFU RFU RFU RFU RFU RFU RFU RFU RFU Notes: 1. RESET# or HOLD# signals can share ball D4 with DQ3, depending on the selected device (see Part Numbering Ordering Information). When using single and dual I/O commands on these parts, DQ3 must be driven HIGH by the host, or an external pull-up resistor must be placed on the PCB, in order to avoid allowing the HOLD# or RESET# input to float. 2. Ball A4 = RESET# or DNU, depending on the part number. This signal has an internal pull-up resistor and may be left unconnected if not used. 256Mb, 3V Multiple I/O Serial Flash Memory Signal Assignments – Package Code: 12 CCMTD-1725822587-3368 mt25q-qljs-L256-ABA-xxT.pdf - Rev. K 07/18 EN 11 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Signal Assignments – Package Code: 14 Figure 5: 24-Ball TBGA, 4 x 6 (Balls Down) A B C D E F 1 2 3 4 MT25QXXXXXXX 8 E14-XXXX RESET# V CC W#/DQ2 DQ3/HOLD# NC NC NC C DQ1 NC NC NC V SS NC DQ0 NC NC NC NC NC NC NC NC A B C D E F 1 2 3 4 MT25QXXXXXXX 1 E14-XXXX DNU V CC W#/DQ2 DQ3/HOLD# NC NC NC C DQ1 NC NC NC V SS NC DQ0 NC NC NC NC NC NC NC NC A B C D E F 1 2 3 4 MT25QXXXXXXX 3 E14-XXXX DNU V CC W#/DQ2 DQ3/RESET# NC NC NC C DQ1 NC NC NC V SS NC DQ0 NC NC NC NC NC NC NC NC Notes: 1. RESET# or HOLD# signals can share ball D4 with DQ3, depending on the selected device (see Part Numbering Ordering Information). When using single and dual I/O commands on these parts, DQ3 must be driven HIGH by the host, or an external pull-up resistor must be placed on the PCB, in order to avoid allowing the HOLD# or RESET# input to float. 2. Ball A4 = RESET# or DNU, depending on the part number. This signal has an internal pull-up resistor and may be left unconnected if not used. 256Mb, 3V Multiple I/O Serial Flash Memory Signal Assignments – Package Code: 14 CCMTD-1725822587-3368 mt25q-qljs-L256-ABA-xxT.pdf - Rev. K 07/18 EN 12 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Signal Assignments – Package Code: SF Figure 6: 16-Pin, Plastic Small Outline – SO16 (Top View) C DQ0 V SS W#/DQ2 DQ3/HOLD# V CC RESET# DNU DNU DNU DNU DNU DNU DNU C DQ0 V SS W#/DQ2 DNU DNU DNU DNU C DQ0 V SS W#/DQ2 DNU DNU DNU DNU DQ1 DQ3/HOLD# V CC DNU DNU DNU DNU DQ1 DQ3/RESET# V CC DNU DNU DNU DNU DQ1 MT25QXXXXXXX 8 EXX-XXXX MT25QXXXXXXX 3 EXX-XXXX MT25QXXXXXXX 1 EXX-XXXX Notes: 1. RESET# or HOLD# signals can share pin 1 with DQ3, depending on the selected device (see Part Numbering Ordering Information). When using single and dual I/O commands on these parts, DQ3 must be driven HIGH by the host, or an external pull-up resistor must be placed on the PCB, in order to avoid allowing the HOLD# or RESET# input to float. 2. Pin 3 = RESET# or DNU, depending on the part number. This signal has an internal pull- up resistor and may be left unconnected if not used. 256Mb, 3V Multiple I/O Serial Flash Memory Signal Assignments – Package Code: SF CCMTD-1725822587-3368 mt25q-qljs-L256-ABA-xxT.pdf - Rev. K 07/18 EN 13 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Signal Assignments – Package Code: W7, W9 Figure 7: 8-Pin, SOP2 or W-PDFN (Top View) DQ1 W#/DQ2 V SS MT25QXXXXXXX 1 EXX-XXXX MT25QXXXXXXX 3 EXX-XXXX DQ1 W#/DQ2 V SS V CC DQ3/HOLD# C DQ0 V CC DQ3/RESET# C DQ0 Notes: 1. RESET# or HOLD# signals can share Pin 7 with DQ3, depending on the selected device (see Part Numbering Ordering Information). When using single and dual I/O commands on these parts, DQ3 must be driven high by the host, or an external pull-up resistor must be placed on the PCB, in order to avoid allowing the HOLD# or RESET# input to float. 2. On the underside of the W-PDFN package, there is an exposed central pad that is pulled internally to VSS. It can be left floating or can be connected to VSS. It must not be con- nected to any other voltage or signal line on the PCB. 3. MT25QXXXXXXX8EXX-XXXX is not available on 8 pin package. 256Mb, 3V Multiple I/O Serial Flash Memory Signal Assignments – Package Code: W7, W9 CCMTD-1725822587-3368 mt25q-qljs-L256-ABA-xxT.pdf - Rev. K 07/18 EN 14 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

The signal description table below is a comprehensive list of signals for the MT25Q fam- ily devices. All signals listed may not be supported on this device. See Signal Assign- ments for information specific to this device. Table 1: Signal Descriptions Symbol Type Description S# Input Chip select: When S# is driven HIGH, the device will enter standby mode, unless an internal PROGRAM, ERASE, or WRITE STATUS REGISTER cycle is in progress. All other input pins are ig- nored and the output pins are tri-stated. On parts with the pin configuration offering a dedica- ted RESET# pin, however, the RESET# input pin remains active even when S# is HIGH. Driving S# LOW enables the device, placing it in the active mode. After power-up, a falling edge on S# is required prior to the start of any command. C Input Clock: Provides the timing of the serial interface. Command inputs are latched on the rising edge of the clock. In STR commands or protocol, address and data inputs are latched on the rising edge of the clock, while data is output on the falling edge of the clock. In DTR com- mands or protocol, address and data inputs are latched on both edges of the clock, and data is output on both edges of the clock. RESET# Input RESET#: When RESET# is driven LOW, the device is reset and the outputs are tri-stated. If RE- SET# is driven LOW while an internal WRITE, PROGRAM, or ERASE operation is in progress, da- ta may be lost. The RESET# functionality can be disabled using bit 4 of the nonvolatile configu- ration register or bit 4 of the enhanced volatile configuration register. For pin configurations that share the DQ3 pin with RESET#, the RESET# functionality is disabled in QIO-SPI mode. HOLD# Input HOLD: Pauses serial communications with the device without deselecting or resetting the de- vice. Outputs are tri-stated and inputs are ignored. The HOLD# functionality can be disabled using bit 4 of the nonvolatile configuration register or bit 4 of the enhanced volatile configura- tion register. For pin configurations that share the DQ3 pin with HOLD#, the HOLD# functionality is disabled in QIO-SPI mode or when DTR operation is enabled. W# Input Write protect: Freezes the status register in conjunction with the enable/disable bit of the sta- tus register. When the enable/disable bit of the status register is set to 1 and the W# signal is driven LOW, the status register nonvolatile bits become read-only and the WRITE STATUS REG- ISTER operation will not execute. During the extended-SPI protocol with QOFR and QIOFR in- structions, and with QIO-SPI protocol, this pin function is an input/output as DQ2 functionality. This signal does not have internal pull-ups, it cannot be left floating and must be driven, even if none of W#/DQ2 function is used. DQ[3:0] I/O Serial I/O: The bidirectional DQ signals transfer address, data, and command information. When using legacy (x1) SPI commands in extended I/O protocol (XIO-SPI), DQ0 is an input and DQ1 is an output. DQ[3:2] are not used. When using dual commands in XIO-SPI or when using DIO-SPI, DQ[1:0] are I/O. DQ[3:2] are not used. When using quad commands in XIO-SPI or when using QIO-SPI, DQ[3:0] are I/O. VCC Supply Core and I/O power supply. 256Mb, 3V Multiple I/O Serial Flash Memory Signal Descriptions CCMTD-1725822587-3368 mt25q-qljs-L256-ABA-xxT.pdf - Rev. K 07/18 EN 15 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Table 1: Signal Descriptions (Continued) Symbol Type Description VSS Supply Core and I/O ground connection. DNU – Do not use: Do not connect to any other signal, or power supply; must be left floating. RFU – Reserved for future use: Reserved by Micron for future device functionality and enhance- ment. Recommend that these be left floating. May be connected internally, but external con- nections will not affect operation. NC – No connect: No internal connection; can be driven or floated. 256Mb, 3V Multiple I/O Serial Flash Memory Signal Descriptions CCMTD-1725822587-3368 mt25q-qljs-L256-ABA-xxT.pdf - Rev. K 07/18 EN 16 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Package Dimensions – Package Code: 12 Figure 8: 24-Ball T-PBGA (5 x 5 ball grid array) – 6mm x 8mm 0.3 ±0.05 1.1 ±0.1

4 CTR

6 ±0.1

1 TYP

8 ±0.1 0.1 A A 24X Ø0.4 Dimensions apply to solder balls post-reflow on Ø0.40 SMD ball pads. A B C D E 135 24 Notes: 1. All dimensions are in millimeters. 2. See Part Number Ordering Information for complete package names and details. 256Mb, 3V Multiple I/O Serial Flash Memory Package Dimensions – Package Code: 12 CCMTD-1725822587-3368 mt25q-qljs-L256-ABA-xxT.pdf - Rev. K 07/18 EN 17 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Package Dimensions – Package Code: 14 Figure 9: 24-Ball T-PBGA (24b05) – 6mm x 8mm

0.2 MIN

1.08 ±0.12

3 CTR

6 ±0.1 8 ±0.1 0.1 A A 24X Ø0.4 Dimensions apply to solder balls post- reflow on Ø0.4 SMD ball pads.

5 CTR

A B C D E F 13 24 Notes: 1. All dimensions are in millimeters. 2. See Part Number Ordering Information for complete package names and details. 256Mb, 3V Multiple I/O Serial Flash Memory Package Dimensions – Package Code: 14 CCMTD-1725822587-3368 mt25q-qljs-L256-ABA-xxT.pdf - Rev. K 07/18 EN 18 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Package Dimensions – Package Code: SF Figure 10: 16-Pin SOP2 – 300 Mils Body Width

0.23 MIN/

0.32 MAX

0.40 MIN/

1.27 MAX

0.20 ±0.12.5 ±0.15 10.30 ±0.20 7.50 ±0.10

10.00 MIN/

10.65 MAX

0.33 MIN/

0.51 MAX

0.1 Z 0° MIN/8° MAX

1.27 TYP

h x 45° Z Notes: 1. All dimensions are in millimeters. 2. See Part Number Ordering Information for complete package names and details. 256Mb, 3V Multiple I/O Serial Flash Memory Package Dimensions – Package Code: SF CCMTD-1725822587-3368 mt25q-qljs-L256-ABA-xxT.pdf - Rev. K 07/18 EN 19 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Package Dimensions – Package Code: W7 Figure 11: W-PDFN-8 (MLP8) – 6mm x 5mm 5 ±0.1 6 ±0.1

0 MIN

0.75 ±0.05 1.27 TYP 3 ±0.1 CTR 3 ±0.1 CTR 8X 0.4 ±0.05 CTR 8X 0.6 ±0.05 Pin A1 ID Pin A1 ID 3.81 CTR Exposed die attach pad. Seating plane 0.08 A A Notes: 1. All dimensions are in millimeters. 2. See Part Number Ordering Information for complete package names and details. 256Mb, 3V Multiple I/O Serial Flash Memory Package Dimensions – Package Code: W7 CCMTD-1725822587-3368 mt25q-qljs-L256-ABA-xxT.pdf - Rev. K 07/18 EN 20 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Package Dimensions – Package Code: W9 Figure 12: W-PDFN-8 (MLP8) – 8mm x 6mm Seating plane 0.08 AA 0.75 ±0.05 3.81 CTR 6 ±0.1 8X 0.5 ±0.05 8 ±0.1 1.27 TYP 8X 0.4 ±0.05 CTR Pin A1 ID 4.3 ±0.1 CTR 3.4 ±0.1 CTR Exposed die attach pad. Pin A1 ID Micron logo to be lazed. Notes: 1. All dimensions are in millimeters. 2. See Part Number Ordering Information for complete package names and details. 256Mb, 3V Multiple I/O Serial Flash Memory Package Dimensions – Package Code: W9 CCMTD-1725822587-3368 mt25q-qljs-L256-ABA-xxT.pdf - Rev. K 07/18 EN 21 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Memory Map – 256Mb Density Table 2: Memory Map Sector Subsector (32KB) Subsector (4KB) Address Range Start End 511 1023 8191 01FF F000h 01FF FFFFh ⋮ ⋮ ⋮ 8184 01FF 8000h 01FF 8FFFh 1022 8183 01FF 7000h 01FF 7FFFh ⋮ ⋮ ⋮ 8176 01FF 0000h 01FF 0FFFh 255 511 4095 00FF F000h 00FF FFFFh ⋮ ⋮ ⋮ 4088 00FF 8000h 00FF 8FFFh 510 4087 00FF 7000h 00FF 7FFFh ⋮ ⋮ ⋮ 4080 00FF 0000h 00FF 0FFFh 127 255 2047 007F F000h 007F FFFFh ⋮ ⋮ ⋮ 2040 007F 8000h 007F 8FFFh 254 2039 007F 7000h 007F 7FFFh ⋮ ⋮ ⋮ 2032 007F 0000h 007F 0FFFh 0 1 15 0000 F000h 0000 FFFFh ⋮ ⋮ ⋮ 8 0000 8000h 0000 8FFFh 0 7 0000 7000h 0000 7FFFh ⋮ ⋮ ⋮ 0 0000 0000h 0000 0FFFh Note: 1. See Part Number Ordering Information, Sector Size – Part Numbers table for options. 256Mb, 3V Multiple I/O Serial Flash Memory Memory Map – 256Mb Density CCMTD-1725822587-3368 mt25q-qljs-L256-ABA-xxT.pdf - Rev. K 07/18 EN 22 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Status register bits can be read from or written to using READ STATUS REGISTER or WRITE STATUS REGISTER commands, respectively. When the status register enable/ disable bit (bit 7) is set to 1 and W# is driven LOW, the status register nonvolatile bits become read-only and the WRITE STATUS REGISTER operation will not execute. The only way to exit this hardware-protected mode is to drive W# HIGH. Table 3: Status Register Bit Name Settings Description Notes

7 Status register

0 = Enabled (Default) 1 = Disabled Nonvolatile control bit: Used with W# to enable or disable writing to the status register.

5 Top/bottom 0 = Top (Default)

1 = Bottom Nonvolatile control bit: Determines whether the pro- tected memory area defined by the block protect bits starts from the top or bottom of the memory array. 6, 4:2 BP[3:0] See Protected Area ta- bles Nonvolatile control bit: Defines memory to be soft- ware protected against PROGRAM or ERASE operations. When one or more block protect bits is set to 1, a desig- nated memory area is protected from PROGRAM and ERASE operations.

1 Write enable latch 0 = Clear (Default)

1 = Set Volatile control bit: The device always powers up with this bit cleared to prevent inadvertent WRITE, PRO- GRAM, or ERASE operations. To enable these operations, the WRITE ENABLE operation must be executed first to set this bit.

0 Write in progress 0 = Ready (Default)

1 = Busy Volatile status bit: Indicates if one of the following command cycles is in progress: WRITE STATUS REGISTER WRITE NONVOLATILE CONFIGURATION REGISTER PROGRAM ERASE Notes: 1. The BULK ERASE command is executed only if all bits = 0. 2. Status register bit 0 is the inverse of flag status register bit 7. 256Mb, 3V Multiple I/O Serial Flash Memory Status Register CCMTD-1725822587-3368 mt25q-qljs-L256-ABA-xxT.pdf - Rev. K 07/18 EN 23 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Table 4: Protected Area Status Register Content Protected Area Top/Bottom BP3 BP2 BP1 BP0 64KB Sectors 0 0 0 0 0 None 0 0 0 0 1 511:511 0 0 0 1 0 511:510 0 0 0 1 1 511:508 0 0 1 0 0 511:504 0 0 1 0 1 511:496 0 0 1 1 0 511:480 0 0 1 1 1 511:448 0 1 0 0 0 511:384 0 1 0 0 1 511:256 0 1 0 1 0 511:0 0 1 0 1 1 511:0 0 1 1 0 0 511:0 0 1 1 0 1 511:0 0 1 1 1 0 511:0 0 1 1 1 1 511:0 1 0 0 0 0 None 1 0 0 0 1 0:0 1 0 0 1 0 1:0 1 0 0 1 1 3:0 1 0 1 0 0 7:0 1 0 1 0 1 15:0 1 0 1 1 0 31:0 1 0 1 1 1 63:0 1 1 0 0 0 127:0 1 1 0 0 1 255:0 1 1 0 1 0 511:0 1 1 0 1 1 511:0 1 1 1 0 0 511:0 1 1 1 0 1 511:0 1 1 1 1 0 511:0 1 1 1 1 1 511:0 256Mb, 3V Multiple I/O Serial Flash Memory Status Register CCMTD-1725822587-3368 mt25q-qljs-L256-ABA-xxT.pdf - Rev. K 07/18 EN 24 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Flag status register bits are read by using READ FLAG STATUS REGISTER command. All bits are volatile and are reset to zero on power-up. Status bits are set and reset automatically by the internal controller. Error bits must be cleared through the CLEAR STATUS REGISTER command. Table 5: Flag Status Register Bit Name Settings Description

7 Program or

0 = Busy 1 = Ready Status bit: Indicates whether one of the following command cycles is in progress: WRITE STATUS REGISTER, WRITE NONVOLATILE CONFIGURATION REGISTER, PROGRAM, or ERASE.

6 Erase suspend 0 = Clear

1 = Suspend Status bit: Indicates whether an ERASE operation has been or is going to be suspended.

5 Erase 0 = Clear

1 = Failure or protection error Error bit: Indicates whether an ERASE operation has suc- ceeded or failed.

4 Program 0 = Clear

1 = Failure or protection error Error bit: Indicates whether a PROGRAM operation has suc- ceeded or failed. It indicates, also, whether a CRC check has succeeded or failed.

3 Reserved 0 Reserved

2 Program sus-

0 = Clear 1 = Suspend Status bit: Indicates whether a PROGRAM operation has been or is going to be suspended.

1 Protection 0 = Clear

1 = Failure or protection error Error bit: Indicates whether an ERASE or PROGRAM opera- tion has attempted to modify the protected array sector, or whether a PROGRAM operation has attempted to access the locked OTP space.

0 Addressing 0 = 3-byte addressing

1 = 4-byte addressing Status bit: Indicates whether 3-byte or 4-byte address mode is enabled. 256Mb, 3V Multiple I/O Serial Flash Memory Flag Status Register CCMTD-1725822587-3368 mt25q-qljs-L256-ABA-xxT.pdf - Rev. K 07/18 EN 25 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

The 3-byte address mode can only access 128Mb of memory. To access the full device in 3-byte address mode, the device includes an extended address register that indirectly provides a fourth address byte A[31:25]. The extended address register bit A0 operates as memory address bit A24 to select one of the two 128Mb segments of the memory array. If 4-byte addressing is enabled, the extended address register settings are ignored. Table 6: Extended Address Register Bit Name Settings Description 7:1 A[31:25] 0000000 Reserved

0 A24 1 = Highest 128Mb segment

0 = Lowest 128Mb segment (default) Enables specified 128Mb memory segment. The de- fault (lowest) setting can be changed to the high- est 128Mb segment using bit 1 of the nonvolatile configuration register. Figure 13: Memory Array Segments A24 = 0 A24 = 1 00FFFFFFh 00000000h 01FFFFFFh 01000000h The PROGRAM and ERASE operations act upon the 128Mb segment selected in the ex- tended address register. The BULK ERASE operation erases the entire device. The READ operation begins reading in the selected 128Mb segment, but is not bound by it. In a continuous READ, when the last byte of the segment is read, the next byte output is the first byte of the next segment. The operation wraps to 0000000h; therefore, a down- load of the whole array is possible with one READ operation. The value of the extended address register does not change when a READ operation crosses the selected 128Mb boundary. 256Mb, 3V Multiple I/O Serial Flash Memory Extended Address Register CCMTD-1725822587-3368 mt25q-qljs-L256-ABA-xxT.pdf - Rev. K 07/18 EN 26 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Internal Configuration Register The memory configuration is set by an internal configuration register that is not directly accessible to users. The user can change the default configuration at power up by using the WRITE NON- VOLATILE CONFIGURATION REGISTER. Information from the nonvolatile configura- tion register overwrites the internal configuration register during power-on or after a re- set. The user can change the configuration during operation by using the WRITE VOLATILE CONFIGURATION REGISTER or the WRITE ENHANCED VOLATILE CONFIGURATION REGISTER commands. Information from the volatile configuration registers overwrite the internal configuration register immediately after the WRITE command completes. Figure 14: Internal Configuration Register Register download is executed only during the power-on phase or after a reset, overwriting configuration register settings on the internal configuration register. Register download is executed after a WRITE VOLATILE OR ENHANCED VOLATILE CONFIGURATION REGISTER command, overwriting configuration register settings on the internal configuration register. Nonvolatile configuration register Internal configuration register Device behavior Volatile configuration register and enhanced volatile configuration register 256Mb, 3V Multiple I/O Serial Flash Memory Internal Configuration Register CCMTD-1725822587-3368 mt25q-qljs-L256-ABA-xxT.pdf - Rev. K 07/18 EN 27 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Nonvolatile Configuration Register This register is read from and written to using the READ NONVOLATILE CONFIGURA- TION REGISTER and the WRITE NONVOLATILE CONFIGURATION REGISTER com- mands, respectively. A register download is executed during power-on or after reset, overwriting the internal configuration register settings that determine device behavior. Table 7: Nonvolatile Configuration Register Bit Name Settings Description Notes 15:12 Number of dummy clock cy- cles 0000 = Identical to 1111 0001 = 1 0010 = 2 1101 = 13 1110 = 14 1111 = Default Sets the number of dummy clock cycles subse- quent to all FAST READ commands. (See the Command Set Table for default setting values.) 11:9 XIP mode at power-on reset 000 = XIP: Fast read 001 = XIP: Dual output fast read 010 = XIP: Dual I/O fast read 011 = XIP: Quad output fast read 100 = XIP: Quad I/O fast read 101 = Reserved 110 = Reserved 111 = Disabled (Default) Enables the device to operate in the selected XIP mode immediately after power-on reset. 8:6 Output driver strength 000 = Reserved 001 = 90 Ohms 010 = Reserved 011 = 45 Ohms 100 = Reserved 101 = 20 Ohms 110 = Reserved 111 = 30 Ohms (Default) Optimizes the impedance at VCC/2 output volt- age.

5 Double transfer

0 = Enabled 1 = Disabled (Default) Set DTR protocol as current one. Once enabled, all commands will work in DTR.

4 Reset/hold 0 = Disabled

1 = Enabled (Default) Enables or disables HOLD# or RESET# on DQ3.

3 Quad I/O

0 = Enabled 1 = Disabled (Default) Enables or disables quad I/O command input (4-4-4 mode).

2 Dual I/O

0 = Enabled 1 = Disabled (Default) Enables or disables dual I/O command input (2-2-2 mode). 1 128Mb segment select 0 = Highest 128Mb segment 1 = Lowest 128Mb segment (De- fault) Selects the power-on default 128Mb segment for 3-byte address operations. See also the extended address register. 256Mb, 3V Multiple I/O Serial Flash Memory Nonvolatile Configuration Register CCMTD-1725822587-3368 mt25q-qljs-L256-ABA-xxT.pdf - Rev. K 07/18 EN 28 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Table 7: Nonvolatile Configuration Register (Continued) Bit Name Settings Description Notes

0 Number of

0 = Enable 4-byte address mode 1 = Enable 3-byte address mode (Default) Defines the number of address bytes for a com- mand. Notes: 1. The number of cycles must be set to accord with the clock frequency, which varies by the type of FAST READ command (See Supported Clock Frequencies table). Insufficient dum- my clock cycles for the operating frequency causes the memory to read incorrect data. 2. When bits 2 and 3 are both set to 0, the device operates in quad I/O protocol. 256Mb, 3V Multiple I/O Serial Flash Memory Nonvolatile Configuration Register CCMTD-1725822587-3368 mt25q-qljs-L256-ABA-xxT.pdf - Rev. K 07/18 EN 29 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Volatile Configuration Register This register is read from and written to by the READ VOLATILE CONFIGURATION REGISTER and the WRITE VOLATILE CONFIGURATION REGISTER commands, respec- tively. A register download is executed after these commands, overwriting the internal configuration register settings that determine device memory behavior. Table 8: Volatile Configuration Register Bit Name Settings Description Notes 7:4 Number of dummy clock cycles 0000 = Identical to 1111 0001 = 1 0010 = 2 1101 = 13 1110 = 14 1111 = Default Sets the number of dummy clock cycles subsequent to all FAST READ commands. (See the Command Set Table for default setting values.)

3 XIP 0 = Enable

1 = Disable (Default) Enables or disables XIP. 2 Reserved 0 0b = Fixed value. 1:0 Wrap 00 = 16-byte boundary aligned 16-byte wrap: Output data wraps within an aligned 16-byte boundary starting from the 3-byte address issued after the command code. 01 = 32-byte boundary aligned 32-byte wrap: Output data wraps within an aligned 32-byte boundary starting from the 3-byte address issued after the command code. 10 = 64-byte boundary aligned 64-byte wrap: Output data wraps within an aligned 64-byte boundary starting from the 3-byte address issued after the command code. 11 = Continuous (Default) Continuously sequences addresses through the entire array. Notes: 1. The number of cycles must be set according to and sufficient for the clock frequency, which varies by the type of FAST READ command, as shown in the Supported Clock Fre- quencies table. An insufficient number of dummy clock cycles for the operating frequen- cy causes the memory to read incorrect data. 2. See the Sequence of Bytes During Wrap table. Table 9: Sequence of Bytes During Wrap Starting Address 16-Byte Wrap 32-Byte Wrap 64-Byte Wrap 256Mb, 3V Multiple I/O Serial Flash Memory Volatile Configuration Register CCMTD-1725822587-3368 mt25q-qljs-L256-ABA-xxT.pdf - Rev. K 07/18 EN 30 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Supported Clock Frequencies Table 10: Clock Frequencies – STR (in MHz) Notes apply to entire table Number of Dummy Clock Cycles FAST READ DUAL OUTPUT FAST READ DUAL I/O FAST READ QUAD OUTPUT FAST READ QUAD I/O FAST READ 1 94 79 60 44 39 2 112 97 77 61 48 3 129 106 86 78 58 4 133 115 97 97 69 5 133 125 106 106 78 6 133 133 115 115 86 7 133 133 125 125 97 8 133 133 133 133 106 9 133 133 133 133 115 10 133 133 133 133 125 11 : 14 133 133 133 133 133 Notes: 1. Values are guaranteed by characterization and not 100% tested in production. 2. A tuning data pattern (TDP) capability provides applications with data patterns for ad- justing the data latching point at the host end when the clock frequency is set higher than 133 MHz in STR mode and higher than 66 MHz in double transfer rate (DTR) mode. For additional details, refer to TN-25-07: Tuning Data Pattern for MT25Q and MT25T De- vices. 256Mb, 3V Multiple I/O Serial Flash Memory Volatile Configuration Register CCMTD-1725822587-3368 mt25q-qljs-L256-ABA-xxT.pdf - Rev. K 07/18 EN 31 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Table 11: Clock Frequencies – DTR (in MHz) Notes apply to entire table Number of Dummy Clock Cycles FAST READ DUAL OUTPUT FAST READ DUAL I/O FAST READ QUAD OUTPUT FAST READ QUAD I/O FAST READ 1 59 45 40 26 20 2 73 59 49 40 30 3 82 68 59 59 39 4 90 76 65 65 49 5 90 83 75 75 58 6 90 90 83 83 68 7 90 90 90 90 78 8 90 90 90 90 85 9 90 90 90 90 90 10 : 14 90 90 90 90 90 Notes: 1. Values are guaranteed by characterization and not 100% tested in production. 2. A tuning data pattern (TDP) capability provides applications with data patterns for ad- justing the data latching point at the host end when the clock frequency is set higher than 133 MHz in STR mode and higher than 66 MHz in double transfer rate (DTR) mode. For additional details, refer to TN-25-07: Tuning Data Pattern for MT25Q and MT25T De- vices. 256Mb, 3V Multiple I/O Serial Flash Memory Volatile Configuration Register CCMTD-1725822587-3368 mt25q-qljs-L256-ABA-xxT.pdf - Rev. K 07/18 EN 32 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Enhanced Volatile Configuration Register This register is read from and written to using the READ ENHANCED VOLATILE CON- FIGURATION REGISTER and the WRITE ENHANCED VOLATILE CONFIGURATION REGISTER commands, respectively. A register download is executed after these com- mands, overwriting the internal configuration register settings that determine device memory behavior. Table 12: Enhanced Volatile Configuration Register Bit Name Settings Description Notes

7 Quad I/O protocol 0 = Enabled

1 = Disabled (Default) Enables or disables quad I/O command input (4-4-4 mode).

6 Dual I/O protocol 0 = Enabled

1 = Disabled (Default) Enables or disables dual I/O command input (2-2-2 mode).

5 Double transfer rate

0 = Enabled 1 = Disabled (Default, single transfer rate) Set DTR protocol as current one. Once enabled, all commands will work in DTR. 1 = Enabled (Default) Enables or disables HOLD# or RESET# on DQ3. (Available only on specified part numbers.)

3 Reserved 1

2:0 Output driver strength 000 = Reserved 001 = 90 ohms 010 = Reserved 011 = 45 ohms 100 = Reserved 101 = 20 ohms 110 = Reserved 111 = 30 ohms (De- fault) Optimizes the impedance at VCC/2 output volt- age. Note: 1. When bits 6 and 7 are both set to 0, the device operates in quad I/O protocol. When ei- ther bit 6 or 7 is set to 0, the device operates in dual I/O or quad I/O respectively. When a bit is set, the device enters the selected protocol immediately after the WRITE EN- HANCED VOLATILE CONFIGURATION REGISTER command. The device returns to the de- fault protocol after the next power-on or reset. Also, the rescue sequence or another WRITE ENHANCED VOLATILE CONFIGURATION REGISTER command will return the de- vice to the default protocol. 256Mb, 3V Multiple I/O Serial Flash Memory Enhanced Volatile Configuration Register CCMTD-1725822587-3368 mt25q-qljs-L256-ABA-xxT.pdf - Rev. K 07/18 EN 33 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Security registers enable sector and password protection on multiple levels using non- volatile and volatile register and bit settings (shown below). The applicable register ta- bles follow. Figure 15: Sector and Password Protection . nn Sector Protection Register 15 1314 2 01 Global Freeze Bit n 1st sector 0 2nd sector 3rd sector Last sector Memory Sectors Volatile Lock Bits locked locked locked locked Nonvolatile Lock Bits (See Note 1) (See Note 2) (See Note 3) (See Note 4) Notes: 1. Sector protection register. This 16-bit nonvolatile register includes two active bits[2:1] to enable sector and password protection. 2. Global freeze bit. This volatile bit protects the settings in all nonvolatile lock bits. 3. Nonvolatile lock bits. Each nonvolatile bit corresponds to and provides nonvolatile protection for an individual memory sector, which remains locked (protection enabled) until its corresponding bit is cleared to 1. 4. Volatile lock bits. Each volatile bit corresponds to and provides volatile protection for an individual memory sector, which is locked temporarily (protection is cleared when the device is reset or powered down). 5. The first and last sectors will have volatile protections at the 4KB subsector level. Each 4KB subsector in these sectors can be individually locked by volatile lock bits setting; nonvolatile protections granularity remain at the sector level. 256Mb, 3V Multiple I/O Serial Flash Memory Security Registers CCMTD-1725822587-3368 mt25q-qljs-L256-ABA-xxT.pdf - Rev. K 07/18 EN 34 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Sector Protection Security Register Table 13: Sector Protection Register Bits Name Settings Description Notes 15:3 Reserved 1 = Default –

2 Password

1 = Disabled (Default) 0 = Enabled Nonvolatile bit: When set to 1, password protection is dis- abled. When set to 0, password protection is enabled per- manently; the 64-bit password cannot be retrieved or reset. 1, 2

1 Sector

1 = Enabled, with password protection (Default) 0 = Enabled, without pass- word protection Nonvolatile bit: When set to 1, nonvolatile lock bits can be set to lock/unlock their corresponding memory sectors; bit 2 can be set to 0, enabling password protection perma- nently. When set to 0, nonvolatile lock bits can be set to lock/ unlock their corresponding memory sectors; bit 2 must re- main set to 1, disabling password protection permanently. 1, 3, 4

0 Reserved 1 = Default –

Notes: 1. Bits 2 and 1 are user-configurable, one-time-programmable, and mutually exclusive in that only one of them can be set to 0. It is recommended that one of the bits be set to 0 when first programming the device. 2. The 64-bit password must be programmed and verified before this bit is set to 0 because after it is set, password changes are not allowed, thus providing protection from mali- cious software. When this bit is set to 0, a 64-bit password is required to reset the global freeze bit from 0 to 1. In addition, if the password is incorrect or lost, the global freeze bit can no longer be set and nonvolatile lock bits cannot be changed. (See the Sector and Password Protection figure and the Global Freeze Bit Definition table). 3. Whether this bit is set to 1 or 0, it enables programming or erasing nonvolatile lock bits (which provide memory sector protection). The password protection bit must be set be- forehand because setting this bit will either enable password protection permanently (bit 2 = 0) or disable password protection permanently (bit 1 = 0). 4. By default, all sectors are unlocked when the device is shipped from the factory. Sectors are locked, unlocked, read, or locked down as explained in the Nonvolatile and Volatile Lock Bits table and the Volatile Lock Bit Register Bit Definitions table. Table 14: Global Freeze Bit Bits Name Settings Description 7:1 Reserved 0 Bit values are 0

0 Global

1 = Disabled (Default) 0 = Enabled Volatile bit: When set to 1, all nonvolatile lock bits can be set to enable or disable locking their corresponding memory sectors. When set to 0, nonvolatile lock bits are protected from PROGRAM or ERASE commands. This bit should not be set to 0 until the nonvolatile lock bits are set. Note: 1. The READ GLOBAL FREEZE BIT command enables reading this bit. When password pro- tection is enabled, this bit is locked upon device power-up or reset. It cannot be changed without the password. After the password is entered, the UNLOCK PASSWORD command resets this bit to 1, enabling programing or erasing the nonvolatile lock bits. After the bits are changed, the WRITE GLOBAL FREEZE BIT command sets this bit to 0, protecting the nonvolatile lock bits from PROGRAM or ERASE operations. 256Mb, 3V Multiple I/O Serial Flash Memory Sector Protection Security Register CCMTD-1725822587-3368 mt25q-qljs-L256-ABA-xxT.pdf - Rev. K 07/18 EN 35 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Nonvolatile and Volatile Sector Lock Bits Security Table 15: Nonvolatile and Volatile Lock Bits Bit Details Nonvolatile Lock Bit Volatile Lock Bit Description Each sector of memory has one corresponding non- volatile lock bit Each sector of memory has one corresponding vola- tile lock bit; this bit is the sector write lock bit descri- bed in the Volatile Lock Bit Register table. Function When set to 0, locks and protects its corresponding memory sector from PROGRAM or ERASE operations. Because this bit is nonvolatile, the sector remains locked, protection enabled, until the bit is cleared to When set to 1, locks and protects its corresponding memory sector from PROGRAM or ERASE operations. Because this bit is volatile, protection is temporary. The sector is unlocked, protection disabled, upon de- vice reset or power-down. Settings 1 = Lock disabled 0 = Lock enabled 0 = Lock disabled 1 = Lock enabled Enabling protection The bit is set to 0 by the WRITE NONVOLATILE LOCK BITS command, enabling protection for designated locked sectors. Programming a sector lock bit re- quires the typical byte programming time. The bit is set to 1 by the WRITE VOLATILE LOCK BITS command, enabling protection for designated locked sectors. Disabling protection All bits are cleared to 1 by the ERASE NONVOLATILE LOCK BITS command, unlocking and disabling pro- tection for all sectors simultaneously. Erasing all sec- tor lock bits requires typical sector erase time. All bits are set to 0 upon reset or power-down, un- locking and disabling protection for all sectors. Reading the bit Bits are read by the READ NONVOLATILE LOCK BITS command. Bits are read by the READ VOLATILE LOCK BITS com- mand. Volatile Lock Bit Security Register One volatile lock bit register is associated with each sector of memory. It enables the sector to be locked, unlocked, or locked-down with the WRITE VOLATILE LOCK BITS command, which executes only when sector lock down (bit 1) is set to 0. Each register can be read with the READ VOLATILE LOCK BITS command. This register is compatible with and provides the same locking capability as the lock register in the Micron N25Q SPI NOR family. Table 16: Volatile Lock Bit Register Bit Name Settings Description 7:2 Reserved 0 Bit values are 0. 0 = Lock-down disabled (Default) 1 = Lock-down enabled Volatile bit: Device always powers up with this bit set to 0 so that sector lock down and sector write lock bits can be set to 1. When this bit set to 1, neither of the two volatile lock bits can be written to until the next power cycle, hardware, or software reset.

0 Sector

0 = Write lock disabled (Default) 1 = Write lock enabled Volatile bit: Device always powers up with this bit set to 0 so that PROGRAM and ERASE operations in this sector can be executed and sector content modified. When this bit is set to 1, PROGRAM and ERASE operations in this sector are not executed. 256Mb, 3V Multiple I/O Serial Flash Memory Nonvolatile and Volatile Sector Lock Bits Security CCMTD-1725822587-3368 mt25q-qljs-L256-ABA-xxT.pdf - Rev. K 07/18 EN 36 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

The device ID data shown in the tables here is read by the READ ID and MULTIPLE I/O READ ID operations. Table 17: Device ID Data Byte# Name Content Value Assigned By Manufacturer ID (1 byte total)

1 Manufacturer ID (1 byte) 20h JEDEC

Device ID (2 bytes total)

2 Memory type (1 byte) BAh = 3V Manufacturer

BBh = 1.8V

3 Memory capacity (1 byte) 22h = 2Gb

21h = 1Gb 20h = 512Mb 19h = 256Mb 18h = 128Mb 17h = 64Mb Unique ID (17 bytes total)

4 Indicates the number of remaining ID bytes

(1 byte) 10h Factory

5 Extended device ID (1 byte) See Extended Device ID table

6 Device configuration information (1 byte) 00h = Standard

7:20 Customized factory data (14 bytes) Unique ID code (UID) Table 18: Extended Device ID Data, First Byte Bit 7 Bit 6 Bit 51 Bit 4 Bit 3 Bit 22 Bit 1 Bit 0 Reserved Device Generation 1 = 2nd generation 1 = Alternate BP scheme 0 = Standard BP scheme Reserved HOLD#/RESET#: 0 = HOLD 1 = RESET Additional HW RESET#: 1 = Available 0 = Not available Sector size: 00 = Uniform 64KB Notes: 1. For alternate BP scheme information, contact the factory. 2. Available for specific part numbers. See Part Number Ordering Information for details. 256Mb, 3V Multiple I/O Serial Flash Memory Device ID Data CCMTD-1725822587-3368 mt25q-qljs-L256-ABA-xxT.pdf - Rev. K 07/18 EN 37 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Serial Flash Discovery Parameter Data The serial Flash discovery parameter (SFDP) provides a standard, consistent method to describe serial Flash device functions and features using internal parameter tables. The parameter tables can be interrogated by host system software, enabling adjustments to accommodate divergent features from multiple vendors. The SFDP standard defines a common parameter table that describes important device characteristics and serial ac- cess methods used to read the parameter table data. Micron's SFDP table information aligns with JEDEC-standard JESD216 for serial Flash discoverable parameters. The latest JEDEC standard includes revision 1.6. Beginning week 42 (2014), Micron's MT25Q production parts will include SFDP data that aligns with revision 1.6. Refer to JEDEC-standard JESD216B for a complete overview of the SFDP table defini- tion. Data in the SFDP tables is read by the READ SERIAL FLASH DISCOVERY PARAMETER operation. See Micron TN-25-06: Serial Flash Discovery Parameters for MT25Q Family for serial Flash discovery parameter data. 256Mb, 3V Multiple I/O Serial Flash Memory Serial Flash Discovery Parameter Data CCMTD-1725822587-3368 mt25q-qljs-L256-ABA-xxT.pdf - Rev. K 07/18 EN 38 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Table 19: Command Set Notes 1 and 2 apply to the entire table Command Code Command-Address-Data Address Bytes Dummy Clock Cycles Data Bytes Notes Extended SPI Dual SPI Quad SPI Extended SPI Dual SPI Quad SPI Software RESET Operations RESET ENABLE 66h 1-0-0 2-0-0 4-0-0 0 0 0 0 0 – RESET MEMORY 99h 1-0-0 2-0-0 4-0-0 0 0 0 0 0 – READ ID Operations READ ID 9E/9Fh 1-0-1 0 0 1 to 20 – MULTIPLE I/O READ ID AFh 1-0-1 2-0-2 4-0-4 0 0 0 0 1 to 20 – READ SERIAL FLASH DISCOVERY PARAMETER 5Ah 1-1-1 2-2-2 4-4-4 3 8 8 8 1 to ∞ 3 READ MEMORY Operations READ 03h 1-1-1 3(4) 0 0 0 1 to ∞ 4 FAST READ 0Bh 1-1-1 2-2-2 4-4-4 3(4) 8 8 10 1 to ∞ 4, 5 DUAL OUTPUT FAST READ 3Bh 1-1-2 2-2-2 3(4) 8 8 1 to ∞ 4, 5 DUAL INPUT/OUTPUT FAST READ BBh 1-2-2 2-2-2 3(4) 8 8 1 to ∞ 4, 5 QUAD OUTPUT FAST READ 6Bh 1-1-4 4-4-4 3(4) 8 10 1 to ∞ 4, 5 QUAD INPUT/OUTPUT FAST READ EBh 1-4-4 4-4-4 3(4) 10 10 1 to ∞ 4, 5 DTR FAST READ 0Dh 1-1-1 2-2-2 4-4-4 3(4) 6 6 8 1 to ∞ 4, 5 DTR DUAL OUTPUT FAST READ 3Dh 1-1-2 2-2-2 3(4) 6 6 1 to ∞ 4, 5 DTR DUAL INPUT/OUTPUT FAST READ BDh 1-2-2 2-2-2 3(4) 6 6 1 to ∞ 4, 5 DTR QUAD OUTPUT FAST READ 6Dh 1-1-4 4-4-4 3(4) 6 8 1 to ∞ 4, 5 DTR QUAD INPUT/OUTPUT FAST READ EDh 1-4-4 4-4-4 3(4) 8 8 1 to ∞ 4, 5 QUAD INPUT/OUTPUT WORD READ E7h 1-4-4 4-4-4 3(4) 4 4 1 to ∞ 4 READ MEMORY Operations with 4-Byte Address 4-BYTE READ 13h 1-1-1 4 0 0 0 1 to ∞ 5 4-BYTE FAST READ 0Ch 1-1-1 2-2-2 4-4-4 4 8 8 10 1 to ∞ 5 4-BYTE DUAL OUTPUT FAST READ 3Ch 1-1-2 2-2-2 4 8 8 1 to ∞ 5 256Mb, 3V Multiple I/O Serial Flash Memory Command Definitions CCMTD-1725822587-3368 mt25q-qljs-L256-ABA-xxT.pdf - Rev. K 07/18 EN39Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Table 19: Command Set (Continued) Notes 1 and 2 apply to the entire table Command Code Command-Address-Data Address Bytes Dummy Clock Cycles Data Bytes Notes Extended SPI Dual SPI Quad SPI Extended SPI Dual SPI Quad SPI 4-BYTE DUAL INPUT/OUTPUT FAST READ BCh 1-2-2 2-2-2 4 8 8 1 to ∞ 5 4-BYTE QUAD OUTPUT FAST READ 6Ch 1-1-4 4-4-4 4 8 10 1 to ∞ 5 4-BYTE QUAD INPUT/OUTPUT FAST READ ECh 1-4-4 4-4-4 4 10 10 1 to ∞ 5 4-BYTE DTR FAST READ 0Eh 1-1-1 2-2-2 4-4-4 4 6 6 8 1 to ∞ 5 4-BYTE DTR DUAL INPUT/OUTPUT FAST READ BEh 1-2-2 2-2-2 4 6 6 1 to ∞ 5 4-BYTE DTR QUAD INPUT/ OUTPUT FAST READ EEh 1-4-4 4-4-4 4 8 8 1 to ∞ 5 WRITE Operations WRITE ENABLE 06h 1-0-0 2-0-0 4-0-0 0 0 0 0 0 – WRITE DISABLE 04h 1-0-0 2-0-0 4-0-0 0 0 0 0 0 – READ REGISTER Operations READ STATUS REGISTER 05h 1-0-1 2-0-2 4-0-4 0 0 0 0 1 to ∞ – READ FLAG STATUS REGISTER 70h 1-0-1 2-0-2 4-0-4 0 0 0 0 1 to ∞ – READ NONVOLATILE CONFIGU- RATION REGISTER B5h 1-0-1 2-0-2 4-0-4 0 0 0 0 2 to ∞ – READ VOLATILE CONFIGURATION REGISTER 85h 1-0-1 2-0-2 4-0-4 0 0 0 0 1 to ∞ – READ ENHANCED VOLATILE CON- FIGURATION REGISTER 65h 1-0-1 2-0-2 4-0-4 0 0 0 0 1 to ∞ – READ EXTENDED ADDRESS REG- ISTER C8h 1-0-1 2-0-2 4-0-4 0 0 0 0 1 to ∞ – READ GENERAL PURPOSE READ REGISTER 96h 1-0-1 2-0-2 4-0-4 0 8 8 8 1 to ∞ 6, 7 WRITE REGISTER Operations WRITE STATUS REGISTER 01h 1-0-1 2-0-2 4-0-4 0 0 0 0 1 8 WRITE NONVOLATILE CONFIGU- RATION REGISTER B1h 1-0-1 2-0-2 4-0-4 0 0 0 0 2 8 256Mb, 3V Multiple I/O Serial Flash Memory Command Definitions CCMTD-1725822587-3368 mt25q-qljs-L256-ABA-xxT.pdf - Rev. K 07/18 EN40Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Table 19: Command Set (Continued) Notes 1 and 2 apply to the entire table Command Code Command-Address-Data Address Bytes Dummy Clock Cycles Data Bytes Notes Extended SPI Dual SPI Quad SPI Extended SPI Dual SPI Quad SPI WRITE VOLATILE CONFIGURA- TION REGISTER 81h 1-0-1 2-0-2 4-0-4 0 0 0 0 1 8 WRITE ENHANCED VOLATILE CONFIGURATION REGISTER 61h 1-0-1 2-0-2 4-0-4 0 0 0 0 1 8 WRITE EXTENDED ADDRESS REG- ISTER C5h 1-0-1 2-0-2 4-0-4 0 0 0 0 1 8 CLEAR FLAG STATUS REGISTER Operation CLEAR FLAG STATUS REGISTER 50h 1-0-0 2-0-0 4-0-0 0 0 0 0 0 – PROGRAM Operations PAGE PROGRAM 02h 1-1-1 2-2-2 4-4-4 3(4) 0 0 0 1 to 256 8 DUAL INPUT FAST PROGRAM A2h 1-1-2 2-2-2 3(4) 0 0 1 to 256 4, 8 EXTENDED DUAL INPUT FAST PROGRAM D2h 1-2-2 2-2-2 3(4) 0 0 1 to 256 4, 8 QUAD INPUT FAST PROGRAM 32h 1-1-4 4-4-4 3(4) 0 0 1 to 256 4, 8 EXTENDED QUAD INPUT FAST PROGRAM 38h 1-4-4 4-4-4 3(4) 0 0 1 to 256 4, 8 PROGRAM Operations with 4-Byte Address 4-BYTE PAGE PROGRAM 12h 1-1-1 2-2-2 4-4-4 4 0 0 0 1 to 256 8 4-BYTE QUAD INPUT FAST PRO- GRAM 34h 1-1-4 4-4-4 4 0 0 1 to 256 8 4-BYTE QUAD INPUT EXTENDED FAST PROGRAM 3Eh 1-4-4 4-4-4 4 0 0 1 to 256 8 ERASE Operations 32KB SUBSECTOR ERASE 52h 1-1-0 2-2-0 4-4-0 3(4) 0 0 0 0 4, 8 4KB SUBSECTOR ERASE 20h 1-1-0 2-2-0 4-4-0 3(4) 0 0 0 0 4, 8 SECTOR ERASE D8h 1-1-0 2-2-0 4-4-0 3(4) 0 0 0 0 4, 8 BULK ERASE C7h/60h 1-0-0 2-0-0 4-0-0 0 0 0 0 0 8 ERASE Operations with 4-Byte Address 4-BYTE SECTOR ERASE DCh 1-1-0 2-2-0 4-4-0 4 0 0 0 0 8 4-BYTE 4KB SUBSECTOR ERASE 21h 1-1-0 2-2-0 4-4-0 4 0 0 0 0 8 SUSPEND/RESUME Operations 256Mb, 3V Multiple I/O Serial Flash Memory Command Definitions CCMTD-1725822587-3368 mt25q-qljs-L256-ABA-xxT.pdf - Rev. K 07/18 EN41Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Table 19: Command Set (Continued) Notes 1 and 2 apply to the entire table Command Code Command-Address-Data Address Bytes Dummy Clock Cycles Data Bytes Notes Extended SPI Dual SPI Quad SPI Extended SPI Dual SPI Quad SPI PROGRAM/ERASE SUSPEND 75h 1-0-0 2-0-0 4-0-0 0 0 0 0 0 – PROGRAM/ERASE RESUME 7Ah 1-0-0 2-0-0 4-0-0 0 0 0 0 0 – ONE-TIME PROGRAMMABLE (OTP) Operations READ OTP ARRAY 4Bh 1-1-1 2-2-2 4-4-4 3(4) 8 8 10 1 to 64 4, 5 PROGRAM OTP ARRAY 42h 1-1-1 2-2-2 4-4-4 3(4) 0 0 0 1 to 64 4, 8 4-BYTE ADDRESS MODE Operations ENTER 4-BYTE ADDRESS MODE B7h 1-0-0 2-0-0 4-0-0 0 0 0 0 0 – EXIT 4-BYTE ADDRESS MODE E9h 1-0-0 2-0-0 4-0-0 0 0 0 0 0 – QUAD PROTOCOL Operations ENTER QUAD INPUT/OUTPUT MODE 35h 1-0-0 2-0-0 4-0-0 0 0 0 0 0 – RESET QUAD INPUT/OUTPUT MODE F5h 1-0-0 2-0-0 4-0-0 0 0 0 0 0 – Deep Power-Down Operations ENTER DEEP POWER DOWN B9h 1-0-0 2-0-0 4-0-0 0 0 0 0 0 – RELEASE FROM DEEP POWER- DOWN ABh 1-0-0 2-0-0 4-0-0 0 0 0 0 0 – ADVANCED SECTOR PROTECTION Operations READ SECTOR PROTECTION 2Dh 1-0-1 2-0-2 4-0-4 0 0 0 0 1 to ∞ – PROGRAM SECTOR PROTECTION 2Ch 1-0-1 2-0-2 4-0-4 0 0 0 0 2 8 READ VOLATILE LOCK BITS E8h 1-1-1 2-2-2 4-4-4 3(4) 0 0 0 1 to ∞ 4, 9 WRITE VOLATILE LOCK BITS E5h 1-1-1 2-2-2 4-4-4 3(4) 0 0 0 1 4, 8, 10 READ NONVOLATILE LOCK BITS E2h 1-1-1 2-2-2 4-4-4 4 0 0 0 1 to ∞ – WRITE NONVOLATILE LOCK BITS E3h 1-1-0 2-2-0 4-4-0 4 0 0 0 0 8 ERASE NONVOLATILE LOCK BITS E4h 1-0-0 2-0-0 4-0-0 0 0 0 0 0 8 READ GLOBAL FREEZE BIT A7h 1-0-1 0 0 0 0 1 to ∞ – WRITE GLOBAL FREEZE BIT A6h 1-0-0 2-0-0 4-0-0 0 0 0 0 0 8 READ PASSWORD 27h 1-0-1 0 0 0 0 1 to ∞ – WRITE PASSWORD 28h 1-0-1 2-0-2 4-0-4 0 0 0 0 8 8 UNLOCK PASSWORD 29h 1-0-1 2-0-2 4-0-4 0 0 0 0 8 – 256Mb, 3V Multiple I/O Serial Flash Memory Command Definitions CCMTD-1725822587-3368 mt25q-qljs-L256-ABA-xxT.pdf - Rev. K 07/18 EN42Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Table 19: Command Set (Continued) Notes 1 and 2 apply to the entire table Command Code Command-Address-Data Address Bytes Dummy Clock Cycles Data Bytes Notes Extended SPI Dual SPI Quad SPI Extended SPI Dual SPI Quad SPI ADVANCED SECTOR PROTECTION Operations with 4-Byte Address 4-BYTE READ VOLATILE LOCK BITS E0h 1-1-1 2-2-2 4-4-4 4 0 0 0 1 to ∞ – 4-BYTE WRITE VOLATILE LOCK BITS E1h 1-1-1 2-2-2 4-4-4 4 0 0 0 1 8 ADVANCED FUNCTION INTERFACE Operations INTERFACE ACTIVATION 9Bh 1-0-0 2-0-0 4-0-0 0 0 0 0 0 – CYCLIC REDUNDANCY CHECK 9Bh/27h 1-0-1 2-0-2 4-0-4 0 0 0 0 10 or 18 – 256Mb, 3V Multiple I/O Serial Flash Memory Command Definitions CCMTD-1725822587-3368 mt25q-qljs-L256-ABA-xxT.pdf - Rev. K 07/18 EN43Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Notes: 1. Micron extended SPI protocol is the standard SPI protocol with additional commands that extend functionality and enable address or data transmission on multiple DQn lines. 2. The command code is always transmitted on DQn = 1, 2, or 4 lines according to the standard, dual, or quad protocol respectively. However, a command may be able to transmit address and data on multiple DQn lines regardless of protocol. The protocol columns show the number of DQn lines a command uses to transmit command, address, and data information as shown in these examples: command-address-data = 1-1-1, or 1-2-2, or 2-4-4, and so on. 3. The READ SERIAL FLASH DISCOVERY PARAMETER operation accepts only 3-byte address even if the device is configured to 4-byte address mode. 4. Requires 4 bytes of address if the device is configured to 4-byte address mode. 5. The number of dummy clock cycles required when shipped from Micron factories. The user can modify the dummy clock cycle number via the nonvolatile configuration regis- ter and the volatile configuration register. 6. The number of dummy cycles for the READ GENERAL PURPOSE READ REGISTER com- mand is fixed (8 dummy cycles) and is not affected by dummy cycle settings in the non- volatile configuration register and volatile configuration register. 7. The general purpose read register is 64 bytes. After the first 64 bytes, the device outputs 00h and does not wrap. 8. The WRITE ENABLE command must be issued first before this operation can be execu- ted. 9. Formerly referred to as the READ LOCK REGISTER operation. 10. Formerly referred to as the WRITE LOCK REGISTER operation. 256Mb, 3V Multiple I/O Serial Flash Memory Command Definitions CCMTD-1725822587-3368 mt25q-qljs-L256-ABA-xxT.pdf - Rev. K 07/18 EN 44 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

RESET ENABLE and RESET MEMORY Commands To initiate these commands, S# is driven LOW and the command code is input on DQn. A minimum de-selection time of tSHSL2 must come between RESET ENABLE and RE- SET MEMORY or reset is not guaranteed. Then, S# must be driven HIGH for the device to enter power-on reset. A time of tSHSL3 is required before the device can be re-selec- ted by driving S# LOW . Table 20: RESET ENABLE and RESET MEMORY Operations Operation Name Description/Conditions RESET ENABLE (66h) To reset the device, the RESET ENABLE command must be followed by the RESET MEMORY command. When the two commands are executed, the device enters a power-on reset con- dition. It is recommended to exit XIP mode before executing these two commands. All volatile lock bits, the volatile configuration register, the enhanced volatile configura- tion register, and the extended address register are reset to the power-on reset default condition according to nonvolatile configuration register settings. If a reset is initiated while a WRITE, PROGRAM, or ERASE operation is in progress or sus- pended, the operation is aborted and data may be corrupted. Reset is effective after the flag status register bit 7 outputs 1 with at least one byte output. A RESET ENABLE command is not accepted during WRITE STATUS REGISTER and WRITE NONVOLATILE CONFIGURATION REGISTER operations. RESET MEMORY (99h) Figure 16: RESET ENABLE and RESET MEMORY Command C DQ0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 Reset enable Reset memory Note: 1. Above timing diagram is showed for Extended-SPI Protocol case, however these com- mands are available in all protocols. In DIO-SPI protocol, the instruction bits are trans- mitted on both DQ0 and DQ1 pins. In QIO-SPI protocol the instruction bits are transmit- ted on all four data pins. In Extended-DTR-SPI protocol, the instruction bits are transmit- ted on DQ0 pin in double transfer rate mode. In DIO-DTR-SPI protocol, the instruction bits are transmitted on both DQ0 and DQ1 pins in double transfer rate mode. In QIO- DTR-SPI protocol, the instruction bits are transmitted on all four data pins in double transfer rate mode. 256Mb, 3V Multiple I/O Serial Flash Memory Software RESET Operations CCMTD-1725822587-3368 mt25q-qljs-L256-ABA-xxT.pdf - Rev. K 07/18 EN 45 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

READ ID and MULTIPLE I/O READ ID Commands To initiate these commands, S# is driven LOW and the command code is input on DQn. When S# is driven HIGH, the device goes to standby. The operation is terminated by driving S# HIGH at any time during data output. Table 21: READ ID and MULTIPLE I/O READ ID Operations Operation Name Description/Conditions READ ID (9Eh/9Fh) Outputs information shown in the Device ID Data tables. If an ERASE or PROGRAM cycle is in progress when the command is initiated, the command is not decoded and the com- mand cycle in progress is not affected. MULTIPLE I/O READ ID (AFh) Figure 17: READ ID and MULTIPLE I/O READ ID Commands UIDDevice identification Manufacturer identification High-ZDQ1 MSB MSB D OUT D OUT D OUT D OUT LSBLSB 7 8 15 16 32310 C MSB DQ0 LSB Command MSB D OUT D OUT LSB Extended (READ ID) Dual (MULTIPLE I/O READ ID ) Quad (MULTIPLE I/O READ ID ) Don’t Care 3 4 7 8 150 C MSB DQ[1:0] LSB Command Device identification Manufacturer identification MSB MSB D OUT D OUT D OUT D OUT LSBLSB 1 2 3 4 70 C MSB DQ[3:0] LSB Command Device identification Manufacturer identification MSB MSB D OUT D OUT D OUT D OUT LSBLSB Note: 1. S# not shown. 256Mb, 3V Multiple I/O Serial Flash Memory READ ID Operations CCMTD-1725822587-3368 mt25q-qljs-L256-ABA-xxT.pdf - Rev. K 07/18 EN 46 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

READ SERIAL FLASH DISCOVERY PARAMETER Operation READ SERIAL FLASH DISCOVERY PARAMETER Command To execute READ SERIAL FLASH DISCOVERY PARAMETER command, S# is driven LOW . The command code is input on DQ0, followed by three address bytes and eight dummy clock cycles (address is always 3 bytes, even if the device is configured to work in 4-byte address mode). The device outputs the information starting from the specified address. When the 2048-byte boundary is reached, the data output wraps to address 0 of the serial Flash discovery parameter table. The operation is terminated by driving S# HIGH at any time during data output. Note: The operation always executes in continuous mode so the read burst wrap setting in the volatile configuration register does not apply. Figure 18: READ SERIAL FLASH DISCOVERY PARAMETER Command – 5Ah 7 8 C x0 C MSB DQ0 LSB Command A[MAX] A[MIN] 3 4 C x0 C MSB DQ[1:0] LSB Command A[MAX] A[MIN] MSB D OUT D OUT D OUT D OUT D OUT LSB Dummy cycles 1 2 C x0 C MSB DQ[3:0] LSB Command A[MAX] A[MIN] MSB D OUT D OUT D OUT LSB Dummy cycles Extended MSB D OUT D OUT D OUT D OUT D OUT LSB D OUT D OUT D OUT D OUT Dummy cycles Dual Quad DQ1 High-Z Don’t Care Notes: 1. For extended protocol, C x = 7 + (A[MAX] + 1); For dual protocol, Cx = 3 + (A[MAX] + 1)/2; For quad protocol, Cx = 1 + (A[MAX] + 1)/4. 2. S# not shown. 256Mb, 3V Multiple I/O Serial Flash Memory READ SERIAL FLASH DISCOVERY PARAMETER Operation CCMTD-1725822587-3368 mt25q-qljs-L256-ABA-xxT.pdf - Rev. K 07/18 EN 47 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

To initiate a command, S# is driven LOW and the command code is input on DQn, fol- lowed by input of the address bytes on DQn. The operation is terminated by driving S# HIGH at any time during data output. Table 22: READ MEMORY Operations Operation Name Description/Conditions READ (03h) The device supports 3-byte addressing (default), with A[23:0] input during address cycle. After any READ command is executed, the device will out- put data from the selected address. After the boundary is reached, the device will start reading again from the beginning. Each address bit is latched in during the rising edge of the clock. The ad- dressed byte can be at any location, and the address automatically incre- ments to the next address after each byte of data is shifted out; there- fore, a die can be read with a single command. FAST READ can operate at a higher frequency (fC). DTR commands function in DTR protocol regardless of settings in the nonvolatile configuration register or enhanced volatile configuration reg- ister; other commands function in DTR protocol only after DTR protocol is enabled by the register settings. E7h is similar to the QUAD I/O FAST READ command except that the low- est address bit (A0) must equal 0 and only four dummy clocks are re- quired prior to the data output. This command is supported in extended- SPI and quad-SPI protocols, but not in the DTR protocol; it is ignored it in dual-SPI protocol. FAST READ (0Bh) DUAL OUTPUT FAST READ (3Bh) DUAL INPUT/OUTPUT FAST READ (BBh) QUAD OUTPUT FAST READ (6Bh) QUAD INPUT/OUTPUT FAST READ (EBh) DTR FAST READ (0Dh) DTR DUAL OUTPUT FAST READ (3Dh) DTR DUAL INPUT/OUTPUT FAST READ (BDh) DTR QUAD OUTPUT FAST READ (6Dh) DTR QUAD INPUT/OUTPUT FAST READ (EDh) QUAD INPUT/OUTPUT WORD READ (E7h) 256Mb, 3V Multiple I/O Serial Flash Memory READ MEMORY Operations CCMTD-1725822587-3368 mt25q-qljs-L256-ABA-xxT.pdf - Rev. K 07/18 EN 48 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

4-BYTE READ MEMORY Operations Table 23: 4-BYTE READ MEMORY Operations Operation Name Description/Conditions 4-BYTE READ (13h) READ MEMORY operations can be extended to a 4-byte address range, with [A31:0] input during address cycle. Selection of the 3-byte or 4-byte address range can be enabled in two ways: through the nonvolatile configuration register or through the ENA- BLE 4-BYTE ADDRESS MODE/EXIT 4-BYTE ADDRESS MODE commands. Each address bit is latched in during the rising edge of the clock. The ad- dressed byte can be at any location, and the address automatically incre- ments to the next address after each byte of data is shifted out; there- fore, a die can be read with a single command. FAST READ can operate at a higher frequency (fC). 4-BYTE commands and DTR 4-BYTE commands function in 4-BYTE and DTR 4-BYTE protocols regardless of settings in the nonvolatile configura- tion register or enhanced volatile configuration register; other commands function in 4-BYTE and DTR protocols only after the specific protocol is enabled by the register settings. 4-BYTE FAST READ (0Ch) 4-BYTE DUAL OUTPUT FAST READ (3Ch) 4-BYTE DUAL INPUT/OUTPUT FAST READ (BCh) 4-BYTE QUAD OUTPUT FAST READ (6Ch) 4-BYTE QUAD INPUT/OUTPUT FAST READ (ECh) DTR 4-BYTE FAST READ (0Eh) DTR 4-BYTE DUAL INPUT/OUTPUT FAST READ (BEh) DTR 4-BYTE QUAD INPUT/OUTPUT FAST READ (EEh) 256Mb, 3V Multiple I/O Serial Flash Memory 4-BYTE READ MEMORY Operations CCMTD-1725822587-3368 mt25q-qljs-L256-ABA-xxT.pdf - Rev. K 07/18 EN 49 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

1. QUAD INPUT/OUTPUT FAST READ and 4-BYTE QUAD INPUT/OUTPUT FAST READ com- mands. Figure 25: QUAD INPUT/OUTPUT WORD READ – E7h3 Four dummy cycles 7 8 C x C MSB DQ0 Extended LSB Command D OUT LSB DQ[3:1] D OUTHigh-Z A[MIN] D OUT D OUT D OUT D OUT MSBA[MAX] 1 2 C x C MSB DQ[3:0] LSB Command A[MAX] A[MIN] MSB D OUT D OUT D OUT LSB Dummy cycles Quad Notes: 1. For extended protocol, C x = 7 + (A[MAX] + 1)/4; For quad protocol, Cx = 1 + (A[MAX] + 1)/4. 2. S# not shown. 3. QUAD INPUT/OUTPUT WORD READ and 4-BYTE QUAD INPUT/OUTPUT WORD READ commands. 256Mb, 3V Multiple I/O Serial Flash Memory READ MEMORY Operations Timings CCMTD-1725822587-3368 mt25q-qljs-L256-ABA-xxT.pdf - Rev. K 07/18 EN 53 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Figure 28: DTR DUAL INPUT/OUTPUT FAST READ – BDh3 C DQ0 DQ1 7 8 C x0 MSB LSB Command D OUT LSB D OUTHigh-Z A[MIN] D OUT MSB D OUT D OUT D OUT D OUT D OUT D OUT D OUT D OUT D OUT D OUT D OUT D OUT D OUT A[MAX] Dummy cycles Dual C DQ[1:0] 3 4 C x0 MSB LSB Command A[MAX] A[MIN] MSB LSB Dummy cycles D OUTD OUT D OUT D OUT D OUT D OUT D OUT D OUT Extended Notes: 1. For extended protocol, C x = 7 + (A[MAX] + 1)/4; For dual protocol, Cx = 3 + (A[MAX] + 1)/8. 2. S# not shown. 3. DTR DUAL INPUT/OUTPUT FAST READ and 4-BYTE DTR DUAL INPUT/OUTPUT FAST READ commands. 256Mb, 3V Multiple I/O Serial Flash Memory READ MEMORY Operations Timings CCMTD-1725822587-3368 mt25q-qljs-L256-ABA-xxT.pdf - Rev. K 07/18 EN 55 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

WRITE ENABLE/DISABLE Operations To initiate a command, S# is driven LOW and held LOW until the eighth bit of the com- mand code has been latched in, after which it must be driven HIGH. For extended-, du- al-, and quad-SPI protocols respectively, the command code is input on DQ0, DQ[1:0], and DQ[3:0]. If S# is not driven HIGH after the command code has been latched in, the command is not executed, flag status register error bits are not set, and the write enable latch remains cleared to its default setting of 0, providing protection against errant data modification. Table 24: WRITE ENABLE/DISABLE Operations Operation Name Description/Conditions WRITE ENABLE (06h) Sets the write enable latch bit before each PROGRAM, ERASE, and WRITE command. WRITE DISABLE (04h) Clears the write enable latch bit. In case of a protection error, WRITE DISABLE will not clear the bit. Instead, a CLEAR FLAG STATUS REGISTER command must be issued to clear both flags. Figure 31: WRITE ENABLE and WRITE DISABLE Timing DQ0 MSB LSB Dual Don’t Care Command Bits DQ0 0 1 2 4 53 76 C Extended High-ZDQ1 MSB LSB 0 0 0 0 0 011 Command Bits 0 0 1 0 MSB C LSB DQ1 DQ2 Quad Command Bits DQ3 0 0 DQ0 0 0 DQ1 0 0 0 1 1 20 C Note: 1. WRITE ENABLE command sequence and code, shown here, is 06h (0000 0110 binary); WRITE DISABLE is identical, but its command code is 04h (0000 0100 binary). 256Mb, 3V Multiple I/O Serial Flash Memory WRITE ENABLE/DISABLE Operations CCMTD-1725822587-3368 mt25q-qljs-L256-ABA-xxT.pdf - Rev. K 07/18 EN 57 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

To initiate a command, S# is driven LOW . For extended SPI protocol, input is on DQ0, output on DQ1. For dual SPI protocol, input/output is on DQ[1:0] and for quad SPI pro- tocol, input/output is on DQ[3:0]. The operation is terminated by driving S# HIGH at any time during data output. Table 25: READ REGISTER Operations Operation Name Description/Conditions Note READ STATUS REGISTER (05h) Can be read continuously and at any time, including during a PRO- GRAM, ERASE, or WRITE operation. If one of these operations is in progress, checking the write in progress bit or P/E controller bit is recommended before executing the command. READ FLAG STATUS REGISTER (70h) READ NONVOLATILE CONFIGURATION REGISTER (B5h) Can be read continuously. After all 16 bits of the register have been read, a 0 is output. All reserved fields output a value of 1. READ VOLATILE CONFIGURATION REGIS- TER (85h) When the register is read continuously, the same byte is output re- peatedly. READ ENHANCED VOLATILE CONFIGURA- TION REGISTER (65h) READ EXTENDED ADDRESS REGISTER (C8h) Note: 1. The operation will have output data starting from the least significant byte. Figure 32: READ REGISTER Timing High-ZDQ1 7 8 9 10 11 12 13 14 150 C MSB DQ0 LSB Command 3 4 5 6 70 C MSB DQ[1:0] LSB Command MSB D OUT D OUT D OUT D OUT D OUT LSB Extended MSB D OUT D OUT D OUT D OUT D OUT LSB D OUT D OUT D OUT D OUT Dual Quad 1 2 30 C MSB DQ[3:0] LSB Command MSB D OUT D OUT D OUT LSB Don’t Care Notes: 1. Supports all READ REGISTER commands except DYNAMIC PROTECTION BITS READ. 256Mb, 3V Multiple I/O Serial Flash Memory READ REGISTER Operations CCMTD-1725822587-3368 mt25q-qljs-L256-ABA-xxT.pdf - Rev. K 07/18 EN 58 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

1. A READ NONVOLATILE CONFIGURATION REGISTER operation will output data starting from the least significant byte. 3. S# not shown. WRITE REGISTER Operations Before a WRITE REGISTER command is initiated, the WRITE ENABLE command must be executed to set the write enable latch bit to 1. To initiate a command, S# is driven LOW and held LOW until the eighth bit of the last data byte has been latched in, after which it must be driven HIGH; for the WRITE NONVOLATILE CONFIGURATION REG- ISTER command, S# is held LOW until the 16th bit of the last data byte has been latched in. For the extended, dual, and quad SPI protocols respectively, input is on DQ0, DQ[1:0], and DQ[3:0], followed by the data bytes. If S# is not driven HIGH, the com- mand is not executed, flag status register error bits are not set, and the write enable latch remains set to 1. The operation is self-timed and its duration is tW for WRITE STA- TUS REGISTER and tNVCR for WRITE NONVOLATILE CONFIGURATION REGISTER. Table 26: WRITE REGISTER Operations Operation Name Description/Conditions Note WRITE STATUS REGISTER (01h) The WRITE STATUS REGISTER command writes new values to status register bits 7:2, enabling software data protection. The status reg- ister can also be combined with the W# signal to provide hardware data protection. This command has no effect on status register bits 1:0. WRITE NONVOLATILE CONFIGURATION REGISTER (B1h) For the WRITE STATUS REGISTER and WRITE NONVOLATILE CONFIG- URATION REGISTER commands, when the operation is in progress, the write in progress bit is set to 1. The write enable latch bit is cleared to 0, whether the operation is successful or not. The status register and flag status register can be polled for the operation sta- tus. When the operation completes, the write in progress bit is cleared to 0, whether the operation is successful or not. WRITE VOLATILE CONFIGURATION REGIS- TER (81h) Because register bits are volatile, change to the bits is immediate. Reserved bits are not affected by this command. WRITE ENHANCED VOLATILE CONFIGURA- TION REGISTER (61h) WRITE EXTENDED ADDRESS REGISTER (C5h) Note: 1. The WRITE NONVOLATILE CONFIGURATION REGISTER operation must have input data starting from the least significant byte. 256Mb, 3V Multiple I/O Serial Flash Memory WRITE REGISTER Operations CCMTD-1725822587-3368 mt25q-qljs-L256-ABA-xxT.pdf - Rev. K 07/18 EN 59 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Figure 33: WRITE REGISTER Timing 7 8 9 10 11 12 13 14 150 C MSB DQ0 LSB Command 3 4 5 6 70 C MSB DQ[1:0] LSB Command MSB D IN D IN D IN D IN D IN LSB Extended MSB LSB D IN D IN D IN D IN D IND IN D IN D IN D IN Dual Quad 1 2 30 C MSB DQ[3:0] LSB Command MSB D IN D IN D IN LSB Notes: 1. Supports all WRITE REGISTER commands except WRITE LOCK REGISTER. 2. Data is two bytes for a WRITE NONVOLATILE CONFIGURATION REGISTER operation, in- put starting from the least significant byte. 3. S# not shown. 256Mb, 3V Multiple I/O Serial Flash Memory WRITE REGISTER Operations CCMTD-1725822587-3368 mt25q-qljs-L256-ABA-xxT.pdf - Rev. K 07/18 EN 60 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

CLEAR FLAG STATUS REGISTER Operation To initiate a command, S# is driven LOW . For the extended-, dual-, and quad-SPI proto- cols respectively, input is on DQ0, DQ[1:0], and DQ[3:0]. The operation is terminated by driving S# HIGH at any time. Table 27: CLEAR FLAG STATUS REGISTER Operation Operation Name Description/Conditions CLEAR FLAG STATUS REGISTER (50h) Resets the error bits (erase, program, and protection) Figure 34: CLEAR FLAG STATUS REGISTER Timing C MSB DQ0 LSB Command C MSB DQ[1:0] LSB Command C MSB DQ[3:0] LSB Command Extended Dual Quad Note: 1. S# not shown. 256Mb, 3V Multiple I/O Serial Flash Memory CLEAR FLAG STATUS REGISTER Operation CCMTD-1725822587-3368 mt25q-qljs-L256-ABA-xxT.pdf - Rev. K 07/18 EN 61 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Before a PROGRAM command is initiated, the WRITE ENABLE command must be exe- cuted to set the write enable latch bit to 1. To initiate a command, S# is driven LOW and held LOW until the eighth bit of the last data byte has been latched in, after which it must be driven HIGH. If S# is not driven HIGH, the command is not executed, flag sta- tus register error bits are not set, and the write enable latch remains set to 1. Each ad- dress bit is latched in during the rising edge of the clock. When a command is applied to a protected sector, the command is not executed, the write enable latch bit remains set to 1, and flag status register bits 1 and 4 are set. If the operation times out, the write ena- ble latch bit is reset and the program fail bit is set to 1. Note: The manner of latching data shown and explained in the timing diagrams ensures that the number of clock pulses is a multiple of one byte before command execution, helping reduce the effects of noisy or undesirable signals and enhancing device data protection. Table 28: PROGRAM Operations Operation Name Description/Conditions PAGE PROGRAM (02h) A PROGRAM operation changes a bit from 1 to 0. When the operation is in progress, the write in progress bit is set to 1. The write enable latch bit is cleared to 0, whether the operation is suc- cessful or not. The status register and flag status register can be polled for the operation status. When the operation completes, the write in progress bit is cleared to 0. An operation can be paused or resumed by the PROGRAM/ERASE SUSPEND or PROGRAM/ERASE RESUME command, respectively. If the bits of the least significant address, which is the starting address, are not all zero, all data transmitted beyond the end of the current page is programmed from the starting address of the same page. If the number of bytes sent to the device exceed the maximum page size, pre- viously latched data is discarded and only the last maximum page-size number of data bytes are guaranteed to be programmed correctly with- in the same page. If the number of bytes sent to the device is less than the maximum page size, they are correctly programmed at the specified addresses without any effect on the other bytes of the same page. DUAL INPUT FAST PROGRAM (A2h) EXTENDED DUAL INPUT FAST PROGRAM (D2h) QUAD INPUT FAST PROGRAM (32h) EXTENDED QUAD INPUT FAST PROGRAM (38h) 256Mb, 3V Multiple I/O Serial Flash Memory PROGRAM Operations CCMTD-1725822587-3368 mt25q-qljs-L256-ABA-xxT.pdf - Rev. K 07/18 EN 62 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Table 29: 4-BYTE PROGRAM Operations Operation Name Description/Conditions 4-BYTE PAGE PROGRAM (12h) PROGRAM operations can be extended to a 4-byte address range, with [A31:0] input during address cycle. Selection of the 3-byte or 4-byte address range can be enabled in two ways: through the nonvolatile configuration register or through the EN- ABLE 4-BYTE ADDRESS MODE/EXIT 4-BYTE ADDRESS MODE commands. 4-BYTE commands and DTR 4-BYTE commands function in 4-BYTE and DTR 4-BYTE protocol regardless of settings in the nonvolatile configura- tion register or enhanced volatile configuration register; other com- mands function in 4-BYTE and DTR protocols only after the specific pro- tocol is enabled by the register settings. 4-BYTE QUAD INPUT FAST PROGRAM (34h) 4-BYTE EXTENDED QUAD INPUT FAST PRO- GRAM (3Eh) PROGRAM Operations Timings Figure 35: PAGE PROGRAM Command 7 8 C x0 C MSB DQ0 LSB Command A[MAX] A[MIN] MSB D IN D IN D IN D IN D IN LSB D IN D IN D IN D IN 3 4 C x0 C MSB DQ[1:0] LSB Command A[MAX] A[MIN] MSB D IN D IN D IN D IN D IN LSB 1 2 C x0 C MSB DQ[3:0] LSB Command A[MAX] A[MIN] MSB D IN D IN D IN LSB Extended Dual Quad Notes: 1. For extended-SPI protocol, C x = 7 + (A[MAX] + 1); For dual-SPI protocol, Cx = 3 + (A[MAX] + 1)/2; For quad-SPI protocol, Cx = 1 + (A[MAX] + 1)/4. 2. S# not shown. The operation is self-timed, and its duration is tPP. 256Mb, 3V Multiple I/O Serial Flash Memory 4-BYTE PROGRAM Operations CCMTD-1725822587-3368 mt25q-qljs-L256-ABA-xxT.pdf - Rev. K 07/18 EN 63 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

An ERASE operation changes a bit from 0 to 1. Before any ERASE command is initiated, the WRITE ENABLE command must be executed to set the write enable latch bit to 1; if not, the device ignores the command and no error bits are set to indicate operation fail- ure. S# is driven LOW and held LOW until the eighth bit of the last data byte has been latched in, after which it must be driven HIGH. The operations are self-timed, and dura- tion is tSSE, tSE, or tBE according to command. If S# is not driven HIGH, the command is not executed, flag status register error bits are not set, and the write enable latch remains set to 1. A command applied to a protected subsector is not executed. Instead, the write enable latch bit remains set to 1, and flag status register bits 1 and 5 are set. When the operation is in progress, the program or erase controller bit of the flag status register is set to 0. In addition, the write in progress bit is set to 1. When the operation completes, the write in progress bit is cleared to 0. The write enable latch bit is cleared to 0, whether the operation is successful or not. If the operation times out, the write en- able latch bit is reset and the erase error bit is set to 1. The status register and flag status register can be polled for the operation status. When the operation completes, these register bits are cleared to 1. Note: For all ERASE operations, noisy or undesirable signal effects can be reduced and device data protection enhanced by holding S# LOW until the eighth bit of the last data byte has been latched in; this ensures that the number of clock pulses is a multiple of one byte before command execution. Table 30: ERASE Operations Operation Name Description/Conditions SUBSECTOR ERASE (52h/20h) Sets the selected subsector or sector bits to FFh. Any address within the subsector is valid for entry. Each address bit is latched in during the rising edge of the clock. The operation can be suspended and resumed by the PROGRAM/ERASE SUSPEND and PROGRAM/ERASE RESUME commands, respectively. SECTOR ERASE (D8h) BULK ERASE (C7h/60h) Sets the device bits to FFh. The command is not executed if any sector is locked. Instead, the write enable latch bit remains set to 1, and flag status register bits 1 and 5 are set. 256Mb, 3V Multiple I/O Serial Flash Memory ERASE Operations CCMTD-1725822587-3368 mt25q-qljs-L256-ABA-xxT.pdf - Rev. K 07/18 EN 66 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

PROGRAM/ERASE SUSPEND Operations A PROGRAM/ERASE SUSPEND command enables the memory controller to interrupt and suspend an array PROGRAM or ERASE operation within the program/erase latency. To initiate the command, S# is driven LOW, and the command code is input on DQn. The operation is terminated by the PROGRAM/ERASE RESUME command. For a PROGRAM SUSPEND, the flag status register bit 2 is set to 1. For an ERASE SUS- PEND, the flag status register bit 6 is set to 1. After an erase/program latency time, the flag status register bit 7 is also set to 1, but the device is considered in suspended state once bit 7 of the flag status register outputs 1 with at least one byte output. In the suspended state, the device is waiting for any oper- ation. If the time remaining to complete the operation is less than the suspend latency, the de- vice completes the operation and clears the flag status register bits 2 or 6, as applicable. Because the suspend state is volatile, if there is a power cycle, the suspend state infor- mation is lost and the flag status register powers up as 80h. It is possible to nest a PROGRAM/ERASE SUSPEND operation inside a PROGRAM/ ERASE SUSPEND operation just once. Issue an ERASE command and suspend it. Then issue a PROGRAM command and suspend it also. With the two operations suspended, the next PROGRAM/ERASE RESUME command resumes the latter operation, and a sec- ond PROGRAM/ERASE RESUME command resumes the former (or first) operation. PROGRAM/ERASE RESUME Operations A PROGRAM/ERASE RESUME operation terminates the PROGRAM/ERASE RESUME command. To initiate the command, S# is driven LOW, and the command code is input on DQn. The operation is terminated by driving S# HIGH. Table 31: SUSPEND/RESUME Operations Operation Name Description/Conditions PROGRAM SUSPEND (75h) A READ operation is possible in any page except the one in a suspended state. Reading from a sector that is in a suspended state will output indeterminate data. ERASE SUSPEND (75h) A PROGRAM or READ operation is possible in any sector except the one in a suspended state. Reading from a sector that is in a suspended state will output indeterminate data. During a SUSPEND SUBSECTOR ERASE operation, reading an address in the sector that contains the suspended subsector could output indeterminate data. The device ignores a PROGRAM command to a sector that is in an erase suspend state; it also sets the flag status register bit 4 to 1 (program failure/protection error) and leaves the write enable latch bit unchanged. When the ERASE resumes, it does not check the new lock status of the WRITE VOLATILE LOCK BITS command. 256Mb, 3V Multiple I/O Serial Flash Memory SUSPEND/RESUME Operations CCMTD-1725822587-3368 mt25q-qljs-L256-ABA-xxT.pdf - Rev. K 07/18 EN 68 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Table 31: SUSPEND/RESUME Operations (Continued) Operation Name Description/Conditions PROGRAM RESUME (7Ah) The status register write in progress bit is set to 1 and the flag status register program erase controller bit is set to 0. The command is ignored if the device is not in a suspen- ded state. When the operation is in progress, the program or erase controller bit of the flag status register is set to 0. The flag status register can be polled for the operation status. When the operation completes, that bit is cleared to 1. ERASE RESUME (7Ah) Note: 1. See the Operations Allowed/Disallowed During Device States table. Figure 42: PROGRAM/ERASE SUSPEND and RESUME Timing C MSB DQ0 LSB Command C MSB DQ[1:0] LSB Command C MSB DQ[3:0] LSB Command Extended Dual Quad Note: 1. S# not shown. 256Mb, 3V Multiple I/O Serial Flash Memory SUSPEND/RESUME Operations CCMTD-1725822587-3368 mt25q-qljs-L256-ABA-xxT.pdf - Rev. K 07/18 EN 69 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

ONE-TIME PROGRAMMABLE Operations READ OTP ARRAY Command To initiate a READ OTP ARRAY command, S# is driven LOW . The command code is in- put on DQ0, followed by address bytes and dummy clock cycles. Each address bit is latched in during the rising edge of C. Data is shifted out on DQ1, beginning from the specified address and at a maximum frequency of fC (MAX) on the falling edge of the clock. The address increments automatically to the next address after each byte of data is shifted out. There is no rollover mechanism; therefore, if read continuously, after lo- cation 0x40, the device continues to output data at location 0x40. The operation is ter- minated by driving S# HIGH at any time during data output. Figure 43: READ OTP ARRAY Command Timing 7 8 C x0 C MSB DQ0 LSB Command A[MAX] A[MIN] 3 4 C x0 C MSB DQ[1:0] LSB Command A[MAX] A[MIN] MSB D OUT D OUT D OUT D OUT D OUT LSB Dummy cycles 1 2 C x0 C MSB DQ[3:0] LSB Command A[MAX] A[MIN] MSB D OUT D OUT D OUT LSB Dummy cycles Extended MSB D OUT D OUT D OUT D OUT D OUT LSB D OUT D OUT D OUT D OUT Dummy cycles Dual Quad DQ1 High-Z Don’t Care Note: 1. For extended-SPI protocol, C x = 7 + (A[MAX] + 1); For dual-SPI protocol, Cx = 3 + (A[MAX] + 1)/2; For quad-SPI protocol, Cx = 1 + (A[MAX] + 1)/4. PROGRAM OTP ARRAY Command To initiate the PROGRAM OTP ARRAY command, the WRITE ENABLE command must be issued to set the write enable latch bit to 1; otherwise, the PROGRAM OTP ARRAY command is ignored and flag status register bits are not set. S# is driven LOW and held LOW until the eighth bit of the last data byte has been latched in, after which it must be driven HIGH. The command code is input on DQ0, followed by address bytes and at least one data byte. Each address bit is latched in during the rising edge of the clock. When S# is driven HIGH, the operation, which is self-timed, is initiated; its duration is tPOTP . There is no rollover mechanism; therefore, after a maximum of 65 bytes are latched in the subsequent bytes are discarded. PROGRAM OTP ARRAY programs, at most, 64 bytes to the OTP memory area and one OTP control byte. When the operation is in progress, the write in progress bit is set to 1. 256Mb, 3V Multiple I/O Serial Flash Memory ONE-TIME PROGRAMMABLE Operations CCMTD-1725822587-3368 mt25q-qljs-L256-ABA-xxT.pdf - Rev. K 07/18 EN 70 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

The write enable latch bit is cleared to 0, whether the operation is successful or not, and the status register and flag status register can be polled for the operation status. When the operation completes, the write in progress bit is cleared to 0. If the operation times out, the write enable latch bit is reset and the program fail bit is set to 1. If S# is not driven HIGH, the command is not executed, flag status register error bits are not set, and the write enable latch remains set to 1. The operation is considered complete once bit 7 of the flag status register outputs 1 with at least one byte output. The OTP control byte (byte 64) is used to permanently lock the OTP memory array. Table 32: OTP Control Byte (Byte 64) Bit Name Settings Description

0 OTP control byte 0 = Locked

1 = Unlocked (default) Used to permanently lock the 64-byte OTP array. When bit 0 = 1, the 64-byte OTP array can be programmed. When bit 0 = 0, the 64-byte OTP array is read only. Once bit 0 has been programmed to 0, it can no longer be changed to 1. Program OTP array is ignored, the write enable latch bit remains set, and flag status register bits 1 and 4 are set. Figure 44: PROGRAM OTP Command Timing 7 8 C x0 C MSB DQ0 LSB Command A[MAX] A[MIN] MSB D IN D IN D IN D IN D IN LSB D IN D IN D IN D IN 3 4 C x0 C MSB DQ[1:0] LSB Command A[MAX] A[MIN] MSB D IN D IN D IN D IN D IN LSB 1 2 C x0 C MSB DQ[3:0] LSB Command A[MAX] A[MIN] MSB D IN D IN D IN LSB Extended Dual Quad Note: 1. For extended-SPI protocol, C x = 7 + (A[MAX] + 1); For dual-SPI protocol, Cx = 3 + (A[MAX] + 1)/2; For quad-SPI protocol, Cx = 1 + (A[MAX] + 1)/4. 256Mb, 3V Multiple I/O Serial Flash Memory ONE-TIME PROGRAMMABLE Operations CCMTD-1725822587-3368 mt25q-qljs-L256-ABA-xxT.pdf - Rev. K 07/18 EN 71 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

ENTER and EXIT 4-BYTE ADDRESS MODE Command To initiate these commands, S# is driven LOW, and the command is input on DQn. Table 33: ENTER and EXIT 4-BYTE ADDRESS MODE Operations Operation Name Description/Conditions ENTER 4-BYTE ADDRESS MODE (B7h) The effect of the command is immediate. The default address mode is three bytes, and the device returns to the default upon exiting the 4-byte address mode.EXIT 4-BYTE ADDRESS MODE (E9h) DEEP POWER-DOWN Operations ENTER DEEP POWER-DOWN Command To execute ENTER DEEP POWER-DOWN, S# must be driven HIGH after the eighth bit of the command code is latched in, after which, tDP time must elapse before the supply current is reduced to ICC2.. Any attempt to execute ENTER DEEP POWER-DOWN during a WRITE operation is rejected without affecting the operation. In deep power-down mode, no device error bits are set, the WEL state is unchanged, and the device ignores all commands except RELEASE FROM DEEP POWER-DOWN, RESET ENABLE, RESET , hardware reset, and power-loss rescue sequence commands. RELEASE FROM DEEP POWER-DOWN Command To execute the RELEASE FROM DEEP POWER-DOWN command, S# is driven LOW, fol- lowed by the command code. Sending additional clock cycles on C while S# is driven LOW voids the command. RELEASE FROM DEEP POWER-DOWN is terminated by driving S# HIGH. The device enters standby mode after S# is driven HIGH followed by a delay of tRDP . S# must re- main HIGH during this time. Table 34: DEEP POWER-DOWN Operations Operation Name Description/Conditions ENTER DEEP POWER-DOWN (B9h) The command is used to place the device in deep power-down mode for the lowest device power consumption, with device current reduced to ICC2. This command can also be used as a software protection mechanism while the device is not in active use. RELEASE FROM DEEP POWER-DOWN (ABh) The command is used to exit from deep power-down mode. The device also exits deep power-down mode upon: A power-down, entering standby mode with the next power-up. A hardware or software reset operation, entering standby mode with a recovery time as specified in the AC Reset Specifications. 256Mb, 3V Multiple I/O Serial Flash Memory ADDRESS MODE Operations CCMTD-1725822587-3368 mt25q-qljs-L256-ABA-xxT.pdf - Rev. K 07/18 EN 72 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Figure 45: ENTER DEEP POWER-DOWN Timing Extended t DP MSB LSB CommandDQ0 C Deep Power-Down Mode Standby Mode Quad MSB LSB CommandDQ0[3:0] C Deep Power-Down Mode Standby Mode Dual MSB LSB CommandDQ0[1:0] Deep Power-Down Mode Standby Mode C t DP t DP 256Mb, 3V Multiple I/O Serial Flash Memory DEEP POWER-DOWN Operations CCMTD-1725822587-3368 mt25q-qljs-L256-ABA-xxT.pdf - Rev. K 07/18 EN 73 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Figure 46: RELEASE FROM DEEP POWER-DOWN Timing Extended MSB LSB CommandDQ0 C Deep Power-Down Mode Standby Mode Quad MSB LSB CommandDQ[3:0] C Dual MSB LSB CommandDQ[1:0] C Deep Power-Down Mode Standby Mode Deep Power-Down Mode Standby Mode t RDP t RDP t RDP 256Mb, 3V Multiple I/O Serial Flash Memory DEEP POWER-DOWN Operations CCMTD-1725822587-3368 mt25q-qljs-L256-ABA-xxT.pdf - Rev. K 07/18 EN 74 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

ENTER or RESET QUAD INPUT/OUTPUT MODE Command To initiate these commands, the WRITE ENABLE command must not be executed. S# must be driven LOW, and the command must be input on DQn. Table 35: ENTER and RESET QUAD PROTOCOL Operations Operation Name Description/Conditions ENTER QUAD INPUT/OUTPUT MODE (35h) The effect of the command is immediate. RESET QUAD INPUT/OUTPUT MODE (F5h) 256Mb, 3V Multiple I/O Serial Flash Memory QUAD PROTOCOL Operations CCMTD-1725822587-3368 mt25q-qljs-L256-ABA-xxT.pdf - Rev. K 07/18 EN 75 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

CYCLIC REDUNDANCY CHECK Operations A CYCLIC REDUNDANCY CHECK (CRC) operation is a hash function designed to de- tect accidental changes to raw data and is used commonly in digital networks and stor- age devices such as hard disk drives. A CRC-enabled device calculates a short, fixed- length binary sequence, known as the CRC code or just CRC, for each block of data. CRC can be a higher performance alternative to reading data directly in order to verify re- cently programmed data. Or, it can be used to check periodically the data integrity of a large block of data against a stored CRC reference over the life of the product. CRC helps improve test efficiency for programmer or burn-in stress tests. No system hardware changes are required to enable CRC. The CRC-64 operation follows the ECMA standard. The generating polynomial is: G(x) = x64 + x62 + x57 + x55 + x54 + x53 + x52 + x47 + x46 + x45 + x40 + x39 + x38 + x37 + x35 + x33 + x32 + x31 + x29 + x27 + x24 + x23 + x22 + x21 + x19 + x17 + x13 + x12 + x10 + x9 + x7 + x4 + x + 1 Note: The data stream sequence is from LSB to MSB and the default initial CRC value is all zero. The device CRC operation generates the CRC result of the entire device or of an address range specified by the operation. Then the CRC result is compared with the expected CRC data provided in the sequence. Finally the device indicates a pass or fail through the bit #4 of FLAG STATUS REGISTER. If the CRC fails, it is possible to take corrective action such as verifying with a normal read mode or by rewriting the array data. CRC operation supports CRC data read back when CRC check fails; the CRC data gener- ated from the target address range or entire device will be stored in a dedicated register: general purpose read register (GPRR) only when CRC check fails, and it can be read out through the GPRR read sequence with command 96h, least significant byte first. GPRR is reset to default all 0 at the beginning of the CRC operation, and so customer will read all 0 if CRC operation pass. Note that the GPRR is a volatile register. It is cleared to all 0s on power-up and hard- ware/software reset. Read GPRR starts from the first location, when clocked continu- ously, will output 00h after location 64. The CYCLIC REDUNDANCY CHECK operation command sequences are shown in the tables below, for an entire die or for a selected range. Table 36: CRC Command Sequence on Entire Device Command Sequence DescriptionByte# Data 1 9Bh Command code for interface activation 2 27h Sub-command code for CRC operation

3 FFh CRC operation option selection (CRC operation on entire device)

4 CRC[7:0] 1st byte of expected CRC value

5–10 CRC[55:8] 2nd to 7th byte of expected CRC value

11 CRC[63:56] 8th byte of expected CRC value

Drive S# HIGH Operation sequence confirmed; CRC operation starts 256Mb, 3V Multiple I/O Serial Flash Memory CYCLIC REDUNDANCY CHECK Operations CCMTD-1725822587-3368 mt25q-qljs-L256-ABA-xxT.pdf - Rev. K 07/18 EN 76 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Table 37: CRC Command Sequence on a Range Command Sequence DescriptionByte# Data 1 9Bh Command code for interface activation 2 27h Sub-command code for CRC operation

3 FEh CRC operation option selection (CRC operation on a range)

5–10 CRC[55:8] 2nd to 7th byte of expected CRC value

12 Start Address [7:0] Specifies the starting byte address for CRC operation

13–14 Start Address [23:8]

15 Start Address [31:24]

16 Stop Address [7:0] Specifies the ending byte address for CRC operation

17–18 Stop Address [23:8]

19 Stop Address [31:24]

Drive S# HIGH Operation sequence confirmed; CRC operation starts 256Mb, 3V Multiple I/O Serial Flash Memory CYCLIC REDUNDANCY CHECK Operations CCMTD-1725822587-3368 mt25q-qljs-L256-ABA-xxT.pdf - Rev. K 07/18 EN 77 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

The device can be in only one state at a time. Depending on the state of the device, some operations as shown in the table below are allowed (Yes) and others are not (No). For example, when the device is in the standby state, all operations except SUSPEND are allowed in any sector. For all device states except the erase suspend state, if an oper- ation is allowed or disallowed in one sector, it is allowed or disallowed in all other sec- tors. In the erase suspend state, a PROGRAM operation is allowed in any sector except the one in which an ERASE operation has been suspended. Table 38: Operations Allowed/Disallowed During Device States Operation Standby State Program or Erase State Subsector Erase Suspend or Program Suspend State Erase Suspend State Notes READ (memory) Yes No Yes Yes 1 READ (status/flag status registers) Yes Yes Yes Yes 6 PROGRAM Yes No No Yes/No 2 ERASE (sector/subsector) Yes No No No 3 WRITE Yes No No No 4 WRITE Yes No Yes Yes 5 SUSPEND No Yes No No 7 Notes: 1. All READ operations except READ STATUS REGISTER and READ FLAG REGISTER. When is- sued to a sector or subsector that is simultaneously in an erase suspend state, the READ operation is accepted, but the data output is not guaranteed until the erase has comple- ted. 2. All PROGRAM operations except PROGRAM OTP. In the erase suspend state, a PROGRAM operation is allowed in any sector (Yes) except the sector (No) in which an ERASE opera- tion has been suspended. 3. Applies to the SECTOR ERASE or SUBSECTOR ERASE operation. 4. Applies to the following operations: WRITE STATUS REGISTER, WRITE NONVOLATILE CONFIGURATION REGISTER, PROGRAM OTP, and BULK ERASE. 5. Applies to the WRITE VOLATILE CONFIGURATION REGISTER, WRITE ENHANCED VOLA- TILE CONFIGURATION REGISTER, WRITE ENABLE, WRITE DISABLE, CLEAR FLAG STATUS REGISTER, WRITE EXTENDED ADDRESS REGISTER, or WRITE LOCK REGISTER operation. 6. Applies to the READ STATUS REGISTER or READ FLAG STATUS REGISTER operation. 7. Applies to the PROGRAM SUSPEND or ERASE SUSPEND operation. 256Mb, 3V Multiple I/O Serial Flash Memory State Table CCMTD-1725822587-3368 mt25q-qljs-L256-ABA-xxT.pdf - Rev. K 07/18 EN 78 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Execute-in-place (XIP) mode allows the memory to be read by sending an address to the device and then receiving the data on one, two, or four pins in parallel, depending on the customer requirements. XIP mode offers maximum flexibility to the application, saves instruction overhead, and reduces random access time. Activate and Terminate XIP Using Volatile Configuration Register Applications that boot in SPI and must switch to XIP use the volatile configuration reg- ister. XIP provides faster memory READ operations by requiring only an address to exe- cute, rather than a command code and an address. To activate XIP requires two steps. First, enable XIP by setting volatile configuration reg- ister bit 3 to 0. Next, drive the XIP confirmation bit to 0 during the next FAST READ op- eration. XIP is then active. Once in XIP , any command that occurs after S# is toggled re- quires only address bits to execute; a command code is not necessary, and device oper- ations use the SPI protocol that is enabled. XIP is terminated by driving the XIP confir- mation bit to 1. The device automatically resets volatile configuration register bit 3 to 1. Activate and Terminate XIP Using Nonvolatile Configuration Register Applications that must boot directly in XIP use the nonvolatile configuration register. To enable a device to power-up in XIP using this register, set nonvolatile configuration reg- ister bits [11:9]. Settings vary according to protocol, as explained in the Nonvolatile Configuration Register section. Because the device boots directly in XIP , after the power cycle, no command code is necessary. XIP is terminated by driving the XIP confirmation bit to 1. Figure 47: XIP Mode Directly After Power-On C V CC DQ0 DQ[3:1] D OUTXb D OUT D OUT D OUT D OUT D OUT D OUT D OUT D OUT D OUT 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 t VSI (<100µ) NVCR check: XIP enabled Dummy cycles Mode 3 Mode 0 A[MAX] MSB A[MIN] LSB Note: 1. Xb is the XIP confirmation bit and should be set as follows: 0 to keep XIP state; 1 to exit XIP mode and return to standard read mode. 256Mb, 3V Multiple I/O Serial Flash Memory XIP Mode CCMTD-1725822587-3368 mt25q-qljs-L256-ABA-xxT.pdf - Rev. K 07/18 EN 79 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Confirmation Bit Settings Required to Activate or Terminate XIP The XIP confirmation bit setting activates or terminates XIP after it has been enabled or disabled. This bit is the value on DQ0 during the first dummy clock cycle in the FAST READ operation. In dual I/O XIP mode, the value of DQ1 during the first dummy clock cycle after the addresses is always "Don't Care." In quad I/O XIP mode, the values of DQ3, DQ2, and DQ1 during the first dummy clock cycle after the addresses are always "Don't Care." Table 39: XIP Confirmation Bit Bit Value Description 0 Activates XIP: While this bit is 0, XIP remains activated. 1 Terminates XIP: When this bit is set to 1, XIP is terminated and the device returns to SPI. Table 40: Effects of Running XIP in Different Protocols Protocol Effect Extended I/O and Dual I/O In a device with a dedicated part number where RESET# is enabled, a LOW pulse on that pin re- sets XIP and the device to the state it was in previous to the last power-up, as defined by the nonvolatile configuration register. Dual I/O Values of DQ1 during the first dummy clock cycle are "Don't Care." Quad I/O1 Values of DQ[3:1] during the first dummy clock cycle are "Don't Care." In a device with a dedica- ted part number, it is only possible to reset memory when the device is deselected. Note: 1. In a device with a dedicated part number where RESET# is enabled, a LOW pulse on that pin resets XIP and the device to the state it was in previous to the last power-up, as de- fined by the nonvolatile configuration register only when the device is deselected. Terminating XIP After a Controller and Memory Reset The system controller and the device can become out of synchronization if, during the life of the application, the system controller is reset without the device being reset. In such a case, the controller can reset the memory to power-on reset if the memory has reset functionality. (Reset is available in devices with a dedicated part number.)

• 7 clock cycles within S# LOW (S# becomes HIGH before 8th clock cycle)
• + 9 clock cycles within S# LOW (S# becomes HIGH before 10th clock cycle)
• + 13 clock cycles within S# LOW (S# becomes HIGH before 14th clock cycle)
• + 17 clock cycles within S# LOW (S# becomes HIGH before 18th clock cycle)
• + 25 clock cycles within S# LOW (S# becomes HIGH before 26th clock cycle)
• + 33 clock cycles within S# LOW (S# becomes HIGH before 34th clock cycle) These sequences cause the controller to set the XIP confirmation bit to 1, thereby termi- nating XIP . However, it does not reset the device or interrupt PROGRAM/ERASE opera- tions that may be in progress. After terminating XIP , the controller must execute RESET ENABLE and RESET MEMORY to implement a software reset and reset the device. 256Mb, 3V Multiple I/O Serial Flash Memory XIP Mode CCMTD-1725822587-3368 mt25q-qljs-L256-ABA-xxT.pdf - Rev. K 07/18 EN 80 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Power-Up and Power-Down Requirements At power-up and power-down, the device must not be selected; that is, S# must follow the voltage applied on VCC until VCC reaches the correct values: VCC,min at power-up and VSS at power-down. To provide device protection and prevent data corruption and inadvertent WRITE oper- ations during power-up, a power-on reset circuit is included. The logic inside the device is held to RESET while VCC is less than the power-on reset threshold voltage shown here; all operations are disabled, and the device does not respond to any instruction. During a standard power-up phase, the device ignores all commands except READ STATUS REGISTER and READ FLAG STATUS REGISTER. These operations can be used to check the memory internal state. After power-up, the device is in standby power mode; the write enable latch bit is reset; the write in progress bit is reset; and the dynamic protec- tion register is configured as: (write lock bit, lock down bit) = (0,0). Normal precautions must be taken for supply line decoupling to stabilize the VCC sup- ply. Each device in a system should have the VCC line decoupled by a suitable capacitor (typically 100nF) close to the package pins. At power-down, when VCC drops from the operating voltage to below the power-on-reset threshold voltage shown here, all opera- tions are disabled and the device does not respond to any command. When the operation is in progress, the program or erase controller bit of the status reg- ister is set to 0. To obtain the operation status, the flag status register must be polled. When the operation completes, the program or erase controller bit is cleared to 1. The cycle is complete after the flag status register outputs the program or erase controller bit to 1. Note: If power-down occurs while a WRITE, PROGRAM, or ERASE cycle is in progress, data corruption may result. Note: In extended-SPI protocol, 1Gb and 2Gb device must wait 100µs after VCC reaches VCC,min before polling the status register or flag status register. 256Mb, 3V Multiple I/O Serial Flash Memory Power-Up and Power-Down CCMTD-1725822587-3368 mt25q-qljs-L256-ABA-xxT.pdf - Rev. K 07/18 EN 81 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Figure 48: Power-Up Timing V CC V CC,min V WI Chip reset Chip selection not allowed Polling allowed t VSL Time Device fully accessible V CC,max Extended-SPI protocol Flag status register bit 7 = 0 Status register bit 0 = 1 Notes: 1. tVSL polling has to be in extended-SPI protocol and STR mode. 2. During tVSL period, HOLD# is enabled, RESET# disabled, and output strength is in de- fault setting. 3. In a system that uses a fast V CC ramp rate, current design requires a minimum 100µs af- ter VCC reaches tVWI, and before the polling is allowed, even though VCC,min is achieved. 4. In extended-SPI protocol, 1Gb and 2Gb device must wait 100µs after V CC reaches VCC,min before polling the status register or flag status register. Table 41: Power-Up Timing and VWI Threshold Note 1 applies to entire table Symbol Parameter Min Max Unit Notes tVSL VCC,min to device fully accessible – 300 µs 2, 3 VWI Write inhibit voltage 1.5 2.5 V 2 Notes: 1. When V CC reaches VCC,min, to determine whether power-up initialization is complete, the host can poll status register bit 0 or flag status register bit 7 only in extended-SPI protocol because the device will accept commands only on DQ0 and output data only on DQ1. When the device is ready, the host has full access using the protocol configured in the nonvolatile configuration register. If the host cannot poll the status register in x1 SPI mode, it is recommended to wait tVSL before accessing the device. 2. Parameters listed are characterized only. 3. On the first power-up after an event causing a subsector erase operation interrupt (for example, due to power-loss), the maximum time for tVSL will be up to 4.5ms in case of 4KB subsector erase interrupt and up to 36ms in case of 32KB subsector erase interrupt; this accounts for erase recovery embedded operation. 256Mb, 3V Multiple I/O Serial Flash Memory Power-Up and Power-Down CCMTD-1725822587-3368 mt25q-qljs-L256-ABA-xxT.pdf - Rev. K 07/18 EN 82 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Active, Standby, and Deep Power-Down Modes When S# is LOW, the device is selected and in active power mode. When S# is HIGH, the device is deselected but could remain in active power mode until ongoing internal op- erations are completed. Then the device goes into standby power mode and device cur- rent consumption drops to ICC1. Deep power-down mode enbles users to place the device in the lowest power consump- tion mode, ICC2. The ENTER DEEP POWER-DOWN command is used to put the device in deep power-down mode, and the RELEASE FROM DEEP POWER-DOWN command is used to bring the device out of deep power-down mode. Command details are in the Command Set table and the DEEP POWER-DOWN Operations section of this data sheet. Power Loss and Interface Rescue If a power loss occurs during a WRITE NONVOLATILE CONFIGURATION REGISTER command, after the next power-on, the device might begin in an undetermined state (XIP mode or an unnecessary protocol). If this occurs, a power loss recovery sequence must reset the device to a fixed state (extended-SPI protocol without XIP) until the next power-up. If the controller and memory device get out of synchronization, the controller can fol- low an interface rescue sequence to reset the memory device interface to power-up to the last reset state (as defined by latest nonvolatile configuration register). This resets only the interface, not the entire memory device, and any ongoing operations are not interrupted. After each sequence, the issue should be resolved definitively by running the WRITE NONVOLATILE CONFIGURATION REGISTER command again. Note: The two steps in each sequence must be in the correct order, and tSHSL2 must be at least 50ns for the duration of each sequence. The first step for both the power loss recovery and interface rescue sequences is descri- bed under "Recovery." The second step in the power loss recovery sequence is under "Power Loss Recovery" and the second step in the interface rescue sequence is under "Interface Rescue." Recovery Step one of both the power loss recovery and interface rescue sequences is DQ0 (PAD DATA) and DQ3 (PAD HOLD) equal to 1 for the situations listed here:

• 7 clock cycles within S# LOW (S# becomes HIGH before 8th clock cycle)
• + 9 clock cycles within S# LOW (S# becomes HIGH before 10th clock cycle)
• + 13 clock cycles within S# LOW (S# becomes HIGH before 14th clock cycle)
• + 17 clock cycles within S# LOW (S# becomes HIGH before 18th clock cycle)
• + 25 clock cycles within S# LOW (S# becomes HIGH before 26th clock cycle)
• + 33 clock cycles within S# LOW (S# becomes HIGH before 34th clock cycle) 256Mb, 3V Multiple I/O Serial Flash Memory Active, Standby, and Deep Power-Down Modes CCMTD-1725822587-3368 mt25q-qljs-L256-ABA-xxT.pdf - Rev. K 07/18 EN 83 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

For power loss recovery, the second part of the sequence is exiting from dual- or quad- SPI protocol by using the following FFh sequence: DQ0 and DQ3 equal to 1 for 8 clock cycles within S# LOW; S# becomes HIGH before 9th clock cycle. After this two-part se- quence the extended-SPI protocol is active. Interface Rescue For interface rescue, the second part of the sequence is for exiting from dual or quad- SPI protocol by using the following FFh sequence: DQ0 and DQ3 equal to 1 for 16 clock cycles within S# LOW; S# becomes HIGH before 17th clock cycle. For DTR protocol, 1 should be driven on both edges of clock for 16 cycles with S# LOW . After this two-part sequence, the extended-SPI protocol is active. Initial Delivery Status The device is delivered as follows:

• Memory array erased: all bits are set to 1 (each byte contains FFh)
• Status register contains 00h (all status register bits are 0)
• Nonvolatile configuration register (NVCR) bits all erased (FFFFh) 256Mb, 3V Multiple I/O Serial Flash Memory Initial Delivery Status CCMTD-1725822587-3368 mt25q-qljs-L256-ABA-xxT.pdf - Rev. K 07/18 EN 84 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Absolute Ratings and Operating Conditions Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only. Exposure to absolute maximum rating for extended periods may ad- versely affect reliability. Stressing the device beyond the absolute maximum ratings may cause permanent damage. Table 42: Absolute Ratings Symbol Parameter Min Max Units Notes TSTG Storage temperature –65 150 °C TLEAD Lead temperature during soldering – See note 1 °C VCC Supply voltage –0.6 4.0 V 2 VIO Input/output voltage with respect to ground –0.6 VCC + 0.6 V 2 VESD Electrostatic discharge voltage (human body model) –2000 2000 V 2, 3 Notes: 1. Compliant with JEDEC Standard J-STD-020C (for small-body, Sn-Pb or Pb assembly), RoHS, and the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU. 2. All specified voltages are with respect to V SS. During infrequent, nonperiodic transitions, the voltage potential between VSS and the VCC may undershoot to –2.0V for periods less than 20ns, or overshoot to VCC,max + 2.0V for periods less than 20ns. 3. JEDEC Standard JESD22-A114A (C1 = 100pF, R1 = 1500 Ω, R2 = 500Ω). Table 43: Operating Conditions Symbol Parameter Min Max Units VCC Supply voltage 2.7 3.6 V TA Ambient operating temperature (IT range) –40 85 °C TA Ambient operating temperature (AT range) –40 105 °C TA Ambient operating temperature (UT range) –40 125 °C Table 44: Input/Output Capacitance Note 1 applies to entire table Symbol Description Min Max Units CIN/OUT Input/output capacitance (DQ0/DQ1/DQ2/DQ3) – 10 pF CIN Input capacitance (other pins) – 6 pF CIN/S# Input/Chip select – 10 pF Note: 1. Verified in device characterization; not 100% tested. These parameters are not subject to a production test. They are verified by design and characterization. The capacitance is measured according to JEP147 ("PROCEDURE FOR MEASURING INPUT CAPACITANCE US- ING A VECTOR NETWORK ANALYZER (VNA)") with VCC and VSS applied and all other pins floating (except the pin under test), VBIAS = VCC/2, TA = 25°C, Frequency = 54 MHz. 256Mb, 3V Multiple I/O Serial Flash Memory Absolute Ratings and Operating Conditions CCMTD-1725822587-3368 mt25q-qljs-L256-ABA-xxT.pdf - Rev. K 07/18 EN 85 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Table 45: AC Timing Input/Output Conditions Symbol Description Min Max Units Notes CL Load capacitance – 30 pF 1 – Input rise and fall times – 1.5 ns Input pulse voltages 0.2VCC to 0.8VCC V 2 Input timing reference voltages 0.3VCC to 0.7VCC V Output timing reference voltages VCC/2 V Notes: 1. Output buffers are configurable by user. 2. For quad/dual operations: 0V to V CC. Figure 49: AC Timing Input/Output Reference Levels 0.8V CC 0.2V CC 0.7V CC 0.5V CC 0.3V CC Input levels 1 I/O timing reference levels Note: 1. 0.8V CC = VCC for dual/quad operations; 0.2VCC = 0V for dual/quad operations. 256Mb, 3V Multiple I/O Serial Flash Memory Absolute Ratings and Operating Conditions CCMTD-1725822587-3368 mt25q-qljs-L256-ABA-xxT.pdf - Rev. K 07/18 EN 86 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

DC Characteristics and Operating Conditions Table 46: DC Current Characteristics and Operating Conditions Notes 1–5 apply to entire table Parameter Symbol Test Conditions Typ Max Unit Input leakage current ILI – ±2 µA Output leakage current ILO – ±2 µA Standby current (IT range) ICC1 S# = VCC, VIN = VSS or VCC 30 75 µA Standby current (AT range) ICC1 S# = VCC, VIN = VSS or VCC 30 120 µA Standby current (UT range) ICC1 S# = VCC, VIN = VSS or VCC 30 180 µA Deep power-down current (IT range) ICC2 S# = VCC, VIN = VSS or VCC 5 35 µA Deep power-down current (AT range) ICC2 S# = VCC, VIN = VSS or VCC 5 80 µA Deep power-down current (UT range) ICC2 S# = VCC, VIN = VSS or VCC 5 120 µA Operating current (fast-read extended I/O) ICC3 C = 0.1VCC/0.9VCC at 133 MHz, DQ1 = open – 16 mA C = 0.1VCC/0.9VCC at 54 MHz, DQ1 = open – 10 mA Operating current (fast-read dual I/O) C = 0.1VCC/0.9VCC at 133 MHz DQ = open – 20 mA Operating current (fast-read quad I/O) C = 0.1VCC/0.9VCC at 133 MHz DQ = open – 22 mA C = 0.1VCC / 0.9VCC at 80 MHz DTR DQ = open – 28 mA C = 0.1VCC / 0.9VCC at 90 MHz DTR DQ = open – 31 mA Operating current (PROGRAM operations) ICC4 S# = VCC – 35 mA Operating current (WRITE operations) ICC5 S# = VCC – 35 mA Operating current (ERASE operations) ICC6 S# = VCC – 35 mA Notes: 1. All currents are RMS unless noted. Typical values at typical V CC (3.0/1.8V); VIO = 0V/VCC; TC = +25°C. 2. Standby current is the average current measured over any time interval 5µs after S de- assertion (and any internal operations are complete). 3. Deep power-down current is the average current measured 5ms over any 5ms time in- terval, 100µs after the ENTER DEEP POWER-DOWN operation (and any internal opera- tions are complete). 4. All read currents are the average current measured over any 1KB continuous read. No load, checker-board pattern. 5. All program currents are the average current measured over any 256-byte typical data program. 256Mb, 3V Multiple I/O Serial Flash Memory DC Characteristics and Operating Conditions CCMTD-1725822587-3368 mt25q-qljs-L256-ABA-xxT.pdf - Rev. K 07/18 EN 87 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Table 47: DC Voltage Characteristics and Operating Conditions Notes 1 applies to entire table Parameter Symbol Conditions Min Max Unit Input low voltage VIL –0.5 0.3VCC V Input high voltage VIH 0.7VCC VCC + 0.4 V Output low voltage VOL IOL = 1.6mA – 0.4 V Output high voltage VOH IOH = –100µA VCC - 0.2 – V Note: 1. V IL can undershoot to –1.0V for periods <2ns and VIH may overshoot to VCC,max + 1.0V for periods less than 2ns. 256Mb, 3V Multiple I/O Serial Flash Memory DC Characteristics and Operating Conditions CCMTD-1725822587-3368 mt25q-qljs-L256-ABA-xxT.pdf - Rev. K 07/18 EN 88 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

AC Characteristics and Operating Conditions Table 48: AC Characteristics and Operating Conditions Parameter Symbol Data Transfer Rate Min Typ Max Unit Notes Clock frequency for all commands other than READ (Extended-SPI, DIO-SPI, and QIO-SPI protocol) fC STR DC – 133 MHz DTR DC – 90 Clock frequency for READ command (03h) fR STR DC – 54 MHz DTR DC – 27 Clock HIGH time tCH STR 3.375 – – ns 2 DTR 5.0 – – Clock LOW time tCL STR 3.375 – – ns 2 DTR 5.0 – – Clock rise time (peak-to-peak) tCLCH STR/DTR 0.1 – – V/ns 3, 4 Clock fall time (peak-to-peak) tCHCL STR/DTR 0.1 – – V/ns 3, 4 S# active setup time (relative to clock) tSLCH STR/DTR 3.375 – – ns S# not active hold time (relative to clock) tCHSL STR/DTR 3.375 – – ns Data in setup time tDVCH STR 1.75 – – ns DTR 1.5 – – ns tDVCL DTR only 1.5 – – ns Data in hold time tCHDX STR/DTR 2.3 – – ns tCLDX DTR only 2.3 – – ns S# active hold time (relative to clock) tCHSH STR 3.375 – – ns DTR 5.0 – – S# active hold time (relative to clock LOW) Only for writes in DTR tCLSH DTR only 3.375 – – ns S# not active setup time (relative to clock) tSHCH STR 3.375 – – ns DTR 5.0 – – ns S# deselect time after a READ command tSHSL1 STR/DTR 20 – – ns S# deselect time after a nonREAD com- mand tSHSL2 STR/DTR 50 – – ns 5 Output disable time tSHQZ STR/DTR – – 7 ns 3 Clock LOW to output valid under 30pF tCLQV STR/DTR – – 6 ns Clock LOW to output valid under 10pF STR/DTR – – 5 ns Clock HIGH to output valid under 30pF tCHQV DTR only – – 6 ns Clock HIGH to output valid under 10pF DTR only – – 5 ns Output hold time tCLQX STR/DTR 1.5 – – ns Output hold time tCHQX DTR only 1.5 – – ns HOLD setup time (relative to clock) tHLCH STR/DTR 3.375 – – ns HOLD hold time (relative to clock) tCHHH STR/DTR 3.375 – – ns 256Mb, 3V Multiple I/O Serial Flash Memory AC Characteristics and Operating Conditions CCMTD-1725822587-3368 mt25q-qljs-L256-ABA-xxT.pdf - Rev. K 07/18 EN 89 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Table 48: AC Characteristics and Operating Conditions (Continued) Parameter Symbol Data Transfer Rate Min Typ Max Unit Notes HOLD setup time (relative to clock) tHHCH STR/DTR 3.375 – – ns HOLD hold time (relative to clock) tCHHL STR/DTR 3.375 – – ns HOLD to output Low-Z tHHQX STR/DTR – – 8 ns 3 HOLD to output High-Z tHLQZ STR/DTR – – 8 ns 3 CRC check time: main block tCRC STR/DTR – 1.3 - ms CRC check time: full chip (256Mb) tCRC STR/DTR – 1 - s Write protect setup time tWHSL STR/DTR 20 – – ns 6 Write protect hold time tSHWL STR/DTR 100 – – ns 6 S# HIGH to deep power-down tDP STR/DTR 3 – – us S# HIGH to standby mode (DPD exit time) tRDP STR/DTR 30 – – us WRITE STATUS REGISTER cycle time tW STR/DTR – 1.3 8 ms WRITE NONVOLATILE CONFIGURATION REGISTER cycle time tWNVCR STR/DTR – 0.2 1 s Nonvolatile sector lock time tPPBP STR/DTR – 0.1 2.8 ms Program ASP register tASPP STR/DTR – 0.1 0.5 ms Program password tPASSP STR/DTR – 0.2 0.8 ms Erase nonvolatile sector lock array tPPBE STR/DTR – 0.2 1 s Page program time (256 bytes) tPP STR/DTR – 120 1800 us 7 Page program time (n bytes) – 18 + 2.5 x int(n/6) 1800 us 8 PROGRAM OTP cycle time (64 bytes) tPOTP STR/DTR – 0.12 0.8 ms Sector erase time tSE STR/DTR – 0.15 1 s 4KB subsector erase time tSSE STR/DTR – 0.05 0.4 s 32KB subsector erase time tSSE STR/DTR – 0.1 1 s 256Mb bulk erase time tBE STR/DTR – 77 231 s Notes: 1. Typical values given for T A = 25 °C. 2. tCH + tCL must add up to 1/fC. 3. Value guaranteed by characterization; not 100% tested. 4. Expressed as a slew-rate. 5. nonREAD commands are WRITE, PROGRAM, and ERASE. 6. Only applicable as a constraint for a WRITE STATUS REGISTER command when STATUS REGISTER WRITE is set to 1. 7. Typical value is applied for pattern: 50% "0" and 50% "1". 8. int(n) correspond to the integer part of n, For example int (12/8) = 1, int (32/8) = 4, int(15.3) = 15. 256Mb, 3V Multiple I/O Serial Flash Memory AC Characteristics and Operating Conditions CCMTD-1725822587-3368 mt25q-qljs-L256-ABA-xxT.pdf - Rev. K 07/18 EN 90 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Table 49: AC RESET Conditions Note 1 applies to entire table Parameter Symbol Conditions Min Typ Max Unit Reset pulse width tRLRH2 50 – – ns Reset recovery time tRHSL Device deselected (S# HIGH) and is in XIP mode 40 – – ns Device deselected (S# HIGH) and is in standby mode 40 – – ns Commands are being decoded, any READ operations are in progress or any WRITE operation to volatile registers are in progress 40 – – ns Any device array PROGRAM/ERASE/SUSPEND/RESUME, PROGRAM OTP, NONVOLATILE SECTOR LOCK, and ERASE NONVOLATILE SECTOR LOCK ARRAY operations are in progress 30 – – µs While a WRITE STATUS REGISTER operation is in progress – tW – ms While a WRITE NONVOLATILE CONFIGURATION REGIS- TER operation is in progress – tWNVCR – ms On completion or suspension of a SUBSECTOR ERASE op- eration – tSSE – s Device in deep power-down mode – tRDP – ms While ADVANCED SECTOR PROTECTION PROGRAM oper- ation is in progress – tASPP – ms While PASSWORD PROTECTION PROGRAM operation is in progress – tPASSP – ms Software reset recovery time tSHSL3 Device deselected (S# HIGH) and is in standby mode 40 – – ns Any Flash array PROGRAM/ERASE/SUSPEND/RESUME, PROGRAM OTP, NONVOLATILE SECTOR LOCK, and ERASE NONVOLATILE SECTOR LOCK ARRAY operations are in progress 30 – – µs While WRITE STATUS REGISTER operation is in progress – tW – ms While a WRITE NONVOLATILE CONFIGURATION REGIS- TER operation is in progress – tWNVCR – ms On completion or suspension of a SUBSECTOR ERASE op- eration – tSSE – s Device in deep power-down mode – tRDP – ms While ADVANCED SECTOR PROTECTION PROGRAM oper- ation is in progress – tASPP – ms While PASSWORD PROTECTION PROGRAM operation is in progress – tPASSP – ms 256Mb, 3V Multiple I/O Serial Flash Memory AC Reset Specifications CCMTD-1725822587-3368 mt25q-qljs-L256-ABA-xxT.pdf - Rev. K 07/18 EN 91 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Program/Erase Specifications Table 50: Program/Erase Specifications Parameter Condition Typ Max Units Notes Erase to suspend Sector erase or erase resume to erase suspend 150 – µs 1 Program to suspend Program resume to program suspend 5 – µs 1 Subsector erase to sus- pend Subsector erase or subsector erase resume to erase sus- pend 50 – µs 1 Suspend latency Program 7 25 µs 2 Suspend latency Subsector erase 15 30 µs 2 Suspend latency Erase 15 30 µs 3 Notes: 1. Timing is not internally controlled. 2. Any READ command accepted. 3. Any command except the following are accepted: SECTOR, SUBSECTOR, or BULK ERASE; WRITE STATUS REGISTER; WRITE NONVOLATILE CONFIGURATION REGISTER; and PRO- GRAM OTP. 256Mb, 3V Multiple I/O Serial Flash Memory Program/Erase Specifications CCMTD-1725822587-3368 mt25q-qljs-L256-ABA-xxT.pdf - Rev. K 07/18 EN 95 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Revision History

Rev. K – 07/18

• Added I cc1 and Icc2 for UT in DC Characteristics and Operating Conditions
• Added tSHRH in AC RESET Conditions table Rev. J – 03/18
• Added Important Notes and Warnings section for further clarification aligning to in- dustry standards
• Added DEEP POWER-DOWN Operations
• Added Active Power, Standby Power, and Deep Power-Down modes
• Added figure for Serial Input Timing DTR
• Added tCRC in AC Characteristics and Operating Conditions Rev. I – 07/17
• Added UT device (operating temperature range: from –40°C to +125°C)
• Updated page program time in AC Characteristics and Operating Conditions table
• Added Output Timing for DTR figure in AC Reset Specifications Rev. H – 10/16
• Update Part Number Ordering Information figure Rev. G – 07/16
• Changed W# description
• Updated DTR (MAX) frequency to 90 MHz
• Changed Status Register table
• Changed Nonvolatile Configuration Register and Volatile Configuration Register ta- bles
• Added Initial Delivery Status Rev. F – 06/16
• Added general purpose read register notes to Command Definitions table Rev. E – 01/16
• Added code 60h for BULK ERASE Command in ERASE Operations in Command Set table in Command Definitions section
• Added note for READ and WRITE REGISTER Operations tables
• Updated I CC2,max to 35µA in DC Current Characteristics and Operating Conditions table Rev. D – 10/15
• Typo correction in Output Timing figure in AC Reset Specifications section 256Mb, 3V Multiple I/O Serial Flash Memory

mt25q-qljs-L256-ABA-xxT.pdf - Rev. K 07/18 EN 96 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Rev. C – 9/15

• Revised wrap table
• Revised supported clock frequencies DTR
• Change bit 3 setting of Enhanced Volatile Configuration Register from 0 to 1
• Revised AC table Rev. B – 6/15
• Added reference to serial flash discovery parameter data, which is now contained in a technical note
• Change DTR frequency at 80Mhz
• Revised cover page part number to: MT25QL256ABA.
• Revised signal assignments
• Revised supported clock frequencies with a note to reference TN-25-07: Tuning Data Pattern for MT25Q and MT25T Devices
• Revised serial flash discovery parameter with a note to reference TN-25-06: SFDP for MT25Q Family
• Increase ICC4 ,ICC5 and ICC6 at 35mA
• Added 80MHz information for I CC3 in DC specifications Rev. A – 06/14
• Initial release 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-4000 www.micron.com/products/support Sales inquiries: 800-932-4992 Micron and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered final, these specifications are subject to change, as further product development and data characterization some- times occur. 256Mb, 3V Multiple I/O Serial Flash Memory

mt25q-qljs-L256-ABA-xxT.pdf - Rev. K 07/18 EN 97 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.