MT24061 AEROFLEX | Alldatasheet
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Technical content
en MT24076 ARINCG29 PROTOCOL —->A—4 ee MCE= Micro Circuit Engineering Snuis eiches Putte LumsedCompany Note: This Device Supercedes MT24061. DEVICE INTERNAL ORGANISATION Rg bus E 3 g rege bs mT24e61 Pacey pe fff PLR) PAL(2) 4! i i, paged BL a | x i MONERNL eo! (Jr pF | MONERNE. CHKENL 4 1. CHKEN2 - 1 a i { XICKENL 4 “,, XECKENZ iar Fo i |seettnnenenrtn ttn renee RICK
FEATURES
SUPPORTS BOTH BP AND CP DATA BUS CONTAINS DUAL PROTOCOL LOGIC CIRCUITS ~ SYSTEMS. WITH CROSS-MONITORING. USE WITH MCE RECEIVER/MONITOR AND CONFIGURABLE AS TWO INDEPENDENT PROTOCOL TRANSMITTER CHIPS FOR FULL-FUNCTION UNITS FOR BUS SIMULATOR APPLICATIONS. ARINC 629 TERMINAL, LOW POWER CMOS TECHNOLOGY. SUPPORT FOR BUILT-IN TEST FUNCTIONS. 48 PIN DIL OR 44 PIN J-LEAD PACKAGES. i MT24076 ARINC 629 Protocol Chip Data Sheet - November 1991 Page 1
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1.0 General Description
This device is designed to work with the MCE ARINC 629 Transmitter and receiver/monitor chips. The three chips together implement a full function transmit and receive terminal. The chip implements the ARINC 629 bus access protocol logic for both BP and cP modes of operation. It uses Bus Quiet and other inputs to generate a Go-Ahead signal (TXGO) commanding the transmitter chip to start sending a message at the appropriate time. In CP mode it also generates output signals to indicate the current level of operation and examines an input to see if there is a request pending at this level. The chip contains two copies of the protocol logic with independent sources of timing parameters, and it uses two independent clock signals. Dual monitor circuits check the two protocol circuits agree on Go-Ahead time and current level of operation (CP), and also check the frequencies of the two clock sources agree within specified tolerances. When any disagreement is detected, a bi- directional signal (MONERN) is pulled low and the protocol circuits are re- initialised. The MONERN signal may be used to increment an error counter in the receiver/monitor chip. MONERN may be pulled low by the receiver/monitor chip to indicate a bus clash or transmission error has been detected. When this happens, the protocol logic executes the clash recovery sequence specified in the ARINC standard. Facilities are provided to allow in-system testing of the protocol monitoring logic. This is vital to prevent the build-up of latent faults in the monitoring logic which can prevent the detection of faults in the protocol circuits. Four separate clock enables are provided to allow simulation of timing errors. Different groups of clocks may be inhibited for a few cycles to simulate timer and clock frequency errors. The width of the resulting MONERN output pulse indicates whether neither, one or both of the monitor circuits detected the aiscrepancy. A future application note will deal with this subject in detail. The protocol chip can be specially configured for applications in bus simulator equipment. These units can contain many terminals, but high integrity is not needed, In these cases, the monitoring functions may be disabled, and the chip operated as two independent protocol circuits with separate Go-Ahead outputs, separate timing parameters and separate clock sources. Many protocol circuits may be used with a single receiver/monitor and transmitter chip. The device includes strap inputs to enable extensions to the protocol which are currently under evaluation.
2.0 Bus Access Timing Parameters
When the chip is used with MCE transmitter and receiver/monitor chips, timing parameters are loaded as follows. Timing parameters for the first channel are stored in the RPP prom and loaded under the control of the receiver chip. Timing parameters for the second channel are stored in the XPP prom and loaded through a separate port under the control of the transmitter chip. Each channel is loaded with 3 bytes using 8 parallel data inputs, two address inputs and a load input, Both channels must be loaded with the same parameter values. The protocol circuits will not operate until all parameters have been loaded. Parameters may be re~loaded at any time, but changing values or BP/CP modes without disabling the chip first is likely to cause erroneous behaviour. Channel Address Inputs Data inputs
1 PA11,PA10 P17,P16,P15,P14,P13,P12,P11,P10 |
2 PA21,PA20 P27,P26,P25,P24,P23,P22,P21,P20
1 oO 8G1,T16,TI5,TI4,TI3,TI2,TI1,TIO 1 1 SGO,TG6,TG5S,TG4,TG3,TG2,TG1,TGO ° 1 BCP,ML6,ML5,ML4,ML3,ML2,ML1,MLO i MT24076 ARINC 629 Protocol Chip Data Sheet - November 1991 Page 2 '
TI6-0, SG1-0, TG6-0 are the binary values for Transmit Interval, Synchronisation Gap, and Terminal Gap timers respectively as defined in the ARINC 629 standard. BCP is a single bit BP/CP mode selector, BCP=1 for BP, BCP=0 for CP. ML6-0 is a binary value to set the AT timer (CP only). It specifies the time difference between TI and AT. This time difference must be set greater than (MAL + PSG) where MAL is the longest level 2 or 3 message length. Time differences map onto ML binary values as follows: ML Time Difference (>MAL+PSG) 3 118yus 4 149puS i26 3962s 127 3993ys The specific formula for AT is: . where TI and ML are the respective binary values. AT may vary by up to +2uS from the calculated value due to logic and synchronisation delays.
3.0 Initialisation and Error Recovery
The TXE inputs initialise and enable the protocol circuits. After taking TXE low to high, all timing parameters must be loaded before the chip becomes active. This prevents the protocol operating with invalid parameter values. When a discrepancy is detected by the monitoring circuits, an error output is asserted (MONERN) and the protocol circuits are initialised and immediately re- started. The two protocol circuits are reset and started at the same time even when the error is detected by only one of the monitor circuits. It is not necessary to re-load the timing parameters after MONERN. When MONERN is pulled low by an external device, the protocol circuits are forced to hold their TG counters in the reset state until the next time TI elapses. This is the collision recovery action specified in the ARINC standard.
4.0 Signals
Note: Some signals are not bonded out independently in the standard package options. Special bonding options may be ordered from MCE. PA2-P1LO_& P27-P20 Two 8 bit data input busses for parameter loading. P17-P10 are used to load channel 1. P27-P20 are used to load channel 2. P17 and P27 are the most significant bits. Internal register data fields are defined in section 2.0. PALL. PALO & PA21,PA2O Two 2 bit address input busses for parameter loading. PA11,PA10 are used to load channel 1. PA21,PA20 are used to load channel 2. Internal register addresses are defined in section 2.0. PLOADNI & PLOADN2 Active low inputs to load parameters for each channel.
24076 ARINC 629 Protocol Chip Data Sheet - November 1992 Page 3 |
PLOADN \\—__f . 7-0 RRRKERIRKERRESEERERERRRERRK BATA VAIO KUREREER rat eno EEERXRIEERIIN ———ADOREES Va To —— ROO 2nd Hin 208 Hin’ 2Sn5 Min SLLENN This strap input enables an extension to the protocol associated with clash recovery on fibre-optic busses. This is an experimental feature currently under investigation. Tie this input high for standard protocol operation. SPMOD This strap input enables an extension to the combined protocol (CP) associated with improving bus utilisation at level 3. This is an experimental feature currently under investigation. Tie this input low for standard protocol operation. RICK & XICK Two independent clock inputs. RICK is the receiver clock. XICK is the transmitter clock. These should be 32MHz for a 2M bus bit rate. Minimum pulse high or low time is 12.5nS. The frequency should be maintained within 10.01% of nominal under all conditions. RICKENL. XICKENL, RICKEN2, XICKEN2 Active high clock enable inputs toa the two protocol channels. Each channel uses both XICK and RICK, and each may be enabled independently. ‘The use of these inputs for in-system testing of the monitoring logic will be described in a separate application note. For normal operation all of these inputs should be tied high. CHKEN]_& CHKEN2 These active high strap inputs enable the monitoring circuits. For normal operation they should be both tied high. They should be both tied low only when the two protocol channels are being used independently and monitoring is not required. TXEL & TXE2 Active high enable inputs to the two protocol channels. These signals will be normally tied together and driven from TXE on the receiver/monitor chip. They are internally linked to a single pin on the 44 pin j-lead package option. MONERN] & MONERN2 Bi-directional active low error signals from/to each protocol channel. A low going output pulse indicates the monitoring circuits have detected a discrepancy between the two protocol channels or clocks. ‘These signals have open-drain drivers and they should be normally joined together (they are internally linked on the 44 pin j-lead package option). When one monitor channel detects an error, the MONERN pulse width is nominally 593.75nS wide (low). When the two MONERN signals are linked and both monitor channels detect an error, the resulting pulse width is nominally 1093.75nS. On input MONERN should be pulled low for a minimum of 25nS to initiate clash recovery action. MT24076 ARINC 629 Protocol Chip Data Sheet - November 1991 Page 4
WWLILLVLIO & LYL2L. LVL20 Two 2 bit output busses indicating the current level of operation. In BP mode they always indicate level 1. LVL11,LVL10 are outputs from protocol channel 1. LVL21,LVL20 are outputs from protocol channel 2. The levels are encoded as follows: GYLXL.LVLxO =—-_ LEVEL oo Level 12 o1 Level 2
11 Level 3 Backlog
10 Level 3 New
In normal use both channels will output the same levels. Only one channel is used to drive the associated transmitter chip. Channel 2 outputs are not brought out to pins on the 44 pin j-lead package option. REQSTIN1 & REOSTNZ : Active low inputs tell the protocol logic there is a request pending at the current level (indicated by the LVLxx outputs). These inputs are sampled just before each transmission opportunity. The Go-Ahead signal will only be issued if there is a request pending. REQSTN1 controls protocol channel 1 and REQSTN2 controls protocol channel 2. They are normally linked together and driven from the REQSTN output of the associated transmitter chip. They are internally linked and brought out to a single pin on the 44 pin J-lead package option. REOSTN. SCN nade t ee as a es. a A609 Bis Min 0.3505 Hin @.65US Max® % This time can be much Longer in BP and CP Level 1 when TXGO 1s controlled by TI. BQ & BO2 Active high Bus Quiet inputs generally driven from the 8Q output of the associated receiver chip. The protocol timers are optimised for a median delay of 190nS from the end of the last bit of a wordstring at the receiver inputs (RXI/RXN) to the assertion of BQ. BQ1l controls protocol channel 1 and BQ2 controls protocol channel 2. They are normally linked together. They are internally linked and brought out to a single pin on the 44 pin J-lead package option. TXGQl & TXGO2 Active high transmit go-ahead output to the associated transmitter chip. Nominal pulse width is 250nS. TXGO1 is generated by protocol channel 1 and TXGO2 is generated by protocol channel 2. TXOIN_& TXNIN Manchester encoded data inputs from the Transmitter chip (MT25003). Note that TXNIN must be inverted between MT25003 and this chip using an external inverter with propagation delay of less than 1lons. TXO_& TEN Manchester encoded data outputs to the SIM. The protocol chip reconstructs the missing parity bit in data from the transmitter and delivers the corrected data to the SIM with a one clock cycle (31.25nS) delay from TXOIN/TXNIN. Note that TXN must be inverted between this chip and the SIM using an external inverter. MT24076 ARINC 629 Protocol Chip Data Sheet ~- November 1991 Page § t
antue see 100-8207 7-4 core " nONETOR CHT pee oor PRON By wreseot mot To iad ] [Es] lit RICK PLOADNL mab Pale HE mee ntz4e78 Pais [Per] MONERNL Pe tvocer cure PLC-PLT to smn( TT xo So 8 ae) 1H Tagot 8 P2e-Pe7 mea z rere | ea Perea 2B TE gy rlomone Hae FE bb EG rowm if $ ; +4 Danan oar oa N ARINC 529 " R21 rf wr TRANSMITTER CHIP 8200-8207 LV onra £.0 Configuring the chip as Two Independent Protocol Circuits This requires a special bonding option with CHKEN1 & 2 tied low and MONERNI & MONERN2 bonded out to separate pins. XICK should be tied high and RICK should be tied low. Channel 1 clock is supplied to XICKEN1 and channel 2 clock is supplied to XICKEN2. CHKEN] & CHKEN2 are both tied low to disable the monitor circuits. This also disables the check for valid timing parameters before activating the protocol circuits. The protocol circuits are now activated immediately TXE is taken high. Timing parameters are loaded in the usual way except the two channels may be supplied with different values. JITENN and CPMOD are common and so will be configured the same in both channels. TXE1, REQSTN1, BQ1, LVL11,LVL10 & TXGOl are associated with channel 1 only. TXE2, REQSTN2, 8Q2, LVL21,LVL20 & TXGO2 are associated with channel 2 only. MONERN1 is only used as an input to signal clash detection to channel 1. MONERN2 performs the same function for channel 2.
1.0 General Electrical Characteristics
All timing parameters are specified for the following conditions unless otherwise stated: Ambient temperature range -55°C to 125°C VDD voltage range 4.5v to 5.5v Output load Capacitance SopF Falling edge measurements are made to Vol=0.8v Rising edge measurements are made to Voh=2.0v All outputs have 4mA drive except TXGO1 & TXGO2 which have 6mA drive. MONERN1 & MONERN2 are open drain output stages. The following signals have internal high value (50KN approx.) pullup resistors: JITENN, CPMOD, CHKEN1, CHKEN2, PLOADN1, PLOADN2, RICKEN1, RICKEN2, XICKEN1, XICKENZ, MONERN1, MONERN2. The following signals have internal high value (50KN approx.) pulidow resistors: BQl, BQ2, TXE1, TXE2. MT24076 ARINC 629 Protocol Chip Data Sheet - November 1991 Page 6 {
S1.67mm 17. 27mm [ [ee 18.30me {] ES ete TE Eng T cy P a 7 a?
48 PIN DIL CERAMIC PACKAGE
TOP UIEW 44 PIN J-LEAD PACKAGE TOP view
2.0 Pin Assignments
48.Pin OTL Package 44 Pin J-Lead Package Rin signal Pin Signal Pin Signal Pin Signal
1 PL4 25 P27 1 P13 23° «P27
2 P15 26 P2i 2 Pl4 24 P21
3 P16 27) «P22 3) «PIs 25 P22
4 P17 28 = P20 4 P16 26 =©P20
5 BQ2 29 PA2O 5 P17 27 PA2O
6 BQL 30 -PA21 6 BQ 28 «PA21
7 VSS (Ov) 31 0 «XICK 7 VSS (Ov) 29 «XICK
8 TXE2 32 RICKEN2 8 XE 30 RICKEN2
9 TXE1 33 XICKEN2 9 TXGOL 31 =X ICKEN2
10° = TXGOL 34 TXOIN 10 MONERN 32 TXOIN
11 MONERN 35 CPMOD 11s Tx 33° «CPMOD
- «TXO 36 0 = LVL21 12. PLOADN1 34 = VSS(0v) 13 PLOADN1 37 -LVL20 13. PLOADN2 35 TXNIN 14 ~— PLOADN2 38 TXNIN 14 -TXGO2 36 RICKEN1
15 TXGO2 39 RICKEN1 15 LVL10 37 XICKEN2
16 LVL1O 40 XICKEN1 16 LVL11 38 TXN
17) sOLWL11 41 TXN 17. VDD (+5v) 39 RICK 18 ~=VDD (+5v) 42° RICK 18 REQSTN 40 P12
19 REQSTN2 43° P12 19 P23 41 Pll
20 = REQSTN1 44 Pll 20 P24 42 P10 2100 «P23 45 P10 21 (P25 43 PALO 220 «P24 46 = PA1O 22 (P26 44 PALL 2300 «P25 47 PALL \\
24 P26 48 P13 |
Note: JITENN, CHKEN1 & CHKEN2 are not bonded out. MONERN1 & MONERN2 are both bonded to a single pin. Special bonding options are available from MCE. = c= Alexandra Way, Ashchurch, Tewkesbury | — Gloucestershire GL20 8TB Mino Crom chee Toler 32 Pay ee) 2008 subsidiary of vat Reg. No. wscnsn i a . . Simhs Industnes Pubhe LamuedCompany Regutered in England 1047888 | MT24076 ARINC 629 Protocol Chip Data Sheet - November 1991 Page 7 | f