MT16VDDF12864HG-262

MT16VDDF6464H MICRON | Alldatasheet

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Features

• 200-pin, small-outline, dual in-line memory module (SODIMM)  Fast data transfer rates: PC1600, PC2100, and PC2700  Utilizes 200 MT/s, 266 MT/s, or 333 MT/s DDR SDRAM components  512MB (64 Meg x 64), 1GB (128 Meg x 64) DD = VDDQ = +2.5V V DDSPD = +2.3V to +3.6V  2.5V I/O (SSTL_2 compatible)  Commands entered on each positive CK edge  DQS edge-aligned with data for READs; center- aligned with data for WRITEs  Internal, pipelined double data rate (DDR) architecture; two data accesses per clock cycle  Bidirectional data strobe (DQS) transmitted/ received with data—i.e., source-synchronous data capture  Differential clock inputs CK and CK#  Four internal device banks for concurrent operation  Programmable burst lengths: 2, 4, or 8  Auto precharge option  Auto Refresh and Self Refresh Modes  7.8125µs maximum average periodic refresh interval  Serial Presence Detect (SPD) with EEPROM  Programmable READ CAS latency G o l d e d g e c o n t a c t s Figure 1: 200-Pin SODIMM (MO-224) NOTE: 1. Contact factory for availability of lead-free prod- ucts. 2. CL = CAS (READ) latency. OPTIONS MARKING P a c k a g e 200-pin SODIMM (standard) G 200-pin SODIMM (lead-free)1 Y F r e q u e n c y / C A S L a t e n c y2 167 MHz (333 MT/s) CL = 2.5 -335

133 MHz (266 MT/s) CL = 2 -262

133 MHz (266 MT/s) CL = 2

-26A 133 MHz (266 MT/s) CL = 2.5 -265

100 MHz (200 MT/s) CL = 2 -202

Table 1: Address Table 512MB 1GB Refresh Count 8K 8K Device Row Addressing 8K (A0–A12) 8K (A0–A12) Device Bank Addressing 4 (BA0, BA1) 4 (BA0, BA1) Device Configuration 32 Meg x 8 64 Meg x 8 Device Column Addressing 1K (A0–A9) 2K (A0–A9, A11) Module Rank Addressing 2 (S0#, S1#) 2 (S0#, S1#)

512MB, 1GB (x64) 200-PIN DDR SODIMM 09005aef80a646bc Micron Technology, Inc., reserves the right to change products or specifications without notice. DDF16C64_128x64HG_B.fm - Rev. B 7/03 EN 2 ©2003 Micron Technology, Inc. NOTE: All part numbers end with a two-place code (not shown), designating component and PCB revisions. Consult factory for current Revision codes. Example: MT16VDDF6464HG-265A1. Table 2: Part Numbers and Timing Parameters PART NUMBER MODULE DENSITY CONFIGURATION TRANSFER RATE MEMORY CLOCK/ DATA BIT RATE LATENCY (CL - tRCD - tRP) MT16VDDF6464HG-335__ 512MB 64 Meg x 64 2.7 GB/s 6ns/333 MT/s 2.5-3-3 MT16VDDF6464HY-335__ 512MB 64 Meg x 64 2.7 GB/s 6ns/333 MT/s 2.5-3-3 MT16VDDF6464HG-262__ 512MB 64 Meg x 64 2.1 GB/s 7.5ns/266 MT/s 2-2-2 MT16VDDF6464HY-262__ 512MB 64 Meg x 64 2.1 GB/s 7.5ns/266 MT/s 2-2-2 MT16VDDF6464HG-26A__ 512MB 64 Meg x 64 2.1 GB/s 7.5ns/266 MT/s 2-3-3 MT16VDDF6464HY-26A__ 512MB 64 Meg x 64 2.1 GB/s 7.5ns/266 MT/s 2-3-3 MT16VDDF6464HG-265__ 512MB 64 Meg x 64 2.1 GB/s 7.5ns/266 MT/s 2.5-3-3 MT16VDDF6464HY-265__ 512MB 64 Meg x 64 2.1 GB/s 7.5ns/266 MT/s 2.5-3-3 MT16VDDF6464HG-202__ 512MB 64 Meg x 64 1.6 GB/s 10ns/200 MT/s 2-2-2 MT16VDDF6464HY-202__ 512MB 64 Meg x 64 1.6 GB/s 10ns/200 MT/s 2-2-2 MT16VDDF12864HG-335__ 1GB 128 Meg x 64 2.7 GB/s 6ns/333 MT/s 2.5-3-3 MT16VDDF12864HY-335__ 1GB 128 Meg x 64 2.7 GB/s 6ns/333 MT/s 2.5-3-3 MT16VDDF12864HG-262__ 1GB 128 Meg x 64 2.1 GB/s 7.5ns/266 MT/s 2-2-2 MT16VDDF12864HY-262__ 1GB 128 Meg x 64 2.1 GB/s 7.5ns/266 MT/s 2-2-2 MT16VDDF12864HG-26A__ 1GB 128 Meg x 64 2.1 GB/s 7.5ns/266 MT/s 2-3-3 MT16VDDF12864HY-26A__ 1GB 128 Meg x 64 2.1 GB/s 7.5ns/266 MT/s 2-3-3 MT16VDDF12864HG-265__ 1GB 128 Meg x 64 2.1 GB/s 7.5ns/266 MT/s 2.5-3-3 MT16VDDF12864HY-265__ 1GB 128 Meg x 64 2.1 GB/s 7.5ns/266 MT/s 2.5-3-3 MT16VDDF12864HG-202__ 1GB 128 Meg x 64 1.6 GB/s 10ns/200 MT/s 2-2-2 MT16VDDF12864HY-202__ 1GB 128 Meg x 64 1.6 GB/s 10ns/200 MT/s 2-2-2

512MB, 1GB (x64) 200-PIN DDR SODIMM 09005aef80a646bc Micron Technology, Inc., reserves the right to change products or specifications without notice. DDF16C64_128x64HG_B.fm - Rev. B 7/03 EN 3 ©2003 Micron Technology, Inc. Figure 2: Module Layout Table 3: Pin Assignment (200-Pin SODIMM Front) PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL 1V REF 51 V SS 101 A9 151 DQ42 3V SS 53 DQ19 103 V SS 153 DQ43 5D Q 0 5 5 D Q 2 4 105 A7 155 V DD 7D Q 1 57 V DD 107 A5 157 V DD 9V DD 59 DQ25 109 A3 159 V SS

11 DQS0 61 DQS3 111 A1 161 V SS

13 DQ2 63 V SS 113 V DD 163 DQ48

15 V SS 65 DQ26 115 A10 165 DQ49

17 DQ3 67 DQ27 117 BA0 167 V DD

19 DQ8 69 V DD 119 WE# 169 DQS6

21 V DD 71 DNU 121 S0# 171 DQ50

23 DQ9 73 DNU 123 NC 173 V SS

25 DQS1 75 V SS 125 V SS 175 DQ51

27 V SS 77 DNU 127 DQ32 177 DQ56

29 DQ10 79 DNU 129 DQ33 179 V DD

31 DQ11 81 V DD 131 V DD 181 DQ57

33 V DD 83 DNU 133 DQS4 183 DQS7

35 CK0 85 NC 135 DQ34 185 V SS

37 CK0# 87 V SS 137 V SS 187 DQ58

39 V SS 89 DNU 139 DQ35 189 DQ59

41 DQ16 91 DNU 141 DQ40 191 V DD

43 DQ17 93 V DD 143 V DD 193 SDA

45 V DD 95 CKE1 145 DQ41 195 SCL

47 DQS2 97 NC 147 DQS5 197 V DDSPD

49 DQ18 99 A12 149 V SS 199 NC

Table 4: Pin Assignment (200-Pin SODIMM Back) PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL 2V REF 52 V SS 102 A8 152 DQ46 4V SS 54 DQ23 104 V SS 154 DQ47

6 DQ4 56 DQ28 106 A6 156 V DD

8D Q 5 58 V DD 108 A4 158 CK1#

10 V DD 60 DQ29 110 A2 160 CK1

1 2D M 06 2D M 3 112 A0 162 V SS

14 DQ6 64 V SS 114 V DD 164 DQ52

16 V SS 66 DQ30 116 BA1 166 DQ53

18 DQ7 68 DQ31 1 1 8R A S #1 6 8 V DD

20 DQ12 70 V DD 1 2 0C A S #1 7 0D M 6

22 V DD 72 DNU 122 S1# 172 DQ54

24 DQ13 74 DNU 124 NC 174 V SS

26 DM1 76 V SS 126 V SS 176 DQ55

28 V SS 78 DNU 128 DQ36 178 DQ60

30 DQ14 80 DNU 130 DQ37 180 V DD

32 DQ15 82 V DD 132 V DD 182 DQ61

34 V DD 84 DNU 134 DM4 184 DM7

36 V DD 86 DNU 136 DQ38 186 V SS

38 V SS 88 V SS 138 V SS 188 DQ62

40 V SS 90 V SS 140 DQ39 190 DQ63

42 DQ20 92 V DD 142 DQ44 192 V DD

44 DQ21 94 V DD 144 V DD 194 SA0

46 V DD 96 CKE0 146 DQ45 196 SA1

48 DM2 98 NC 148 DM5 198 SA2

50 DQ22 100 A11 150 V SS 200 V SS

PIN 1 PIN 199(all odd pins) PIN 2PIN 200 (all even pins) Front View Back View Indicates a VDD or VDDQ pin Indicates a V SS pin U1 U2 U3 U4 U5 U6 U7 U8 U17 U9 U10 U11 U12 U16U15U14U13 PIN 1 PIN 199(all odd pins) PIN 2PIN 200 (all even pins) Front View Back View

512MB, 1GB (x64) 200-PIN DDR SODIMM 09005aef80a646bc Micron Technology, Inc., reserves the right to change products or specifications without notice. DDF16C64_128x64HG_B.fm - Rev. B 7/03 EN 4 ©2003 Micron Technology, Inc. Table 5: Pin Descriptions Pin numbers may not correlate with symbols. Refer to Pin Assignment Tables on page 3 for more information PIN NUMBERS SYMBOL TYPE DESCRIPTION 118, 119, 120 WE#, CAS#,RAS# Input Command Inputs: RAS#, CAS#, and WE# (along with S#) define the command being entered. 35, 37, 158, 160 CK0, CK0# CK1, CK1# Input Clock: CK, CK# are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK, and negative edge of CK#. Output data (DQs and DQS) is referenced to the crossings of CK and CK#. 95, 96 CKE0, CKE1 Input Clock Enable: CKE HIGH activates and CKE LOW deactivates the internal clock, input buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER-DOWN and SELF REFRESH operations (all device banks idle), or ACTIVE POWER-DOWN (row ACTIVE in any device bank). CKE is synchronous for POWER-DOWN entry and exit, and for SELF REFRESH entry. CKE is asynchronous for SELF REFRESH exit and for disabling the outputs. CKE must be maintained HIGH throughout read and write accesses. Input buffers (excluding CK, CK# and CKE) are disabled during POWER-DOWN. Input buffers (excluding CKE) are disabled during SELF REFRESH. CKE is an SSTL_2 input but will detect an LVCMOS LOW level after VDD is applied and until CKE is first brought HIGH. After CKE is brought HIGH, it becomes an SSTL_2 input only. 121, 122 S0#, S1# Input Chip Selects: S# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when S# is registered HIGH. S# is considered part of the command code. 116, 117 BA0, BA1 Input Bank Address: BA0 and BA1 define to which device bank an ACTIVE, READ, WRITE, or PRECHARGE command is being applied. 99, 100, 101, 102, 105,106, 107, 108, 109, 110, 111, 112, 115 A0-A12 Input Address Inputs: Provide the row address for ACTIVE commands, and the column address and auto precharge bit (A10) for READ/WRITE commands, to select one location out of the memory array in the respective device bank. A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one device bank (A10 LOW, device bank selected by BA0, BA1) or all device banks (A10 HIGH). The address inputs also provide the op-code during a MODE REGISTER SET command. BA0 and BA1 define which mode register (mode register or extended mode register) is loaded during the LOAD MODE REGISTER command. 1, 2 V REF Input SSTL_2 reference voltage.

195 SCL Input Serial Clock for Presence-Detect: SCL is used to synchronize the

presence-detect data transfer to and from the module. 194, 196, 198 SA0-SA2 Input Presence-Detect Address Inputs: These pins are used to configure the presence-detect device.

193 SDA Input/

Serial Presence-Detect Data: SDA is a bidirectional pin used to transfer addresses and data into and out of the presence- detect portion of the module. 12, 26, 48, 62, 134, 148, 170, 184 DM0-DM7 Input Data Write Mask. DM LOW allows WRITE operation. DM HIGH blocks WRITE operation. DM lines do not affect READ operation.

512MB, 1GB (x64) 200-PIN DDR SODIMM 09005aef80a646bc Micron Technology, Inc., reserves the right to change products or specifications without notice. DDF16C64_128x64HG_B.fm - Rev. B 7/03 EN 5 ©2003 Micron Technology, Inc. 11, 25, 47, 61, 133, 147, 169, 183 DQS0-DQS7 Input/ Output Data Strobe: Output with READ data, input with WRITE data. DQS is edge-aligned with READ data, centered in WRITE data. Used to capture data. 56, 59, 60, 65, 66, 67, 68, 127, 128, 129, 130, 135, 136, 139, 140, 141, 142, 145, 146, 151, 152, 153, 154, 163, 164, 165, 166, 171, 172, 175, 176, 177, 178, 181, 182, 187, 188, 189, 190 DQ0-DQ63 Input/ Output Data I/Os: Data bus. 93, 94, 113, 114, 131, 132, 143, 144, 155, 156, 157, 167, 168, 179, 180, 191, 192 V DD Supply Power Supply: +2.5V ±0.2V. 90, 103, 104, 125, 126, 137, 138, 149, 150, 159, 161, 162, 173, 174, 185, 186, 200 VSS Supply Ground. 197 V DDSPD Supply Serial EEPROM positive power supply: +2.3V to +3.6V 85, 97, 98, 123, 124, 199 NC — No Connect: These pins should be left unconnected. 83, 84, 86, 89, 91 DNU — Do Not Use: These pins are not connected on this module, but are assigned pins on other modules in this product family. Table 5: Pin Descriptions (Continued) Pin numbers may not correlate with symbols. Refer to Pin Assignment Tables on page 3 for more information PIN NUMBERS SYMBOL TYPE DESCRIPTION

512MB, 1GB (x64) 200-PIN DDR SODIMM 09005aef80a646bc Micron Technology, Inc., reserves the right to change products or specifications without notice. DDF16C64_128x64HG_B.fm - Rev. B 7/03 EN 6 ©2003 Micron Technology, Inc. Figure 3: Functional Block Diagram – 512MB SA0 SERIAL PD U17 SDA SA1 SA2 BA0, BA1 A0-A12 RAS# BA0, BA1: DDR SDRAMs A0-A12: DDR SDRAMs RAS#: DDR SDRAMs CAS#: DDR SDRAMs CKE0: DDR SDRAMs U1-U8 CKE1: DDR SDRAMs U9-U16 WE#: DDR SDRAMs CAS# CKE0 CKE1 WE# VREF VSS DDR SDRAMs DDR SDRAMs DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DQ DQ DQ DQ DQ DQ DQ DQ DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ DQ DQ DQ DQ DQ DQ DQ DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ DQ DQ DQ DQ DQ DQ DQ DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ DQ DQ DQ DQ DQ DQ DQ DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ DQ DQ DQ DQ DQ DQ DQ DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DM CS# DQS DQ DQ DQ DQ DQ DQ DQ DQ DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM0 S0# DQ DQ DQ DQ DQ DQ DQ DQ WP SCL U14 DQ DQ DQ DQ DQ DQ DQ DQ U13 DQ DQ DQ DQ DQ DQ DQ DQ U11 DQ DQ DQ DQ DQ DQ DQ DQ U16 DQ DQ DQ DQ DQ DQ DQ DQ S1# DM CS# DQS DM CS# DQS DM CS# DQS DM CS# DQS DM CS# DQS DM CS# DQS DQS0 DM7 DQS7 DM2 DQS2 DM5 DQS5 U12 DQ DQ DQ DQ DQ DQ DQ DQ DM CS# DQS DM4 DQS4 DM3 DQS3 DM CS# DQS DM CS# DQS DQ DQ DQ DQ DQ DQ DQ DQ U10 DQ DQ DQ DQ DQ DQ DQ DQ DM CS# DQS DM CS# DQS DM CS# DQS DM CS# DQS DM6 DQS6 DM1 DQS1 U15 DQ DQ DQ DQ DQ DQ DQ DQ DM CS# DQS DQ DQ DQ DQ DQ DQ DQ DQ DM CS# DQS VDDSPD VDD DDR SDRAMs SPD/EEPROM DDR SDRAMs U1, U2, U3, U7 U12, U13, U14, U16 CK0 CK0# 120 DDR SDRAMs U4, U5, U6, U8 U9, U10, U11, U15 CK1 CK1# 120 120ΩCK2 CK2# NOTE: 1. All resistor values are 22 /g87 unless otherwise specified. 2. Per industry standard, Micron utilizes various component speed grades as referenced in the Module Part Numbering Guide at www.micron.com/ numberguide. DDR SDRAMs: MT46V32M8S2FD DDR SDRAMs: MT46V64M8S2FD

512MB, 1GB (x64) 200-PIN DDR SODIMM 09005aef80a646bc Micron Technology, Inc., reserves the right to change products or specifications without notice. DDF16C64_128x64HG_B.fm - Rev. B 7/03 EN 7 ©2003 Micron Technology, Inc. Figure 4: Functional Block Diagram – 1GB SA0 SERIAL PD U17 SDA SA1 SA2 BA0, BA1 A0-A12 RAS# BA0, BA1: DDR SDRAMs A0-A12: DDR SDRAMs RAS#: DDR SDRAMs CAS#: DDR SDRAMs CKE0: DDR SDRAMs U1-U8 CKE1: DDR SDRAMs U9-U16 WE#: DDR SDRAMs CAS# CKE0 CKE1 WE# VREF VSS DDR SDRAMs DDR SDRAMs DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DQ DQ DQ DQ DQ DQ DQ DQ DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ DQ DQ DQ DQ DQ DQ DQ DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ DQ DQ DQ DQ DQ DQ DQ DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ DQ DQ DQ DQ DQ DQ DQ DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ DQ DQ DQ DQ DQ DQ DQ DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DM CS# DQS DQ DQ DQ DQ DQ DQ DQ DQ DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM0 S0# DQ DQ DQ DQ DQ DQ DQ DQ WP SCL U12 DQ DQ DQ DQ DQ DQ DQ DQ U11 DQ DQ DQ DQ DQ DQ DQ DQ U10 DQ DQ DQ DQ DQ DQ DQ DQ U16 DQ DQ DQ DQ DQ DQ DQ DQ S1# DM CS# DQS DM CS# DQS DM CS# DQS DM CS# DQS DM CS# DQS DM CS# DQS DQS0 DM7 DQS7 DM2 DQS2 DM5 DQS5 U15 DQ DQ DQ DQ DQ DQ DQ DQ DM CS# DQS DM4 DQS4 DM3 DQS3 DM CS# DQS DM CS# DQS DQ DQ DQ DQ DQ DQ DQ DQ U14 DQ DQ DQ DQ DQ DQ DQ DQ DM CS# DQS DM CS# DQS DM CS# DQS DM CS# DQS DM6 DQS6 DM1 DQS1 DQ DQ DQ DQ DQ DQ DQ DQ DM CS# DQS U13 DQ DQ DQ DQ DQ DQ DQ DQ DM CS# DQS VDDSPD VDD DDR SDRAMs SPD/EEPROM DDR SDRAMs U1, U2, U3, U7 U12, U13, U14, U16 CK0 CK0# 120 DDR SDRAMs U4, U5, U6, U8 U9, U10, U11, U15 CK1 CK1# 120 120ΩCK2 CK2# NOTE: 1. All resistor values are 22 /g87 unless otherwise specified. 2. Per industry standard, Micron utilizes various component speed grades as referenced in the Module Part Numbering Guide at www.micron.com/ numberguide. DDR SDRAMs: MT46V32M8S2FD DDR SDRAMs: MT46V64M8S2FD

512MB, 1GB (x64) 200-PIN DDR SODIMM 09005aef80a646bc Micron Technology, Inc., reserves the right to change products or specifications without notice. DDF16C64_128x64HG_B.fm - Rev. B 7/03 EN 8 ©2003 Micron Technology, Inc. General Description The MT16VDDF6464H and MT16VDDF12864H are high-speed CMOS, dynamic random-access, 512MB and 1GB memory modules organized in a x64 configu- ration. These modules use internally configured quad- bank DRAM devices. DDR SDRAM modules use a double data rate archi- tecture to achieve high-speed operation. The double data rate architecture is essentially a 2 n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the DDR SDRAM module effectively consists of a single 2 n-bit wide, one-clock-cycle data transfer at the internal DRAM core and two corre- sponding n-bit wide, one-half-clock-cycle data trans- fers at the I/O pins. A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in data capture at the receiver. DQS is an intermittent strobe transmitted by the DDR SDRAM during READs and by the memory controller during WRITEs. DQS is edge-aligned with data for READs and center-aligned with data for WRITEs. DDR SDRAM modules operate from a differential clock (CK and CK#); the crossing of CK going HIGH and CK# going LOW will be referred to as the positive edge of CK. Commands (address and control signals) are registered at every positive edge of CK. Input data is registered on both edges of DQS, and output data is referenced to both edges of DQS, as well as to both edges of CK. Read and write accesses to DDR SDRAM modules are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then fol- lowed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the device bank and row to be accessed (BA0, BA1 select devices bank; A0–A12 select device row). The address bits registered coincident with the READ or WRITE command are used to select the device bank and the starting device column loca- tion for the burst access. DDR SDRAM modules provides for programmable read or write burst lengths of 2, 4, or 8 locations. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. As with standard SDR SDRAM modules, the pipe- lined, multibank architecture of DDR SDRAM modules allows for concurrent operation, thereby providing high effective bandwidth by hiding row precharge and activation time. An auto refresh mode is provided, along with a power-saving power-down mode. All inputs are com- patible with the JEDEC Standard for SSTL_2. All out- puts are SSTL_2, Class II compatible. For more information regarding DDR SDRAM operation, refer to the 256Mb or 512Mb DDR SDRAM data sheets. Serial Presence-Detect Operation DDR SDRAM modules incorporate serial presence- detect (SPD). The SPD function is implemented using a 2,048-bit EEPROM. This nonvolatile storage device contains 256 bytes. The first 128 bytes can be pro- g r a m m e d b y M i c r o n t o i d e n t i f y t h e m o d u l e t y p e a n d various SDRAM organizations and timing parameters. The remaining 128 bytes of storage are available for use by the customer. System READ/WRITE operations between the master (system logic) and the slave EEPROM device (DIMM) occur via a standard I 2C bus using the DIMM’ s SCL (clock) and SDA (data) signals, together with SA (2:0), which provide eight unique DIMM/EEPROM addresses. Write protect (WP) is tied to ground on the module, permanently disabling hard- ware write protect. Mode Register Definition The mode register is used to define the specific mode of operation of the DDR SDRAM. This definition includes the selection of a burst length, a burst type, a CAS latency and an operating mode, as shown in Figure 5, Mode Register Definition Diagram, on page 9. The mode register is programmed via the MODE REG- ISTER SET command (with BA0 = 0 and BA1 = 0) and will retain the stored information until it is pro- grammed again or the device loses power (except for bit A8, which is self-clearing). Reprogramming the mode register will not alter the contents of the memory, provided it is performed cor- rectly. The mode register must be loaded (reloaded) when all device banks are idle and no bursts are in progress, and the controller must wait the specified time before initiating the subsequent operation. Vio- lating either of these requirements will result in unspecified operation. Mode register bits A0–A2 specify the burst length, A3 specifies the type of burst (sequential or inter- leaved), A4–A6 specify the CAS latency, and A7–A12 specify the operating mode.

512MB, 1GB (x64) 200-PIN DDR SODIMM 09005aef80a646bc Micron Technology, Inc., reserves the right to change products or specifications without notice. DDF16C64_128x64HG_B.fm - Rev. B 7/03 EN 9 ©2003 Micron Technology, Inc. Burst Length Read and write accesses to the DDR SDRAM are burst oriented, with the burst length being program- mable, as shown in Figure 5, Mode Register Definition Diagram. The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE command. Burst lengths of 2, 4, or 8 locations are available for both the sequential and the interleaved burst types. Reserved states should not be used, as unknown operation or incompatibility with future versions may result. When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached. The block is uniquely selected by A1–A i when the burst length is set to two, by A2–Ai when the burst length is set to four and by A3–Ai when the burst length is set to eight (where A i is the most significant column address bit for a given configuration. See Note 5 of Table 6, Burst Definition Table, on page 10, for A i values). The remaining (least significant) address bit(s) is (are) used to select the starting location within the block. The programmed burst length applies to both read and write bursts. Burst Type Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit M3. T h e o r d e r i n g o f a c c e s s e s w i t h i n a b u r s t i s d e t e r - mined by the burst length, the burst type and the start- ing column address, as shown in Table 6, Burst Definition Table, on page 10. Read Latency The READ latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first bit of output data. The latency can be set to 2 or 2.5 clocks, as shown in Figure 6, CAS Latency Diagram, on page 10. I f a R E A D c o m m a n d i s r e g i s t e r e d a t c l o c k e d g e n, and the latency is m clocks, the data will be available nominally coincident with clock edge n + m. The CAS Latency T able indicates the operating frequencies at which each CAS latency setting can be used. Reserved states should not be used as unknown operation or incompatibility with future versions may result. Figure 5: Mode Register Definition Diagram Burst LengthCAS Latency BT0* A9 A7 A6 A5 A4 A3A8 A2 A1 A0 Mode Register (Mx) Address Bus 9 7 654 38 2 1 0 Operating Mode A10A12 A11BA1 BA0 10111213 * M14 and M13 (BA1 and BA0) must be “0, 0” to select the base mode register (vs. the extended mode register). M3 = 0 Reserved Reserved Reserved Reserved Reserved Operating Mode Normal Operation Normal Operation/Reset DLL All other states reserved Valid Valid Burst Type Sequential Interleaved CAS Latency Reserved Reserved Reserved Reserved Reserved 2.5 Reserved Burst Length M6-M0 M8 M7M9M10M12 M11 M13

512MB, 1GB (x64) 200-PIN DDR SODIMM 09005aef80a646bc Micron Technology, Inc., reserves the right to change products or specifications without notice. DDF16C64_128x64HG_B.fm - Rev. B 7/03 EN 10 ©2003 Micron Technology, Inc. NOTE: 1. For a burst length of two, A1-Ai select the two-data-ele- ment block; A0 selects the first access within the block. 2. For a burst length of four, A2-Ai select the four-data- element block; A0-A1 select the first access within the block. 3. For a burst length of eight, A3-Ai select the eight-data- element block; A0-A2 select the first access within the block. 4. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. 5. i = 9 (512MB); i = 9,11 (1GB) Figure 6: CAS Latency Diagram Operating Mode The normal operating mode is selected by issuing a M O D E R E G I S T E R S E T c o m m a n d w i t h b i t s A 7 – A 1 2 each set to zero, and bits A0–A6 set to the desired val- ues. A DLL reset is initiated by issuing a MODE REGIS- TER SET command with bits A7 and A9–A12 each set to zero, bit A8 set to one, and bits A0–A6 set to the desired values. Although not required by the Micron device, JEDEC specifications recommend when a L O A D M O D E R E G I S T E R c o m m a n d i s i s s u e d t o r e s e t t h e D L L , i t s h o u l d a l w a y s b e f o l l o w e d b y a L O A D MODE REGISTER command to select normal oper at - ing mode. All other combinations of values for A7–A12 are reserved for future use and/or test modes. T est modes and reserved states should not be used because unknown operation or incompatibility with future ver- sions may result. Extended Mode Register The extended mode register controls functions beyond those controlled by the mode register; these additional functions are DLL enable/disable and out- put drive strength. These functions are controlled via the bits shown in Figure 7, Extended Mode Register Definition Diagram, on page 11. The extended mode register is programmed via the LOAD MODE REGIS- TER command to the mode register (with BA0 = 1 and Table 6: Burst Definition Table BURST LENGTH STARTING COLUMN ADDRESS ORDER OF ACCESSES WITHIN A BURST TYPE = SEQUENTIAL TYPE = INTERLEAVED 00 - 1 0 - 1 11 - 0 1 - 0 A1 A0 A2 A1 A0 Table 7: CAS Latency (CL) Table ALLOWABLE OPERATING CLOCK FREQUENCY (MHZ) SPEED CL = 2 CL = 2.5 -335 75 /g163 f /g163 133 75 /g163 f /g163 167 -262 75 /g163 f /g163 133 75 /g163 f /g163 133 -26A 75 /g163 f /g163 133 75 /g163 f /g163 133 -265 75 /g163 f /g163 100 75 /g163 f /g163 133 -202 75 /g163 f /g163 100 75 /g163 f /g163 125 CK CK# COMMAND DQ DQS CL = 2 READ NOP NOP NOP READ NOP NOP NOP Burst Length = 4 in the cases shown Shown with nominal tAC, tDQSCK, and tDQSQ CK CK# COMMAND DQ DQS CL = 2.5 T0 T1 T2 T2n T3 T3n T0 T1 T2 T2n T3 T3n DON T CARETRANSITIONING DATA

512MB, 1GB (x64) 200-PIN DDR SODIMM 09005aef80a646bc Micron Technology, Inc., reserves the right to change products or specifications without notice. DDF16C64_128x64HG_B.fm - Rev. B 7/03 EN 11 ©2003 Micron Technology, Inc. BA1 = 0) and will retain the stored information until it is programmed again or the device loses power. The e n a b l i n g o f t h e D L L s h o u l d a l w a y s b e f o l l o w e d b y a LOAD MODE REGISTER command to the mode regis- ter (BA0/ BA1 both LOW) to reset the DLL. The extended mode register must be loaded when all device banks are idle and no bursts are in progress, and the controller must wait the specified time before initiating any subsequent operation. Violating either of these requirements could result in unspecified opera- tion. DLL Enable/Disable The DLL must be enabled for normal operation. DLL enable is required during power-up initialization and upon returning to normal operation after having disabled the DLL for the purpose of debug or evalua- tion. (When the device exits self refresh mode, the DLL is enabled automatically.) Any time the DLL is enabled, 200 clock cycles must occur before a READ command can be issued. Figure 7: Extended Mode Register Definition Diagram NOTE: 1. BA1 and BA0 (E14 and E13) must be “0, 1” to select the Extended Mode Register (vs. the base Mode Register). 2. The QFC# option is not supported. DLL1101 A9 A7 A6 A5 A4 A3A8 A2 A1 A0 Extended Mode Register (Ex) Address Bus 9 7 654 38 2 1 0 Operating Mode A10A11A12BA1 BA0 1011121314 DS Operating Mode Reserved Reserved Valid DLL Enable Disable Drive Strength Normal Reduced E22 E0E1,E3E4 E6 E5E7E8E9 E10E11 E12 E13

512MB, 1GB (x64) 200-PIN DDR SODIMM 09005aef80a646bc Micron Technology, Inc., reserves the right to change products or specifications without notice. DDF16C64_128x64HG_B.fm - Rev. B 7/03 EN 12 ©2003 Micron Technology, Inc. Commands The Truth T ables below provides a general reference of available commands. For a more detailed descrip- tion of commands and operations, refer to the 256Mb or 512Mb DDR SDRAM component data sheet. NOTE: 1. DESELECT and NOP are functionally interchangeable. 2. BA0–BA1 provide device bank address and A0–A12 provide device row address. 3. BA0–BA1 provide device bank address; A0–A9 (512MB) or A0–A9, A11 (1GB) provide device column address; A10 HIGH enables the auto precharge feature (nonpersistent), and A10 LOW disables the auto precharge feature. 4. Applies only to read bursts with auto precharge disabled; this command is undefined (and should not be used) for READ bursts with auto precharge enabled and for WRITE bursts. 5. A10 LOW: BA0-BA1 determine which device bank is precharged. A10 HIGH: all device banks are precharged and BA0– BA1 are “Don’t Care.” 6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW. 7. Internal refresh counter controls device row addressing; all inputs and I/Os are “Don’t Care” except for CKE. 8. BA0–BA1 select either the mode register or the extended mode register (BA0 = 0, BA1 = 0 select the mode register; BA0 = 1, BA1 = 0 select extended mode register; other combinations of BA0-BA1 are reserved). A0–A12 provide the op-code to be written to the selected mode register. Table 8: Commands Truth Table CKE is HIGH for all commands shown except SELF REFRESH NAME (FUNCTION) CS# RAS# CAS# WE# ADDR NOTES DESELECT (NOP) HXXX X 1 NO OPERATION (NOP) LHHH X 1 ACTIVE (Select bank and activate row) L L H H Bank/Row 2 READ (Select bank and column, and start READ burst) L H L H Bank/Col 3 WRITE (Select bank and column, and start WRITE burst) L H L L Bank/Col 3 BURST TERMINATE LHHL X 4 PRECHARGE (Deactivate row in bank or banks) L L H L Code 5 AUTO REFRESH or SELF REFRESH (Enter self refresh mode) LLLH X 6 , 7 LOAD MODE REGISTER LLLLO p - C o d e 8 Table 9: DM Operation Truth Table Used to mask write data; provided coincident with the corresponding data NAME (FUNCTION) DM DQS WRITE Enable L Valid WRITE Inhibit HX

512MB, 1GB (x64) 200-PIN DDR SODIMM 09005aef80a646bc Micron Technology, Inc., reserves the right to change products or specifications without notice. DDF16C64_128x64HG_B.fm - Rev. B 7/03 EN 13 ©2003 Micron Technology, Inc. Absolute Maximum Ratings Stresses greater than those listed may cause perma- nent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the opera- tional sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Voltage on V DD Supply Voltage on VDDQ Supply Voltage on VREF and Inputs Voltage on I/O Pins Operating Temperature Table 10: DC Electrical Characteristics and Operating Conditions Notes: 1–5, 14; notes appear on pages 20–23; 0°C/g32/g163 TA /g163 +70°C PARAMETER/CONDITION SYMBOL MIN MAX UNITS NOTES Supply Voltage VDD 2.3 2.7 V 32, 36 I/O Supply Voltage VDDQ 2.3 2.7 V 32, 36, 39 I/O Reference Voltage VREF 0.49/g32/g180/g32 VDDQ 0.51/g32/g180/g32 VDDQ V6 , 3 9 I/O Termination Voltage (system) VTT VREF - 0.04 V REF + 0.04 V 7, 39 Input High (Logic 1) Voltage VIH(DC) V REF + 0.15 V DD + 0.3 V 25 Input Low (Logic 0) Voltage VIH(DC) -0.3 V REF - 0.15 V 25 INPUT LEAKAGE CURRENT Any input 0V /g163 VIN /g163 VDD, VREF pin 0V /g163 VIN /g163/g321.35V (All other pins not under test = 0V) Command/Address, RAS#, CAS#, WE# II -32 32 µA 47 S#, CKE, CK, CK# -16 16 DM -4 4 OUTPUT LEAKAGE CURRENT (DQs are disabled; 0V /g163 VOUT /g163/g32VDDQ) DQ, DQS IOZ -10 10 µA 47 OUTPUT LEVELS High Current (VOUT = VDDQ - 0.373V, minimum VREF, minimum VTT) Low Current (VOUT = 0.373V, maximum VREF, maximum VTT) IOH -16.8 – mA 33, 34IOL 16.8 – mA Table 11: AC Input Operating Conditions Notes: 1–5, 14; notes appear on pages 20–23; 0°C/g32/g163 TA /g163 +70°C; VDD = VDDQ = +2.5V ±0.2V PARAMETER/CONDITION SYMBOL MIN MAX UNIT S NOTES Input High (Logic 1) Voltage VIH(AC) V REF + 0.310 – V 12, 25, 35 Input Low (Logic 0) Voltage VIL(AC) – V REF - 0.310 V 12, 25, 35 I/O Reference Voltage VREF(AC) 0.49 /g180 VDDQ 0.49 /g180 VDDQV 6

512MB, 1GB (x64) 200-PIN DDR SODIMM 09005aef80a646bc Micron Technology, Inc., reserves the right to change products or specifications without notice. DDF16C64_128x64HG_B.fm - Rev. B 7/03 EN 14 ©2003 Micron Technology, Inc. Table 12: I DD Specifications and Conditions – 512MB Notes: 1–5, 8, 10, 12, 48; DDR SDRAM devices only; notes appear on pages 20–23; 0°C/g32/g163 TA /g163 +70°C; VDD, VDDQ = +2.5V ±0.2V MAX PARAMETER/CONDITION SYM -335 -262 -26A/- 265 -202 UNIT S NOTE S OPERATING CURRENT: One device bank; Active- Precharge; tRC = tRC (MIN); tCK = tCK (MIN); DQ, DM and DQS inputs changing once per clock cycle; Address and control inputs changing once every two clock cycles IDD0a 1,032 1,032 872 992 mA 20, 42 OPERATING CURRENT: One device bank; Active-Read- Precharge; Burst = 4; tRC = tRC (MIN); tCK = tCK (MIN); IOUT = 0mA; Address and control inputs changing once per clock cycle IDD1a 1,392 1,312 1,192 1,272 mA 20, 42 PRECHARGE POWER-DOWN STANDBY CURRENT: All device banks idle; Power-down mode; tCK = tCK (MIN); CKE = (LOW) IDD2Pb 64 64 64 64 mA 21, 28, IDLE STANDBY CURRENT: CS# = HIGH; All device banks are idle; tCK = tCK (MIN); CKE = HIGH; Address and other control inputs changing once per clock cycle. VIN = VREF for DQ, DQS, and DM IDD2Fb 800 720 720 720 mA 45 ACTIVE POWER-DOWN STANDBY CURRENT: One device bank active; Power-down mode; tCK = tCK (MIN); CKE = LOW IDD3Pb 480 400 400 480 mA 21, 28, ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One device bank active; tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle IDD3Nb 960 800 800 800 mA 41 OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); IOUT = 0mA IDD4Ra 1,432 1,232 1,232 1,432 mA 20, 42 OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle IDD4Wa 1,272 1,112 1,122 1,552 mA 20 AUTO REFRESH BURST CURRENT: tRC = tRFC (MIN) tRFC = 7.8125µs IDD5b 4,080 3,760 3,760 3,920 mA 20, 44 IDD5A b 96 96 96 96 mA 24, 44 SELF REFRESH CURRENT: CKE /g163 0.2V IDD6b 64 64 64 64 mA 9 OPERATING CURRENT: Four device bank interleaving READs (Burst = 4) with auto precharge, tRC = minimum tRC allowed; tCK = tCK (MIN); Address and control inputs change only during Active READ, or WRITE commands IDD7a 3,272 2,832 2,832 2,952 mA 20, 43 NOTE: a - Value calculated as one module rank in this operating condition, and all other module ranks in IDD2p (CKE LOW) mode. b - Value calculated reflects all module ranks in this operating condition.

512MB, 1GB (x64) 200-PIN DDR SODIMM 09005aef80a646bc Micron Technology, Inc., reserves the right to change products or specifications without notice. DDF16C64_128x64HG_B.fm - Rev. B 7/03 EN 15 ©2003 Micron Technology, Inc. Table 13: I DD Specifications and Conditions – 1GB Notes: 1–5, 8, 10, 12, 48; DDR SDRAM devices only; notes appear on pages 20–23; 0°C/g32/g163 TA /g163 +70°C; VDD, VDDQ = +2.5V ±0.2V MAX PARAMETER/CONDITION SYM -335 -262 -26A/- 265 -202 UNIT S NOTE S OPERATING CURRENT: One device bank; Active- Precharge; tRC = tRC (MIN); tCK = tCK (MIN); DQ, DM and DQS inputs changing once per clock cycle; Address and control inputs changing once every two clock cycles IDD0 1,080 1,080 960 960 mA 20, 42 OPERATING CURRENT: One device bank; Active-Read- Precharge; Burst = 4; tRC = tRC (MIN); tCK = tCK (MIN); IOUT = 0mA; Address and control inputs changing once per clock cycle IDD1 1,320 1,320 1,200 1,200 mA 20, 42 PRECHARGE POWER-DOWN STANDBY CURRENT: All device banks idle; Power-down mode; tCK = tCK (MIN); CKE = (LOW) IDD2P 80 80 80 80 mA 21, 28, IDLE STANDBY CURRENT: CS# = HIGH; All device banks are idle; tCK = tCK (MIN); CKE = HIGH; Address and other control inputs changing once per clock cycle. VIN = VREF for DQ, DQS, and DM IDD2F 720 720 640 640 mA 45 ACTIVE POWER-DOWN STANDBY CURRENT: One device bank active; Power-down mode; tCK = tCK (MIN); CKE = LOW IDD3P 560 560 480 480 mA 21, 28, ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One device bank active; tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle IDD3N 720 720 640 640 mA 41 OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); IOUT = 0mA IDD4R 1,360 1,360 1,200 1,200 mA 20, 42 OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle IDD4W 1,280 1,280 1,120 1,120 mA 20 AUTO REFRESH BURST CURRENT: tRC = tRFC (MIN) IDD5 4,640 4,640 4,480 4,480 mA 20, 44 tRC = 7.8125µs IDD5A 160 160 160 160 mA 24, 44 SELF REFRESH CURRENT: CKE /g163 0.2V IDD6 80 80 80 80 mA 9 OPERATING CURRENT: Four device bank interleaving READs (Burst = 4) with auto precharge, tRC = minimum tRC allowed; tCK = tCK (MIN); Address and control inputs change only during Active READ, or WRITE commands IDD7 3,280 3,240 2,840 2,840 mA 20, 43 NOTE: a - Value calculated as one module rank in this operating condition, and all other module ranks in IDD2p (CKE LOW) mode. b - Value calculated reflects all module ranks in this operating condition.

512MB, 1GB (x64) 200-PIN DDR SODIMM 09005aef80a646bc Micron Technology, Inc., reserves the right to change products or specifications without notice. DDF16C64_128x64HG_B.fm - Rev. B 7/03 EN 16 ©2003 Micron Technology, Inc. Table 14: Capacitance Note: 11; notes appear notes appear on pages 20–23 PARAMETER SYMBOL MIN MAX UNITS Input/Output Capacitance: DQ, DQS,DM CIO 79 p F Input Capacitance: Command and Address, RAS#, CAS#, WE# CI1 24 40 pF Input Capacitance:CK, CK#, CKE, S# CI2 12 20 pF Table 15: DDR SDRAM Component Electrica l Characteristics and Recommended AC Operating Conditions (-335, -262) Notes: 1–5, 12–15, 29, 40; notes appear on pages 20–23; 0°C/g32/g163 TA /g163 +70°C; VDD = VDDQ = +2.5V ±0.2V AC CHARACTERISTICS -335 -262 UNITS NOTESPARAMETER SYMBOL MIN MAX MIN MAX Access window of DQs from CK/CK# tAC -0.70 +0.70 -0.75 +0.75 ns CK high-level width tCH 0.45 0.55 0.45 0.55 tCK 26 CK low-level width tCL 0.45 0.55 0.45 0.55 tCK 26 Clock cycle time CL=2.5 tCK (2.5) 6 13 7.5 13 ns 40, 46 CL=2 tCK (2) 7.5 13 7.5 13 ns 40, 46 DQ and DM input hold time relative to DQS tDH 0.45 0.5 ns 23, 27 DQ and DM input setup time relative to DQS tDS 0.45 0.5 ns 23, 27 DQ and DM input pulse width (for each input) tDIPW 1.75 1.75 ns 27 Access window of DQS from CK/CK# tDQSCK -0.60 +0.60 -0.75 +0.75 ns DQS input high pulse width tDQSH 0.35 0.35 tCK DQS input low pulse width tDQSL 0.35 0.35 tCK DQS-DQ skew, DQS to last DQ valid, per group, per access tDQSQ 0.4 0.5 ns 22, 23 Write command to first DQS latching transition tDQSS 0.75 1.25 0.75 1.25 tCK DQS falling edge to CK rising - setup time tDSS 0.20 0.20 tCK DQS falling edge from CK rising - hold time tDSH 0.20 0.20 tCK Half clock period tHP tCH,tCL tCH,tCL ns 8 Data-out high-impedance window from CK/CK# tHZ +0.70 +0.75 ns 16, 37 Data-out low-impedance window from CK/CK# tLZ -0.70 -0.75 ns 16, 38 Address and control input hold time (fast slew rate) tIHF 0.75 0.90 ns 12 Address and control input setup time (fast slew rate) tISF 0.75 0.90 ns 12 Address and control input hold time (slow slew rate) tIHS 0.8 1 ns 12 Address and control input setup time (slow slew rate) tISS 0.8 1 ns 12 Address and Control input pulse width (for each input) tIPW 2.2 2.2 ns LOAD MODE REGISTER command cycle time tMRD 12 15 ns DQ-DQS hold, DQS to first DQ to go non-valid, per access tQH tHP -tQHS tHP -tQHS ns 22, 23 Data hold skew factor tQHS 0.75 0.75 ns ACTIVE to PRECHARGE command tRAS 42 70,000 40 120,000 ns 31 ACTIVE to READ with Auto precharge command tRAP 18 15 ns

512MB, 1GB (x64) 200-PIN DDR SODIMM 09005aef80a646bc Micron Technology, Inc., reserves the right to change products or specifications without notice. DDF16C64_128x64HG_B.fm - Rev. B 7/03 EN 17 ©2003 Micron Technology, Inc. ACTIVE to ACTIVE/AUTO REFRESH command period tRC 60 60 ns AUTO REFRESH command period tRFC 72 75 ns 44 ACTIVE to READ or WRITE delay tRCD 18 15 ns PRECHARGE command period tRP 18 15 ns DQS read preamble tRPRE 0.9 1.1 0.9 1.1 tCK 37 DQS read postamble tRPST 0.4 0.6 0.4 0.6 tCK ACTIVE bank a to ACTIVE bank b command tRRD 12 15 ns DQS write preamble tWPRE 0.25 0.25 tCK DQS write preamble setup time tWPRES 0 0 ns 18, 19 DQS write postamble tWPST 0.4 0.6 0.4 0.6 tCK 17 Write recovery time tWR 15 15 ns Internal WRITE to READ command delay tWTR 11 tCK Data valid output window NA tQH -tDQSQ tQH -tDQSQ ns 22 REFRESH to REFRESH command interval tREFC 70.3 70.3 µs 21 Average periodic refresh interval tREFI 7.8 7.8 µs 21 Terminating voltage delay to VDD tVTD 00 n s Exit SELF REFRESH to non-READ command tXSNR 75 75 ns Exit SELF REFRESH to READ command tXSRD 200 200 tCK Table 15: DDR SDRAM Component Electrica l Characteristics and Recommended AC Operating Conditions (-335, -262) (Continued) Notes: 1–5, 12–15, 29, 40; notes appear on pages 20–23; 0°C/g32/g163 TA /g163 +70°C; VDD = VDDQ = +2.5V ±0.2V AC CHARACTERISTICS -335 -262 UNITS NOTESPARAMETER SYMBOL MIN MAX MIN MAX

512MB, 1GB (x64) 200-PIN DDR SODIMM 09005aef80a646bc Micron Technology, Inc., reserves the right to change products or specifications without notice. DDF16C64_128x64HG_B.fm - Rev. B 7/03 EN 18 ©2003 Micron Technology, Inc. Table 16: DDR SDRAM Component Electrica l Characteristics and Recommended AC Operating Conditions (-26A, -265, -202) Notes: 1–5, 12–15, 29, 40; notes appear on pages 20–23; 0°C/g32/g163 TA /g163 +70°C; VDD = VDDQ = +2.5V ±0.2V AC CHARACTERISTICS -26A -265 -202 UNITS NOTESPARAMETER SYMBOL MIN MAX MIN MAX MIN MAX Clock cycle time CL=2.5 tCK (2.5) 7.5 13 7.5 13 8 13 ns 40, 46 CL=2 tCK (2) 7 . 5 1 31 01 3 1 0 1 3 n s 4 0 , 4 6 DQ and DM input hold time relative to DQS tDH 0.5 0.5 0.6 ns 23, 27 DQ and DM input setup time relative to DQS tDS 0.5 0.5 0.6 ns 23, 27 DQ and DM input pulse width (for each input) tDIPW 1.75 1.75 2 ns 27 DQS input high pulse width tDQSH 0.35 0.35 0.35 tCK DQS input low pulse width tDQSL 0.35 0.35 0.35 tCK DQS-DQ skew, DQS to last DQ valid, per group, per access tDQSQ 0.5 0.5 0.6 ns 22, 23 DQS falling edge to CK rising - setup time tDSS 0.20 0.20 0.20 tCK DQS falling edge from CK rising - hold time tDSH 0.20 0.20 0.20 tCK Half clock period tHP tCH,tCL tCH,tCL tCH,tCL ns 8 Data-out high-impedance window from CK/CK# tHZ +0.75 +0.75 +0.8 ns 16, 37 Data-out low-impedance window from CK/CK# tLZ -0.75 -0.75 -0.8 ns 16, 38 Address and control input hold time (fast slew rate) tIHF 0.90 0.90 1.1 ns 12 Address and control input setup time (fast slew rate) tISF .900 0.90 1.1 ns 12 Address and control input hold time (slow slew rate) tIHS 11 1 . 1 n s 1 2 Address and control input setup time (slow slew rate) tISS 11 1 . 1 n s 1 2 Address and Control input pulse width (for each input) tIPW 2.2 2.2 2.2 ns LOAD MODE REGISTER command cycle time tMRD 15 15 16 ns DQ-DQS hold, DQS to first DQ to go non-valid, per access tQH tHP -tQHS tHP -tQHS tHP -tQHS ns 22, 23 Data hold skew factor tQHS 0.75 0.75 1 ns ACTIVE to PRECHARGE command tRAS 40 120,000 40 120,000 40 120,000 ns 31 ACTIVE to READ with Auto precharge command tRAP 20 20 20 ns ACTIVE to ACTIVE/AUTO REFRESH command period tRC 65 65 70 ns AUTO REFRESH command period tRFC 75 75 80 ns 44 ACTIVE to READ or WRITE delay tRCD 20 20 20 ns PRECHARGE command period tRP 20 20 20 ns

512MB, 1GB (x64) 200-PIN DDR SODIMM 09005aef80a646bc Micron Technology, Inc., reserves the right to change products or specifications without notice. DDF16C64_128x64HG_B.fm - Rev. B 7/03 EN 19 ©2003 Micron Technology, Inc. ACTIVE bank a to ACTIVE bank b command tRRD 15 15 15 ns DQS write preamble tWPRE 0.25 0.25 0.25 tCK DQS write preamble setup time tWPRES 0 0 0 ns 18, 19 Write recovery time tWR 15 15 15 ns Internal WRITE to READ command delay tWTR 11 1 tCK Data valid output window NA tQH -tDQSQ tQH -tDQSQ tQH - tDQSQ ns 22 REFRESH to REFRESH command interval tREFC 70.3 70.3 70.3 µs 21 Average periodic refresh interval tREFI 7.8 7.8 7.8 µs 21 Terminating voltage delay to VDD tVTD 00 0 n s Exit SELF REFRESH to non-READ command tXSNR 75 75 80 ns Exit SELF REFRESH to READ command tXSRD 200 200 200 tCK Table 16: DDR SDRAM Component Electrica l Characteristics and Recommended AC Operating Conditions (-26A, -265, -202) (Continued) Notes: 1–5, 12–15, 29, 40; notes appear on pages 20–23; 0°C/g32/g163 TA /g163 +70°C; VDD = VDDQ = +2.5V ±0.2V AC CHARACTERISTICS -26A -265 -202 UNITS NOTESPARAMETER SYMBOL MIN MAX MIN MAX MIN MAX

512MB, 1GB (x64) 200-PIN DDR SODIMM 09005aef80a646bc Micron Technology, Inc., reserves the right to change products or specifications without notice. DDF16C64_128x64HG_B.fm - Rev. B 7/03 EN 20 ©2003 Micron Technology, Inc. Notes 1. All voltages referenced to V SS. 2. Tests for AC timing, I DD, and electrical AC and DC characteristics may be conducted at nominal ref- erence/supply voltage levels, but the related spec- ifications and device operation are guaranteed for the full voltage range specified. 3. Outputs measured with equivalent load: 4. AC timing and I DD tests may use a V IL-to-VIH s w i n g o f u p t o 1 . 5 V i n t h e t e s t e n v i r o n m e n t , b u t input timing is still referenced to V REF (or to the crossing point for CK/CK#), and parameter speci- fications are guaranteed for the specified AC input levels under normal use conditions. The mini- mum slew rate for the input signals used to test the device is 1V/ns in the range between V IL(AC) and VIH(AC). 5. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e., the receiver will effectively switch as a result of the signal crossing the AC input level, and will remain in that state as long as the signal does not ring back above [below] the DC input LOW [HIGH] level). 6. V REF is expected to equal V DDQ/2 of the transmit- ting device and to track variations in the DC level of the same. Peak-to-peak noise (non-common mode) on V REF may not exceed ±2 percent of the DC value. Thus, from V DDQ/2, V REF is allowed ±25mV for DC error and an additional ±25mV for AC noise. This measurement is to be taken at the nearest V REF bypass capacitor. 7. V TT is not applied directly to the device. V TT is a system supply for signal termination resistors, is expected to be set equal to V REF and must track variations in the DC level of VREF. 8. I DD is dependent on output loading and cycle rates. Specified values are obtained with mini- mum cycle time at CL = 2 for -262, -26A, and -202, CL = 2.5 for-335 and -265 with the outputs open. 9. Enables on-chip refresh and address counters. 10. I DD specifications are tested after the device is properly initialized, and is averaged at the defined cycle rate. 11. This parameter is sampled. V DD = +2.5V ±0.2V , VDDQ = +2.5V ±0.2V , VREF = V SS, f = 100 MHz, = 25°C, VOUT(DC) = VDDQ/2, VOUT (peak to peak) TA = 0.2V . DM input is grouped with I/O pins, reflect- ing the fact that they are matched in loading. 12. Command/Address input slew rate = 0.5V/ns. For -262, -26A, and -265 with slew rates 1V/ns and faster, tIS and tIH are reduced to 900ps; for -335, they are reduced to 750ps. If the slew rate is less than 0.5 V/ns, timing must be derated: tIS has an additional 50ps per each 100mV/ns reduction in slew rate from the 500mV/ns, while tIH remains constant. If the slew rate exceeds 4.5V/ns, func- tionality is uncertain. 13. The CK/CK# input reference level (for timing ref- erenced to CK/CK#) is the point at which CK and CK# cross; the input reference level for signals other than CK/CK# is V REF. 14. Inputs are not recognized as valid until V REF stabi- l i z e s . E x c e p t i o n : d u r i n g t h e p e r i o d b e f o r e VREF stabilizes, CKE /g163 0.3 x VDDQ is recognized as LOW. 15. The output timing reference level, as measured at the timing reference point indicated in Note 3, is V TT. 16. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referenced to a specific voltage level, but specify when the device output is no longer driving (HZ) or begins driving (LZ). 17. The intent of the Don’t Care state after completion of the postamble is the DQS-driven signal should either be high, lo w , or high-Z and that any signal transition within the input switching region must follow valid input requirements. That is, if DQS transitions high (above V IH DC (MIN) then it must not transition low (below V IH DC) prior to tDQSH (MIN). 18. This is not a device limit. The device will operate with a negative value, but system performance could be degraded due to bus turnaround. 1 9 . I t i s r e c o m m e n d e d t h a t D Q S b e v a l i d ( H I G H o r LOW) on or before the WRITE command. The case shown (DQS going from High-Z to logic LOW) applies when no WRITEs were previously in progress on the bus. If a previous WRITE was in progress, DQS could be HIGH during this time, depending on tDQSS. 20. MIN ( tRC or tRFC) for I DD measurements is the smallest multiple of tCK that meets the minimum absolute Value for the respective parameter. tRAS (MAX) for IDD measurements is the largest multi- Output (VOUT) Reference Point 50Ω VTT 30pF

512MB, 1GB (x64) 200-PIN DDR SODIMM 09005aef80a646bc Micron Technology, Inc., reserves the right to change products or specifications without notice. DDF16C64_128x64HG_B.fm - Rev. B 7/03 EN 21 ©2003 Micron Technology, Inc. ple of tCK that meets the maximum absolute value for tRAS. 21. The refresh period 64ms. This equates to an aver- age refresh rate of 7.8125µs. However, an AUTO REFRESH command must be asserted at least once every 70.3µs; burst refreshing or posting by the DRAM controller greater than eight refresh cycles is not allowed. 22. The valid data window is derived by achieving other specifications: tHP (tCK/2), tDQSQ, and tQH (tQH = tHP - tQHS). The data valid window derates directly porportional with the clock duty cycle and a practical data valid window can be derived. The clock is allowed a maximum duty cycle varia- tion of 45/55. Functionality is uncertain when operating beyond a 45/55 ratio. Figure 8, Derating Data Valid Window, shows derating curves for duty cycles ranging between 50/50 and 45/55. 23. Each byte lane has a corresponding DQS. 24. This limit is actually a nominal value and does not r e s u l t i n a f a i l v a l u e . C K E i s H I G H d u r i n g REFRESH command period ( tRFC [MIN]) else CKE is LOW (i.e., during standby). 25. T o maintain a valid level, the transitioning edge of the input must: a. Sustain a constant slew rate from the current AC level through to the target AC level, V IL(AC) or VIH(AC). b. Reach at least the target AC level. c. After the AC target level is reached, continue to maintain at least the target DC level, V IL(DC) or VIH(DC). 26. JEDEC specifies CK and CK# input slew rate must be /g179 1V/ns (2V/ns differentially). 27. DQ and DM input slew rates must not deviate from DQS by more than 10 percent. If the DQ/ D M / D Q S s l e w r a t e i s l e s s t h a n 0 . 5 V / n s , t i m i n g must be derated: 50ps must be added to tDS and tDH for each 100mv/ns reduction in slew rate. If slew rate exceeds 4V/ns, functionality is uncer- tain. 28. V DD must not vary more than 4 percent if CKE is not active while any bank is active. 2 9 . T h e c l o c k i s a l l o w e d u p t o ± 1 5 0 p s o f j i t t e r . E a c h timing parameter is allowed to vary by the same amount. Figure 8: Derating Data Valid Window 3.750 3.700 3.650 3.600 3.550 3.500 3.450 3.400 3.350 3.300 3.250 3.400 3.350 3.300 3.250 3.200 3.150 3.100 3.050 3.000 2.950 2.900 2.500 2.463 2.425 2.388 2.350 2.313 2.275 2.238 2.200 2.163 2.125 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 Clock Duty Cycle ns -335 -202 @ tCK = 10ns -202 @ tCK = 8ns NA

512MB, 1GB (x64) 200-PIN DDR SODIMM 09005aef80a646bc Micron Technology, Inc., reserves the right to change products or specifications without notice. DDF16C64_128x64HG_B.fm - Rev. B 7/03 EN 22 ©2003 Micron Technology, Inc. 30. tHP min is the lesser of tCL minimum and tCH minimum actually applied to the device CK and CK# inputs, collectively during bank active. 31. READs and WRITEs with auto precharge are not allowed to be issued until tRAS(MIN) can be satis- fied prior to the internal precharge command being issued. 3 2 . A n y p o s i t i v e g l i t c h m u s t b e l e s s t h a n 1 / 3 o f t h e clock and not more than +400mV or 2.9V , which- ever is less. Any negative glitch must be less than 1/3 of the clock cycle and not exceed either - 300mV or 2.2V , whichever is more positive. 33. Normal Output Drive Curves: a. The full variation in driver pull-down current from minimum to maximum process, temper- ature and voltage will lie within the outer bounding lines of the V-I curve of Figure 9, Pull-Down Characteristics. b. The variation in driver pull-down current within nominal limits of voltage and tempera- ture is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve of Figure 9, Pull-Down Characteristics. c. The full variation in driver pull-up current from minimum to maximum process, temper- ature and voltage will lie within the outer bounding lines of the V-I curve of Figure 10, Pull-Up Characteristics. d. The variation in driver pull-up current within nominal limits of voltage and temperature is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve of Figure 10, Pull-Up Characteristics. e. The full variation in the ratio of the maximum to minimum pull-up and pull-down current should be between 0.71 and 1.4, for device drain-to-source voltages from 0.1V to 1.0V , and at the same voltage and temperature. f. The full variation in the ratio of the nominal pull-up to pull-down current should be unity ±10 percent, for device drain-to-source volt- ages from 0.1V to 1.0V . 34. The voltage levels used are derived from a mini- mum V DD level and the referenced test load. In practice, the voltage levels obtained from a prop- erly terminated bus will provide significantly dif- ferent voltage values. 35. V IH overshoot: V IH (MAX) = V DDQ + 1.5V for a pulse width/g32/g163 3ns and the pulse width can not be greater than 1/3 of the cycle rate. V IL undershoot: VIL (MIN) = -1.5V for a pulse width /g163/g32 3ns and the pulse width can not be greater than 1/3 of the cycle rate. 36. V DD and VDDQ must track each other. 37. This maximum value is derived from the refer- enced test load. In practice, the values obtained in a typical terminated design may reflect up to 310ps less for tHZ(MAX) and the last DVW . tHZ (MAX) will prevail over tDQSCK (MAX) + tRPST (MAX) condition. tLZ (MIN) will prevail over tDQSCK (MIN) + tRPRE (MAX) condition. 38. For slew rates greater than 1V/ns the (LZ) transi- tion will start about 310ps earlier. 39. During Initialization, V DDQ, V TT, and V REF must be equal to or less than V DD + 0.3V . Alternatively, VTT may be 1.35V maximum during power up, even if V DD/VDDQ are 0.0V , provided a minimum of 42/g87 of series resistance is used between the VTT supply and the input pin. 40. The current Micron part operates below the slow- est JEDEC operating frequency of 83 MHz. As such, future die may not reflect this option. Figure 9: Pull-Down Characteristics Figure 10: Pull-Up Characteristics

512MB, 1GB (x64) 200-PIN DDR SODIMM 09005aef80a646bc Micron Technology, Inc., reserves the right to change products or specifications without notice. DDF16C64_128x64HG_B.fm - Rev. B 7/03 EN 23 ©2003 Micron Technology, Inc. 41. For -265, -26A, -262 and -335, I DD3N is specified to be 35mA at 100 MHz. 42. Random addressing changing and 50 percent of data changing at every transfer. 43. Random addressing changing and 100 percent of data changing at every transfer. 44. CKE must be active (high) during the entire time a refresh command is executed. That is, from the time the AUTO REFRESH command is registered, CKE must be active at each rising clock edge, until tREF later. 45. IDD2N specifies the DQ, DQS, and DM to be driven to a valid high or low logic level. IDD2Q is similar to IDD2F except IDD2Q specifies the address and control inputs to remain stable. Although IDD2F , IDD2N, and IDD2Q are similar, IDD2F is “worst case.” 46. Whenever the operating frequency is altered, not including jitter, the DLL is required to be reset. This is followed by 200 clock cycles. 47. Leakage number reflects the worst case leakage possible through the module pin, not what each memory device contributes. 4 8 . W h e n a n i n p u t s i g n a l i s H I G H o r L O W , i t i s defined as a steady state logic HIGH or LOW .

512MB, 1GB (x64) 200-PIN DDR SODIMM 09005aef80a646bc Micron Technology, Inc., reserves the right to change products or specifications without notice. DDF16C64_128x64HG_B.fm - Rev. B 7/03 EN 25 ©2003 Micron Technology, Inc. Figure 14: SPD EEPROM Timing Diagram Table 17: EEPROM Device Select Code Most significant bit (b7) is sent first. SELECT CODE DEVICE TYPE IDENTIFIER CHIP ENABLE RW b7 b6 b5 b4 b3 b2 b1 B0 Memory Area Select Code (two arrays) 1 0 1 0 SA2 SA1 SA0 RW Protection Register Select Code 0 1 1 0 SA2 SA1 SA0 RW Table 18: EEPROM Operating Modes MODE RW BIT WC BYTES INITIAL SEQUENCE Current Address Read 1V IH or VIL 1 START, Device Select, RW = ‘1’ Random Address Read 0V IH or VIL 1 START, Device Select, RW = ‘0’, Address 1V IH or VIL 1 reSTART, Device Select, RW = ‘1’ Sequential Read 1V IH or VIL /g179 1 Similar to Current or Random Address Read Byte Write 0V IL 1 START, Device Select, RW = ‘0’ Page Write 0V IL /g163 16 START, Device Select, RW = ‘0’ SCL SDA IN SDA OUT tLOW tSU:STA tHD:STA tF tHIGH tR tBUFtDHtAA tSU:STOtSU:DATtHD:DAT UNDEFINED

512MB, 1GB (x64) 200-PIN DDR SODIMM 09005aef80a646bc Micron Technology, Inc., reserves the right to change products or specifications without notice. DDF16C64_128x64HG_B.fm - Rev. B 7/03 EN 26 ©2003 Micron Technology, Inc. NOTE: 1. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA. 2. This parameter is sampled. 3. For a reSTART condition, or following a WRITE cycle. 4. The SPD EEPROM WRITE cycle time (tWRC) is the time from a valid stop condition of a write sequence to the end of the EEPROM internal erase/program cycle. During the WRITE cycle, the EEPROM bus interface circuit is disabled, SDA remains HIGH due to pull-up resistor, and the EEPROM does not respond to its slave address. Table 19: Serial Presence-Detect EEPROM DC Operating Conditions All voltages referenced to VSS; VDDSPD = +2.3V to +3.6V PARAMETER/CONDITION SYMBOL MIN MAX UNITS SUPPLY VOLTAGE VDDSPD 2.3 3.6 V INPUT HIGH VOLTAGE: Logic 1; All inputs VIH VDD /g180/g320.7 V DD + 0.5 V INPUT LOW VOLTAGE: Logic 0; All inputs VIL -1 V DD /g180/g320.3 V OUTPUT LOW VOLTAGE: IOUT = 3mA VOL –0 . 4V INPUT LEAKAGE CURRENT: VIN = GND to VDD ILI –1 0 µ A OUTPUT LEAKAGE CURRENT: VOUT = GND to VDD ILO –1 0 µ A STANDBY CURRENT: SCL = SDA = VDD - 0.3V; All other inputs = VDD or VSS ISB –3 0 µ A POWER SUPPLY CURRENT: SCL clock frequency = 100 KHz ICC –2 m A Table 20: Serial Presence-Detect EEPROM AC Operating Conditions All voltages referenced to VSS; VDDSPD = +2.3V TO +3.6V PARAMETER/CONDITION SYMBOL MIN MAX UNITS NOTES SCL LOW to SDA data-out valid tAA 0.2 0.9 µs 1 Time the bus must be free before a new transition can start tBUF 1.3 µs Data-out hold time tDH 200 ns SDA and SCL fall time tF 300 ns 2 Data-in hold time tHD:DAT 0 µs Start condition hold time tHD:STA 0.6 µs Clock HIGH period tHIGH 0.6 µs Noise suppression time constant at SCL, SDA inputs tI5 0 n s Clock LOW period tLOW 1.3 µs SDA and SCL rise time tR0 . 3 µ s 2 SCL clock frequency fSCL 400 KHz Data-in setup time tSU:DAT 100 ns Start condition setup time tSU:STA 0.6 µs 3 Stop condition setup time tSU:STO 0.6 µs WRITE cycle time tWRC 10 ms 4

512MB, 1GB (x64) 200-PIN DDR SODIMM 09005aef80a646bc Micron Technology, Inc., reserves the right to change products or specifications without notice. DDF16C64_128x64HG_B.fm - Rev. B 7/03 EN 27 ©2003 Micron Technology, Inc. Table 21: Serial Presence-Detect Matrix “1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW”; notes appear on page 29 BYTE DESCRIPTION ENTRY (VERSION) MT16VDDF6464H MT16VDDF12864H

0 Number of Bytes Used by Micron 128 80 80

1 Total Number of Bytes in SPD Device 256 08 08

2 Fundamental Memory Type SDRAM DDR 07 07

3 Number of Rows Addresses on Assembly 13 0D 0D

4 Number of Column Addresses on Assembly 11, 12 0A 0B

5 Number of Physical Ranks on DIMM 20 2 0 2

6 Module Data With 64 40 40

7 Module Data With (Continued) 00 0 0 0

8 Moduel Voltage Interface Levels SSTL 2.5V 04 04 9 SDRAM Cycle Time, (tCK), CAS Latency = 2.5 (See note 1) 6ns (-335) 7ns (-262/-26A) 7.5ns( -265) 8ns (-202)

10 SDRAM Access From Clock,(tAC),

CAS Latency = 2.5 0.7ns (-335) 0.8ns (-202)

11 Module Configuration Type Non-ECC 00 00

12 Refresh Rate/Type 7.8µs/SELF 82 82

13 SDRAM Device Width (Primary SDRAM) x8 08 08

14 Error-checking SDRAM Data Width Non-ECC 00 00

15 Minimum Clock Delay, Back-to-Back Random

16 Burst Lengths Supported 2, 4, 8 0E 0E

17 Number of Banks on SDRAM Device 40 4 0 4

18 CAS Latencies Supported 2, 2.5 0C 0C

19 CS Latency 00 1 0 1

20 WE Latency 10 2 0 2

21 SDRAM Module Attributes Unbuffered/Diff. Clock 20 20

22 SDRAM Device Attributes: General Fast/Concurrent AP C0 C0

23 SDRAM Cycle Time, (

tCK), CAS Latency = 2 (See note 1) 10ns (-265/-202) 24 SDRAM Access From CK, (tAC), CAS Latency = 2 0.7ns (-335) 0.8ns (-202)

25 SDRAM Cycle Time, (

tCK), CAS Latency = 1.5 N/A 00 00

26 SDRAM Access From CK, (tAC),

CAS Latency = 1.5 N/A 00 00

27 Minimum Row Precharge Time, (tRP) 18ns (-335)

15ns (-262)

28 Minimum Row to Row Active, (tRRD) 12ns (-335)

29 Minimum RAS# to CAS# Delay, (tRCD) 18ns (-335)

15ns (-262)

512MB, 1GB (x64) 200-PIN DDR SODIMM 09005aef80a646bc Micron Technology, Inc., reserves the right to change products or specifications without notice. DDF16C64_128x64HG_B.fm - Rev. B 7/03 EN 28 ©2003 Micron Technology, Inc.

30 Minimum RAS# Pulse Width, (tRAS)

(See note 2) 42ns (-335) 40ns (-202)

31 Module Rank Density 256MB, 512MB 40 80

32 Address and Command Setup Time, (tIS)

(See note 3) 0.8ns (-335) 1.1ns (-202)

33 Address and Command Hold Time, (tIH)

(See note 3) 0.8ns (-335) 1.1ns (-202) 34 Data/ Data Mask Input Setup Time, (tDS) 0.45ns (-335) 0.6ns (-202)

35 Data/ Data Mask Input Hold Time, (

tDH) 0.45ns (-335) 0.6ns (-202) 36-40 Reserved 00 00

41 Minimum Active Auto Refresh Time (tRC) 60ns (-335/-262)

65ns (-26A/-265) 70ns (-202)

42 Minimum Auto Refresh to Active/Auto Refresh

Command Period, (tRFC) 72ns (-335) 80ns (-202)

43 SDRAM Device Max Cycle Time (tCKMAX) 12ns (-335)

44 SDRAM Device Max DQS-DQ Skew Time

(tDQSQ) 0.40ns (-335) 0.6ns (-202)

45 SDRAM Device Max Read Data Hold Skew

Factor (tQHS) 0.5ns (-335) 0.75ns (-26A/-265) 1.0ns (-202)

46 Reserved 00 00

47 DIMM Height 01 01

48–61 Reserved 00 00

63 Checksum for Bytes 0-62 -335

-262 -26A -265 -202 BB FC

64 Manufacturer’s JEDEC ID Code MICRON 2C 2C

65-71 Manufacturer’s JEDEC ID Code (Continued) 00 00

72 Manufacturing Location 01–12 01–0C 01–0D

73-90 Module Part Number (ASCII) Variable Data Variable Data

91 PCB Identification Code 1-9 01-09 01-09

92 Identification Code (Continued) 00 0 0 0

93 Year of Manufacture in BCD Variable Data Variable Data

Table 21: Serial Presence-Detect Matrix (Continued) “1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW”; notes appear on page 29 BYTE DESCRIPTION ENTRY (VERSION) MT16VDDF6464H MT16VDDF12864H

512MB, 1GB (x64) 200-PIN DDR SODIMM 09005aef80a646bc Micron Technology, Inc., reserves the right to change products or specifications without notice. DDF16C64_128x64HG_B.fm - Rev. B 7/03 EN 29 ©2003 Micron Technology, Inc. NOTE: 1. Device latencies used for SPD values. 2. The value of tRAS used for -262/-26A/-265 modules is calculated from tRC - tRP. Actual device spec value is 40 ns. 3. The JEDEC SPD specification allows fast or slow slew rate values for these bytes. The worst-case (slow slew rate) value is represented here. Systems requiring the fast slew rate setup and hold values are supported, provided the faster mini- mum slew rate is met.

94 Week of Manufacture in BCD Variable Data Variable Data

95-98 Module Serial Number Variable Data Variable Data 99-127 Manufacturer-Specific Data (RSVD) –– Table 21: Serial Presence-Detect Matrix (Continued) “1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW”; notes appear on page 29 BYTE DESCRIPTION ENTRY (VERSION) MT16VDDF6464H MT16VDDF12864H

512MB, 1GB (x64) 200-PIN DDR SODIMM 09005aef80a646bc Micron Technology, Inc., reserves the right to change products or specifications without notice. DDF16C64_128x64HG_B.fm - Rev. B 7/03 EN 30 ©2003 Micron Technology, Inc. Figure 15: 200-PIN SODIMM Dimensions – 512MB NOTE: All dimensions are in inches (millimeters) or typical where noted. 0.150 (3.80) MAX 0.043 (1.10) 0.035 (0.90) PIN 1 2.666 (67.72) 2.656 (67.45) 0.787 (20.00) TYP 0.071 (1.80) (2X) 0.024 (.61) TYP 0.018 (.46) TYP 0.079 (2.00) R (2X) PIN 199 PIN 200 PIN 2 FRONT VIEW 0.079 (2.00) 0.236 (6.00) 2.504 (63.60) 0.096 (2.44) 0.039 (.99) TYP 1.255 (31.88) 1.245 (31.62) TYP BACK VIEW U1 U2 U3 U4 U5 U6 U7 U8 U17 U9 U10 U11 U12 U13 U14 U15 U16 MAX MIN

512MB, 1GB (x64) 200-PIN DDR SODIMM 09005aef80a646bc Micron Technology, Inc., reserves the right to change products or specifications without notice.. DDF16C64_128x64HG_B.fm - Rev. B 7/03 EN 31 ©2003 Micron Technology, Inc 8000 S. Federal Way, P .O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992 Micron, the M logo, and the Micron logo are trademarks and/or service marks of Micron Technology, Inc. All other trademarks are the property of their respective owners. Figure 16: 200-PIN SODIMM Dimensions – 1GB NOTE: All dimensions are in inches (millimeters) or typical where noted. Data Sheet Designation Released (No Mark): This data sheet contains mini- mum and maximum limits specified over the complete power supply and temperature range for production devices. Although considered final, these specifica- tions are subject to change, as further product devel- opment and data characterization sometimes occur. U1 U2 U3 U4 U5 U6 U7 U8 U17 U9 U10 U11 U12 U16U15U14U13 0.150 (3.80) MAX 0.043 (1.10) 0.035 (0.90) PIN 1 2.666 (67.72) 2.656 (67.45) 0.787 (20.00) TYP 0.071 (1.80) (2X) 0.024 (.61) TYP 0.018 (.46) TYP 0.079 (2.00) R (2X) PIN 199 PIN 200 PIN 2 FRONT VIEW 0.079 (2.00) 0.236 (6.00) 2.504 (63.60) 0.096 (2.44) 0.039 (.99) TYP 1.255 (31.88) 1.245 (31.62) TYP BACK VIEW MAX MIN