MT16HTF12864AY-667

MT16HTF12864AY MICRON | Alldatasheet

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PDF: 09005aef80f09084/Source: 09005aef80f09068 Micron Technology, Inc., reserves the right to change products or specifications without notice. HTF16C64_128_256x64AG.fm - Rev. D 5/06 EN 1 ©2003 Micron Technology, Inc. All rights reserved. DDR2 SDRAM Unbuffered DIMM MT16HTF6464A – 512MB MT16HTF12864A – 1GB MT16HTF25664A – 2GB For component specifications, refer to the Micron’s Web site: www.micron.com/ddr2

• 240-pin, unbuffered, dual in-line memory module (UDIMM)  Fast data transfer rates: PC2-3200, PC2-4200, PC2- 5300, or PC2-6400  512MB (64 Meg x 64), 1GB (128 Meg x 64), and 2GB (256 Meg x 64) V DD = VDDQ = +1.8V V DDSPD = +1.7V to +3.6V  JEDEC standard 1.8V I/O (SSTL_18-compatible)  Differential data strobe (DQS, DQS#) option  Four-bit prefetch architecture  DLL to align DQ and DQS transitions with CK  Multiple internal device banks for concurrent operation  Programmable CAS latency (CL)  Posted CAS additive latency (AL)  WRITE latency = READ latency - 1 tCK  Programmable burst lengths: 4 or 8  Adjustable data-output drive strength  64ms, 8,192-cycle refresh  On-die termination (ODT)  Serial presence-det ect (SPD) with EEPROM  Gold edge contacts D u a l r a n k Figure 1: 240-Pin DIMM (MO-237 R/C “B”) Notes: 1. CL = CAS (READ) latency. 2. Not available in 512MB density. 3. Not available in 2GB density. Options Marking P a c k a g e 240-pin DIMM (lead-free) Y F r e q u e n c y / C L1 2.5ns @ CL = 5 (DDR2-800)2 -80E 3.0ns @ CL = 5 (DDR2-667)3 -667 3.75ns @ CL = 4 (DDR2-533) -53E 5.0ns @ CL = 3 (DDR2-400) -40E P C B h e i g h t 29.97mm (1.18in) PCB height: 29.97mm (1.18in)

PDF: 09005aef80f09084/Source: 09005aef80f09068 Micron Technology, Inc., reserves the right to change products or specifications without notice. HTF16C64_128_256x64AG.fm - Rev. D 5/06 EN 2 ©2003 Micron Technology, Inc. All rights reserved. 512MB, 1GB, 2GB: (x64, DR) 240-Pin DDR2 SDRAM UDIMM Notes: 1. All part numbers end with a two-place code (not shown), designating component and PCB revisions. Consult factory for current revision codes. Example: MT16HTF12864AY-80ED4. Table 1: Address Table 512MB 1GB 2GB Refresh count 8K 8K 8K Row addressing 8K (A0–A12) 16K (A0–A13) 16K (A0–A13) Device bank addressing 4 (BA0, BA1) 4 (BA0, BA1) 8 (BA0, BA1, BA2) Device page size per bank 1KB 1KB 1KB Device configuration 256Mb (32 Meg x 8) 512Mb (64 Meg x 8) 1Gb (128 Meg x 8) Column addressing 1K (A0–A9) 1K (A0–A9) 1K (A0–A9) Module rank addressing 2 (S0#, S1#) 2 (S0#, S1#) 2 (S0#, S1#) Table 2: Key Timing Parameters Speed Grade Data Rate (MT/s) tRCD (ns) tRP (ns) tRC (ns)CL = 3 CL = 4 CL = 5 -80E – 533 800 12.5 12.5 55 -667 400 533 667 15 15 55 -53E 400 533 – 15 15 55 -40E 400 400 – 15 15 55 Table 3: Part Numbers and Timing Parameters Part Number1 Module Density Configuration Module Bandwidth Memory Clock/ Data Rate Latency (CL-tRCD-tRP) MT16HTF6464AY-667__ 512MB 64 Meg x 64 5.3 GB/s 3.0ns/667 MT/s 5-5-5 MT16HTF6464AY-53E__ 512MB 64 Meg x 64 4.3 GB/s 3.75ns/533 MT/s 4-4-4 MT16HTF6464AY-40E__ 512MB 64 Meg x 64 3.2 GB/s 5.0ns/400 MT/s 3-3-3 MT16HTF12864AY-80E__ 1GB 128 Meg x 64 6.4 GB/s 2.5ns/800 MT/s 5-5-5 MT16HTF12864AY-667__ 1GB 128 Meg x 64 5.3 GB/s 3.0ns/667 MT/s 5-5-5 MT16HTF12864AY-53E__ 1GB 128 Meg x 64 4.3 GB/s 3.75ns/533 MT/s 4-4-4 MT16HTF12864AY-40E__ 1GB 128 Meg x 64 3.2 GB/s 5.0ns/400 MT/s 3-3-3 MT16HTF25664AY-80E__ 2GB 256 Meg x 64 6.4 GB/s 2.5ns/800 MT/s 5-5-5 MT16HTF25664AY-667__ 2GB 256 Meg x 64 5.3 GB/s 3.0ns/667 MT/s 5-5-5 MT16HTF25664AY-53E__ 2GB 256 Meg x 64 4.3 GB/s 3.75ns/533 MT/s 4-4-4 MT16HTF25664AY-40E__ 2GB 256 Meg x 64 3.2 GB/s 5.0ns/400 MT/s 3-3-3

PDF: 09005aef80f09084/Source: 09005aef80f09068 Micron Technology, Inc., reserves the right to change products or specifications without notice. HTF16C64_128_256x64AG.fm - Rev. D 5/06 EN 3 ©2003 Micron Technology, Inc. All rights reserved. 512MB, 1GB, 2GB: (x64, DR) 240-Pin DDR2 SDRAM UDIMM Pin Assignments and Descriptions Pin Assignments and Descriptions Note: Pin 196 is NC for 512MB, or A13 for 1GB an d 2GB; pin 54 is NC for 512MB and 1GB, or BA2 for 2GB. Figure 2: Pin Locations Table 4: Pin Assignment 240-pin DIMM Front 240-pin DIMM Back Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol 1V REF 31 DQ19 61 A4 91 V SS 121 V SS 151 VSS 181 V DDQ 211 DM5 2V SS 32 VSS 62 V DDQ 92 DQS5# 122 DQ4 152 DQ28 182 A3 212 NC

3 DQ0 33 DQ24 63 A2 93 DQS5 123 DQ5 153 DQ29 183 A1 213 V SS

4 DQ1 34 DQ25 64 V DD 94 V SS 124 V SS 154 V SS 184 V DD 214 DQ46

5V SS 35 VSS 65 V SS 95 DQ42 125 DM0 155 DM3 185 CK0 215 DQ47

6 DQS0# 36 DQS3# 66 V SS 96 DQ43 126 NC 156 NC 186 CK0# 216 V SS

7 D Q S 03 7D Q S 36 7 V DD 97 V SS 127 V SS 157 V SS 187 V DD 217 DQ52

8V SS 38 V SS 68 NC 98 DQ48 128 DQ6 158 DQ30 188 A0 218 DQ53

9 DQ2 39 DQ26 69 VDD 99 DQ49 129 DQ7 159 DQ31 189 V DD 219 V SS

10 DQ3 40 DQ27 70 A10/AP 100 V SS 130 V SS 160 V SS 190 BA1 220 CK2

11 V SS 41 V SS 71 BA0 101 SA2 131 DQ12 161 NC 191 V DDQ 221 CK2#

12 DQ8 42 NC 72 VDDQ 102 NC 132 DQ13 162 NC 192 RAS# 222 V SS

13 DQ9 43 NC 73 WE# 103 V SS 133 V SS 163 V SS 193 S0# 223 DM6

14 V SS 44 V SS 74 CAS# 104 DQS6# 134 DM1 164 DM8 194 V DDQ 224 NC

15 DQS1# 45 NC 75 V DDQ 105 DQS6 135 NC 165 NC 195 ODT0 225 V SS

16 DQS1 46 NC 76 S1# 106 V SS 136 V SS 166 V SS 196 NC/A13 226 DQ54

17 V SS 47 V SS 77 ODT1 107 DQ50 137 CK1 167 NC 197 V DD 227 DQ55

18 NC 48 NC 78 V DDQ 108 DQ51 138 CK1# 168 NC 198 V SS 228 V SS

19 NC 49 NC 79 V SS 109 V SS 139 V SS 169 V SS 199 DQ36 229 DQ60

20 V SS 50 V SS 80 DQ32 110 DQ56 140 DQ14 170 V DDQ 200 DQ37 230 DQ61

21 DQ10 51 V DDQ 81 DQ33 111 DQ57 141 DQ15 171 CKE1 201 V SS 231 V SS

22 DQ11 52 CKE0 82 V SS 112 V SS 142 V SS 172 V DD 202 DM4 232 DM7

23 VSS 53 V DD 83 DQS4# 113 DQS7# 143 DQ20 173 NC 203 NC 233 NC

24 DQ16 54 NC/BA2 84 DQS4 114 DQS7 144 DQ21 174 NC 204 V SS 234 V SS

25 DQ17 55 NC 85 V SS 115 V SS 145 V SS 175 V DDQ 205 DQ38 235 DQ62

26 V SS 56 V DDQ 86 DQ34 116 DQ58 146 DM2 176 A12 206 DQ39 236 DQ63

27 DQS2# 57 A11 87 DQ35 117 DQ59 147 NC 177 A9 207 V SS 237 V SS

28 DQS2 58 A7 88 V SS 118 V SS 148 V SS 178 VDD 208 DQ44 238 V DDSPD

29 V SS 59 V DD 89 DQ40 119 SDA 149 DQ22 179 A8 209 DQ45 239 SA0

30 DQ18 60 A5 90 DQ41 120 SCL 150 DQ23 180 A6 210 V SS 240 SA1

U6 U7 U8 U9 U10 U11 U12 U13 U15 U16 U17 U18 PIN 121PIN 184PIN 185PIN 240PIN 1 PIN 64 PIN 65 PIN 120 Indicates a VDD or VDDQ pin Indicates a VSS pin Front View Back View

PDF: 09005aef80f09084/Source: 09005aef80f09068 Micron Technology, Inc., reserves the right to change products or specifications without notice. HTF16C64_128_256x64AG.fm - Rev. D 5/06 EN 4 ©2003 Micron Technology, Inc. All rights reserved. 512MB, 1GB, 2GB: (x64, DR) 240-Pin DDR2 SDRAM UDIMM Pin Assignments and Descriptions Table 5: Pin Descriptions Pin numbers may not correlate with symbols; refer to Table 4 on page 3 for more information Pin Numbers Symbol Type Description 77, 195 ODT0, ODT1 Input On-die termination: ODT (registered HIGH) enables termination resistance internal to the DDR2 SDRAM. When enabled, ODT is only applied to each of the following pins: DQ, DQS, DQS#, and DM. The ODT input will be ignored if disabled via the LOAD MODE command. 137, 138, 185, 186, 220, 221 CK0, CK0#, CK1, CK1#, CK2, CK2# Input Clock: CK and CK# are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK#. Output data (DQs and DQS/DQS#) is referenced to the crossings of CK and CK#. 52, 171 CKE0, CKE1 Input Clock enable: CKE (registered HIGH) activates and CKE (registered LOW) deactivates clocking circuitry on the DDR2 SDRAM. The specific circuitry that is enabled/disabled is dependent on the DDR2 SDRAM configuration and operating mode. CKE LOW provides precharge power-down and SELF REFRESH operations (all device banks idle), or ACTIVE power- down (row ACTIVE in any device bank). CKE is synchronous for power-down entry, power-down exit, output disable, and for SELF REFRESH entry. CKE is asynchronous for SELF REFRESH exit. Input buffers (excluding CK, CK#, CKE, and ODT) are disabled during power-down. Input buffers (excluding CKE) are disabled during SELF REFRESH. CKE is an SSTL_18 input but will detect a LVCMOS LOW level when V DD is applied during first power-up. After VREF has become stable during the power on and initialization sequence, it must be maintained for proper operation of the CKE receiver. For proper SELF REFRESH operation, VREF must be maintained to this input. 76, 193 S0#, S1# Input Chip select: S# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when S# is registered HIGH. S# provides for external rank selection on systems with multiple ranks. S# is considered part of the command code. 73, 74, 192 RAS#, CAS#, WE# Input Command inputs: RAS#, CAS#, and WE# (along with S#) define the command being entered. 54 (2GB), 71, 190 BA0, BA1, BA2 (2GB) Input Bank address inputs: BA0–BA1/BA2 define to which device bank an ACTIVE, READ, WRITE, or PRECHARGE command is being applied. BA0–BA1/BA2 define which mode register including MR, EMR, EMR(2), and EMR(3) is loaded during the LMR command. 57, 58, 60, 61, 63, 70, 176, 177, 179, 180, 182, 183, 188, 196 (1GB, 2GB) A0–A12 (512MB) A0–A13 (1GB, 2GB) Input Address inputs: Provide the row address for ACTIVE commands, and the column address and auto precharge bit (A10) for READ/ WRITE commands, to select one location out of the memory array in the respective bank. A10 sampled during a PRECHARGE command determines whether the precharge applies to one device bank (A10 LOW, device bank selected by BA0–BA1/BA2) or all device banks (A10 HIGH). The address inputs also provide the op-code during a LMR command. 125, 134, 146, 155, 202, 211, 223, 232 DM0–DM7 Input Input data mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH along with that input data during a WRITE access. DM is sampled on both edges of DQS. Although DM pins are input-only, the DM loading is designed to match that of DQ and DQS pins.

PDF: 09005aef80f09084/Source: 09005aef80f09068 Micron Technology, Inc., reserves the right to change products or specifications without notice. HTF16C64_128_256x64AG.fm - Rev. D 5/06 EN 5 ©2003 Micron Technology, Inc. All rights reserved. 512MB, 1GB, 2GB: (x64, DR) 240-Pin DDR2 SDRAM UDIMM Pin Assignments and Descriptions

120 SCL Input Serial clock for presence-detect: SCL is used to synchronize the

presence-detect data transfer to and from the module. 101, 239, 240 SA0–SA2 Input Presence-detect address inputs: These pins are used to configure the presence-detect device. 99, 107, 108, 110, 111, 116, 117, 122, 123, 128, 129, 131, 132, 140, 141, 143, 144, 149, 150, 152, 153, 158, 159, 199, 200, 205, 206, 208, 209, 214, 215, 217, 218, 226, 227, 229, 230, 235, 236 DQ0–DQ63 I/O Data Input/output: Bidirectional data bus. 83, 84, 92, 93, 104, 105, 113, 114, DQS0–DQS7, DQS0#–DQS7# I/O Data strobe: Output with read data, input with write data for source synchronous operation. Edge-aligned with read data, center aligned with write data. DQS# is only used when differential data strobe mode is enabled via the LOAD MODE command.

119 SDA I/O Serial presence-detect data: SDA is a bidirectional pin used to

transfer addresses and data into and out of the presence-detect portion of the module. 53, 59, 64, 67, 69, 172, 178, 184, 187, 189, 197, V DD Supply Power supply: +1.8V ±0.1V. 51, 56, 62, 72, 75, 78, 170, 175, 181, 191, 194, VDDQ Supply DQ Power supply: +1.8V ±0.1V. 1V REF Supply SSTL_18 reference voltage. 97,100, 103, 106, 109,112, 115, 118, 121, 124, 127, 130, 133, 136, 139, 142, 145, 148, 151, 154, 157, 160, 163, 166, 169, 198, 201, 204, 207, 210, 213, 216, 219, 222, 225, 228, 231, 234, 237 V SS Supply Ground. 238 V DDSPD Supply Serial EEPROM positive power supply: +1.7V to +3.6V. 54 (512MB, 1GB), 55, 68, 76, 102, 125, 126, 134, 135, 146, 147, 155, 156, 161, 162, 164, 165, 167, 168, 171, 173, 174, 196 (512MB), 202, 203, 211, 212, 223, 224, 232, 233 NC – No connect: These pins should be left unconnected. Table 5: Pin Descriptions Pin numbers may not correlate with symbols; refer to Table 4 on page 3 for more information Pin Numbers Symbol Type Description

PDF: 09005aef80f09084/Source: 09005aef80f09068 Micron Technology, Inc., reserves the right to change products or specifications without notice. HTF16C64_128_256x64AG.fm - Rev. D 5/06 EN 6 ©2003 Micron Technology, Inc. All rights reserved. 512MB, 1GB, 2GB: (x64, DR) 240-Pin DDR2 SDRAM UDIMM Functional Block Diagram Functional Block Diagram Unless otherwise noted, resistor values are 22Ω. Micron module part numbers are explained in the module part numbering guide at www.micron.com/numbering.html. Modules use the following DDR2 SDRAM devices: MT47H32M8BT (512MB); MT47H64M8BT (1GB); and MT47H128M8BT (2GB). Figure 3: Functional Block Diagram DQ DQ DQ DQ DQ DQ DQ DQ DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM CS# DQ DQS# DQ DQ DQ DQ DQ DQ DQ DQ U19 DQ DQ DQ DQ DQ DQ DQ DQ DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ DQ DQ DQ DQ DQ DQ DQ U14 DM CS# DQ DQS# DM CS# DQ DQS# DM CS# DQ DQS# DQ DQ DQ DQ DQ DQ DQ DQ DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DM CS# DQ DQS# DQ DQ DQ DQ DQ DQ DQ DQ U18 DM CS# DQ DQS# DQ DQ DQ DQ DQ DQ DQ DQ DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DM CS# DQ DQS# DQ DQ DQ DQ DQ DQ DQ DQ U17 DM CS# DQ DQS# DQ DQ DQ DQ DQ DQ DQ DQ DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DM CS# DQ DQS# DQ DQ DQ DQ DQ DQ DQ DQ U16 DM CS# DQ DQS# DQ DQ DQ DQ DQ DQ DQ DQ DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ DQ DQ DQ DQ DQ DQ DQ U13 DM CS# DQ DQS# DM CS# DQ DQS# DQ DQ DQ DQ DQ DQ DQ DQ DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ DQ DQ DQ DQ DQ DQ DQ U12 DM CS# DQ DQS# DM CS# DQ DQS# DQ DQ DQ DQ DQ DQ DQ DQ DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DQ DQ DQ DQ DQ DQ DQ DQ U11 DM CS# DQ DQS# DM CS# DQ DQS# DQS0# DQS0 DM0 S0# S1# DQS1# DQS1 DM1 DQS2# DQS2 DM2 DQS3# DQS3 DM3 DQS4# DQS4 DM4 DQS5# DQS5 DM5 DQS6# DQS6 DM6 DQS7# DQS7 DM7 U4, U6 U14, U16 CK0 CK0# 67Ω U1–U3, U17–U19 CK1 CK1# U7–U10, U11–U13 CK2 CK2# Serial PD A1 A2 SA0 SA1 SA2 SDASCL WP U10 VDDSPD VDD, VDDL, VDDQ VREF VSS Serial PD DDR2 SDRAMS DDR2 SDRAMS DDR2 SDRAMS, EEPROM 1pF BA0–BA1 (512MB, 1GB) BA0–BA2 (2GB) A0–A12 (512M) A0–A13 (1GB, 2GB) RAS# CAS# WE# CKE0 CKE1 ODT0 ODT1 BA0–BA1: DDR2 SDRAMs BA0–BA2: DDR2 SDRAMs A0–A12: DDR2 SDRAMs A0–A13: DDR2 SDRAMs RAS#: DDR2 SDRAMs CAS#: DDR2 SDRAMs WE#: DDR2 SDRAMs CKE0: U1–U4, U6–U9 CKE1: U11–U14, U16–U19 ODT0: U1–U4, U6–U9 ODT1: U11–U14, U16–U19 25pF 25pF 25pF 25pF 25pF 25pF 7.5Ω 67Ω 67Ω

PDF: 09005aef80f09084/Source: 09005aef80f09068 Micron Technology, Inc., reserves the right to change products or specifications without notice. HTF16C64_128_256x64AG.fm - Rev. D 5/06 EN 7 ©2003 Micron Technology, Inc. All rights reserved. 512MB, 1GB, 2GB: (x64, DR) 240-Pin DDR2 SDRAM UDIMM General Description General Description The MT16HTF6464A, MT16HTF12864A, and MT16HTF25664A DDR2 SDRAM modules are high-speed, CMOS, dynamic random-access 512MB, 1GB, and 2GB memory modules organized in x64 configuration. DDR2 modules use internally configured 4- bank (512MB, 1GB) or 8-bank (2GB) DDR2 devices. DDR2 SDRAM modules use double data rate architecture to achieve high-speed opera- tion. The double data rate architecture is essentially a 4n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the DDR2 SDRAM module effectively consists of a single 4 n-bit- wide, one-clock-cycle data transfer at the internal DDR2 device core and four corre- sponding n-bit-wide, one-half-clock-cycle data transfers at the I/O pins. A bidirectional data strobe (DQS, DQS#) is transmitted externally, along with data, for use in data capture at the receiver. DQS is a strobe transmitted by the DDR2 device during READs and by the memory controller during WRITEs. DQS is edge-aligned with data for READs and center-aligned with data for WRITEs. DDR2 modules operate from a differential clock (CK and CK#); the crossing of CK going HIGH and CK# going LOW will be referred to as the positive edge of CK. Commands (address and control signals) are registered at every positive edge of CK. Input data is registered on both edges of DQS, and output data is referenced to both edges of DQS, as well as to both edges of CK. Serial Presence-Detect Operation DDR2 SDRAM modules incorporate serial presence-detect (SPD). The SPD function is implemented using a 2,048-bit EEPROM. This nonvolatile storage device contains 256 bytes. The first 128 bytes can be programmed by Micron to identify the module type and various DDR2 organizations and timing parameters. The remaining 128 bytes of storage are available for use by the customer. System READ/WRITE operations between the master (system logic) and the slave EEPROM device occur via a standard I 2C bus using the DIMM’ s SCL (clock) and SDA (data) signals, together with SA (2:0), which provide eight unique DIMM/EEPROM addresses. Write protect (WP) is tied to ground on the module, permanently disabling hardware write protect.

PDF: 09005aef80f09084/Source: 09005aef80f09068 Micron Technology, Inc., reserves the right to change products or specifications without notice. HTF16C64_128_256x64AG.fm - Rev. D 5/06 EN 8 ©2003 Micron Technology, Inc. All rights reserved. 512MB, 1GB, 2GB: (x64, DR) 240-Pin DDR2 SDRAM UDIMM Electrical Specifications Electrical Specifications Stresses greater than those listed in Table 6 may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Notes: 1. S# is defined to be S0# and S1#. CKE includes both CKE0 and CKE1. 2. V DDL is the power supply for the DDR2 devices’ DLL; however, this power supply is not brought directy to a DIMM pin. Capacitance At DDR2 data rates, Micron encourages designers to simulate the performance of the module to achieve optimum values. When inductance and delay parameters associated with trace lengths are used in simulations, they are significantly more accurate and real- istic than a gross estimation of module capacitance. Simulations can then render a considerably more accurate result. JEDEC modules are now designed by using simula- tions to close timing budgets. Table 6: Absolute Maximum Ratings Parameter Symbol Min Max Units VDD supply voltage relative to VSS VDD –1.0 2.3 V VDDQ supply voltage relative to VSS VDDQ– 0 . 52 . 3 V VDDL supply voltage relative to Vss VDDL2 –0.5 2.3 V Voltage on any pin relative to VSS VIN, VOUT –0.5 2.3 V Storage temperature TSTG –55 100 °C DDR2 SDRAM device operating temperature (ambient) Tcase 08 5 ° C Operating temperature (ambient) TOPR 05 5 ° C Input leakage current; Any input 0V ≤ VIN ≤ VDD; VREF input 0V ≤ VIN ≤0.95V; (All other pins not under test = 0V) Command/address, RAS#, CAS#, WE# II –80 80 µA S#, CKE1 –40 40 CK0, CK0# –20 20 CK1, CK1#, CK2, CK2# –30 30 DM –10 10 Output leakage current; 0V ≤ VOUT ≤ VDDQ; DQ and ODT are disabled DQ, DQS, DQS# IOZ –10 10 µA VREF leakage current; VREF = Valid VREF level – –32 32 µA

PDF: 09005aef80f09084/Source: 09005aef80f09068 Micron Technology, Inc., reserves the right to change products or specifications without notice. HTF16C64_128_256x64AG.fm - Rev. D 5/06 EN 9 ©2003 Micron Technology, Inc. All rights reserved. 512MB, 1GB, 2GB: (x64, DR) 240-Pin DDR2 SDRAM UDIMM Electrical Specifications Notes: 1. a = Value calculated as one module rank in this operating condition, and all other module ranks in IDD2P (CKE LOW). 2. b = Value calculated reflects all modu le ranks in this operating condition. Table 7: DDR2 I DD Specifications and Conditions – 512MB Values shown for DDR2 SDRAM components only Parameter/Condition Symbol -667 -53E -40E Units Operating one device bank active-precharge current; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching IDD0a 680 680 640 mA Operating one device bank active-read-precharge current; IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN (IDD), tRCD = tRCD (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data pattern is same as IDD4W IDD1a 760 760 720 mA Precharge power-down current; All device banks idle; tCK = tCK (IDD); CKE is LOW; Other control and address bus inputs are stable; Data bus inputs are floating IDD2Pb 80 80 80 mA Precharge quiet standby current; All device banks idle; tCK = tCK (IDD); CKE is HIGH, S# is HIGH; Other control and address bus inputs are stable; Data bus inputs are floating IDD2Qb 560 560 400 mA Precharge standby current; All device banks idle; tCK = tCK (IDD); CKE is HIGH, S# is HIGH; Other control and address bus inputs are switching; Data bus inputs are switching IDD2Nb 640 560 480 mA Active power-down current; All device banks open; tCK = tCK (IDD); CKE is LOW; Other control and address bus inputs are stable; Data bus inputs are floating Fast PDN exit MR[12] = 0 IDD3Pb 480 400 320 mA Slow PDN exit MR[12] = 1 96 96 96 mA Active standby current; All device banks open; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Other control and address bus inputs are switching; Data bus inputs are switching IDD3Nb 800 640 480 mA Operating burst write current; All device banks open; Continuous burst writes; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching IDD4Wa 1,560 1,320 1,040 mA Operating burst read current; All device banks open; Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching IDD4Ra 1,480 1,240 960 mA Burst refresh current; tCK = tCK (IDD); REFRESH command at every tRFC (IDD) interval; CKE is HIGH, S# is HIGH between valid commands; Other control and address bus inputs are switching; Data bus inputs are switching IDD5b 2,880 2,720 2,640 mA Self refresh current; CK and CK# at 0V; CKE ≤ 0.2V; Other control and address bus inputs are floating; Data bus inputs are floating IDD6b 80 80 80 mA Operating device bank interleave read current; All device banks interleaving reads, IOUT = 0mA; BL = 4, CL = CL (IDD), AL = tRCD (IDD) - 1 × tCK (IDD); tCK = tCK (IDD), tRC = tRC (IDD), tRRD = tRRD (IDD), tRCD = tRCD (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are stable during DESELECTs; Data bus inputs are switching; See IDD7 conditions in component data sheet for detail IDD7a 2,040 1,960 1,880 mA

PDF: 09005aef80f09084/Source: 09005aef80f09068 Micron Technology, Inc., reserves the right to change products or specifications without notice. HTF16C64_128_256x64AG.fm - Rev. D 5/06 EN 10 ©2003 Micron Technology, Inc. All rights reserved. 512MB, 1GB, 2GB: (x64, DR) 240-Pin DDR2 SDRAM UDIMM Electrical Specifications Notes: 1. a = Value calculated as one module rank in this operating condition, and all other module ranks in IDD2P (CKE LOW). 2. b = Value calculated reflects all modu le ranks in this operating condition. Table 8: DDR2 I DD Specifications and Conditions – 1GB Values shown for DDR2 SDRAM components only Parameter/Condition Symbol -80E -667 -53E -40E Units Operating one device bank active-precharge current; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching IDD0a 856 776 696 696 mA Operating one device bank active-read-precharge current; IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN (IDD), tRCD = tRCD (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data pattern is same as IDD4W IDD1a 976 896 816 776 mA Precharge power-down current; All device banks idle; tCK = tCK (IDD); CKE is LOW; Other control and address bus inputs are stable; Data bus inputs are floating IDD2Pb 112 112 112 112 mA Precharge quiet standby current; All device banks idle; tCK = tCK (IDD); CKE is HIGH, S# is HIGH; Other control and address bus inputs are stable; Data bus inputs are floating IDD2Qb 800 720 640 560 mA Precharge standby current; All device banks idle; tCK = tCK (IDD); CKE is HIGH, S# is HIGH; Other control and address bus inputs are switching; Data bus inputs are switching IDD2Nb 880 800 720 640 mA Active power-down current; All device banks open; tCK = tCK (IDD); CKE is LOW; Other control and address bus inputs are stable; Data bus inputs are floating Fast PDN exit MR[12] = 0 IDD3Pb 640 560 480 400 mA Slow PDN exit MR[12] = 1 192 192 192 192 mA Active standby current; All device banks open; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Other control and address bus inputs are switching; Data bus inputs are switching IDD3Nb 1,120 1,040 880 720 mA Operating burst write current; All device banks open; Continuous burst writes; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching IDD4Wa 1,616 1,416 1,1176 976 mA Operating burst read current; All device banks open; Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching IDD4Ra 1,696 1,496 1,216 976 mA Burst refresh current; tCK = tCK (IDD); REFRESH command at every tRFC (IDD) interval; CKE is HIGH, S# is HIGH between valid commands; Other control and address bus inputs are switching; Data bus inputs are switching IDD5b 3,680 2,880 2,720 2,640 mA Self refresh current; CK and CK# at 0V; CKE ≤ 0.2V; Other control and address bus inputs are floating; Data bus inputs are floating IDD6b 112 112 112 112 mA Operating device bank interleave read current; All device banks interleaving reads, IOUT = 0mA; BL = 4, CL = CL (IDD), AL = tRCD (IDD) - 1 × tCK (IDD); tCK = tCK (IDD), tRC = tRC (IDD), tRRD = tRRD (IDD), tRCD = tRCD (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are stable during DESELECTs; Data bus inputs are switching; See IDD7 conditions in component data sheet for detail IDD7a 2,456 1,976 1,856 1,816 mA

PDF: 09005aef80f09084/Source: 09005aef80f09068 Micron Technology, Inc., reserves the right to change products or specifications without notice. HTF16C64_128_256x64AG.fm - Rev. D 5/06 EN 11 ©2003 Micron Technology, Inc. All rights reserved. 512MB, 1GB, 2GB: (x64, DR) 240-Pin DDR2 SDRAM UDIMM Electrical Specifications Notes: 1. a = Value calculated as one module rank in this operating condition, and all other module ranks in IDD2P (CKE LOW). 2. b = Value calculated reflects all modu le ranks in this operating condition. Table 9: DDR2 I DD Specifications and Conditions – 2GB Values shown for DDR2 SDRAM components only Parameter/Condition Symbol -80E -667 -53E -40E Units Operating one device bank active-precharge current; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching IDD0a 856 776 696 616 mA Operating one device bank active-read-precharge current; IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN (IDD), tRCD = tRCD (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data pattern is same as IDD4W IDD1a 936 856 816 696 mA Precharge power-down current; All device banks idle; tCK = tCK (IDD); CKE is LOW; Other control and address bus inputs are stable; Data bus inputs are floating IDD2Pb 112 112 112 112 mA Precharge quiet standby current; All device banks idle; tCK = tCK (IDD); CKE is HIGH, S# is HIGH; Other control and address bus inputs are stable; Data bus inputs are floating IDD2Qb 1,040 880 656 560 mA Precharge standby current; All device banks idle; tCK = tCK (IDD); CKE is HIGH, S# is HIGH; Other control and address bus inputs are switching; Data bus inputs are switching IDD2Nb 1,120 960 720 640 mA Active power-down current; All device banks open; tCK = tCK (IDD); CKE is LOW; Other control and address bus inputs are stable; Data bus inputs are floating Fast PDN exit MR[12] = 0 IDD3Pb 720 640 480 400 mA Slow PDN exit MR[12] = 1 160 160 160 160 mA Active standby current; All device banks open; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Other control and address bus inputs are switching; Data bus inputs are switching IDD3Nb 1,200 1,120 880 720 mA Operating burst write current; All device banks open; Continuous burst writes; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching IDD4Wa 1,536 1,336 1,096 936 mA Operating burst read current; All device banks open; Ccontinuous burst reads, IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching IDD4Ra 1,576 1,336 1,216 936 mA Burst refresh current; tCK = tCK (IDD); REFRESH command at every tRFC (IDD) interval; CKE is HIGH, S# is HIGH between valid commands; Other control and address bus inputs are switching; Data bus inputs are switching IDD5b 4,480 4,160 4,000 3,520 mA Self refresh current; CK and CK# at 0V; CKE ≤ 0.2V; Other control and address bus inputs are floating; Data bus inputs are floating IDD6b 112 112 112 112 mA Operating device bank interleave read current; All device banks interleaving reads, IOUT = 0mA; BL = 4, CL = CL (IDD), AL = tRCD (IDD) - 1 × tCK (IDD); tCK = tCK (IDD), tRC = tRC (IDD), tRRD = tRRD (IDD), tRCD = tRCD (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are stable during DESELECTs; Data bus inputs are switching; See IDD7 conditions in component data sheet for detail IDD7a 2,736 2,456 2,376 2,136 mA

PDF: 09005aef80f09084/Source: 09005aef80f09068 Micron Technology, Inc., reserves the right to change products or specifications without notice. HTF16C64_128_256x64AG.fm - Rev. D 5/06 EN 12 ©2003 Micron Technology, Inc. All rights reserved. 512MB, 1GB, 2GB: (x64, DR) 240-Pin DDR2 SDRAM UDIMM AC Timing and Operating Conditions AC Timing and Operating Conditions Recommended AC operating conditions are given in the DDR2 component data sheets. Component specifications are available on Micron’ s Web site: www.micron.com/ddr2. Module speed grades correlate with component speed grades as shown in the following table: Table 10: Module and Component Speed Grade Table Module Speed Grade Component Speed Grade -80E -25E -667 -3 -53E -37E -40E -5E

PDF: 09005aef80f09084/Source: 09005aef80f09068 Micron Technology, Inc., reserves the right to change products or specifications without notice. HTF16C64_128_256x64AG.fm - Rev. D 5/06 EN 13 ©2003 Micron Technology, Inc. All rights reserved. 512MB, 1GB, 2GB: (x64, DR) 240-Pin DDR2 SDRAM UDIMM Serial Presence-Detect Serial Presence-Detect SPD Clock and Data Conventions Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions (Figures 4 and 5 on page 14). SPD Start Condition All commands are preceded by the start condition, which is a HIGH-to-LOW transition of SDA when SCL is HIGH. The SPD device continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition has been met. SPD Stop Condition All communications are terminated by a stop condition, which is a LOW-to-HIGH tran- sition of SDA when SCL is HIGH. The stop condition is also used to place the SPD device into standby power mode. SPD Acknowledge Acknowledge is a software convention used to indicate successful data transfers. The transmitting device, either master or slave, will release the bus after transmitting 8 bits. During the ninth clock cycle, the receiver will pull the SDA line LOW to acknowledge that it received the 8 bits of data (Figure 6 on page 14). The SPD device will always respond with an acknowledge after recognition of a start condition and its slave address. If both the device and a WRITE operation have been selected, the SPD device will respond with an acknowledge after the receipt of each subsequent 8-bit word. In the read mode the SPD device will transmit 8 bits of data, release the SDA line and monitor the line for an acknowledge. If an acknowledge is detected and no stop condition is generated by the master, the slave will continue to transmit data. If an acknowledge is not detected, the slave will terminate further data transmissions and await the stop condition to return to standby power mode.

PDF: 09005aef80f09084/Source: 09005aef80f09068 Micron Technology, Inc., reserves the right to change products or specifications without notice. HTF16C64_128_256x64AG.fm - Rev. D 5/06 EN 15 ©2003 Micron Technology, Inc. All rights reserved. 512MB, 1GB, 2GB: (x64, DR) 240-Pin DDR2 SDRAM UDIMM Serial Presence-Detect Figure 7: SPD EEPROM Timing Diagram Table 11: EEPROM Device Select Code The most significant bit (b7) is sent first Select Code Device Type Identifier Chip Enable RW b7 b6 b5 b4 b3 b2 b1 b0 Memory area select code (two arrays) 1 0 1 0 SA2 SA1 SA0 RW Protection register select code 0 1 1 0 SA2 SA1 SA0 RW Table 12: EEPROM Operating Modes Mode RW Bit WC Bytes Initial Sequence Current address READ 1V IH or VIL 1 Start, device select, RW = 1 Random address READ 0V IH or VIL 1 Start, device select, RW = 0, address 1V IH or VIL 1 Restart, device select, RW = 1 Sequential READ 1V IH or VIL ≥ 1 Similar to current or random address READ Byte WRITE 0V IL 1 Start, device select, RW = 0 Page WRITE 0V IL ≤ 16 Start, device select, RW = 0 SCL SDA In SDA Out tLOW tSU:STA tHD:STA tF tHIGH tR tBUFtDHtAA tSU:STOtSU:DATtHD:DAT UNDEFINED

PDF: 09005aef80f09084/Source: 09005aef80f09068 Micron Technology, Inc., reserves the right to change products or specifications without notice. HTF16C64_128_256x64AG.fm - Rev. D 5/06 EN 16 ©2003 Micron Technology, Inc. All rights reserved. 512MB, 1GB, 2GB: (x64, DR) 240-Pin DDR2 SDRAM UDIMM Serial Presence-Detect Notes: 1. To avoid spurious start and stop conditions, a minimum delay is placed between SCL = 1 and the falling or rising edge of SDA. 2. This parameter is sampled. 3. For a restart condition, or following a WRITE cycle. 4. The SPD EEPROM WRITE cycle time ( tWRC) is the time from a valid stop condition of a write sequence to the end of the EEPROM internal erase/program cycle. During the WRITE cycle, the EEPROM bus interface circuit is disabled, SDA remains HIGH due to pull-up resistor, and the EEPROM does not respond to its slave address. Table 13: Serial Presence-Detec t EEPROM DC Operating Conditions All voltages referenced to VSS; VDDSPD = +1.7V to +3.6V Parameter/Condition Symbol Min Max Units Supply voltage VDDSPD 1.7 3.6 V Input high voltage: Logic 1; All inputs VIH VDDSPD × 0.7 V DDSPD + 0.5 V Input low voltage: Logic 0; All inputs VIL –0.6 V DDSPD × 0.3 V Output low voltage: IOUT = 3mA VOL –0 . 4 V Input leakage current: VIN = GND to VDD ILI 0.10 3 µA Output leakage current: VOUT = GND to VDD ILO 0.05 3 µA Standby current: ISB 1.6 4 µA Power supply current, READ: SCL clock frequency = 100 KHz ICCR 0.4 1 mA Power supply current, WRITE: SCL clock frequency = 100 KHz ICCW 23 m A Table 14: Serial Presence-Detec t EEPROM AC Operating Conditions All voltages referenced to VSS; VDDSPD = +1.7V to +3.6V Parameter/Condition Symbol Min Max Units Notes SCL LOW to SDA data-out valid tAA 0.2 0.9 µs 1 Time the bus must be free before a new transition can start tBUF 1.3 – µs Data-out hold time tDH 200 – ns SDA and SCL fall time tF– 3 0 0 n s 2 Data-in hold time tHD:DAT 0 – µs Start condition hold time tHD:STA 0.6 – µs Clock HIGH period tHIGH 0.6 – µs Noise suppression time constant at SCL, SDA inputs tI– 5 0 n s Clock LOW period tLOW 1.3 – µs SDA and SCL rise time tR– 0 . 3 µ s 2 SCL clock frequency fSCL – 400 KHz Data-in setup time tSU:DAT 100 – ns Start condition setup time tSU:STA 0.6 – µs 3 Stop condition setup time tSU:STO 0.6 – µs WRITE cycle time tWRC – 10 ms 4

PDF: 09005aef80f09084/Source: 09005aef80f09068 Micron Technology, Inc., reserves the right to change products or specifications without notice. HTF16C64_128_256x64AG.fm - Rev. D 5/06 EN 17 ©2003 Micron Technology, Inc. All rights reserved. 512MB, 1GB, 2GB: (x64, DR) 240-Pin DDR2 SDRAM UDIMM Serial Presence-Detect Table 15: Serial Presence-Detect Matrix “1”/“0”: Serial Data, “driven to HIGH”/“driv en to LOW”; table notes located on page 19 Byte Description Entry (Version) MT16HTF6464A MT16HTF12864A MT16HTF25664A

0 Number of SPD bytes used by Micron 1 2 88 08 08 0

1 Total number of bytes in SPD device 2 5 60 80 80 8

2 Fundamental memory type D D R 2 S D R A M 0 80 80 8

3 Number of row addresses on assembly 13, 14 0D 0E 0E

4 Number of column addresses on

5 DIMM height and module ranks 1.18in, dual rank 61 61 61

6 Module data width 64 40 40 40

7 Reserved 0 0 00 00 0

8 Module voltage interface levels SSTL 1.8V 05 05 05

9 DDR2 cycle time, tCK (CL = MAX value,

see byte 18) -80E -667 -53E -40E

10 DDR2 access from clock,

tAC (CL = MAX value, see byte 18) -80E -667 -53E -40E

11 Module configuration type 00 00 00

12 Refresh rate/type 7.81µs/self 82 82 82

13 DDR2 SDRAM device width (primary

device) 8 0 80 80 8

14 Error-checking DDR2 data width N / A0 00 00 0

15 Reserved 1 c l o c k 0 00 00 0

16 Burst lengths supported 4 , 80 C0 C0 C

17 Number of banks on DDR2 device 4 o r 8 0 40 40 8

18 CAS latencies supported -80E (6, 5, 4)

-667 (5, 4, 3) -53E/-40E (4, 3)

19 Module thickness 01 01 01

20 DDR2 DIMM type Unbuffered 02 02 02

21 DDR2 module attributes 00 00 00

22 DDR2 device attributes: weak driver

(01) or 50Ω ODT (03) -80E/-667 -53E/-40E

23 DDR2 cycle time,

tCK, MAX CL - 1 -80E/-667 -53E -40E

24 SDRAM access from CK,

tAC, MAX CL - 1 -80E -667 -53E -40E

25 SDRAM cycle time,

tCK, MAX CL - 2 -80E -667 -53E/-40E(N/A)

26 SDRAM access from CK,

tAC, MAX CL - 2 -80E -667 -53E/-40E(N/A)

27 MIN row precharge time,

-667/-53E/-40E

PDF: 09005aef80f09084/Source: 09005aef80f09068 Micron Technology, Inc., reserves the right to change products or specifications without notice. HTF16C64_128_256x64AG.fm - Rev. D 5/06 EN 18 ©2003 Micron Technology, Inc. All rights reserved. 512MB, 1GB, 2GB: (x64, DR) 240-Pin DDR2 SDRAM UDIMM Serial Presence-Detect

28 MIN row active to row active, tRRD 1E 1E 1E

29 MIN RAS#-to-CAS# delay, tRCD -80E

-667/-53E/-40E

30 MIN RAS# pulse width, tRAS -80E/-667/-53E

-40E

31 Module rank density 256MB, 512MB, 1GB 40 80 01

32 Address and command setup time, tISb -80E

-667 -53E -40E

33 Address and command hold time,

-667 -53E -40E

34 Data/data mask input setup time,

-667/-53E -40E

35 Data/data mask input hold time,

-667 -53E -40E

36 Write recovery time,

37 WRITE-to-READ command delay, tWTR -80E/-667/-53E

-40E

38 READ-to-PRECHARGE command delay,

39 Mem analysis probe 00 00 00

40 Extension for bytes 41 and 42 -80E

-667/-53E/-40E

41 MIN active auto refresh time, tRC -80E

-667/-53E -40E

42 MIN AUTO REFRESH-to-ACTIVE/

AUTO REFRESH command period, tRFC 69 69 7F

43 DDR2 device MAX cycle time, tCKMAX 80 80 80

44 DDR2 device MAX DQS-DQ skew time,

-80E -667 -53E -40E

45 DDR2 device MAX read data hold skew

factor, tQHS -80E -667 -53E -40E

46 PLL relock time 00 00 00

47–61 Optional features, not supported 00 00 00 62 SPD revision Release 1.2 12 12 12

63 Checksum for bytes 0–62 -80E

-667 -53E -40E ED FF ED FF Table 15: Serial Presence-Detect Matrix “1”/“0”: Serial Data, “driven to HIGH”/“driv en to LOW”; table notes located on page 19 Byte Description Entry (Version) MT16HTF6464A MT16HTF12864A MT16HTF25664A

PDF: 09005aef80f09084/Source: 09005aef80f09068 Micron Technology, Inc., reserves the right to change products or specifications without notice. HTF16C64_128_256x64AG.fm - Rev. D 5/06 EN 19 ©2003 Micron Technology, Inc. All rights reserved. 512MB, 1GB, 2GB: (x64, DR) 240-Pin DDR2 SDRAM UDIMM Serial Presence-Detect Notes: 1. The tRAS SPD value shown is based on the JEDEC standard value of 45ns; the actual device specification is tRAS = 40ns.

64 Manufacturer’s JEDEC ID code MICRON 2C 2C 2C

65-71 Manufacturer’s JEDEC ID code (Continued) FF FF FF

72 Manufacturing location 01–12 01–0C 01–0C 01–0C

73-90 Module part number (ASCII) Variable data Variable data Variable data

91 PCB identification code 1–9 01–09 01–09 01–09

92 Identification code (continued) 0 0 00 00 0

93 Year of manufacture in BCD Variable data Variable data Variable data

94 Week of manufacture in BCD Variable data Variable data Variable data

95-98 Module serial number Variable data Variable data Variable data 99-127 Manufacturer-specific data (RSVD) ––– Table 15: Serial Presence-Detect Matrix “1”/“0”: Serial Data, “driven to HIGH”/“driv en to LOW”; table notes located on page 19 Byte Description Entry (Version) MT16HTF6464A MT16HTF12864A MT16HTF25664A

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 prodmktg@micron.com www.micron.com Customer Comment Line: 800-932-4992 Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. This data sheet contains minimum and maximum limits specified over the complete power supply and temperature range for production devices. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. 512MB, 1GB, 2GB: (x64, DR) 240-Pin DDR2 SDRAM UDIMM Module Dimensions PDF: 09005aef80f09084/Source: 09005aef80f09068 Micron Technology, Inc., reserves the right to change products or specifications without notice. HTF16C64_128_256x64AG.fm - Rev. D 5/06 EN 20 ©2003 Micron Technology, Inc. All rights reserved. Module Dimensions Figure 8: 240-pin DIMM DDR2 Module Dimensions Notes: 1. All dimensions are in millimet ers (inches); or typical where noted. 2. The dimensional diagram is for reference on ly. Refer to the MO document for complete design dimensions. 30.50 (1.200) 29.85 (1.175) PIN 1 17.78 (0.700) TYP. 2.50 (0.098) D (2X) 2.30 (0.091) TYP. 5.0 (0.197) TYP. 123.0 (4.840) TYP. 1.0 (0.039) TYP. 0.80 (0.031) TYP. 2.00 (0.079) R (4X) 0.76 (0.030) R PIN 120 FRONT VIEW 133.50 (5.256) 133.20 (5.244) 63.0 (2.48) TYP. 55.0 (2.165) TYP. 10.00 (0.394) TYP. BACK VIEW PIN 240 PIN 121 1.37 (0.054) 1.17 (0.046) 4.0 (0.157) MAX U1 U2 U3 U4 U10 U6 U7 U8 U9 U11 U12 U13 U14 U16 U17 U18 U19 MAX MIN

PDF: 09005aef80f09084/Source: 09005aef80f09068 Micron Technology, Inc., reserves the right to change products or specifications without notice. HTF16C64_128_256x64AG.fm - Rev. D 5/06 EN 21 ©2003 Micron Technology, Inc. All rights reserved. 512MB, 1GB, 2GB: (x64, DR) 240-Pin DDR2 SDRAM UDIMM

Revision History

 Added -80E speed grade to 1GB and 2GB densities  Removed component data  Updated format, style  Corrected 1GB -53E SPD  Added -667 speed grade  Updated Initialization process U p d a t e d I d d s  Updated features list  Updated part numbers  Removed OCD, updated General Description  Updated Initialization diagram, EMR diagrams  Updated Table 15, AC Operating Conditions U p d a t e d S P D  New Datasheet, lvg’ d from HTF8C32_64_128x72AG