M67206H ATMEL | Alldatasheet
Document overview
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Technical content
Features
- First-in First-out Dual Port Memory
- 16384 bits x 9 Organization
- Fast Flag and Access Times: 15, 30 ns
- Wide Temperature Range: - 55 °C to + 125 °C
- Fully Expandable by Word Width or Depth
- Asynchronous Read/Write Operations
- Empty, Full and Half Flags in Single Device Mode
- Retransmit Capability
- Bi-directional Applications
- Battery Back-up Operation: 2V Data Retention
- TTL Compatible
- Single 5V ± 10% Power Supply
- No Single Event Latch-up below a LET Threshold of 80 MeV/mg/cm 2
- Tested up to a Total Dose of 30 krads (Si) according to MIL STD 883 Method 1019
- Quality grades: QML Q and V with SMD 5962-93177 and ESCC with specification
Description
The M67206H implements a first-in first-out algorit hm, featuring asynchronous read/write operations. The FULL and EMPTY flags pre vent data overflow and under- flow. The Expansion logic allows unlimited expansio n in word size and depth with no timing penalties. Twin address pointers automatically generate internal read and write addresses, and no external address information is r equired. Address pointers are automatically incremented with the write pin and re ad pin. The 9 bits wide data are used in data communications applications where a pa rity bit for error checking is nec- essary. The Retransmit pin resets the Read pointer to zero without affecting the write pointer. This is very useful for retransmitting dat a when an error is detected in the system. Using an array of eight transistors (8T) memory cel l, the M67206H combines an extremely low standby supply current (typ = 0.1 µ A) with a fast access time at 15 ns over the full temperature range. All versions offer battery backup data retention capa- bility with a typical power consumption at less than 2 µ W. The M67206H is processed according to the methods o f the latest revision of the MIL PRF 38535 (Q and V) or ESCC 9000. Rad. Tolerant High Speed
16 Kb x 9
4143J–AERO–04/07 Block Diagram Pin Configuration DIL ceramic 28-pin 300 mils FP 28-pin 400 mils
Figure 1. Reset Notes: 1. EF , FF and HF may change status during reset, but flags will be valid at t RSC .
- W and R = VIH around the rising edge of RS .
4143J–AERO–04/07 Write Enable (W) A write cycle is initiated on the falling edge of t his input if the Full Flag (FF ) is not set. Data set-up and hold times must be maintained in th e rise time of the leading edge of the Write Enable (W ). Data is stored sequentially in the Ram array, re gardless of any current read operation. Once half the memory is filled, and during the fall ing edge of the next write operation, the Half-Full Flag (HF ) will be set to low and remain in this state until the difference between the write and read pointers is less than or equal to half of the total available memory in the device. The Half-Full Flag (HF ) is then reset by the rising edge of the read operation. To prevent data overflow, the Full Flag (FF ) will go low, inhibiting further write opera- tions. On completion of a valid read operation, the Full Flag (FF ) will go high after TRFF, allowing a valid write to begin. When the FIFO stac k is full, the internal write pointer is blocked from W, so that external changes to W will have no effect on the full FIFO stack. Read Enable (R) A read cycle is initiated on the falling edge of th e Read Enable (R ) provided that the Empty Flag (EF ) is not set. The data is accessed on a first-in/fi rst-out basis, not includ- ing any current write operations. After Read Enable (R) goes high, the Data Outputs (Q0 - Q8) will return to a high impedance state until t he next Read operation. When all the data in the FIFO stack has been read, the Empty Fla g (EF ) will go low, allowing the “final” read cycle, but inhibiting further read ope rations while the data outputs remain in a high impedance state. Once a valid write operatio n has been completed, the Empty Flag (EF ) will go high after tWEF and a valid read may then be initiated. When the FIFO stack is empty, the internal read pointer is blocked from R, so that external changes to R will have no effect on the empty FIFO stack. First Load/Retransmit (FL /RT ) This pin is a dual-purpose input. In the Depth Expa nsion Mode, this pin is connected to ground to indicate that it is the first loaded (see Operating Modes). In the Single Device Mode, this pin acts as the retransmit input. The Si ngle Device Mode is initiated by con- necting the Expansion In (XI ) to ground. The M67206H can be set to retransmit data when the Retransmit Enable Control (RT ) input is pulsed low. A retransmit operation will set the internal read point to the first loca- tion and will not affect the write pointer. Read En able (R) and Write Enable (W) must be in the high state during retransmit. The retransmit feature is intended for use when a number of writes are equal to or less than the dept h of the FIFO has occurred since the last RS cycle. The retransmit feature is not compatible wi th the Depth Expansion Mode and will affect the Half-Full Flag (HF ), in accordance with the relative locations of the read and write pointers. Expansion In (XI ) The XI input is a dual-purpose pin. Expansion In (XI ) is connected to GND to indicate an operation in the single device mode. Expansion In ( XI ) is connected to Expansion Out (XO ) of the previous device in the Depth Expansion or Daisy Chain modes. Full Flag (FF ) The Full Flag (FF ) will go low, inhibiting further write operations when the write pointer is one location less than the read pointer, indicating that the device is full. If the read pointer is not moved after Reset (RS ), the Full Flag (FF ) will go low after 16384 writes. Empty Flag (EF ) The Empty Flag (EF ) will go low, inhibiting further read operations when the read pointer is equal to the write pointer, indicating that the device is empty.
4143J–AERO–04/07 Expansion Out/Half-Full Flag (XO /HF ) The XO /HF pin is a dual-purpose output. In the single device mode, when Expansion In (XI ) is connected to ground, this output acts as an indication of a half-full memory. After half the memory is filled and on the falling edge of the next write operation, the Half-Full Flag (HF ) will be set to low and will remain set until the difference between the write and read pointers is less than or equal to ha lf of the total memory of the device. The Half-Full Flag (HF ) is then reset by the rising edge of the read operation. In the Depth Expansion Mode, Expansion In (XI ) is connected to Expansion Out (XO ) of the previous device. This output acts as a signal to the next device in the Daisy Chain by providing a pulse to the next device when the previ ous device reaches the last memory location. Data Output (Q 0 - Q 8) DATA output for 9-bit wide data. This data is in a high impedance condition whenever Read (R) is in a high state.
Note: 1. Pointer will increment if flag is high. is connected to XO of previous device. be achieved by adding an additional M67206H.
- The first device must be designated by connecting the First Load (FL
- All other devices must have FL in the high state.
- The Expansion Out (XO ) pin of each device must be connected to the Expansion In
- External logic is needed to generate a composite Full Flag (FF ) and Empty Flag
correct composite FF or EF ). See Figure 4.
- The Retransmit (RT ) function and Half-Full Flag (HF ) are not available in the Depth
ate large FIFO arrays (see Figure 5). Table 1. Reset and Retransmit Table 2. Reset and First Load Truth Table
on which R is in use). Both Depth Expansion and Width Expansion may be used in this mode. FIFO will appear on the output bus in accordance with the read cycle timings. FIFO stack and to increment the write pointer. Figure 4. Block Diagram of 49152 bits × 9 FIFO Memory (Depth Expansion)
4143J–AERO–04/07
Electrical Characteristics
Input or Output voltage applied: (GND - 0.3V) to (V cc + 0.3V) *NOTICE: Stresses beyond those listed under "Absolute Maxi- mum Ratings” may cause permanent damage to the device. This is a stress rating only and functional oper- ation of the device at these or any other condition s beyond those indicated in the operational sections of this specification is not implied. Exposure to abso lute maximum rating conditions for extended periods may affect device reliability. DC Test Conditions TA = -55 °C to + 125 °C; Vss = 0V; Vcc = 4.5V to 5.5V Parameter Description M67206H-30 M67206H-15 Unit Value ICCOP (1) Operating supply current 110 120 mA Max ICCSB (2) Standby supply current 5 5 mA Max ICCPD (3) Power down current 400 400 µA Max 1. Icc measurements are made with outputs open. 2. R = W = RS = FL/RT = VIH. 3. All input = Vcc. Parameter Description M67206H Unit Value ILI (1) Input leakage current ± 1 µ A Max ILO (2) Output leakage current ± 1 µ A Max VIL (3) Input low voltage 0.8 V Max VIH (3) Input high voltage 2.2 V Min VOL (4) Output low voltage 0.4 V Max VOH (4) Output high voltage 2.4 V Min C IN (5) Input capacitance 8 pF Max C OUT (5) Output capacitance 8 pF Max 1. 0.4 ≤ Vin ≤ Vcc. 2. R = VIH, 0.4 ≤ VOUT ≤ VCC. 4. Vcc min, IOL = 8 mA, IOH = -2 mA. 5. Guaranteed but not tested.
Figure 7. Output Load Table 3. AC Test Conditions
- Timings referenced as in AC test conditions.
- All parameters tested only.
- Pulse widths less than minimum value are not allo wed.
- Values guaranteed by design, not currently tested .
- Only applies to read data flow-through mode.
Table 3. AC Test Conditions (Continued)
4143J–AERO–04/07
Ordering Information
Note: 1. Contact Atmel for availability. Part Number Temperature Range Speed Package Quality Flow MMCP-67206HV-15-E (1) 25 °C 15 ns SB28.3 Engineering Samples SMCP-67206HV-15SCC -55 to +125 °C 15 ns SB28.3 ESCC SMCP-67206HV-30SCC -55 to +125 °C 30 ns SB28.3 ESCC 5962-9317708QTC -55 to +125 °C 15 ns SB28.3 QML Q 5962-9317707QTC -55 to +125 °C 30 ns SB28.3 QML Q 5962-9317708VTC -55 to +125 °C 15 ns SB28.3 QML V 5962D9317708VTC -55 to +125 °C 15 ns SB28.3 QML V RHA 5962D9317707VTC -55 to +125 °C 30 ns SB28.3 QML V RHA 5962-9317707VTC -55 to +125 °C 30 ns SB28.3 QML V MMDP-67206HV-15-E 25 °C 15 ns FP28.4 Engineering Samples SMDP-67206HV-15SCC -55 to +125 °C 15 ns FP28.4 ESCC SMDP-67206HV-30SCC -55 to +125 °C 30 ns FP28.4 ESCC 5962-9317708QNC -55 to +125 °C 15 ns FP28.4 QML Q 5962-9317707QNC -55 to +125 °C 30 ns FP28.4 QML Q 5962-9317708VNC -55 to +125 °C 15 ns FP28.4 QML V 5962-9317707VNC -55 to +125 °C 30 ns FP28.4 QML V 5962D9317708VNC -55 to +125 °C 15 ns FP28.4 QML V RHA 5962D9317707VNC -55 to +125 °C 30 ns FP28.4 QML V RHA MM0 -67206HV-15SV (1) -55 to +125 °C 15 ns Die QML V MM067206HV-15-E (1) 25 °C 15 ns Die Engineering Samples
4143J–AERO–04/07 Package Drawings 28-lead Side Braze (300 Mils)
4143J–AERO–04/07 28-lead Flat Pack (400 Mils)
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