MGP3006

MGP3006X SIEMENS | Alldatasheet

Document overview

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Technical content

Features

l 1-chip system for MPU-control (I2C Bus) l 4 programmable chip addresses l Short pull-in time for quick channel switch-over and optimized loop stability l 2 high-current band switch outputs (20 mA) l Software-compatible with SDA 3202 series l Oxis III technology Semiconductor Group 1 04.93

UHF/VHF The tuner signal is capacitively coupled at the UHF/VHF-input and subsequently amplified. REF The reference input REF should be decoupled to ground using a capacitor of low series inductance. The signal passes through an asynchronous divider with a fixed ratio of P = 8, an adjustable divider with ratioN = 256 through 32767, and is then compared in a digital frequency/phase detector to a reference frequency fREF = 7.8125 kHz. Q1, Q2 This frequency is derived from a balanced, low-impedance 4-MHz crystal oscillator (pin Q1, Q2) by dividing its output signal byQ = 512. The phase detector has two outputs UP and DOWN that drive the two current sources I+ and I– of a charge pump. If the negative edge of the divided VCO-signal appears prior to the negative edge of the reference signal, the I+ current source pulses for the duration of the phase difference. In the reverse case the I– current source pulses. PD, UD If the two signals are in phase, the charge pump output (PD) goes into the high-impedance state (PLL is locked). An active low-pass filter integrates the current pulses to generate the tuning voltage for the VCO (internal amplifier, external output transistor at UD and external RC-circuitry). The charge pump output is also switched into the high-impedance state when the control bit T0 = 1. Here it should be noted, however, that the tuning voltage can alter over a long period in the high-impedance state as a result of self-discharge in the peripheral circuitry. UD may be switched off by the control bit OS to allow external adjustments. By means of a control bit 5I the pump current can be switched between two values by software. This programmability permits alteration of the control response of the PLL in the locked-in state. In this way different VCO-gains in the different TV-bands can be compensated, for example. P1, P2 The software-switched outputs P1, P2 can be used for direct band selection (20 mA current output). P7 P7 is a general-purpose open-collector output. The test bit T1 = 1 switches the test signal Cy (divided input signal) to P7. CAU Four different chip addresses can be set by appropriate connection of pin CAU.

Data are exchanged between the processor and the PLL on theI2C Bus. SCL, SDA The clock is generated by the processor (input SCL), while pin SDA works as an input or output depending on the direction of the data (open collector; external pull-up resistor). Both inputs have hysteresis and a low-pass characteristic, which enhances the noise immunity of theI Bus. The data from the processor pass through anI2C Bus control. Depending on their function the data are subsequently stored in registers. If the bus is free, both lines will be in the marking state (SDA, SCL are high). Each telegram begins with the start condition and ends with the stop condition. Start condition: SDA goes low, while SCL remains high. Stop condition: SDA goes high while SCL remains high. All further information transfer takes place during SCL = low, and the data is forwarded to the control logic on the positive clock edge. The table “bit allocation” should be referred to in the following paragraph. All telegrams are transmitted byte-by-byte, followed by a ninth clock pulse, during which the control logic returns the SDA-line to low (acknowledge condition). The first byte is comprised of seven address bits. These are used by the processor to select the PLL from several peripheral components (chip select). The eighth bit is always low. In the data portion of the telegram the first bit of the first or third data byte determines whether a divider ratio or control information is to follow. In each case the second byte of the same data type or a stop condition has to follow the first byte. V S, GND When the supply voltage is applied a power-on reset circuit prevents the PLL from setting the SDA-line to low, which would block the bus.

Circuit Description (cont’d) Bit Allocation Divider Ratio N = 16384· n14 + 8192· n13 + 4096· n12 + 2048· n11 + 1024· n10 + 512· n9 + 256 · n8 + 128· n7 + 64· n6 + 32· n5 + 16· n4 + 8· n3 + 4· n2 + 2· n1 + n0 Band Selection P1, P2, P7 = 1 Open-collector output is active. Pump Current Programming 5I = 1 High current UD Disable OS = 1 UD is disabled. Test Mode T1, T0 = 0, 0 Normal operation T1 = 1 P7 = carry Cy of programmable divider T0 = 1 Tristate: charge pump output PD is in high-impedance state. MSB A = Acknowledge Address byte 1 1 0 0 0 MA1 MA0 0 A Prog. divider Byte 1 0 n14 n13 n12 n11 n10 n9 n8 A Prog. divider Byte 2 n7 n6 n5 n4 n3 n2 n1 n0 A Control info. Byte 1 1 5I T1 T0 1 1 1 OS A Control info. Byte 2 P7 X X X X P2 P1 X A

Start-Addr-DR1-DR2-CW1-CW2-Stop Start = start condition Start-Addr-CW1-CW2-DR1-DR2-Stop Addr = address Start-Addr-DR1-DR2-CW1-Stop DR1 = divider ratio 1st byte Start-Addr-CW1-CW2-DR1-Stop DR2 = divider ratio 2nd byte Start-Addr-DR1-DR2-Stop CW1 = control word 1st Byte Start-Addr-CW1-CW2-Stop CW2 = control word 2nd Byte Start-Addr-DR1-Stop Stop = stop condition Start-Addr-CW1-Stop MA1 MA0 Voltage at CAU 0 0 (0 … 0.1) VS 0 1 open-circuit 1 0 (0.4 … 0.6) VS 1 1 (0.9 … 1) VS

(top view)

Pin Definitions and Functions Pin No. Symbol Function

1 PD Input active filter/charge pump output

2 Q1 Quartz crystal

3 Q2 Quartz crystal

4 SDA Data input/output for I

5 SCL Clock input for I2C Bus

6 P7 Port output (open collector)

7 CAU Address switch input

8 P2 Port output (open collector)

9 P1 Port output (open collector)

11 UHF/VHF Signal input

12 REF Amplifier reference input

13 GND Ground

14 UD Output active filter

TA = – 20 to 80°C Parameter Symbol Limit Values Unit Remarks min. max. Supply voltage VS – 0.3 6 V Output PD V1 – 0.3 VS V Crystal oscillator pins Q1, Q2V2 – 0.3 VS V Bus input/output SDA V4 – 0.3 6 V Bus input SCL V5 – 0.3 6 V Port outputs P1, P2, P7 V6 – 0.3 16 V Chip address switch CAU V7 – 0.3 VS V Signal input UHF/VHF V11 – 0.3 0.3 V for VS = 0 V Reference input REF V12 – 0.3 0.3 V for VS = 0 V Output active filter UD V14 – 0.3 VS V Bus output SDA I4L – 1 5 mA open collector Port outputs P7 I6L – 1 7 mA open collector Port outputs P1, P2 I8L – 1 20 mA open collector Total port output current SIL 25 mA Junction temperature Tj 125 °C Storage temperature Tstg – 40 125 °C Thermal resistance (junction to ambient) Rth JA 125 K/W

Supply voltage VS 4.5 5.5 V Ambient temperature TA –2 0 8 0 °C Input frequency f11 16 1300 MHz (at 25 °C) Crystal frequency f2 4 MHz Programmable divider factorN 256 32767 AC/DC Characteristics TA = – 20 to 80°C;VS = 4.5 to 5.5 V Parameter Symbol Limit Values Unit Test Condition Test Circuit min. typ. max. Supply current IS 37 55 mA VS = 5 V 1 Crystal oscillator frequency f2 3.999754.000 4.00025MHz series capacitance 18 pF, fQ = 4 MHz Oscillator amplitude (voltage across crystal) 2.6 1) Vpp Margin from 1st (fundamental) to 2nd and 3rd harmonics 1) dB Signal Input UHF/VHF Sensitivity a11 a11 a11 Ð27/10 Ð27/10 Ð20/22 dBm/ dBm/2) dBm/2) f11 = 70 … 500 MHz f11 = 1000 MHz f11 = 1100 MHz Notes see page 11. Absolute Maximum Ratings (cont’d) TA = – 20 to 80°C Parameter Symbol Limit Values Unit Remarks min. max.

1) Design note only: no 100 % final inspection. 2) mVrms into 50W. 3) The sum of the currents in ports P1, P2, P7 may not exceed 25 mA. Port Output P7 (switch with open collector)3) H-input current I6H 10 mA V6H = 13.5 V 4 L-output voltage V6L 0.5 V I6L = 1.7 mA 4 Port Outputs P1, P2 (switch with open collector)3) H-input current I8H 10 mA V8H = 13.5 V 3 L-output voltage V8L 0.5 V I8L = 20 mA 3 Phase-Detector Output PD (V S = 5 V) Pump current Pump current I1H I1H – 90 – 22 – 220 – 50 – 300 – 75 mA mA 5I = high;V1 = 2 V 5I = low;V1 = 2 V Tristate current I1Z – 5 0 5 nA T1 = 1; V1 = 2 V 5 Output voltage V1L 1.0 2.5 V locked 5 Active Filter Output UD (Test mode T0 = 1; PD = tristate) Output current – I14 500 mA V14 = 0.8 V; I1H = 90mA Output voltage Output voltage V14 V14 100 500 mV mV V1L = 0 V OS = 1; Chip Address Switch CAU Input current Input current I7H – I7H mA mA V7H = 5 V V7H = 5 V AC/DC Characteristics (cont’d) TA = – 20 to 80°C;VS = 4.5 to 5.5 V Parameter Symbol Limit Values Unit Test Condition Test Circuit min. typ. max.

AC/DC Characteristics (cont‘d) TA = – 20 to 80°C;VS = 4.5 to 5.5 V; refer to test circuit 6 Parameter Symbol Limit Values Unit Test Condition min. typ. max. Bus Inputs SCL, SDA H-input voltage V4IH 3 5.5 V L-input voltage V4IL 1.5 V H-input current I4IH 10 mA V4IH =VS L-input current – I4IL 20 mA V4IL = 0 V Bus Output SDA (open collector) H-output current I4OH 10 mA V4OH = 5.5 V L-output voltage V4OL 0.4 V I4OL = 3 mA Edges SCL, SDA Rise time tR 1 ms Fall time tF 0.3 ms Shift Clock SCL Frequency f5 0 100 kHz H-pulse width t5H 4 ms L-pulse width t5L 4.7 ms Start Set-up time tSUSTA 4.7 ms Hold time tHDSTA 4 ms Stop Set-up time tSUSTO 4.7 ms Bus free tBUF 4.7 ms

1) Design note only: no 100 % final inspection. Data Transfer Set-up time tSUDAT 0.25 ms Hold time tHDDAT 0 ms Input hysteresis SCL, SDA1) 300 mV Low-pass cutoff frequency SCL, SDA 500 kHz AC/DC Characteristics (cont‘d) TA = – 20 to 80°C;VS = 4.5 to 5.5 V; refer to test circuit 6 Parameter Symbol Limit Values Unit Test Condition min. typ. max.

Measurement of Input Sensitivity Calibration of Signal Generator

Set-up time (start) tSUSTA Hold time (start) tHDSTA H-pulse width (clock) tHIGH L-pulse width (clock) tLOW Set-up time (data transfer) tSUDAT Hold time (data transfer) tHDDAT Set-up time (stop) tSUSTO Bus free time tBUF Fall time tF Rise time tR All times related to 10 % and 90 % values.

Loop bandwidth: w R = Ö[(IP · K VCO ) / (C 1 · P · N )] Attenuation: a = 0.5·w R · R · C 1 P = prescaler division ratio N = programmable division ratio IP = charge pump current K VCO = tuner slope R,C 1 = loop filter Example for channel 47: P = 8,N = 11520, IP = 50mA,K VCO = 18.7 MHz/V,R = 22 kW ,C 1 = 180 nF, w R = 237 Hz,fR = 38 Hz,a = 0.47 Note: The high-impedance port outputs and CAU can be decoupled from external noise with a capacitor of 1 nF. It is important to keep to theI2C Bus specification concerning maximum capacitance and impedance.

Sensitivity at UHF/VHF-Input I2C Bus Noise Immunity Sinusoidal noise pulses are applied via a coupling capacitance of 33 pF to the SCL- and SDA-inputs.

Plastic Package, P-DSO-14-1 (SMD) (Plastic Dual Small Outline) GPS05093 Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information” Dimensions in mmSMD = Surface Mounted Device