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Document overview

  • Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
  • PDF pages: 16

Technical content

Features

  • Dual, matched-pair LNAs
  • Optimum frequency of operation 800MHz-3GHz
  • Very low noise figure
  • High gain
  • Excellent isolation
  • GaAs E-pHEMT Technology[1]
  • Low cost small package size: 4.0x4.0x0.85 mm3
  • Excellent uniformity in product specifications Specifications 1.95GHz; 4V, 50mA per channel (typ)
  • 0.58 dB Noise Figure
  • 24 dB Gain
  • 38.6 dB Isolation
  • 33.3 dBm Output IP3
  • 18.4 dBm Output Power at 1dB gain compression

Applications

  • Balanced dual low noise amplifier for cellular infrastructure for GSM, CDMA, TD-SCDMA and WiMAX used with 3-dB hybrid couplers at inputs and outputs Notes: 1. Enhancement mode technology employs positive gate bias, thereby eliminating the need of negative gate voltage associated with conventional depletion mode devices. Attention: Observe precautions for handling electrostatic sensitive devices. ESD Machine Model = 70 V ESD Human Body Model = 200 V Refer to Avago Application Note A004R: Electrostatic Discharge, Damage and Control. Pin 1 RFin1 Pin 2 nc Pin 3 nc Pin 4 RFin2 nc Pin 16 nc Pin 15 nc Pin 14 nc Pin 13 RFout1 Pin 12 nc Pin 11 nc Pin 10 RFout2 Pin 9 Pin 5 nc Pin 6 nc Pin 7 nc Pin 8 nc KC2 YYWW XXXX TOP VIEW BOTTOM VIEW nc = not connected GND Simplified Schematic VGG VDD VGG VDD CHN#1 CHN#2 IN1 IN2 OUT1 OUT2 PACKAGE

Symbol Parameter Units Absolute Max. VDD Device Voltage, RF output to ground V 6 VGG Gate Voltage V 0.8 Pin,max (ON) CW RF Input Power (at VDD=4V, VGG=0.58V). dBm 18 Pin,max (OFF) CW RF Input Power( at VDD=4V, VGG=0V) dBm 28 Pdiss Total Power Dissipation [2] W 1.2 Tj Junction Temperature oC 150 TSTG Storage Temperature oC -65 to 150 Thermal Resistance [3], θjc = 34 ºC/Wat VDD= 4V, IDD=50mA per channel Notes: 1. Operation of this device in excess of any of these limits may cause permanent damage. 3. Thermal resistance measured using Infra-red measurement technique, with both channels turned on, hence IDDtotal=100mA. Electrical Specifications RF performance at 4V, 50mA,1.95 GHz, TA = 25 °C, given for each RF channel, measured on the demo board in Fig. 28 with component list in Table 1, for 1.95GHz matching. Symbol Parameter and Test Condition Units Min. Typ. Max. VGG Operational Gate Voltage (to adjust for given IDD) V 0.43 0.58 0.7 NF[4] Noise Figure dB 0.58 0.9 Gain Gain dB 22.3 24 25.8 OIP3[5] Output Third Order Intercept Point dBm 33.3 OP1dB Output Power at 1dB Gain Compression dBm 18.4 IRL Input Return Loss, 50Ω source dB 13.5 ORL Output Return Loss, 50Ω load dB 4.6 |S12| Reverse Isolation dB 38.6 |ISOL1-2| Isolation between IN1 and IN2 dB 43 Notes: 4. Board transmission line losses have been deembedded.

Figure 28. Demo board layout - for single-ended measurements. PCB uses 10 mils Rogers RO4350 material.

Table 1. SMT Component list for 1.95GHz and 2.4GHz matching

  1. Inductor and resistor are stacked-up, in parallel.

Figure 29. Demo board schematic diagram and SMT list.

MGA-12516 Typical Scattering and Noise parameters Reference planes at package pins, measured at TA = +25 °C, VDD = 3V, IDD = 50mA per channel. FREQ S11 S21 S12 S22 (GHz) Mag Ang Mag Ang Mag Ang Mag Ang

MGA-12516 Typical Scattering and Noise parameters Reference planes at package pins, measured at TA = +25 °C, VDD = 4V, IDD = 50mA per channel. FREQ S11 S21 S12 S22 (GHz) Mag Ang Mag Ang Mag Ang Mag Ang

MGA-12516 Typical Scattering and Noise parameters Reference planes at package pins, measured at TA = +25 °C, VDD = 5V, IDD =50mA per channel. FREQ S11 S21 S12 S22 (GHz) Mag Ang Mag Ang Mag Ang Mag Ang

Top View Side View Bottom View 4.00 ± 0.10 4.00 ± 0.10 Pin 1 Dot by marking

0.20 Ref

0.00 ± 0.05 0.85 ± 0.05 2.200 Exp.DAP Pin #1 Identi/f_ication Chamfer 0.450 x 45º 1.95 Ref 0.55

0.65 Bsc

2.200 Exp.DAP 0.30 KC2 YYWW XXXX Package Dimensions PCB Land Pattern (Top View) Stencil Outline Combines PCB & Stencil Layouts All Dimension are in MM 0.650 2.400 0.250 0.300 0.650 2.400 0.650 2.160 0.402 0.270 0.485 2.160 2.1600.270 0.485 0.650 0.300 2.400 2.160 2.400 PCB Land Patterns and Stencil Design

12.00 +0.30/-0.10 8.0 ±0.10 4.0 ±0.10 2.00 ±0.05 5.50 ±.05 1.75 ±0.10 1.50 + .10 .279 ±0.02 10º MAX. 10º MAX. 1.13 ±0.10 Ao Ko Bo USER FEED DIRECTION TOP VIEW END VIEW USER FEED DIRECTION COVER TAPE CARRIER TAPE REEL KC2 YYWW XXXX KC2 YYWW XXXX KC2 YYWW XXXX + + + + 1.50 +0.25 Device Orientation Tape Dimensions Part Number Ordering Information Part Number No. of Devices Container MGA-12516-TR1G 1000 7” Reel MGA-12516-TR2G 3000 13” Reel MGA-12516-BLKG 100 antistatic bag

Ø178.0±0.5 Ø55.0±0.5 6.25mm EMBOSSED LETTERS LETTERING THICKNESS: 1.6mm SEE DETAIL "X" SLOT HOLE "b" SLOT HOLE(2x) 180° APART. SLOT HOLE "a": 3.0±0.5mm(1x) SLOT HOLE "b": 2.5±0.5mm(1x) Ø13.065° 45° R10.65 45° R5.2 EMBOSSED RIBS RAISED: 0.25mm, WIDTH: 1.25mm 18.0* MAX. Ø51.2±0.3 Ø178.0±0.5 RECYCLE LOGO FRONT VIEW 120° 1.5 MIN. Ø20.2 MIN. -0.2 +0.5 DETAIL "X" -0.0 +1.5*12.4 DETAIL "Y"(Slot Hole) 3.5 1.0 SEE DETAIL "Y" FRONT BACK FRONT BACK SLOT HOLE "a" Ø178.0±0.5

For product information and a complete list of distributors, please go to our web site: www.avagotech.com Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries. Data subject to change. Copyright © 2005-2009 Avago Technologies. All rights reserved. AV02-1052EN - March 24, 2009 PS 21121110987 203546 6PS PS6 CPN 12MM MPN Detail "X" RECYCLE LOGO SEE DETAIL "X" R19.0±0.5 Ø12.3±0.5(3x) Ø100.0±0.5 Ø329.0±1.0 11.9-15.4** 18.4 MAX.* SLOT 5.0±0.5(3x) 12.4 +2.0* -0.0 16.0mm HEIGHT x MIN. 0.4mm THICK. EMBOSSED LETTERING EMBOSSED LINE (2x) 89.0mm LENGTH LINES 147.0mm AWAY FROM CENTER POINT 7.5mm HEIGHT EMBOSSED LETTERING DATE CODE ESD LOGO Ø16.0 7.5mm HEIGHT EMBOSSED LETTERING HUB Ø100.0±0.5 Ø329.0±1.0 20.2(MIN.) 1.5(MIN.) Ø13.0 -0.2 +0.5 BACK VIEW FRONT VIEW 8 7 6 5